sound/soc/atmel/mchp-pdmc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Driver for Microchip Pulse Density Microphone Controller (PDMC) interfaces
   4 //
   5 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries
   6 //
   7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
   8
   9 #include <dt-bindings/sound/microchip,pdmc.h>
  10
  11 #include <linux/clk.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16
  17 #include <sound/core.h>
  18 #include <sound/dmaengine_pcm.h>
  19 #include <sound/pcm_params.h>
  20 #include <sound/tlv.h>
  21
  22 /*
  23  * ---- PDMC Register map ----
  24  */
  25 #define MCHP_PDMC_CR                    0x00    /* Control Register */
  26 #define MCHP_PDMC_MR                    0x04    /* Mode Register */
  27 #define MCHP_PDMC_CFGR                  0x08    /* Configuration Register */
  28 #define MCHP_PDMC_RHR                   0x0C    /* Receive Holding Register */
  29 #define MCHP_PDMC_IER                   0x14    /* Interrupt Enable Register */
  30 #define MCHP_PDMC_IDR                   0x18    /* Interrupt Disable Register */
  31 #define MCHP_PDMC_IMR                   0x1C    /* Interrupt Mask Register */
  32 #define MCHP_PDMC_ISR                   0x20    /* Interrupt Status Register */
  33 #define MCHP_PDMC_VER                   0x50    /* Version Register */
  34
  35 /*
  36  * ---- Control Register (Write-only) ----
  37  */
  38 #define MCHP_PDMC_CR_SWRST              BIT(0)  /* Software Reset */
  39
  40 /*
  41  * ---- Mode Register (Read/Write) ----
  42  */
  43 #define MCHP_PDMC_MR_PDMCEN_MASK        GENMASK(3, 0)
  44 #define MCHP_PDMC_MR_PDMCEN(ch)         (BIT(ch) & MCHP_PDMC_MR_PDMCEN_MASK)
  45
  46 #define MCHP_PDMC_MR_OSR_MASK           GENMASK(17, 16)
  47 #define MCHP_PDMC_MR_OSR64              (1 << 16)
  48 #define MCHP_PDMC_MR_OSR128             (2 << 16)
  49 #define MCHP_PDMC_MR_OSR256             (3 << 16)
  50
  51 #define MCHP_PDMC_MR_SINCORDER_MASK     GENMASK(23, 20)
  52 #define MCHP_PDMC_MR_SINCORDER(order)   (((order) << 20) & \
  53                                          MCHP_PDMC_MR_SINCORDER_MASK)
  54
  55 #define MCHP_PDMC_MR_SINC_OSR_MASK      GENMASK(27, 24)
  56 #define MCHP_PDMC_MR_SINC_OSR_DIS       (0 << 24)
  57 #define MCHP_PDMC_MR_SINC_OSR_8         (1 << 24)
  58 #define MCHP_PDMC_MR_SINC_OSR_16        (2 << 24)
  59 #define MCHP_PDMC_MR_SINC_OSR_32        (3 << 24)
  60 #define MCHP_PDMC_MR_SINC_OSR_64        (4 << 24)
  61 #define MCHP_PDMC_MR_SINC_OSR_128       (5 << 24)
  62 #define MCHP_PDMC_MR_SINC_OSR_256       (6 << 24)
  63
  64 #define MCHP_PDMC_MR_CHUNK_MASK         GENMASK(31, 28)
  65 #define MCHP_PDMC_MR_CHUNK(chunk)       (((chunk) << 28) & \
  66                                          MCHP_PDMC_MR_CHUNK_MASK)
  67
  68 /*
  69  * ---- Configuration Register (Read/Write) ----
  70  */
  71 #define MCHP_PDMC_CFGR_BSSEL_MASK       (BIT(0) | BIT(2) | BIT(4) | BIT(6))
  72 #define MCHP_PDMC_CFGR_BSSEL(ch)        BIT((ch) * 2)
  73
  74 #define MCHP_PDMC_CFGR_PDMSEL_MASK      (BIT(16) | BIT(18) | BIT(20) | BIT(22))
  75 #define MCHP_PDMC_CFGR_PDMSEL(ch)       BIT((ch) * 2 + 16)
  76
  77 /*
  78  * ---- Interrupt Enable/Disable/Mask/Status Registers ----
  79  */
  80 #define MCHP_PDMC_IR_RXRDY              BIT(0)
  81 #define MCHP_PDMC_IR_RXEMPTY            BIT(1)
  82 #define MCHP_PDMC_IR_RXFULL             BIT(2)
  83 #define MCHP_PDMC_IR_RXCHUNK            BIT(3)
  84 #define MCHP_PDMC_IR_RXUDR              BIT(4)
  85 #define MCHP_PDMC_IR_RXOVR              BIT(5)
  86
  87 /*
  88  * ---- Version Register (Read-only) ----
  89  */
  90 #define MCHP_PDMC_VER_VERSION           GENMASK(11, 0)
  91
  92 #define MCHP_PDMC_MAX_CHANNELS          4
  93 #define MCHP_PDMC_DS_NO                 2
  94 #define MCHP_PDMC_EDGE_NO               2
  95
  96 struct mic_map {
  97         int ds_pos;
  98         int clk_edge;
  99 };
 100
 101 struct mchp_pdmc_chmap {
 102         struct snd_pcm_chmap_elem *chmap;
 103         struct mchp_pdmc *dd;
 104         struct snd_pcm *pcm;
 105         struct snd_kcontrol *kctl;
 106 };
 107
 108 struct mchp_pdmc {
 109         struct mic_map channel_mic_map[MCHP_PDMC_MAX_CHANNELS];
 110         struct device *dev;
 111         struct snd_dmaengine_dai_dma_data addr;
 112         struct regmap *regmap;
 113         struct clk *pclk;
 114         struct clk *gclk;
 115         u32 pdmcen;
 116         u32 suspend_irq;
 117         int mic_no;
 118         int sinc_order;
 119         bool audio_filter_en;
 120 };
 121
 122 static const char *const mchp_pdmc_sinc_filter_order_text[] = {
 123         "1", "2", "3", "4", "5"
 124 };
 125
 126 static const unsigned int mchp_pdmc_sinc_filter_order_values[] = {
 127         1, 2, 3, 4, 5,
 128 };
 129
 130 static const struct soc_enum mchp_pdmc_sinc_filter_order_enum = {
 131         .items = ARRAY_SIZE(mchp_pdmc_sinc_filter_order_text),
 132         .texts = mchp_pdmc_sinc_filter_order_text,
 133         .values = mchp_pdmc_sinc_filter_order_values,
 134 };
 135
 136 static int mchp_pdmc_sinc_order_get(struct snd_kcontrol *kcontrol,
 137                                     struct snd_ctl_elem_value *uvalue)
 138 {
 139         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 140         struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
 141         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 142         unsigned int item;
 143
 144         item = snd_soc_enum_val_to_item(e, dd->sinc_order);
 145         uvalue->value.enumerated.item[0] = item;
 146
 147         return 0;
 148 }
 149
 150 static int mchp_pdmc_sinc_order_put(struct snd_kcontrol *kcontrol,
 151                                     struct snd_ctl_elem_value *uvalue)
 152 {
 153         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 154         struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
 155         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 156         unsigned int *item = uvalue->value.enumerated.item;
 157         unsigned int val;
 158
 159         if (item[0] >= e->items)
 160                 return -EINVAL;
 161
 162         val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
 163         if (val == dd->sinc_order)
 164                 return 0;
 165
 166         dd->sinc_order = val;
 167
 168         return 1;
 169 }
 170
 171 static int mchp_pdmc_af_get(struct snd_kcontrol *kcontrol,
 172                             struct snd_ctl_elem_value *uvalue)
 173 {
 174         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 175         struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
 176
 177         uvalue->value.integer.value[0] = !!dd->audio_filter_en;
 178
 179         return 0;
 180 }
 181
 182 static int mchp_pdmc_af_put(struct snd_kcontrol *kcontrol,
 183                             struct snd_ctl_elem_value *uvalue)
 184 {
 185         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 186         struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
 187         bool af = uvalue->value.integer.value[0] ? true : false;
 188
 189         if (dd->audio_filter_en == af)
 190                 return 0;
 191
 192         dd->audio_filter_en = af;
 193
 194         return 1;
 195 }
 196
 197 static int mchp_pdmc_chmap_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
 198 {
 199         struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
 200
 201         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 202         uinfo->count = info->dd->mic_no;
 203         uinfo->value.integer.min = 0;
 204         uinfo->value.integer.max = SNDRV_CHMAP_RR; /* maxmimum 4 channels */
 205         return 0;
 206 }
 207
 208 static inline struct snd_pcm_substream *
 209 mchp_pdmc_chmap_substream(struct mchp_pdmc_chmap *info, unsigned int idx)
 210 {
 211         struct snd_pcm_substream *s;
 212
 213         for (s = info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; s; s = s->next)
 214                 if (s->number == idx)
 215                         return s;
 216         return NULL;
 217 }
 218
 219 static struct snd_pcm_chmap_elem *mchp_pdmc_chmap_get(struct snd_pcm_substream *substream,
 220                                                       struct mchp_pdmc_chmap *ch_info)
 221 {
 222         struct snd_pcm_chmap_elem *map;
 223
 224         for (map = ch_info->chmap; map->channels; map++) {
 225                 if (map->channels == substream->runtime->channels)
 226                         return map;
 227         }
 228         return NULL;
 229 }
 230
 231 static int mchp_pdmc_chmap_ctl_get(struct snd_kcontrol *kcontrol,
 232                                    struct snd_ctl_elem_value *ucontrol)
 233 {
 234         struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
 235         struct mchp_pdmc *dd = info->dd;
 236         unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
 237         struct snd_pcm_substream *substream;
 238         const struct snd_pcm_chmap_elem *map;
 239         int i;
 240         u32 cfgr_val = 0;
 241
 242         if (!info->chmap)
 243                 return -EINVAL;
 244         substream = mchp_pdmc_chmap_substream(info, idx);
 245         if (!substream)
 246                 return -ENODEV;
 247         memset(ucontrol->value.integer.value, 0, sizeof(long) * info->dd->mic_no);
 248         if (!substream->runtime)
 249                 return 0; /* no channels set */
 250
 251         map = mchp_pdmc_chmap_get(substream, info);
 252         if (!map)
 253                 return -EINVAL;
 254
 255         for (i = 0; i < map->channels; i++) {
 256                 int map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO :
 257                                                    map->map[i] - SNDRV_CHMAP_FL;
 258
 259                 /* make sure the reported channel map is the real one, so write the map */
 260                 if (dd->channel_mic_map[map_idx].ds_pos)
 261                         cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
 262                 if (dd->channel_mic_map[map_idx].clk_edge)
 263                         cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
 264
 265                 ucontrol->value.integer.value[i] = map->map[i];
 266         }
 267
 268         regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val);
 269
 270         return 0;
 271 }
 272
 273 static int mchp_pdmc_chmap_ctl_put(struct snd_kcontrol *kcontrol,
 274                                    struct snd_ctl_elem_value *ucontrol)
 275 {
 276         struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
 277         struct mchp_pdmc *dd = info->dd;
 278         unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
 279         struct snd_pcm_substream *substream;
 280         struct snd_pcm_chmap_elem *map;
 281         u32 cfgr_val = 0;
 282         int i;
 283
 284         if (!info->chmap)
 285                 return -EINVAL;
 286         substream = mchp_pdmc_chmap_substream(info, idx);
 287         if (!substream)
 288                 return -ENODEV;
 289
 290         map = mchp_pdmc_chmap_get(substream, info);
 291         if (!map)
 292                 return -EINVAL;
 293
 294         for (i = 0; i < map->channels; i++) {
 295                 int map_idx;
 296
 297                 map->map[i] = ucontrol->value.integer.value[i];
 298                 map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO :
 299                                                map->map[i] - SNDRV_CHMAP_FL;
 300
 301                 /* configure IP for the desired channel map */
 302                 if (dd->channel_mic_map[map_idx].ds_pos)
 303                         cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
 304                 if (dd->channel_mic_map[map_idx].clk_edge)
 305                         cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
 306         }
 307
 308         regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val);
 309
 310         return 0;
 311 }
 312
 313 static void mchp_pdmc_chmap_ctl_private_free(struct snd_kcontrol *kcontrol)
 314 {
 315         struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
 316
 317         info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = NULL;
 318         kfree(info);
 319 }
 320
 321 static int mchp_pdmc_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
 322                                    unsigned int size, unsigned int __user *tlv)
 323 {
 324         struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
 325         const struct snd_pcm_chmap_elem *map;
 326         unsigned int __user *dst;
 327         int c, count = 0;
 328
 329         if (!info->chmap)
 330                 return -EINVAL;
 331         if (size < 8)
 332                 return -ENOMEM;
 333         if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
 334                 return -EFAULT;
 335         size -= 8;
 336         dst = tlv + 2;
 337         for (map = info->chmap; map->channels; map++) {
 338                 int chs_bytes = map->channels * 4;
 339
 340                 if (size < 8)
 341                         return -ENOMEM;
 342                 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
 343                     put_user(chs_bytes, dst + 1))
 344                         return -EFAULT;
 345                 dst += 2;
 346                 size -= 8;
 347                 count += 8;
 348                 if (size < chs_bytes)
 349                         return -ENOMEM;
 350                 size -= chs_bytes;
 351                 count += chs_bytes;
 352                 for (c = 0; c < map->channels; c++) {
 353                         if (put_user(map->map[c], dst))
 354                                 return -EFAULT;
 355                         dst++;
 356                 }
 357         }
 358         if (put_user(count, tlv + 1))
 359                 return -EFAULT;
 360         return 0;
 361 }
 362
 363 static const struct snd_kcontrol_new mchp_pdmc_snd_controls[] = {
 364         SOC_SINGLE_BOOL_EXT("Audio Filter", 0, &mchp_pdmc_af_get, &mchp_pdmc_af_put),
 365         {
 366                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
 367                 .name = "SINC Filter Order",
 368                 .info = snd_soc_info_enum_double,
 369                 .get = mchp_pdmc_sinc_order_get,
 370                 .put = mchp_pdmc_sinc_order_put,
 371                 .private_value = (unsigned long)&mchp_pdmc_sinc_filter_order_enum,
 372         },
 373 };
 374
 375 static int mchp_pdmc_close(struct snd_soc_component *component,
 376                            struct snd_pcm_substream *substream)
 377 {
 378         return snd_soc_add_component_controls(component, mchp_pdmc_snd_controls,
 379                                               ARRAY_SIZE(mchp_pdmc_snd_controls));
 380 }
 381
 382 static int mchp_pdmc_open(struct snd_soc_component *component,
 383                           struct snd_pcm_substream *substream)
 384 {
 385         int i;
 386
 387         /* remove controls that can't be changed at runtime */
 388         for (i = 0; i < ARRAY_SIZE(mchp_pdmc_snd_controls); i++) {
 389                 const struct snd_kcontrol_new *control = &mchp_pdmc_snd_controls[i];
 390                 struct snd_ctl_elem_id id;
 391                 struct snd_kcontrol *kctl;
 392                 int err;
 393
 394                 if (component->name_prefix)
 395                         snprintf(id.name, sizeof(id.name), "%s %s", component->name_prefix,
 396                                  control->name);
 397                 else
 398                         strscpy(id.name, control->name, sizeof(id.name));
 399
 400                 id.numid = 0;
 401                 id.iface = control->iface;
 402                 id.device = control->device;
 403                 id.subdevice = control->subdevice;
 404                 id.index = control->index;
 405                 kctl = snd_ctl_find_id(component->card->snd_card, &id);
 406                 if (!kctl) {
 407                         dev_err(component->dev, "Failed to find %s\n", control->name);
 408                         continue;
 409                 }
 410                 err = snd_ctl_remove(component->card->snd_card, kctl);
 411                 if (err < 0) {
 412                         dev_err(component->dev, "%d: Failed to remove %s\n", err,
 413                                 control->name);
 414                         continue;
 415                 }
 416         }
 417
 418         return 0;
 419 }
 420
 421 static const struct snd_soc_component_driver mchp_pdmc_dai_component = {
 422         .name = "mchp-pdmc",
 423         .controls = mchp_pdmc_snd_controls,
 424         .num_controls = ARRAY_SIZE(mchp_pdmc_snd_controls),
 425         .open = &mchp_pdmc_open,
 426         .close = &mchp_pdmc_close,
 427         .legacy_dai_naming = 1,
 428 };
 429
 430 static const unsigned int mchp_pdmc_1mic[] = {1};
 431 static const unsigned int mchp_pdmc_2mic[] = {1, 2};
 432 static const unsigned int mchp_pdmc_3mic[] = {1, 2, 3};
 433 static const unsigned int mchp_pdmc_4mic[] = {1, 2, 3, 4};
 434
 435 static const struct snd_pcm_hw_constraint_list mchp_pdmc_chan_constr[] = {
 436         {
 437                 .list = mchp_pdmc_1mic,
 438                 .count = ARRAY_SIZE(mchp_pdmc_1mic),
 439         },
 440         {
 441                 .list = mchp_pdmc_2mic,
 442                 .count = ARRAY_SIZE(mchp_pdmc_2mic),
 443         },
 444         {
 445                 .list = mchp_pdmc_3mic,
 446                 .count = ARRAY_SIZE(mchp_pdmc_3mic),
 447         },
 448         {
 449                 .list = mchp_pdmc_4mic,
 450                 .count = ARRAY_SIZE(mchp_pdmc_4mic),
 451         },
 452 };
 453
 454 static int mchp_pdmc_startup(struct snd_pcm_substream *substream,
 455                              struct snd_soc_dai *dai)
 456 {
 457         struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
 458
 459         regmap_write(dd->regmap, MCHP_PDMC_CR, MCHP_PDMC_CR_SWRST);
 460
 461         snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
 462                                    &mchp_pdmc_chan_constr[dd->mic_no - 1]);
 463
 464         return 0;
 465 }
 466
 467 static int mchp_pdmc_dai_probe(struct snd_soc_dai *dai)
 468 {
 469         struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
 470
 471         snd_soc_dai_init_dma_data(dai, NULL, &dd->addr);
 472
 473         return 0;
 474 }
 475
 476 static int mchp_pdmc_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 477 {
 478         unsigned int fmt_master = fmt & SND_SOC_DAIFMT_MASTER_MASK;
 479         unsigned int fmt_format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 480
 481         /* IP needs to be bitclock master */
 482         if (fmt_master != SND_SOC_DAIFMT_BP_FP &&
 483             fmt_master != SND_SOC_DAIFMT_BP_FC)
 484                 return -EINVAL;
 485
 486         /* IP supports only PDM interface */
 487         if (fmt_format != SND_SOC_DAIFMT_PDM)
 488                 return -EINVAL;
 489
 490         return 0;
 491 }
 492
 493 static u32 mchp_pdmc_mr_set_osr(int audio_filter_en, unsigned int osr)
 494 {
 495         if (audio_filter_en) {
 496                 switch (osr) {
 497                 case 64:
 498                         return MCHP_PDMC_MR_OSR64;
 499                 case 128:
 500                         return MCHP_PDMC_MR_OSR128;
 501                 case 256:
 502                         return MCHP_PDMC_MR_OSR256;
 503                 }
 504         } else {
 505                 switch (osr) {
 506                 case 8:
 507                         return MCHP_PDMC_MR_SINC_OSR_8;
 508                 case 16:
 509                         return MCHP_PDMC_MR_SINC_OSR_16;
 510                 case 32:
 511                         return MCHP_PDMC_MR_SINC_OSR_32;
 512                 case 64:
 513                         return MCHP_PDMC_MR_SINC_OSR_64;
 514                 case 128:
 515                         return MCHP_PDMC_MR_SINC_OSR_128;
 516                 case 256:
 517                         return MCHP_PDMC_MR_SINC_OSR_256;
 518                 }
 519         }
 520         return 0;
 521 }
 522
 523 static inline int mchp_pdmc_period_to_maxburst(int period_size)
 524 {
 525         if (!(period_size % 8))
 526                 return 8;
 527         if (!(period_size % 4))
 528                 return 4;
 529         if (!(period_size % 2))
 530                 return 2;
 531         return 1;
 532 }
 533
 534 static struct snd_pcm_chmap_elem mchp_pdmc_std_chmaps[] = {
 535         { .channels = 1,
 536           .map = { SNDRV_CHMAP_MONO } },
 537         { .channels = 2,
 538           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
 539         { .channels = 3,
 540           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
 541                    SNDRV_CHMAP_RL } },
 542         { .channels = 4,
 543           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
 544                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
 545         { }
 546 };
 547
 548 static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream,
 549                                struct snd_pcm_hw_params *params,
 550                                struct snd_soc_dai *dai)
 551 {
 552         struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
 553         struct snd_soc_component *comp = dai->component;
 554         unsigned long gclk_rate = 0;
 555         unsigned long best_diff_rate = ~0UL;
 556         unsigned int channels = params_channels(params);
 557         unsigned int osr = 0, osr_start;
 558         unsigned int fs = params_rate(params);
 559         u32 mr_val = 0;
 560         u32 cfgr_val = 0;
 561         int i;
 562         int ret;
 563
 564         dev_dbg(comp->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
 565                 __func__, params_rate(params), params_format(params),
 566                 params_width(params), params_channels(params));
 567
 568         if (channels > dd->mic_no) {
 569                 dev_err(comp->dev, "more channels %u than microphones %d\n",
 570                         channels, dd->mic_no);
 571                 return -EINVAL;
 572         }
 573
 574         dd->pdmcen = 0;
 575         for (i = 0; i < channels; i++) {
 576                 dd->pdmcen |= MCHP_PDMC_MR_PDMCEN(i);
 577                 if (dd->channel_mic_map[i].ds_pos)
 578                         cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
 579                 if (dd->channel_mic_map[i].clk_edge)
 580                         cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
 581         }
 582
 583         for (osr_start = dd->audio_filter_en ? 64 : 8;
 584              osr_start <= 256 && best_diff_rate; osr_start *= 2) {
 585                 long round_rate;
 586                 unsigned long diff_rate;
 587
 588                 round_rate = clk_round_rate(dd->gclk,
 589                                             (unsigned long)fs * 16 * osr_start);
 590                 if (round_rate < 0)
 591                         continue;
 592                 diff_rate = abs((fs * 16 * osr_start) - round_rate);
 593                 if (diff_rate < best_diff_rate) {
 594                         best_diff_rate = diff_rate;
 595                         osr = osr_start;
 596                         gclk_rate = fs * 16 * osr;
 597                 }
 598         }
 599         if (!gclk_rate) {
 600                 dev_err(comp->dev, "invalid sampling rate: %u\n", fs);
 601                 return -EINVAL;
 602         }
 603
 604         /* CLK is enabled by runtime PM. */
 605         clk_disable_unprepare(dd->gclk);
 606
 607         /* set the rate */
 608         ret = clk_set_rate(dd->gclk, gclk_rate);
 609         clk_prepare_enable(dd->gclk);
 610         if (ret) {
 611                 dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n",
 612                         gclk_rate, ret);
 613                 return ret;
 614         }
 615
 616         mr_val |= mchp_pdmc_mr_set_osr(dd->audio_filter_en, osr);
 617
 618         mr_val |= MCHP_PDMC_MR_SINCORDER(dd->sinc_order);
 619
 620         dd->addr.maxburst = mchp_pdmc_period_to_maxburst(snd_pcm_lib_period_bytes(substream));
 621         mr_val |= MCHP_PDMC_MR_CHUNK(dd->addr.maxburst);
 622         dev_dbg(comp->dev, "maxburst set to %d\n", dd->addr.maxburst);
 623
 624         snd_soc_component_update_bits(comp, MCHP_PDMC_MR,
 625                                       MCHP_PDMC_MR_OSR_MASK |
 626                                       MCHP_PDMC_MR_SINCORDER_MASK |
 627                                       MCHP_PDMC_MR_SINC_OSR_MASK |
 628                                       MCHP_PDMC_MR_CHUNK_MASK, mr_val);
 629
 630         snd_soc_component_write(comp, MCHP_PDMC_CFGR, cfgr_val);
 631
 632         return 0;
 633 }
 634
 635 static int mchp_pdmc_trigger(struct snd_pcm_substream *substream,
 636                              int cmd, struct snd_soc_dai *dai)
 637 {
 638         struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
 639         struct snd_soc_component *cpu = dai->component;
 640 #ifdef DEBUG
 641         u32 val;
 642 #endif
 643
 644         switch (cmd) {
 645         case SNDRV_PCM_TRIGGER_RESUME:
 646         case SNDRV_PCM_TRIGGER_START:
 647                 /* Enable overrun and underrun error interrupts */
 648                 regmap_write(dd->regmap, MCHP_PDMC_IER, dd->suspend_irq |
 649                              MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR);
 650                 dd->suspend_irq = 0;
 651                 fallthrough;
 652         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 653                 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR,
 654                                               MCHP_PDMC_MR_PDMCEN_MASK,
 655                                               dd->pdmcen);
 656                 break;
 657         case SNDRV_PCM_TRIGGER_SUSPEND:
 658                 regmap_read(dd->regmap, MCHP_PDMC_IMR, &dd->suspend_irq);
 659                 fallthrough;
 660         case SNDRV_PCM_TRIGGER_STOP:
 661                 /* Disable overrun and underrun error interrupts */
 662                 regmap_write(dd->regmap, MCHP_PDMC_IDR, dd->suspend_irq |
 663                              MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR);
 664                 fallthrough;
 665         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 666                 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR,
 667                                               MCHP_PDMC_MR_PDMCEN_MASK, 0);
 668                 break;
 669         default:
 670                 return -EINVAL;
 671         }
 672
 673 #ifdef DEBUG
 674         regmap_read(dd->regmap, MCHP_PDMC_MR, &val);
 675         dev_dbg(dd->dev, "MR (0x%02x): 0x%08x\n", MCHP_PDMC_MR, val);
 676         regmap_read(dd->regmap, MCHP_PDMC_CFGR, &val);
 677         dev_dbg(dd->dev, "CFGR (0x%02x): 0x%08x\n", MCHP_PDMC_CFGR, val);
 678         regmap_read(dd->regmap, MCHP_PDMC_IMR, &val);
 679         dev_dbg(dd->dev, "IMR (0x%02x): 0x%08x\n", MCHP_PDMC_IMR, val);
 680 #endif
 681
 682         return 0;
 683 }
 684
 685 static const struct snd_soc_dai_ops mchp_pdmc_dai_ops = {
 686         .set_fmt        = mchp_pdmc_set_fmt,
 687         .startup        = mchp_pdmc_startup,
 688         .hw_params      = mchp_pdmc_hw_params,
 689         .trigger        = mchp_pdmc_trigger,
 690 };
 691
 692 static int mchp_pdmc_add_chmap_ctls(struct snd_pcm *pcm, struct mchp_pdmc *dd)
 693 {
 694         struct mchp_pdmc_chmap *info;
 695         struct snd_kcontrol_new knew = {
 696                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 697                 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
 698                         SNDRV_CTL_ELEM_ACCESS_TLV_READ |
 699                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK,
 700                 .info = mchp_pdmc_chmap_ctl_info,
 701                 .get = mchp_pdmc_chmap_ctl_get,
 702                 .put = mchp_pdmc_chmap_ctl_put,
 703                 .tlv.c = mchp_pdmc_chmap_ctl_tlv,
 704         };
 705         int err;
 706
 707         if (WARN_ON(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl))
 708                 return -EBUSY;
 709         info = kzalloc(sizeof(*info), GFP_KERNEL);
 710         if (!info)
 711                 return -ENOMEM;
 712         info->pcm = pcm;
 713         info->dd = dd;
 714         info->chmap = mchp_pdmc_std_chmaps;
 715         knew.name = "Capture Channel Map";
 716         knew.device = pcm->device;
 717         knew.count = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream_count;
 718         info->kctl = snd_ctl_new1(&knew, info);
 719         if (!info->kctl) {
 720                 kfree(info);
 721                 return -ENOMEM;
 722         }
 723         info->kctl->private_free = mchp_pdmc_chmap_ctl_private_free;
 724         err = snd_ctl_add(pcm->card, info->kctl);
 725         if (err < 0)
 726                 return err;
 727         pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = info->kctl;
 728         return 0;
 729 }
 730
 731 static int mchp_pdmc_pcm_new(struct snd_soc_pcm_runtime *rtd,
 732                              struct snd_soc_dai *dai)
 733 {
 734         struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
 735         int ret;
 736
 737         ret = mchp_pdmc_add_chmap_ctls(rtd->pcm, dd);
 738         if (ret < 0) {
 739                 dev_err(dd->dev, "failed to add channel map controls: %d\n", ret);
 740                 return ret;
 741         }
 742
 743         return 0;
 744 }
 745
 746 static struct snd_soc_dai_driver mchp_pdmc_dai = {
 747         .probe  = mchp_pdmc_dai_probe,
 748         .capture = {
 749                 .stream_name    = "Capture",
 750                 .channels_min   = 1,
 751                 .channels_max   = 4,
 752                 .rate_min       = 8000,
 753                 .rate_max       = 192000,
 754                 .rates          = SNDRV_PCM_RATE_KNOT,
 755                 .formats        = SNDRV_PCM_FMTBIT_S24_LE,
 756         },
 757         .ops = &mchp_pdmc_dai_ops,
 758         .pcm_new = &mchp_pdmc_pcm_new,
 759 };
 760
 761 /* PDMC interrupt handler */
 762 static irqreturn_t mchp_pdmc_interrupt(int irq, void *dev_id)
 763 {
 764         struct mchp_pdmc *dd = (struct mchp_pdmc *)dev_id;
 765         u32 isr, msr, pending;
 766         irqreturn_t ret = IRQ_NONE;
 767
 768         regmap_read(dd->regmap, MCHP_PDMC_ISR, &isr);
 769         regmap_read(dd->regmap, MCHP_PDMC_IMR, &msr);
 770
 771         pending = isr & msr;
 772         dev_dbg(dd->dev, "ISR (0x%02x): 0x%08x, IMR (0x%02x): 0x%08x, pending: 0x%08x\n",
 773                 MCHP_PDMC_ISR, isr, MCHP_PDMC_IMR, msr, pending);
 774         if (!pending)
 775                 return IRQ_NONE;
 776
 777         if (pending & MCHP_PDMC_IR_RXUDR) {
 778                 dev_warn(dd->dev, "underrun detected\n");
 779                 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXUDR);
 780                 ret = IRQ_HANDLED;
 781         }
 782         if (pending & MCHP_PDMC_IR_RXOVR) {
 783                 dev_warn(dd->dev, "overrun detected\n");
 784                 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXOVR);
 785                 ret = IRQ_HANDLED;
 786         }
 787
 788         return ret;
 789 }
 790
 791 /* regmap configuration */
 792 static bool mchp_pdmc_readable_reg(struct device *dev, unsigned int reg)
 793 {
 794         switch (reg) {
 795         case MCHP_PDMC_MR:
 796         case MCHP_PDMC_CFGR:
 797         case MCHP_PDMC_IMR:
 798         case MCHP_PDMC_ISR:
 799         case MCHP_PDMC_VER:
 800                 return true;
 801         default:
 802                 return false;
 803         }
 804 }
 805
 806 static bool mchp_pdmc_writeable_reg(struct device *dev, unsigned int reg)
 807 {
 808         switch (reg) {
 809         case MCHP_PDMC_CR:
 810         case MCHP_PDMC_MR:
 811         case MCHP_PDMC_CFGR:
 812         case MCHP_PDMC_IER:
 813         case MCHP_PDMC_IDR:
 814                 return true;
 815         default:
 816                 return false;
 817         }
 818 }
 819
 820 static bool mchp_pdmc_precious_reg(struct device *dev, unsigned int reg)
 821 {
 822         switch (reg) {
 823         case MCHP_PDMC_RHR:
 824         case MCHP_PDMC_ISR:
 825                 return true;
 826         default:
 827                 return false;
 828         }
 829 }
 830
 831 static const struct regmap_config mchp_pdmc_regmap_config = {
 832         .reg_bits       = 32,
 833         .reg_stride     = 4,
 834         .val_bits       = 32,
 835         .max_register   = MCHP_PDMC_VER,
 836         .readable_reg   = mchp_pdmc_readable_reg,
 837         .writeable_reg  = mchp_pdmc_writeable_reg,
 838         .precious_reg   = mchp_pdmc_precious_reg,
 839         .cache_type     = REGCACHE_FLAT,
 840 };
 841
 842 static int mchp_pdmc_dt_init(struct mchp_pdmc *dd)
 843 {
 844         struct device_node *np = dd->dev->of_node;
 845         bool mic_ch[MCHP_PDMC_DS_NO][MCHP_PDMC_EDGE_NO] = {0};
 846         int i;
 847         int ret;
 848
 849         if (!np) {
 850                 dev_err(dd->dev, "device node not found\n");
 851                 return -EINVAL;
 852         }
 853
 854         dd->mic_no = of_property_count_u32_elems(np, "microchip,mic-pos");
 855         if (dd->mic_no < 0) {
 856                 dev_err(dd->dev, "failed to get microchip,mic-pos: %d",
 857                         dd->mic_no);
 858                 return dd->mic_no;
 859         }
 860         if (!dd->mic_no || dd->mic_no % 2 ||
 861             dd->mic_no / 2 > MCHP_PDMC_MAX_CHANNELS) {
 862                 dev_err(dd->dev, "invalid array length for microchip,mic-pos: %d",
 863                         dd->mic_no);
 864                 return -EINVAL;
 865         }
 866
 867         dd->mic_no /= 2;
 868
 869         dev_info(dd->dev, "%d PDM microphones declared\n", dd->mic_no);
 870
 871         /*
 872          * by default, we consider the order of microphones in
 873          * microchip,mic-pos to be the same with the channel mapping;
 874          * 1st microphone channel 0, 2nd microphone channel 1, etc.
 875          */
 876         for (i = 0; i < dd->mic_no; i++) {
 877                 int ds;
 878                 int edge;
 879
 880                 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2,
 881                                                  &ds);
 882                 if (ret) {
 883                         dev_err(dd->dev,
 884                                 "failed to get value no %d value from microchip,mic-pos: %d",
 885                                 i * 2, ret);
 886                         return ret;
 887                 }
 888                 if (ds >= MCHP_PDMC_DS_NO) {
 889                         dev_err(dd->dev,
 890                                 "invalid DS index in microchip,mic-pos array: %d",
 891                                 ds);
 892                         return -EINVAL;
 893                 }
 894
 895                 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2 + 1,
 896                                                  &edge);
 897                 if (ret) {
 898                         dev_err(dd->dev,
 899                                 "failed to get value no %d value from microchip,mic-pos: %d",
 900                                 i * 2 + 1, ret);
 901                         return ret;
 902                 }
 903
 904                 if (edge != MCHP_PDMC_CLK_POSITIVE &&
 905                     edge != MCHP_PDMC_CLK_NEGATIVE) {
 906                         dev_err(dd->dev,
 907                                 "invalid edge in microchip,mic-pos array: %d", edge);
 908                         return -EINVAL;
 909                 }
 910                 if (mic_ch[ds][edge]) {
 911                         dev_err(dd->dev,
 912                                 "duplicated mic (DS %d, edge %d) in microchip,mic-pos array",
 913                                 ds, edge);
 914                         return -EINVAL;
 915                 }
 916                 mic_ch[ds][edge] = true;
 917                 dd->channel_mic_map[i].ds_pos = ds;
 918                 dd->channel_mic_map[i].clk_edge = edge;
 919         }
 920
 921         return 0;
 922 }
 923
 924 /* used to clean the channel index found on RHR's MSB */
 925 static int mchp_pdmc_process(struct snd_pcm_substream *substream,
 926                              int channel, unsigned long hwoff,
 927                              void *buf, unsigned long bytes)
 928 {
 929         struct snd_pcm_runtime *runtime = substream->runtime;
 930         u8 *dma_ptr = runtime->dma_area + hwoff +
 931                       channel * (runtime->dma_bytes / runtime->channels);
 932         u8 *dma_ptr_end = dma_ptr + bytes;
 933         unsigned int sample_size = samples_to_bytes(runtime, 1);
 934
 935         for (; dma_ptr < dma_ptr_end; dma_ptr += sample_size)
 936                 *dma_ptr = 0;
 937
 938         return 0;
 939 }
 940
 941 static struct snd_dmaengine_pcm_config mchp_pdmc_config = {
 942         .process = mchp_pdmc_process,
 943         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
 944 };
 945
 946 static int mchp_pdmc_runtime_suspend(struct device *dev)
 947 {
 948         struct mchp_pdmc *dd = dev_get_drvdata(dev);
 949
 950         regcache_cache_only(dd->regmap, true);
 951
 952         clk_disable_unprepare(dd->gclk);
 953         clk_disable_unprepare(dd->pclk);
 954
 955         return 0;
 956 }
 957
 958 static int mchp_pdmc_runtime_resume(struct device *dev)
 959 {
 960         struct mchp_pdmc *dd = dev_get_drvdata(dev);
 961         int ret;
 962
 963         ret = clk_prepare_enable(dd->pclk);
 964         if (ret) {
 965                 dev_err(dd->dev,
 966                         "failed to enable the peripheral clock: %d\n", ret);
 967                 return ret;
 968         }
 969         ret = clk_prepare_enable(dd->gclk);
 970         if (ret) {
 971                 dev_err(dd->dev,
 972                         "failed to enable generic clock: %d\n", ret);
 973                 goto disable_pclk;
 974         }
 975
 976         regcache_cache_only(dd->regmap, false);
 977         regcache_mark_dirty(dd->regmap);
 978         ret = regcache_sync(dd->regmap);
 979         if (ret) {
 980                 regcache_cache_only(dd->regmap, true);
 981                 clk_disable_unprepare(dd->gclk);
 982 disable_pclk:
 983                 clk_disable_unprepare(dd->pclk);
 984         }
 985
 986         return ret;
 987 }
 988
 989 static int mchp_pdmc_probe(struct platform_device *pdev)
 990 {
 991         struct device *dev = &pdev->dev;
 992         struct mchp_pdmc *dd;
 993         struct resource *res;
 994         void __iomem *io_base;
 995         u32 version;
 996         int irq;
 997         int ret;
 998
 999         dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL);
1000         if (!dd)
1001                 return -ENOMEM;
1002
1003         dd->dev = &pdev->dev;
1004         ret = mchp_pdmc_dt_init(dd);
1005         if (ret < 0)
1006                 return ret;
1007
1008         irq = platform_get_irq(pdev, 0);
1009         if (irq < 0)
1010                 return irq;
1011
1012         dd->pclk = devm_clk_get(dev, "pclk");
1013         if (IS_ERR(dd->pclk)) {
1014                 ret = PTR_ERR(dd->pclk);
1015                 dev_err(dev, "failed to get peripheral clock: %d\n", ret);
1016                 return ret;
1017         }
1018
1019         dd->gclk = devm_clk_get(dev, "gclk");
1020         if (IS_ERR(dd->gclk)) {
1021                 ret = PTR_ERR(dd->gclk);
1022                 dev_err(dev, "failed to get GCK: %d\n", ret);
1023                 return ret;
1024         }
1025
1026         io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1027         if (IS_ERR(io_base)) {
1028                 ret = PTR_ERR(io_base);
1029                 dev_err(dev, "failed to remap register memory: %d\n", ret);
1030                 return ret;
1031         }
1032
1033         dd->regmap = devm_regmap_init_mmio(dev, io_base,
1034                                            &mchp_pdmc_regmap_config);
1035         if (IS_ERR(dd->regmap)) {
1036                 ret = PTR_ERR(dd->regmap);
1037                 dev_err(dev, "failed to init register map: %d\n", ret);
1038                 return ret;
1039         }
1040
1041         ret = devm_request_irq(dev, irq, mchp_pdmc_interrupt, 0,
1042                                dev_name(&pdev->dev), (void *)dd);
1043         if (ret < 0) {
1044                 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
1045                         irq, ret);
1046                 return ret;
1047         }
1048
1049         /* by default audio filter is enabled and the SINC Filter order
1050          * will be set to the recommended value, 3
1051          */
1052         dd->audio_filter_en = true;
1053         dd->sinc_order = 3;
1054
1055         dd->addr.addr = (dma_addr_t)res->start + MCHP_PDMC_RHR;
1056         platform_set_drvdata(pdev, dd);
1057
1058         pm_runtime_enable(dd->dev);
1059         if (!pm_runtime_enabled(dd->dev)) {
1060                 ret = mchp_pdmc_runtime_resume(dd->dev);
1061                 if (ret)
1062                         return ret;
1063         }
1064
1065         /* register platform */
1066         ret = devm_snd_dmaengine_pcm_register(dev, &mchp_pdmc_config, 0);
1067         if (ret) {
1068                 dev_err(dev, "could not register platform: %d\n", ret);
1069                 goto pm_runtime_suspend;
1070         }
1071
1072         ret = devm_snd_soc_register_component(dev, &mchp_pdmc_dai_component,
1073                                               &mchp_pdmc_dai, 1);
1074         if (ret) {
1075                 dev_err(dev, "could not register CPU DAI: %d\n", ret);
1076                 goto pm_runtime_suspend;
1077         }
1078
1079         /* print IP version */
1080         regmap_read(dd->regmap, MCHP_PDMC_VER, &version);
1081         dev_info(dd->dev, "hw version: %#lx\n",
1082                  version & MCHP_PDMC_VER_VERSION);
1083
1084         return 0;
1085
1086 pm_runtime_suspend:
1087         if (!pm_runtime_status_suspended(dd->dev))
1088                 mchp_pdmc_runtime_suspend(dd->dev);
1089         pm_runtime_disable(dd->dev);
1090
1091         return ret;
1092 }
1093
1094 static int mchp_pdmc_remove(struct platform_device *pdev)
1095 {
1096         struct mchp_pdmc *dd = platform_get_drvdata(pdev);
1097
1098         if (!pm_runtime_status_suspended(dd->dev))
1099                 mchp_pdmc_runtime_suspend(dd->dev);
1100
1101         pm_runtime_disable(dd->dev);
1102
1103         return 0;
1104 }
1105
1106 static const struct of_device_id mchp_pdmc_of_match[] = {
1107         {
1108                 .compatible = "microchip,sama7g5-pdmc",
1109         }, {
1110                 /* sentinel */
1111         }
1112 };
1113 MODULE_DEVICE_TABLE(of, mchp_pdmc_of_match);
1114
1115 static const struct dev_pm_ops mchp_pdmc_pm_ops = {
1116         SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1117         RUNTIME_PM_OPS(mchp_pdmc_runtime_suspend, mchp_pdmc_runtime_resume,
1118                        NULL)
1119 };
1120
1121 static struct platform_driver mchp_pdmc_driver = {
1122         .driver = {
1123                 .name           = "mchp-pdmc",
1124                 .of_match_table = of_match_ptr(mchp_pdmc_of_match),
1125                 .pm             = pm_ptr(&mchp_pdmc_pm_ops),
1126         },
1127         .probe  = mchp_pdmc_probe,
1128         .remove = mchp_pdmc_remove,
1129 };
1130 module_platform_driver(mchp_pdmc_driver);
1131
1132 MODULE_DESCRIPTION("Microchip PDMC driver under ALSA SoC architecture");
1133 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");
1134 MODULE_LICENSE("GPL v2");