2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
4 * Copyright (c) 2003 Winfried Ritsch (IEM)
5 * code based on hdsp.c Paul Davis
8 * Modified 2006-06-01 for AES32 support by Remy Bruno
9 * <remy.bruno@trinnov.com>
11 * Modified 2009-04-13 for proper metering by Florian Faber
14 * Modified 2009-04-14 for native float support by Florian Faber
17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
20 * Modified 2009-04-30 added hw serial number support by Florian Faber
22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/module.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/math64.h>
50 #include <sound/core.h>
51 #include <sound/control.h>
52 #include <sound/pcm.h>
53 #include <sound/pcm_params.h>
54 #include <sound/info.h>
55 #include <sound/asoundef.h>
56 #include <sound/rawmidi.h>
57 #include <sound/hwdep.h>
58 #include <sound/initval.h>
60 #include <sound/hdspm.h>
62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
69 module_param_array(id, charp, NULL, 0444);
70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
78 "Winfried Ritsch <ritsch_AT_iem.at>, "
79 "Paul Davis <paul@linuxaudiosystems.com>, "
80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
81 "Remy Bruno <remy.bruno@trinnov.com>, "
82 "Florian Faber <faberman@linuxproaudio.org>, "
83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
85 MODULE_DESCRIPTION("RME HDSPM");
86 MODULE_LICENSE("GPL");
87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
89 /* --- Write registers. ---
90 These are defined as byte-offsets from the iobase value. */
92 #define HDSPM_WR_SETTINGS 0
93 #define HDSPM_outputBufferAddress 32
94 #define HDSPM_inputBufferAddress 36
95 #define HDSPM_controlRegister 64
96 #define HDSPM_interruptConfirmation 96
97 #define HDSPM_control2Reg 256 /* not in specs ???????? */
98 #define HDSPM_freqReg 256 /* for AES32 */
99 #define HDSPM_midiDataOut0 352 /* just believe in old code */
100 #define HDSPM_midiDataOut1 356
101 #define HDSPM_eeprom_wr 384 /* for AES32 */
103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut 8192
110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
116 /* --- Read registers. ---
117 These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister 0
119 /*#define HDSPM_statusRegister2 96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121 * offset 192, for AES32 *and* MADI
122 * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2 192
124 #define HDSPM_timecodeRegister 128
127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192
132 #define HDSPM_RD_TCO 256
133 #define HDSPM_RD_PLL_FREQ 512
134 #define HDSPM_WR_TCO 128
136 #define HDSPM_TCO1_TCO_lock 0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
144 #define HDSPM_TCO1_set_TC 0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800
149 #define HDSPM_TCO2_TC_run 0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
154 #define HDSPM_TCO2_set_jam_sync 0x00200000
155 #define HDSPM_TCO2_set_flywheel 0x00400000
157 #define HDSPM_TCO2_set_01_4 0x01000000
158 #define HDSPM_TCO2_set_pull_down 0x02000000
159 #define HDSPM_TCO2_set_pull_up 0x04000000
160 #define HDSPM_TCO2_set_freq 0x08000000
161 #define HDSPM_TCO2_set_term_75R 0x10000000
162 #define HDSPM_TCO2_set_input_LSB 0x20000000
163 #define HDSPM_TCO2_set_input_MSB 0x40000000
164 #define HDSPM_TCO2_set_freq_from_app 0x80000000
167 #define HDSPM_midiDataOut0 352
168 #define HDSPM_midiDataOut1 356
169 #define HDSPM_midiDataOut2 368
171 #define HDSPM_midiDataIn0 360
172 #define HDSPM_midiDataIn1 364
173 #define HDSPM_midiDataIn2 372
174 #define HDSPM_midiDataIn3 376
176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0 384
178 #define HDSPM_midiStatusOut1 388
179 #define HDSPM_midiStatusOut2 400
181 #define HDSPM_midiStatusIn0 392
182 #define HDSPM_midiStatusIn1 396
183 #define HDSPM_midiStatusIn2 404
184 #define HDSPM_midiStatusIn3 408
187 /* the meters are regular i/o-mapped registers, but offset
188 considerably from the rest. the peak registers are reset
189 when read; the least-significant 4 bits are full-scale counters;
190 the actual peak value is in the most-significant 24 bits.
193 #define HDSPM_MADI_INPUT_PEAK 4096
194 #define HDSPM_MADI_PLAYBACK_PEAK 4352
195 #define HDSPM_MADI_OUTPUT_PEAK 4608
197 #define HDSPM_MADI_INPUT_RMS_L 6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400
199 #define HDSPM_MADI_OUTPUT_RMS_L 6656
201 #define HDSPM_MADI_INPUT_RMS_H 7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424
203 #define HDSPM_MADI_OUTPUT_RMS_H 7680
205 /* --- Control Register bits --------- */
206 #define HDSPM_Start (1<<0) /* start engine */
208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1 (1<<2) /* where n is defined */
210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings
214 register [RayDAT, AIO] */
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
225 56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
229 0=off, 1=on */ /* MADI ONLY */
230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
237 #define HDSPM_SyncRef2 (1<<13)
238 #define HDSPM_SyncRef3 (1<<25)
240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
242 AES additional bits in
243 lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT 0x2000000
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
259 #define HDSPM_wclk_sel (1<<30)
261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical 0
267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269 HDSPM_SyncRef2|HDSPM_SyncRef3)
271 #define HDSPM_c0_SyncRef0 0x2
272 #define HDSPM_c0_SyncRef1 0x4
273 #define HDSPM_c0_SyncRef2 0x8
274 #define HDSPM_c0_SyncRef3 0x10
275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO 2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3
283 #define HDSPM_Frequency32KHz HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK 1
299 #define HDSPM_SYNC_CHECK_SYNC 2
301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD 0
303 #define HDSPM_AUTOSYNC_FROM_MADI 1
304 #define HDSPM_AUTOSYNC_FROM_TCO 2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
306 #define HDSPM_AUTOSYNC_FROM_NONE 4
308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0 /* optical */
310 #define HDSPM_COAXIAL 1 /* BNC */
312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
318 /* --- control2 register bits --- */
319 #define HDSPM_TMS (1<<0)
320 #define HDSPM_TCK (1<<1)
321 #define HDSPM_TDI (1<<2)
322 #define HDSPM_JTAG (1<<3)
323 #define HDSPM_PWDN (1<<4)
324 #define HDSPM_PROGRAM (1<<5)
325 #define HDSPM_CONFIG_MODE_0 (1<<6)
326 #define HDSPM_CONFIG_MODE_1 (1<<7)
327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE (1<<9)
329 #define HDSPM_RD_MULTIPLE (1<<10)
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332 that do not conflict with specific bits for AES32 seem to be valid also
335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */
344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351 /* since 64byte accurate, last 6 bits are not used */
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
365 #define HDSPM_tco_detect 0x08000000
366 #define HDSPM_tco_lock 0x20000000
368 #define HDSPM_s2_tco_detect 0x00000040
369 #define HDSPM_s2_AEBO_D 0x00000080
370 #define HDSPM_s2_AEBI_D 0x00000100
373 #define HDSPM_midi0IRQPending 0x40000000
374 #define HDSPM_midi1IRQPending 0x80000000
375 #define HDSPM_midi2IRQPending 0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending 0x00200000
379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381 HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
392 /* Status2 Register bits */ /* MADI ONLY */
394 #define HDSPM_version0 (1<<0) /* not really defined but I guess */
395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2)
398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */
404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */
406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000
409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0)
417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2)
420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
423 #define HDSPM_status1_F_0 0x0400000
424 #define HDSPM_status1_F_1 0x0800000
425 #define HDSPM_status1_F_2 0x1000000
426 #define HDSPM_status1_F_3 0x2000000
427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
432 #define HDSPM_SelSyncRef_WORD 0
433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
440 For AES32, bits for status, status2 and timecode are different
443 #define HDSPM_AES32_wcLock 0x0200000
444 #define HDSPM_AES32_wcFreq_bit 22
445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
447 #define HDSPM_AES32_syncref_bit 16
448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
463 #define HDSPM_LockAES 0x80
464 #define HDSPM_LockAES1 0x80
465 #define HDSPM_LockAES2 0x40
466 #define HDSPM_LockAES3 0x20
467 #define HDSPM_LockAES4 0x10
468 #define HDSPM_LockAES5 0x8
469 #define HDSPM_LockAES6 0x4
470 #define HDSPM_LockAES7 0x2
471 #define HDSPM_LockAES8 0x1
474 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
486 NB: Timecode register doesn't seem to work on AES32 card revision 230
490 #define UNITY_GAIN 32768 /* = 65536/2 */
491 #define MINUS_INFINITY_GAIN 0
493 /* Number of channels for different Speed Modes */
494 #define MADI_SS_CHANNELS 64
495 #define MADI_DS_CHANNELS 32
496 #define MADI_QS_CHANNELS 16
498 #define RAYDAT_SS_CHANNELS 36
499 #define RAYDAT_DS_CHANNELS 20
500 #define RAYDAT_QS_CHANNELS 12
502 #define AIO_IN_SS_CHANNELS 14
503 #define AIO_IN_DS_CHANNELS 10
504 #define AIO_IN_QS_CHANNELS 8
505 #define AIO_OUT_SS_CHANNELS 16
506 #define AIO_OUT_DS_CHANNELS 12
507 #define AIO_OUT_QS_CHANNELS 10
509 #define AES32_CHANNELS 16
511 /* the size of a substream (1 mono data stream) */
512 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
513 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
515 /* the size of the area we need to allocate for DMA transfers. the
516 size is the same regardless of the number of channels, and
517 also the latency to use.
518 for one direction !!!
520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
523 #define HDSPM_RAYDAT_REV 211
524 #define HDSPM_AIO_REV 212
525 #define HDSPM_MADIFACE_REV 213
527 /* speed factor modes */
528 #define HDSPM_SPEED_SINGLE 0
529 #define HDSPM_SPEED_DOUBLE 1
530 #define HDSPM_SPEED_QUAD 2
532 /* names for speed modes */
533 static char *hdspm_speed_names[] = { "single", "double", "quad" };
535 static char *texts_autosync_aes_tco[] = { "Word Clock",
536 "AES1", "AES2", "AES3", "AES4",
537 "AES5", "AES6", "AES7", "AES8",
539 static char *texts_autosync_aes[] = { "Word Clock",
540 "AES1", "AES2", "AES3", "AES4",
541 "AES5", "AES6", "AES7", "AES8" };
542 static char *texts_autosync_madi_tco[] = { "Word Clock",
543 "MADI", "TCO", "Sync In" };
544 static char *texts_autosync_madi[] = { "Word Clock",
547 static char *texts_autosync_raydat_tco[] = {
549 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
550 "AES", "SPDIF", "TCO", "Sync In"
552 static char *texts_autosync_raydat[] = {
554 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
555 "AES", "SPDIF", "Sync In"
557 static char *texts_autosync_aio_tco[] = {
559 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
561 static char *texts_autosync_aio[] = { "Word Clock",
562 "ADAT", "AES", "SPDIF", "Sync In" };
564 static char *texts_freq[] = {
577 static char *texts_ports_madi[] = {
578 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
579 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
580 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
581 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
582 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
583 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
584 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
585 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
586 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
587 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
588 "MADI.61", "MADI.62", "MADI.63", "MADI.64",
592 static char *texts_ports_raydat_ss[] = {
593 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
594 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
595 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
596 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
597 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
598 "ADAT4.7", "ADAT4.8",
603 static char *texts_ports_raydat_ds[] = {
604 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
605 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
606 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
607 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
612 static char *texts_ports_raydat_qs[] = {
613 "ADAT1.1", "ADAT1.2",
614 "ADAT2.1", "ADAT2.2",
615 "ADAT3.1", "ADAT3.2",
616 "ADAT4.1", "ADAT4.2",
622 static char *texts_ports_aio_in_ss[] = {
623 "Analogue.L", "Analogue.R",
625 "SPDIF.L", "SPDIF.R",
626 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
630 static char *texts_ports_aio_out_ss[] = {
631 "Analogue.L", "Analogue.R",
633 "SPDIF.L", "SPDIF.R",
634 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
639 static char *texts_ports_aio_in_ds[] = {
640 "Analogue.L", "Analogue.R",
642 "SPDIF.L", "SPDIF.R",
643 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
646 static char *texts_ports_aio_out_ds[] = {
647 "Analogue.L", "Analogue.R",
649 "SPDIF.L", "SPDIF.R",
650 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
654 static char *texts_ports_aio_in_qs[] = {
655 "Analogue.L", "Analogue.R",
657 "SPDIF.L", "SPDIF.R",
658 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
661 static char *texts_ports_aio_out_qs[] = {
662 "Analogue.L", "Analogue.R",
664 "SPDIF.L", "SPDIF.R",
665 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
669 static char *texts_ports_aes32[] = {
670 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
671 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
675 /* These tables map the ALSA channels 1..N to the channels that we
676 need to use in order to find the relevant channel buffer. RME
677 refers to this kind of mapping as between "the ADAT channel and
678 the DMA channel." We index it using the logical audio channel,
679 and the value is the DMA channel (i.e. channel buffer number)
680 where the data for that channel can be read/written from/to.
683 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
684 0, 1, 2, 3, 4, 5, 6, 7,
685 8, 9, 10, 11, 12, 13, 14, 15,
686 16, 17, 18, 19, 20, 21, 22, 23,
687 24, 25, 26, 27, 28, 29, 30, 31,
688 32, 33, 34, 35, 36, 37, 38, 39,
689 40, 41, 42, 43, 44, 45, 46, 47,
690 48, 49, 50, 51, 52, 53, 54, 55,
691 56, 57, 58, 59, 60, 61, 62, 63
694 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
695 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
696 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
697 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
698 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
702 -1, -1, -1, -1, -1, -1, -1, -1,
703 -1, -1, -1, -1, -1, -1, -1, -1,
704 -1, -1, -1, -1, -1, -1, -1, -1,
707 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
708 4, 5, 6, 7, /* ADAT 1 */
709 8, 9, 10, 11, /* ADAT 2 */
710 12, 13, 14, 15, /* ADAT 3 */
711 16, 17, 18, 19, /* ADAT 4 */
715 -1, -1, -1, -1, -1, -1, -1, -1,
716 -1, -1, -1, -1, -1, -1, -1, -1,
717 -1, -1, -1, -1, -1, -1, -1, -1,
718 -1, -1, -1, -1, -1, -1, -1, -1,
719 -1, -1, -1, -1, -1, -1, -1, -1,
722 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
730 -1, -1, -1, -1, -1, -1, -1, -1,
731 -1, -1, -1, -1, -1, -1, -1, -1,
732 -1, -1, -1, -1, -1, -1, -1, -1,
733 -1, -1, -1, -1, -1, -1, -1, -1,
734 -1, -1, -1, -1, -1, -1, -1, -1,
735 -1, -1, -1, -1, -1, -1, -1, -1,
738 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
741 10, 11, /* spdif in */
742 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
744 -1, -1, -1, -1, -1, -1, -1, -1,
745 -1, -1, -1, -1, -1, -1, -1, -1,
746 -1, -1, -1, -1, -1, -1, -1, -1,
747 -1, -1, -1, -1, -1, -1, -1, -1,
748 -1, -1, -1, -1, -1, -1, -1, -1,
749 -1, -1, -1, -1, -1, -1, -1, -1,
752 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
755 10, 11, /* spdif out */
756 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
757 6, 7, /* phone out */
758 -1, -1, -1, -1, -1, -1, -1, -1,
759 -1, -1, -1, -1, -1, -1, -1, -1,
760 -1, -1, -1, -1, -1, -1, -1, -1,
761 -1, -1, -1, -1, -1, -1, -1, -1,
762 -1, -1, -1, -1, -1, -1, -1, -1,
763 -1, -1, -1, -1, -1, -1, -1, -1,
766 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
769 10, 11, /* spdif in */
770 12, 14, 16, 18, /* adat in */
771 -1, -1, -1, -1, -1, -1,
772 -1, -1, -1, -1, -1, -1, -1, -1,
773 -1, -1, -1, -1, -1, -1, -1, -1,
774 -1, -1, -1, -1, -1, -1, -1, -1,
775 -1, -1, -1, -1, -1, -1, -1, -1,
776 -1, -1, -1, -1, -1, -1, -1, -1,
777 -1, -1, -1, -1, -1, -1, -1, -1
780 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
783 10, 11, /* spdif out */
784 12, 14, 16, 18, /* adat out */
785 6, 7, /* phone out */
787 -1, -1, -1, -1, -1, -1, -1, -1,
788 -1, -1, -1, -1, -1, -1, -1, -1,
789 -1, -1, -1, -1, -1, -1, -1, -1,
790 -1, -1, -1, -1, -1, -1, -1, -1,
791 -1, -1, -1, -1, -1, -1, -1, -1,
792 -1, -1, -1, -1, -1, -1, -1, -1
795 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
798 10, 11, /* spdif in */
799 12, 16, /* adat in */
800 -1, -1, -1, -1, -1, -1, -1, -1,
801 -1, -1, -1, -1, -1, -1, -1, -1,
802 -1, -1, -1, -1, -1, -1, -1, -1,
803 -1, -1, -1, -1, -1, -1, -1, -1,
804 -1, -1, -1, -1, -1, -1, -1, -1,
805 -1, -1, -1, -1, -1, -1, -1, -1,
806 -1, -1, -1, -1, -1, -1, -1, -1
809 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
812 10, 11, /* spdif out */
813 12, 16, /* adat out */
814 6, 7, /* phone out */
815 -1, -1, -1, -1, -1, -1,
816 -1, -1, -1, -1, -1, -1, -1, -1,
817 -1, -1, -1, -1, -1, -1, -1, -1,
818 -1, -1, -1, -1, -1, -1, -1, -1,
819 -1, -1, -1, -1, -1, -1, -1, -1,
820 -1, -1, -1, -1, -1, -1, -1, -1,
821 -1, -1, -1, -1, -1, -1, -1, -1
824 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
825 0, 1, 2, 3, 4, 5, 6, 7,
826 8, 9, 10, 11, 12, 13, 14, 15,
827 -1, -1, -1, -1, -1, -1, -1, -1,
828 -1, -1, -1, -1, -1, -1, -1, -1,
829 -1, -1, -1, -1, -1, -1, -1, -1,
830 -1, -1, -1, -1, -1, -1, -1, -1,
831 -1, -1, -1, -1, -1, -1, -1, -1,
832 -1, -1, -1, -1, -1, -1, -1, -1
838 struct snd_rawmidi *rmidi;
839 struct snd_rawmidi_substream *input;
840 struct snd_rawmidi_substream *output;
841 char istimer; /* timer in use */
842 struct timer_list timer;
859 int term; /* 0 = off, 1 = on */
864 /* only one playback and/or capture stream */
865 struct snd_pcm_substream *capture_substream;
866 struct snd_pcm_substream *playback_substream;
868 char *card_name; /* for procinfo */
869 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
873 int monitor_outs; /* set up monitoring outs init flag */
875 u32 control_register; /* cached value */
876 u32 control2_register; /* cached value */
877 u32 settings_register;
879 struct hdspm_midi midi[4];
880 struct tasklet_struct midi_tasklet;
883 unsigned char ss_in_channels;
884 unsigned char ds_in_channels;
885 unsigned char qs_in_channels;
886 unsigned char ss_out_channels;
887 unsigned char ds_out_channels;
888 unsigned char qs_out_channels;
890 unsigned char max_channels_in;
891 unsigned char max_channels_out;
893 signed char *channel_map_in;
894 signed char *channel_map_out;
896 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
897 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
899 char **port_names_in;
900 char **port_names_out;
902 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
903 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
905 unsigned char *playback_buffer; /* suitably aligned address */
906 unsigned char *capture_buffer; /* suitably aligned address */
908 pid_t capture_pid; /* process id which uses capture */
909 pid_t playback_pid; /* process id which uses capture */
910 int running; /* running status */
912 int last_external_sample_rate; /* samplerate mystic ... */
913 int last_internal_sample_rate;
914 int system_sample_rate;
916 int dev; /* Hardware vars... */
919 void __iomem *iobase;
921 int irq_count; /* for debug */
924 struct snd_card *card; /* one card */
925 struct snd_pcm *pcm; /* has one pcm */
926 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
927 struct pci_dev *pci; /* and an pci info */
930 /* fast alsa mixer */
931 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
932 /* but input to much, so not used */
933 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
934 /* full mixer accessible over mixer ioctl or hwdep-device */
935 struct hdspm_mixer *mixer;
937 struct hdspm_tco *tco; /* NULL if no TCO detected */
939 char **texts_autosync;
940 int texts_autosync_items;
942 cycles_t last_interrupt;
946 struct hdspm_peak_rms peak_rms;
950 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
952 .vendor = PCI_VENDOR_ID_XILINX,
953 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
954 .subvendor = PCI_ANY_ID,
955 .subdevice = PCI_ANY_ID,
962 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
965 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
966 struct hdspm * hdspm);
967 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
968 struct hdspm * hdspm);
970 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
971 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
972 static int hdspm_autosync_ref(struct hdspm *hdspm);
973 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
974 static int hdspm_system_clock_mode(struct hdspm *hdspm);
975 static void hdspm_set_sgbuf(struct hdspm *hdspm,
976 struct snd_pcm_substream *substream,
977 unsigned int reg, int channels);
979 static inline int HDSPM_bit2freq(int n)
981 static const int bit2freq_tab[] = {
982 0, 32000, 44100, 48000, 64000, 88200,
983 96000, 128000, 176400, 192000 };
986 return bit2freq_tab[n];
989 /* Write/read to/from HDSPM with Adresses in Bytes
990 not words but only 32Bit writes are allowed */
992 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
995 writel(val, hdspm->iobase + reg);
998 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1000 return readl(hdspm->iobase + reg);
1003 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1004 mixer is write only on hardware so we have to cache him for read
1005 each fader is a u32, but uses only the first 16 bit */
1007 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1010 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1013 return hdspm->mixer->ch[chan].in[in];
1016 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1019 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1021 return hdspm->mixer->ch[chan].pb[pb];
1024 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1025 unsigned int in, unsigned short data)
1027 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1031 HDSPM_MADI_mixerBase +
1032 ((in + 128 * chan) * sizeof(u32)),
1033 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1037 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1038 unsigned int pb, unsigned short data)
1040 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1044 HDSPM_MADI_mixerBase +
1045 ((64 + pb + 128 * chan) * sizeof(u32)),
1046 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1051 /* enable DMA for specific channels, now available for DSP-MADI */
1052 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1054 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1057 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1059 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1062 /* check if same process is writing and reading */
1063 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1065 unsigned long flags;
1068 spin_lock_irqsave(&hdspm->lock, flags);
1069 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1070 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1073 spin_unlock_irqrestore(&hdspm->lock, flags);
1077 /* check for external sample rate */
1078 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1080 unsigned int status, status2, timecode;
1081 int syncref, rate = 0, rate_bits;
1083 switch (hdspm->io_type) {
1085 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1086 status = hdspm_read(hdspm, HDSPM_statusRegister);
1087 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1089 syncref = hdspm_autosync_ref(hdspm);
1091 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1092 status & HDSPM_AES32_wcLock)
1093 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1095 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1096 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1097 status2 & (HDSPM_LockAES >>
1098 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1099 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1104 status = hdspm_read(hdspm, HDSPM_statusRegister);
1106 if (!(status & HDSPM_madiLock)) {
1107 rate = 0; /* no lock */
1109 switch (status & (HDSPM_status1_freqMask)) {
1110 case HDSPM_status1_F_0*1:
1111 rate = 32000; break;
1112 case HDSPM_status1_F_0*2:
1113 rate = 44100; break;
1114 case HDSPM_status1_F_0*3:
1115 rate = 48000; break;
1116 case HDSPM_status1_F_0*4:
1117 rate = 64000; break;
1118 case HDSPM_status1_F_0*5:
1119 rate = 88200; break;
1120 case HDSPM_status1_F_0*6:
1121 rate = 96000; break;
1122 case HDSPM_status1_F_0*7:
1123 rate = 128000; break;
1124 case HDSPM_status1_F_0*8:
1125 rate = 176400; break;
1126 case HDSPM_status1_F_0*9:
1127 rate = 192000; break;
1138 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1139 status = hdspm_read(hdspm, HDSPM_statusRegister);
1142 /* if wordclock has synced freq and wordclock is valid */
1143 if ((status2 & HDSPM_wcLock) != 0 &&
1144 (status2 & HDSPM_SelSyncRef0) == 0) {
1146 rate_bits = status2 & HDSPM_wcFreqMask;
1149 switch (rate_bits) {
1150 case HDSPM_wcFreq32:
1153 case HDSPM_wcFreq44_1:
1156 case HDSPM_wcFreq48:
1159 case HDSPM_wcFreq64:
1162 case HDSPM_wcFreq88_2:
1165 case HDSPM_wcFreq96:
1174 /* if rate detected and Syncref is Word than have it,
1175 * word has priority to MADI
1178 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1181 /* maybe a madi input (which is taken if sel sync is madi) */
1182 if (status & HDSPM_madiLock) {
1183 rate_bits = status & HDSPM_madiFreqMask;
1185 switch (rate_bits) {
1186 case HDSPM_madiFreq32:
1189 case HDSPM_madiFreq44_1:
1192 case HDSPM_madiFreq48:
1195 case HDSPM_madiFreq64:
1198 case HDSPM_madiFreq88_2:
1201 case HDSPM_madiFreq96:
1204 case HDSPM_madiFreq128:
1207 case HDSPM_madiFreq176_4:
1210 case HDSPM_madiFreq192:
1218 /* QS and DS rates normally can not be detected
1219 * automatically by the card. Only exception is MADI
1220 * in 96k frame mode.
1222 * So if we read SS values (32 .. 48k), check for
1223 * user-provided DS/QS bits in the control register
1224 * and multiply the base frequency accordingly.
1226 if (rate <= 48000) {
1227 if (hdspm->control_register & HDSPM_QuadSpeed)
1229 else if (hdspm->control_register &
1240 /* return latency in samples per period */
1241 static int hdspm_get_latency(struct hdspm *hdspm)
1245 n = hdspm_decode_latency(hdspm->control_register);
1247 /* Special case for new RME cards with 32 samples period size.
1248 * The three latency bits in the control register
1249 * (HDSP_LatencyMask) encode latency values of 64 samples as
1250 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1251 * denotes 8192 samples, but on new cards like RayDAT or AIO,
1252 * it corresponds to 32 samples.
1254 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1257 return 1 << (n + 6);
1260 /* Latency function */
1261 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1263 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1267 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1271 position = hdspm_read(hdspm, HDSPM_statusRegister);
1273 switch (hdspm->io_type) {
1276 position &= HDSPM_BufferPositionMask;
1277 position /= 4; /* Bytes per sample */
1280 position = (position & HDSPM_BufferID) ?
1281 (hdspm->period_bytes / 4) : 0;
1288 static inline void hdspm_start_audio(struct hdspm * s)
1290 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1291 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1294 static inline void hdspm_stop_audio(struct hdspm * s)
1296 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1297 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1300 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1301 static void hdspm_silence_playback(struct hdspm *hdspm)
1304 int n = hdspm->period_bytes;
1305 void *buf = hdspm->playback_buffer;
1310 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1312 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1316 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1320 spin_lock_irq(&s->lock);
1323 /* Special case for new RME cards like RayDAT/AIO which
1324 * support period sizes of 32 samples. Since latency is
1325 * encoded in the three bits of HDSP_LatencyMask, we can only
1326 * have values from 0 .. 7. While 0 still means 64 samples and
1327 * 6 represents 4096 samples on all cards, 7 represents 8192
1328 * on older cards and 32 samples on new cards.
1330 * In other words, period size in samples is calculated by
1331 * 2^(n+6) with n ranging from 0 .. 7.
1343 s->control_register &= ~HDSPM_LatencyMask;
1344 s->control_register |= hdspm_encode_latency(n);
1346 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1348 hdspm_compute_period_size(s);
1350 spin_unlock_irq(&s->lock);
1355 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1362 switch (hdspm->io_type) {
1365 freq_const = 110069313433624ULL;
1369 freq_const = 104857600000000ULL;
1372 freq_const = 131072000000000ULL;
1379 return div_u64(freq_const, period);
1383 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1389 else if (rate >= 56000)
1392 switch (hdspm->io_type) {
1394 n = 131072000000000ULL; /* 125 MHz */
1398 n = 110069313433624ULL; /* 105 MHz */
1402 n = 104857600000000ULL; /* 100 MHz */
1409 n = div_u64(n, rate);
1410 /* n should be less than 2^32 for being written to FREQ register */
1411 snd_BUG_ON(n >> 32);
1412 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1415 /* dummy set rate lets see what happens */
1416 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1421 int current_speed, target_speed;
1423 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1424 it (e.g. during module initialization).
1427 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1430 if (called_internally) {
1432 /* request from ctl or card initialization
1433 just make a warning an remember setting
1434 for future master mode switching */
1436 snd_printk(KERN_WARNING "HDSPM: "
1437 "Warning: device is not running "
1438 "as a clock master.\n");
1442 /* hw_param request while in AutoSync mode */
1444 hdspm_external_sample_rate(hdspm);
1446 if (hdspm_autosync_ref(hdspm) ==
1447 HDSPM_AUTOSYNC_FROM_NONE) {
1449 snd_printk(KERN_WARNING "HDSPM: "
1450 "Detected no Externel Sync \n");
1453 } else if (rate != external_freq) {
1455 snd_printk(KERN_WARNING "HDSPM: "
1456 "Warning: No AutoSync source for "
1457 "requested rate\n");
1463 current_rate = hdspm->system_sample_rate;
1465 /* Changing between Singe, Double and Quad speed is not
1466 allowed if any substreams are open. This is because such a change
1467 causes a shift in the location of the DMA buffers and a reduction
1468 in the number of available buffers.
1470 Note that a similar but essentially insoluble problem exists for
1471 externally-driven rate changes. All we can do is to flag rate
1472 changes in the read/write routines.
1475 if (current_rate <= 48000)
1476 current_speed = HDSPM_SPEED_SINGLE;
1477 else if (current_rate <= 96000)
1478 current_speed = HDSPM_SPEED_DOUBLE;
1480 current_speed = HDSPM_SPEED_QUAD;
1483 target_speed = HDSPM_SPEED_SINGLE;
1484 else if (rate <= 96000)
1485 target_speed = HDSPM_SPEED_DOUBLE;
1487 target_speed = HDSPM_SPEED_QUAD;
1491 rate_bits = HDSPM_Frequency32KHz;
1494 rate_bits = HDSPM_Frequency44_1KHz;
1497 rate_bits = HDSPM_Frequency48KHz;
1500 rate_bits = HDSPM_Frequency64KHz;
1503 rate_bits = HDSPM_Frequency88_2KHz;
1506 rate_bits = HDSPM_Frequency96KHz;
1509 rate_bits = HDSPM_Frequency128KHz;
1512 rate_bits = HDSPM_Frequency176_4KHz;
1515 rate_bits = HDSPM_Frequency192KHz;
1521 if (current_speed != target_speed
1522 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1525 "cannot change from %s speed to %s speed mode "
1526 "(capture PID = %d, playback PID = %d)\n",
1527 hdspm_speed_names[current_speed],
1528 hdspm_speed_names[target_speed],
1529 hdspm->capture_pid, hdspm->playback_pid);
1533 hdspm->control_register &= ~HDSPM_FrequencyMask;
1534 hdspm->control_register |= rate_bits;
1535 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1537 /* For AES32, need to set DDS value in FREQ register
1538 For MADI, also apparently */
1539 hdspm_set_dds_value(hdspm, rate);
1541 if (AES32 == hdspm->io_type && rate != current_rate)
1542 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1544 hdspm->system_sample_rate = rate;
1546 if (rate <= 48000) {
1547 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1548 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1549 hdspm->max_channels_in = hdspm->ss_in_channels;
1550 hdspm->max_channels_out = hdspm->ss_out_channels;
1551 hdspm->port_names_in = hdspm->port_names_in_ss;
1552 hdspm->port_names_out = hdspm->port_names_out_ss;
1553 } else if (rate <= 96000) {
1554 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1555 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1556 hdspm->max_channels_in = hdspm->ds_in_channels;
1557 hdspm->max_channels_out = hdspm->ds_out_channels;
1558 hdspm->port_names_in = hdspm->port_names_in_ds;
1559 hdspm->port_names_out = hdspm->port_names_out_ds;
1561 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1562 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1563 hdspm->max_channels_in = hdspm->qs_in_channels;
1564 hdspm->max_channels_out = hdspm->qs_out_channels;
1565 hdspm->port_names_in = hdspm->port_names_in_qs;
1566 hdspm->port_names_out = hdspm->port_names_out_qs;
1575 /* mainly for init to 0 on load */
1576 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1581 if (sgain > UNITY_GAIN)
1588 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1589 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1590 hdspm_write_in_gain(hdspm, i, j, gain);
1591 hdspm_write_pb_gain(hdspm, i, j, gain);
1595 /*----------------------------------------------------------------------------
1597 ----------------------------------------------------------------------------*/
1599 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1602 /* the hardware already does the relevant bit-mask with 0xff */
1603 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1606 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1609 /* the hardware already does the relevant bit-mask with 0xff */
1610 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1613 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1615 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1618 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1620 int fifo_bytes_used;
1622 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1624 if (fifo_bytes_used < 128)
1625 return 128 - fifo_bytes_used;
1630 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1632 while (snd_hdspm_midi_input_available (hdspm, id))
1633 snd_hdspm_midi_read_byte (hdspm, id);
1636 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1638 unsigned long flags;
1642 unsigned char buf[128];
1644 /* Output is not interrupt driven */
1646 spin_lock_irqsave (&hmidi->lock, flags);
1647 if (hmidi->output &&
1648 !snd_rawmidi_transmit_empty (hmidi->output)) {
1649 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1651 if (n_pending > 0) {
1652 if (n_pending > (int)sizeof (buf))
1653 n_pending = sizeof (buf);
1655 to_write = snd_rawmidi_transmit (hmidi->output, buf,
1658 for (i = 0; i < to_write; ++i)
1659 snd_hdspm_midi_write_byte (hmidi->hdspm,
1665 spin_unlock_irqrestore (&hmidi->lock, flags);
1669 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1671 unsigned char buf[128]; /* this buffer is designed to match the MIDI
1674 unsigned long flags;
1678 spin_lock_irqsave (&hmidi->lock, flags);
1679 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1680 if (n_pending > 0) {
1682 if (n_pending > (int)sizeof (buf))
1683 n_pending = sizeof (buf);
1684 for (i = 0; i < n_pending; ++i)
1685 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1688 snd_rawmidi_receive (hmidi->input, buf,
1691 /* flush the MIDI input FIFO */
1693 snd_hdspm_midi_read_byte (hmidi->hdspm,
1698 spin_unlock_irqrestore(&hmidi->lock, flags);
1700 spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1701 hmidi->hdspm->control_register |= hmidi->ie;
1702 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1703 hmidi->hdspm->control_register);
1704 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1706 return snd_hdspm_midi_output_write (hmidi);
1710 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1712 struct hdspm *hdspm;
1713 struct hdspm_midi *hmidi;
1714 unsigned long flags;
1716 hmidi = substream->rmidi->private_data;
1717 hdspm = hmidi->hdspm;
1719 spin_lock_irqsave (&hdspm->lock, flags);
1721 if (!(hdspm->control_register & hmidi->ie)) {
1722 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1723 hdspm->control_register |= hmidi->ie;
1726 hdspm->control_register &= ~hmidi->ie;
1729 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1730 spin_unlock_irqrestore (&hdspm->lock, flags);
1733 static void snd_hdspm_midi_output_timer(unsigned long data)
1735 struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1736 unsigned long flags;
1738 snd_hdspm_midi_output_write(hmidi);
1739 spin_lock_irqsave (&hmidi->lock, flags);
1741 /* this does not bump hmidi->istimer, because the
1742 kernel automatically removed the timer when it
1743 expired, and we are now adding it back, thus
1744 leaving istimer wherever it was set before.
1747 if (hmidi->istimer) {
1748 hmidi->timer.expires = 1 + jiffies;
1749 add_timer(&hmidi->timer);
1752 spin_unlock_irqrestore (&hmidi->lock, flags);
1756 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1758 struct hdspm_midi *hmidi;
1759 unsigned long flags;
1761 hmidi = substream->rmidi->private_data;
1762 spin_lock_irqsave (&hmidi->lock, flags);
1764 if (!hmidi->istimer) {
1765 init_timer(&hmidi->timer);
1766 hmidi->timer.function = snd_hdspm_midi_output_timer;
1767 hmidi->timer.data = (unsigned long) hmidi;
1768 hmidi->timer.expires = 1 + jiffies;
1769 add_timer(&hmidi->timer);
1773 if (hmidi->istimer && --hmidi->istimer <= 0)
1774 del_timer (&hmidi->timer);
1776 spin_unlock_irqrestore (&hmidi->lock, flags);
1778 snd_hdspm_midi_output_write(hmidi);
1781 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1783 struct hdspm_midi *hmidi;
1785 hmidi = substream->rmidi->private_data;
1786 spin_lock_irq (&hmidi->lock);
1787 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1788 hmidi->input = substream;
1789 spin_unlock_irq (&hmidi->lock);
1794 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1796 struct hdspm_midi *hmidi;
1798 hmidi = substream->rmidi->private_data;
1799 spin_lock_irq (&hmidi->lock);
1800 hmidi->output = substream;
1801 spin_unlock_irq (&hmidi->lock);
1806 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1808 struct hdspm_midi *hmidi;
1810 snd_hdspm_midi_input_trigger (substream, 0);
1812 hmidi = substream->rmidi->private_data;
1813 spin_lock_irq (&hmidi->lock);
1814 hmidi->input = NULL;
1815 spin_unlock_irq (&hmidi->lock);
1820 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1822 struct hdspm_midi *hmidi;
1824 snd_hdspm_midi_output_trigger (substream, 0);
1826 hmidi = substream->rmidi->private_data;
1827 spin_lock_irq (&hmidi->lock);
1828 hmidi->output = NULL;
1829 spin_unlock_irq (&hmidi->lock);
1834 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1836 .open = snd_hdspm_midi_output_open,
1837 .close = snd_hdspm_midi_output_close,
1838 .trigger = snd_hdspm_midi_output_trigger,
1841 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1843 .open = snd_hdspm_midi_input_open,
1844 .close = snd_hdspm_midi_input_close,
1845 .trigger = snd_hdspm_midi_input_trigger,
1848 static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1849 struct hdspm *hdspm, int id)
1854 hdspm->midi[id].id = id;
1855 hdspm->midi[id].hdspm = hdspm;
1856 spin_lock_init (&hdspm->midi[id].lock);
1859 if (MADIface == hdspm->io_type) {
1860 /* MIDI-over-MADI on HDSPe MADIface */
1861 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1862 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1863 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1864 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1865 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1866 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1868 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1869 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1870 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1871 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1872 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1873 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1875 } else if (1 == id) {
1876 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1877 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1878 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1879 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1880 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1881 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1882 } else if ((2 == id) && (MADI == hdspm->io_type)) {
1883 /* MIDI-over-MADI on HDSPe MADI */
1884 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1885 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1886 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1887 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1888 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1889 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1890 } else if (2 == id) {
1891 /* TCO MTC, read only */
1892 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1893 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1894 hdspm->midi[2].dataOut = -1;
1895 hdspm->midi[2].statusOut = -1;
1896 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1897 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1898 } else if (3 == id) {
1899 /* TCO MTC on HDSPe MADI */
1900 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1901 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1902 hdspm->midi[3].dataOut = -1;
1903 hdspm->midi[3].statusOut = -1;
1904 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1905 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1908 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1909 (MADIface == hdspm->io_type)))) {
1910 if ((id == 0) && (MADIface == hdspm->io_type)) {
1911 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1912 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1913 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1915 sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1917 err = snd_rawmidi_new(card, buf, id, 1, 1,
1918 &hdspm->midi[id].rmidi);
1922 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1924 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1926 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1927 SNDRV_RAWMIDI_STREAM_OUTPUT,
1928 &snd_hdspm_midi_output);
1929 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1930 SNDRV_RAWMIDI_STREAM_INPUT,
1931 &snd_hdspm_midi_input);
1933 hdspm->midi[id].rmidi->info_flags |=
1934 SNDRV_RAWMIDI_INFO_OUTPUT |
1935 SNDRV_RAWMIDI_INFO_INPUT |
1936 SNDRV_RAWMIDI_INFO_DUPLEX;
1938 /* TCO MTC, read only */
1939 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1940 err = snd_rawmidi_new(card, buf, id, 1, 1,
1941 &hdspm->midi[id].rmidi);
1945 sprintf(hdspm->midi[id].rmidi->name,
1946 "%s MTC %d", card->id, id+1);
1947 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1949 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1950 SNDRV_RAWMIDI_STREAM_INPUT,
1951 &snd_hdspm_midi_input);
1953 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1960 static void hdspm_midi_tasklet(unsigned long arg)
1962 struct hdspm *hdspm = (struct hdspm *)arg;
1965 while (i < hdspm->midiPorts) {
1966 if (hdspm->midi[i].pending)
1967 snd_hdspm_midi_input_read(&hdspm->midi[i]);
1974 /*-----------------------------------------------------------------------------
1976 ----------------------------------------------------------------------------*/
1978 /* get the system sample rate which is set */
1982 * Calculate the real sample rate from the
1983 * current DDS value.
1985 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
1987 unsigned int period, rate;
1989 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
1990 rate = hdspm_calc_dds_value(hdspm, period);
1992 if (rate > 207000) {
1993 /* Unreasonable high sample rate as seen on PCI MADI cards. */
1994 if (0 == hdspm_system_clock_mode(hdspm)) {
1995 /* master mode, return internal sample rate */
1996 rate = hdspm->system_sample_rate;
1998 /* slave mode, return external sample rate */
1999 rate = hdspm_external_sample_rate(hdspm);
2007 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2008 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2011 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2012 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2013 .info = snd_hdspm_info_system_sample_rate, \
2014 .put = snd_hdspm_put_system_sample_rate, \
2015 .get = snd_hdspm_get_system_sample_rate \
2018 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2019 struct snd_ctl_elem_info *uinfo)
2021 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2023 uinfo->value.integer.min = 27000;
2024 uinfo->value.integer.max = 207000;
2025 uinfo->value.integer.step = 1;
2030 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2031 struct snd_ctl_elem_value *
2034 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2036 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2040 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2041 struct snd_ctl_elem_value *
2044 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2046 hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]);
2052 * Returns the WordClock sample rate class for the given card.
2054 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2058 switch (hdspm->io_type) {
2061 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2062 return (status >> 16) & 0xF;
2074 * Returns the TCO sample rate class for the given card.
2076 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2081 switch (hdspm->io_type) {
2084 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2085 return (status >> 20) & 0xF;
2097 * Returns the SYNC_IN sample rate class for the given card.
2099 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2104 switch (hdspm->io_type) {
2107 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2108 return (status >> 12) & 0xF;
2120 * Returns the sample rate class for input source <idx> for
2121 * 'new style' cards like the AIO and RayDAT.
2123 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2125 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2127 return (status >> (idx*4)) & 0xF;
2132 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2133 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2135 .private_value = xindex, \
2136 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2137 .info = snd_hdspm_info_autosync_sample_rate, \
2138 .get = snd_hdspm_get_autosync_sample_rate \
2142 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2143 struct snd_ctl_elem_info *uinfo)
2145 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2147 uinfo->value.enumerated.items = 10;
2149 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2150 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2151 strcpy(uinfo->value.enumerated.name,
2152 texts_freq[uinfo->value.enumerated.item]);
2157 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2158 struct snd_ctl_elem_value *
2161 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2163 switch (hdspm->io_type) {
2165 switch (kcontrol->private_value) {
2167 ucontrol->value.enumerated.item[0] =
2168 hdspm_get_wc_sample_rate(hdspm);
2171 ucontrol->value.enumerated.item[0] =
2172 hdspm_get_tco_sample_rate(hdspm);
2175 ucontrol->value.enumerated.item[0] =
2176 hdspm_get_sync_in_sample_rate(hdspm);
2179 ucontrol->value.enumerated.item[0] =
2180 hdspm_get_s1_sample_rate(hdspm,
2181 kcontrol->private_value-1);
2185 switch (kcontrol->private_value) {
2187 ucontrol->value.enumerated.item[0] =
2188 hdspm_get_wc_sample_rate(hdspm);
2191 ucontrol->value.enumerated.item[0] =
2192 hdspm_get_tco_sample_rate(hdspm);
2194 case 5: /* SYNC_IN */
2195 ucontrol->value.enumerated.item[0] =
2196 hdspm_get_sync_in_sample_rate(hdspm);
2199 ucontrol->value.enumerated.item[0] =
2200 hdspm_get_s1_sample_rate(hdspm,
2201 ucontrol->id.index-1);
2206 switch (kcontrol->private_value) {
2208 ucontrol->value.enumerated.item[0] =
2209 hdspm_get_wc_sample_rate(hdspm);
2212 ucontrol->value.enumerated.item[0] =
2213 hdspm_get_tco_sample_rate(hdspm);
2215 case 10: /* SYNC_IN */
2216 ucontrol->value.enumerated.item[0] =
2217 hdspm_get_sync_in_sample_rate(hdspm);
2219 default: /* AES1 to AES8 */
2220 ucontrol->value.enumerated.item[0] =
2221 hdspm_get_s1_sample_rate(hdspm,
2222 kcontrol->private_value-1);
2234 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2235 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2238 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2239 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2240 .info = snd_hdspm_info_system_clock_mode, \
2241 .get = snd_hdspm_get_system_clock_mode, \
2242 .put = snd_hdspm_put_system_clock_mode, \
2247 * Returns the system clock mode for the given card.
2248 * @returns 0 - master, 1 - slave
2250 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2252 switch (hdspm->io_type) {
2255 if (hdspm->settings_register & HDSPM_c0Master)
2260 if (hdspm->control_register & HDSPM_ClockModeMaster)
2269 * Sets the system clock mode.
2270 * @param mode 0 - master, 1 - slave
2272 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2274 switch (hdspm->io_type) {
2278 hdspm->settings_register |= HDSPM_c0Master;
2280 hdspm->settings_register &= ~HDSPM_c0Master;
2282 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2287 hdspm->control_register |= HDSPM_ClockModeMaster;
2289 hdspm->control_register &= ~HDSPM_ClockModeMaster;
2291 hdspm_write(hdspm, HDSPM_controlRegister,
2292 hdspm->control_register);
2297 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2298 struct snd_ctl_elem_info *uinfo)
2300 static char *texts[] = { "Master", "AutoSync" };
2302 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2304 uinfo->value.enumerated.items = 2;
2305 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2306 uinfo->value.enumerated.item =
2307 uinfo->value.enumerated.items - 1;
2308 strcpy(uinfo->value.enumerated.name,
2309 texts[uinfo->value.enumerated.item]);
2313 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2314 struct snd_ctl_elem_value *ucontrol)
2316 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2318 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2322 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2323 struct snd_ctl_elem_value *ucontrol)
2325 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2328 if (!snd_hdspm_use_is_exclusive(hdspm))
2331 val = ucontrol->value.enumerated.item[0];
2337 hdspm_set_system_clock_mode(hdspm, val);
2343 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2344 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2347 .info = snd_hdspm_info_clock_source, \
2348 .get = snd_hdspm_get_clock_source, \
2349 .put = snd_hdspm_put_clock_source \
2353 static int hdspm_clock_source(struct hdspm * hdspm)
2355 switch (hdspm->system_sample_rate) {
2356 case 32000: return 0;
2357 case 44100: return 1;
2358 case 48000: return 2;
2359 case 64000: return 3;
2360 case 88200: return 4;
2361 case 96000: return 5;
2362 case 128000: return 6;
2363 case 176400: return 7;
2364 case 192000: return 8;
2370 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2375 rate = 32000; break;
2377 rate = 44100; break;
2379 rate = 48000; break;
2381 rate = 64000; break;
2383 rate = 88200; break;
2385 rate = 96000; break;
2387 rate = 128000; break;
2389 rate = 176400; break;
2391 rate = 192000; break;
2395 hdspm_set_rate(hdspm, rate, 1);
2399 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2400 struct snd_ctl_elem_info *uinfo)
2402 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2404 uinfo->value.enumerated.items = 9;
2406 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2407 uinfo->value.enumerated.item =
2408 uinfo->value.enumerated.items - 1;
2410 strcpy(uinfo->value.enumerated.name,
2411 texts_freq[uinfo->value.enumerated.item+1]);
2416 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2417 struct snd_ctl_elem_value *ucontrol)
2419 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2421 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2425 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2426 struct snd_ctl_elem_value *ucontrol)
2428 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2432 if (!snd_hdspm_use_is_exclusive(hdspm))
2434 val = ucontrol->value.enumerated.item[0];
2439 spin_lock_irq(&hdspm->lock);
2440 if (val != hdspm_clock_source(hdspm))
2441 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2444 spin_unlock_irq(&hdspm->lock);
2449 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2450 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2453 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2454 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2455 .info = snd_hdspm_info_pref_sync_ref, \
2456 .get = snd_hdspm_get_pref_sync_ref, \
2457 .put = snd_hdspm_put_pref_sync_ref \
2462 * Returns the current preferred sync reference setting.
2463 * The semantics of the return value are depending on the
2464 * card, please see the comments for clarification.
2466 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2468 switch (hdspm->io_type) {
2470 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2471 case 0: return 0; /* WC */
2472 case HDSPM_SyncRef0: return 1; /* AES 1 */
2473 case HDSPM_SyncRef1: return 2; /* AES 2 */
2474 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2475 case HDSPM_SyncRef2: return 4; /* AES 4 */
2476 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2477 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2478 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2479 return 7; /* AES 7 */
2480 case HDSPM_SyncRef3: return 8; /* AES 8 */
2481 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2488 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2489 case 0: return 0; /* WC */
2490 case HDSPM_SyncRef0: return 1; /* MADI */
2491 case HDSPM_SyncRef1: return 2; /* TCO */
2492 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2493 return 3; /* SYNC_IN */
2496 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2497 case 0: return 0; /* WC */
2498 case HDSPM_SyncRef0: return 1; /* MADI */
2499 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2500 return 2; /* SYNC_IN */
2507 switch ((hdspm->settings_register &
2508 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2509 case 0: return 0; /* WC */
2510 case 3: return 1; /* ADAT 1 */
2511 case 4: return 2; /* ADAT 2 */
2512 case 5: return 3; /* ADAT 3 */
2513 case 6: return 4; /* ADAT 4 */
2514 case 1: return 5; /* AES */
2515 case 2: return 6; /* SPDIF */
2516 case 9: return 7; /* TCO */
2517 case 10: return 8; /* SYNC_IN */
2520 switch ((hdspm->settings_register &
2521 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2522 case 0: return 0; /* WC */
2523 case 3: return 1; /* ADAT 1 */
2524 case 4: return 2; /* ADAT 2 */
2525 case 5: return 3; /* ADAT 3 */
2526 case 6: return 4; /* ADAT 4 */
2527 case 1: return 5; /* AES */
2528 case 2: return 6; /* SPDIF */
2529 case 10: return 7; /* SYNC_IN */
2537 switch ((hdspm->settings_register &
2538 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2539 case 0: return 0; /* WC */
2540 case 3: return 1; /* ADAT */
2541 case 1: return 2; /* AES */
2542 case 2: return 3; /* SPDIF */
2543 case 9: return 4; /* TCO */
2544 case 10: return 5; /* SYNC_IN */
2547 switch ((hdspm->settings_register &
2548 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2549 case 0: return 0; /* WC */
2550 case 3: return 1; /* ADAT */
2551 case 1: return 2; /* AES */
2552 case 2: return 3; /* SPDIF */
2553 case 10: return 4; /* SYNC_IN */
2565 * Set the preferred sync reference to <pref>. The semantics
2566 * of <pref> are depending on the card type, see the comments
2567 * for clarification.
2569 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2573 switch (hdspm->io_type) {
2575 hdspm->control_register &= ~HDSPM_SyncRefMask;
2580 hdspm->control_register |= HDSPM_SyncRef0;
2583 hdspm->control_register |= HDSPM_SyncRef1;
2586 hdspm->control_register |=
2587 HDSPM_SyncRef1+HDSPM_SyncRef0;
2590 hdspm->control_register |= HDSPM_SyncRef2;
2593 hdspm->control_register |=
2594 HDSPM_SyncRef2+HDSPM_SyncRef0;
2597 hdspm->control_register |=
2598 HDSPM_SyncRef2+HDSPM_SyncRef1;
2601 hdspm->control_register |=
2602 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2605 hdspm->control_register |= HDSPM_SyncRef3;
2608 hdspm->control_register |=
2609 HDSPM_SyncRef3+HDSPM_SyncRef0;
2619 hdspm->control_register &= ~HDSPM_SyncRefMask;
2625 hdspm->control_register |= HDSPM_SyncRef0;
2628 hdspm->control_register |= HDSPM_SyncRef1;
2630 case 3: /* SYNC_IN */
2631 hdspm->control_register |=
2632 HDSPM_SyncRef0+HDSPM_SyncRef1;
2642 hdspm->control_register |= HDSPM_SyncRef0;
2644 case 2: /* SYNC_IN */
2645 hdspm->control_register |=
2646 HDSPM_SyncRef0+HDSPM_SyncRef1;
2658 case 0: p = 0; break; /* WC */
2659 case 1: p = 3; break; /* ADAT 1 */
2660 case 2: p = 4; break; /* ADAT 2 */
2661 case 3: p = 5; break; /* ADAT 3 */
2662 case 4: p = 6; break; /* ADAT 4 */
2663 case 5: p = 1; break; /* AES */
2664 case 6: p = 2; break; /* SPDIF */
2665 case 7: p = 9; break; /* TCO */
2666 case 8: p = 10; break; /* SYNC_IN */
2671 case 0: p = 0; break; /* WC */
2672 case 1: p = 3; break; /* ADAT 1 */
2673 case 2: p = 4; break; /* ADAT 2 */
2674 case 3: p = 5; break; /* ADAT 3 */
2675 case 4: p = 6; break; /* ADAT 4 */
2676 case 5: p = 1; break; /* AES */
2677 case 6: p = 2; break; /* SPDIF */
2678 case 7: p = 10; break; /* SYNC_IN */
2687 case 0: p = 0; break; /* WC */
2688 case 1: p = 3; break; /* ADAT */
2689 case 2: p = 1; break; /* AES */
2690 case 3: p = 2; break; /* SPDIF */
2691 case 4: p = 9; break; /* TCO */
2692 case 5: p = 10; break; /* SYNC_IN */
2697 case 0: p = 0; break; /* WC */
2698 case 1: p = 3; break; /* ADAT */
2699 case 2: p = 1; break; /* AES */
2700 case 3: p = 2; break; /* SPDIF */
2701 case 4: p = 10; break; /* SYNC_IN */
2708 switch (hdspm->io_type) {
2711 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2712 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2713 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2719 hdspm_write(hdspm, HDSPM_controlRegister,
2720 hdspm->control_register);
2727 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2728 struct snd_ctl_elem_info *uinfo)
2730 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2732 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2734 uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2736 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2737 uinfo->value.enumerated.item =
2738 uinfo->value.enumerated.items - 1;
2740 strcpy(uinfo->value.enumerated.name,
2741 hdspm->texts_autosync[uinfo->value.enumerated.item]);
2746 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2747 struct snd_ctl_elem_value *ucontrol)
2749 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2750 int psf = hdspm_pref_sync_ref(hdspm);
2753 ucontrol->value.enumerated.item[0] = psf;
2760 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2761 struct snd_ctl_elem_value *ucontrol)
2763 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2764 int val, change = 0;
2766 if (!snd_hdspm_use_is_exclusive(hdspm))
2769 val = ucontrol->value.enumerated.item[0];
2773 else if (val >= hdspm->texts_autosync_items)
2774 val = hdspm->texts_autosync_items-1;
2776 spin_lock_irq(&hdspm->lock);
2777 if (val != hdspm_pref_sync_ref(hdspm))
2778 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2780 spin_unlock_irq(&hdspm->lock);
2785 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2786 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2789 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2790 .info = snd_hdspm_info_autosync_ref, \
2791 .get = snd_hdspm_get_autosync_ref, \
2794 static int hdspm_autosync_ref(struct hdspm *hdspm)
2796 if (AES32 == hdspm->io_type) {
2797 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2798 unsigned int syncref =
2799 (status >> HDSPM_AES32_syncref_bit) & 0xF;
2801 return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2804 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2805 } else if (MADI == hdspm->io_type) {
2806 /* This looks at the autosync selected sync reference */
2807 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2809 switch (status2 & HDSPM_SelSyncRefMask) {
2810 case HDSPM_SelSyncRef_WORD:
2811 return HDSPM_AUTOSYNC_FROM_WORD;
2812 case HDSPM_SelSyncRef_MADI:
2813 return HDSPM_AUTOSYNC_FROM_MADI;
2814 case HDSPM_SelSyncRef_TCO:
2815 return HDSPM_AUTOSYNC_FROM_TCO;
2816 case HDSPM_SelSyncRef_SyncIn:
2817 return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2818 case HDSPM_SelSyncRef_NVALID:
2819 return HDSPM_AUTOSYNC_FROM_NONE;
2829 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2830 struct snd_ctl_elem_info *uinfo)
2832 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2834 if (AES32 == hdspm->io_type) {
2835 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2836 "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2838 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2840 uinfo->value.enumerated.items = 10;
2841 if (uinfo->value.enumerated.item >=
2842 uinfo->value.enumerated.items)
2843 uinfo->value.enumerated.item =
2844 uinfo->value.enumerated.items - 1;
2845 strcpy(uinfo->value.enumerated.name,
2846 texts[uinfo->value.enumerated.item]);
2847 } else if (MADI == hdspm->io_type) {
2848 static char *texts[] = {"Word Clock", "MADI", "TCO",
2849 "Sync In", "None" };
2851 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2853 uinfo->value.enumerated.items = 5;
2854 if (uinfo->value.enumerated.item >=
2855 uinfo->value.enumerated.items)
2856 uinfo->value.enumerated.item =
2857 uinfo->value.enumerated.items - 1;
2858 strcpy(uinfo->value.enumerated.name,
2859 texts[uinfo->value.enumerated.item]);
2864 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2865 struct snd_ctl_elem_value *ucontrol)
2867 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2869 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2874 #define HDSPM_LINE_OUT(xname, xindex) \
2875 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2878 .info = snd_hdspm_info_line_out, \
2879 .get = snd_hdspm_get_line_out, \
2880 .put = snd_hdspm_put_line_out \
2883 static int hdspm_line_out(struct hdspm * hdspm)
2885 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
2889 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
2892 hdspm->control_register |= HDSPM_LineOut;
2894 hdspm->control_register &= ~HDSPM_LineOut;
2895 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2900 #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info
2902 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
2903 struct snd_ctl_elem_value *ucontrol)
2905 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2907 spin_lock_irq(&hdspm->lock);
2908 ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
2909 spin_unlock_irq(&hdspm->lock);
2913 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
2914 struct snd_ctl_elem_value *ucontrol)
2916 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2920 if (!snd_hdspm_use_is_exclusive(hdspm))
2922 val = ucontrol->value.integer.value[0] & 1;
2923 spin_lock_irq(&hdspm->lock);
2924 change = (int) val != hdspm_line_out(hdspm);
2925 hdspm_set_line_output(hdspm, val);
2926 spin_unlock_irq(&hdspm->lock);
2931 #define HDSPM_TX_64(xname, xindex) \
2932 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2935 .info = snd_hdspm_info_tx_64, \
2936 .get = snd_hdspm_get_tx_64, \
2937 .put = snd_hdspm_put_tx_64 \
2940 static int hdspm_tx_64(struct hdspm * hdspm)
2942 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
2945 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
2948 hdspm->control_register |= HDSPM_TX_64ch;
2950 hdspm->control_register &= ~HDSPM_TX_64ch;
2951 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2956 #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info
2958 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
2959 struct snd_ctl_elem_value *ucontrol)
2961 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2963 spin_lock_irq(&hdspm->lock);
2964 ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
2965 spin_unlock_irq(&hdspm->lock);
2969 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
2970 struct snd_ctl_elem_value *ucontrol)
2972 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2976 if (!snd_hdspm_use_is_exclusive(hdspm))
2978 val = ucontrol->value.integer.value[0] & 1;
2979 spin_lock_irq(&hdspm->lock);
2980 change = (int) val != hdspm_tx_64(hdspm);
2981 hdspm_set_tx_64(hdspm, val);
2982 spin_unlock_irq(&hdspm->lock);
2987 #define HDSPM_C_TMS(xname, xindex) \
2988 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2991 .info = snd_hdspm_info_c_tms, \
2992 .get = snd_hdspm_get_c_tms, \
2993 .put = snd_hdspm_put_c_tms \
2996 static int hdspm_c_tms(struct hdspm * hdspm)
2998 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
3001 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
3004 hdspm->control_register |= HDSPM_clr_tms;
3006 hdspm->control_register &= ~HDSPM_clr_tms;
3007 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3012 #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info
3014 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
3015 struct snd_ctl_elem_value *ucontrol)
3017 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3019 spin_lock_irq(&hdspm->lock);
3020 ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
3021 spin_unlock_irq(&hdspm->lock);
3025 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
3026 struct snd_ctl_elem_value *ucontrol)
3028 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3032 if (!snd_hdspm_use_is_exclusive(hdspm))
3034 val = ucontrol->value.integer.value[0] & 1;
3035 spin_lock_irq(&hdspm->lock);
3036 change = (int) val != hdspm_c_tms(hdspm);
3037 hdspm_set_c_tms(hdspm, val);
3038 spin_unlock_irq(&hdspm->lock);
3043 #define HDSPM_SAFE_MODE(xname, xindex) \
3044 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3047 .info = snd_hdspm_info_safe_mode, \
3048 .get = snd_hdspm_get_safe_mode, \
3049 .put = snd_hdspm_put_safe_mode \
3052 static int hdspm_safe_mode(struct hdspm * hdspm)
3054 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
3057 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
3060 hdspm->control_register |= HDSPM_AutoInp;
3062 hdspm->control_register &= ~HDSPM_AutoInp;
3063 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3068 #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info
3070 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
3071 struct snd_ctl_elem_value *ucontrol)
3073 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3075 spin_lock_irq(&hdspm->lock);
3076 ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
3077 spin_unlock_irq(&hdspm->lock);
3081 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
3082 struct snd_ctl_elem_value *ucontrol)
3084 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3088 if (!snd_hdspm_use_is_exclusive(hdspm))
3090 val = ucontrol->value.integer.value[0] & 1;
3091 spin_lock_irq(&hdspm->lock);
3092 change = (int) val != hdspm_safe_mode(hdspm);
3093 hdspm_set_safe_mode(hdspm, val);
3094 spin_unlock_irq(&hdspm->lock);
3099 #define HDSPM_EMPHASIS(xname, xindex) \
3100 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3103 .info = snd_hdspm_info_emphasis, \
3104 .get = snd_hdspm_get_emphasis, \
3105 .put = snd_hdspm_put_emphasis \
3108 static int hdspm_emphasis(struct hdspm * hdspm)
3110 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
3113 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
3116 hdspm->control_register |= HDSPM_Emphasis;
3118 hdspm->control_register &= ~HDSPM_Emphasis;
3119 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3124 #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info
3126 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
3127 struct snd_ctl_elem_value *ucontrol)
3129 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3131 spin_lock_irq(&hdspm->lock);
3132 ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
3133 spin_unlock_irq(&hdspm->lock);
3137 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
3138 struct snd_ctl_elem_value *ucontrol)
3140 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3144 if (!snd_hdspm_use_is_exclusive(hdspm))
3146 val = ucontrol->value.integer.value[0] & 1;
3147 spin_lock_irq(&hdspm->lock);
3148 change = (int) val != hdspm_emphasis(hdspm);
3149 hdspm_set_emphasis(hdspm, val);
3150 spin_unlock_irq(&hdspm->lock);
3155 #define HDSPM_DOLBY(xname, xindex) \
3156 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3159 .info = snd_hdspm_info_dolby, \
3160 .get = snd_hdspm_get_dolby, \
3161 .put = snd_hdspm_put_dolby \
3164 static int hdspm_dolby(struct hdspm * hdspm)
3166 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
3169 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
3172 hdspm->control_register |= HDSPM_Dolby;
3174 hdspm->control_register &= ~HDSPM_Dolby;
3175 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3180 #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info
3182 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
3183 struct snd_ctl_elem_value *ucontrol)
3185 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3187 spin_lock_irq(&hdspm->lock);
3188 ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
3189 spin_unlock_irq(&hdspm->lock);
3193 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
3194 struct snd_ctl_elem_value *ucontrol)
3196 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3200 if (!snd_hdspm_use_is_exclusive(hdspm))
3202 val = ucontrol->value.integer.value[0] & 1;
3203 spin_lock_irq(&hdspm->lock);
3204 change = (int) val != hdspm_dolby(hdspm);
3205 hdspm_set_dolby(hdspm, val);
3206 spin_unlock_irq(&hdspm->lock);
3211 #define HDSPM_PROFESSIONAL(xname, xindex) \
3212 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3215 .info = snd_hdspm_info_professional, \
3216 .get = snd_hdspm_get_professional, \
3217 .put = snd_hdspm_put_professional \
3220 static int hdspm_professional(struct hdspm * hdspm)
3222 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
3225 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
3228 hdspm->control_register |= HDSPM_Professional;
3230 hdspm->control_register &= ~HDSPM_Professional;
3231 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3236 #define snd_hdspm_info_professional snd_ctl_boolean_mono_info
3238 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
3239 struct snd_ctl_elem_value *ucontrol)
3241 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3243 spin_lock_irq(&hdspm->lock);
3244 ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
3245 spin_unlock_irq(&hdspm->lock);
3249 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
3250 struct snd_ctl_elem_value *ucontrol)
3252 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3256 if (!snd_hdspm_use_is_exclusive(hdspm))
3258 val = ucontrol->value.integer.value[0] & 1;
3259 spin_lock_irq(&hdspm->lock);
3260 change = (int) val != hdspm_professional(hdspm);
3261 hdspm_set_professional(hdspm, val);
3262 spin_unlock_irq(&hdspm->lock);
3266 #define HDSPM_INPUT_SELECT(xname, xindex) \
3267 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3270 .info = snd_hdspm_info_input_select, \
3271 .get = snd_hdspm_get_input_select, \
3272 .put = snd_hdspm_put_input_select \
3275 static int hdspm_input_select(struct hdspm * hdspm)
3277 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3280 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3283 hdspm->control_register |= HDSPM_InputSelect0;
3285 hdspm->control_register &= ~HDSPM_InputSelect0;
3286 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3291 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3292 struct snd_ctl_elem_info *uinfo)
3294 static char *texts[] = { "optical", "coaxial" };
3296 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3298 uinfo->value.enumerated.items = 2;
3300 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3301 uinfo->value.enumerated.item =
3302 uinfo->value.enumerated.items - 1;
3303 strcpy(uinfo->value.enumerated.name,
3304 texts[uinfo->value.enumerated.item]);
3309 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3310 struct snd_ctl_elem_value *ucontrol)
3312 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3314 spin_lock_irq(&hdspm->lock);
3315 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3316 spin_unlock_irq(&hdspm->lock);
3320 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3321 struct snd_ctl_elem_value *ucontrol)
3323 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3327 if (!snd_hdspm_use_is_exclusive(hdspm))
3329 val = ucontrol->value.integer.value[0] & 1;
3330 spin_lock_irq(&hdspm->lock);
3331 change = (int) val != hdspm_input_select(hdspm);
3332 hdspm_set_input_select(hdspm, val);
3333 spin_unlock_irq(&hdspm->lock);
3338 #define HDSPM_DS_WIRE(xname, xindex) \
3339 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3342 .info = snd_hdspm_info_ds_wire, \
3343 .get = snd_hdspm_get_ds_wire, \
3344 .put = snd_hdspm_put_ds_wire \
3347 static int hdspm_ds_wire(struct hdspm * hdspm)
3349 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3352 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3355 hdspm->control_register |= HDSPM_DS_DoubleWire;
3357 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3358 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3363 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3364 struct snd_ctl_elem_info *uinfo)
3366 static char *texts[] = { "Single", "Double" };
3368 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3370 uinfo->value.enumerated.items = 2;
3372 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3373 uinfo->value.enumerated.item =
3374 uinfo->value.enumerated.items - 1;
3375 strcpy(uinfo->value.enumerated.name,
3376 texts[uinfo->value.enumerated.item]);
3381 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3382 struct snd_ctl_elem_value *ucontrol)
3384 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3386 spin_lock_irq(&hdspm->lock);
3387 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3388 spin_unlock_irq(&hdspm->lock);
3392 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3393 struct snd_ctl_elem_value *ucontrol)
3395 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3399 if (!snd_hdspm_use_is_exclusive(hdspm))
3401 val = ucontrol->value.integer.value[0] & 1;
3402 spin_lock_irq(&hdspm->lock);
3403 change = (int) val != hdspm_ds_wire(hdspm);
3404 hdspm_set_ds_wire(hdspm, val);
3405 spin_unlock_irq(&hdspm->lock);
3410 #define HDSPM_QS_WIRE(xname, xindex) \
3411 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3414 .info = snd_hdspm_info_qs_wire, \
3415 .get = snd_hdspm_get_qs_wire, \
3416 .put = snd_hdspm_put_qs_wire \
3419 static int hdspm_qs_wire(struct hdspm * hdspm)
3421 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3423 if (hdspm->control_register & HDSPM_QS_QuadWire)
3428 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3430 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3435 hdspm->control_register |= HDSPM_QS_DoubleWire;
3438 hdspm->control_register |= HDSPM_QS_QuadWire;
3441 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3446 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3447 struct snd_ctl_elem_info *uinfo)
3449 static char *texts[] = { "Single", "Double", "Quad" };
3451 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3453 uinfo->value.enumerated.items = 3;
3455 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3456 uinfo->value.enumerated.item =
3457 uinfo->value.enumerated.items - 1;
3458 strcpy(uinfo->value.enumerated.name,
3459 texts[uinfo->value.enumerated.item]);
3464 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3465 struct snd_ctl_elem_value *ucontrol)
3467 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3469 spin_lock_irq(&hdspm->lock);
3470 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3471 spin_unlock_irq(&hdspm->lock);
3475 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3476 struct snd_ctl_elem_value *ucontrol)
3478 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3482 if (!snd_hdspm_use_is_exclusive(hdspm))
3484 val = ucontrol->value.integer.value[0];
3489 spin_lock_irq(&hdspm->lock);
3490 change = val != hdspm_qs_wire(hdspm);
3491 hdspm_set_qs_wire(hdspm, val);
3492 spin_unlock_irq(&hdspm->lock);
3496 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3497 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3500 .info = snd_hdspm_info_madi_speedmode, \
3501 .get = snd_hdspm_get_madi_speedmode, \
3502 .put = snd_hdspm_put_madi_speedmode \
3505 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3507 if (hdspm->control_register & HDSPM_QuadSpeed)
3509 if (hdspm->control_register & HDSPM_DoubleSpeed)
3514 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3516 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3521 hdspm->control_register |= HDSPM_DoubleSpeed;
3524 hdspm->control_register |= HDSPM_QuadSpeed;
3527 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3532 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3533 struct snd_ctl_elem_info *uinfo)
3535 static char *texts[] = { "Single", "Double", "Quad" };
3537 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3539 uinfo->value.enumerated.items = 3;
3541 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3542 uinfo->value.enumerated.item =
3543 uinfo->value.enumerated.items - 1;
3544 strcpy(uinfo->value.enumerated.name,
3545 texts[uinfo->value.enumerated.item]);
3550 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3551 struct snd_ctl_elem_value *ucontrol)
3553 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3555 spin_lock_irq(&hdspm->lock);
3556 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3557 spin_unlock_irq(&hdspm->lock);
3561 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3562 struct snd_ctl_elem_value *ucontrol)
3564 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3568 if (!snd_hdspm_use_is_exclusive(hdspm))
3570 val = ucontrol->value.integer.value[0];
3575 spin_lock_irq(&hdspm->lock);
3576 change = val != hdspm_madi_speedmode(hdspm);
3577 hdspm_set_madi_speedmode(hdspm, val);
3578 spin_unlock_irq(&hdspm->lock);
3582 #define HDSPM_MIXER(xname, xindex) \
3583 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3587 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3588 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3589 .info = snd_hdspm_info_mixer, \
3590 .get = snd_hdspm_get_mixer, \
3591 .put = snd_hdspm_put_mixer \
3594 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3595 struct snd_ctl_elem_info *uinfo)
3597 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3599 uinfo->value.integer.min = 0;
3600 uinfo->value.integer.max = 65535;
3601 uinfo->value.integer.step = 1;
3605 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3606 struct snd_ctl_elem_value *ucontrol)
3608 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3612 source = ucontrol->value.integer.value[0];
3615 else if (source >= 2 * HDSPM_MAX_CHANNELS)
3616 source = 2 * HDSPM_MAX_CHANNELS - 1;
3618 destination = ucontrol->value.integer.value[1];
3619 if (destination < 0)
3621 else if (destination >= HDSPM_MAX_CHANNELS)
3622 destination = HDSPM_MAX_CHANNELS - 1;
3624 spin_lock_irq(&hdspm->lock);
3625 if (source >= HDSPM_MAX_CHANNELS)
3626 ucontrol->value.integer.value[2] =
3627 hdspm_read_pb_gain(hdspm, destination,
3628 source - HDSPM_MAX_CHANNELS);
3630 ucontrol->value.integer.value[2] =
3631 hdspm_read_in_gain(hdspm, destination, source);
3633 spin_unlock_irq(&hdspm->lock);
3638 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3639 struct snd_ctl_elem_value *ucontrol)
3641 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3647 if (!snd_hdspm_use_is_exclusive(hdspm))
3650 source = ucontrol->value.integer.value[0];
3651 destination = ucontrol->value.integer.value[1];
3653 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3655 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3658 gain = ucontrol->value.integer.value[2];
3660 spin_lock_irq(&hdspm->lock);
3662 if (source >= HDSPM_MAX_CHANNELS)
3663 change = gain != hdspm_read_pb_gain(hdspm, destination,
3665 HDSPM_MAX_CHANNELS);
3667 change = gain != hdspm_read_in_gain(hdspm, destination,
3671 if (source >= HDSPM_MAX_CHANNELS)
3672 hdspm_write_pb_gain(hdspm, destination,
3673 source - HDSPM_MAX_CHANNELS,
3676 hdspm_write_in_gain(hdspm, destination, source,
3679 spin_unlock_irq(&hdspm->lock);
3684 /* The simple mixer control(s) provide gain control for the
3685 basic 1:1 mappings of playback streams to output
3689 #define HDSPM_PLAYBACK_MIXER \
3690 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3691 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3692 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3693 .info = snd_hdspm_info_playback_mixer, \
3694 .get = snd_hdspm_get_playback_mixer, \
3695 .put = snd_hdspm_put_playback_mixer \
3698 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3699 struct snd_ctl_elem_info *uinfo)
3701 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3703 uinfo->value.integer.min = 0;
3704 uinfo->value.integer.max = 64;
3705 uinfo->value.integer.step = 1;
3709 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3710 struct snd_ctl_elem_value *ucontrol)
3712 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3715 channel = ucontrol->id.index - 1;
3717 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3720 spin_lock_irq(&hdspm->lock);
3721 ucontrol->value.integer.value[0] =
3722 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3723 spin_unlock_irq(&hdspm->lock);
3728 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3729 struct snd_ctl_elem_value *ucontrol)
3731 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3736 if (!snd_hdspm_use_is_exclusive(hdspm))
3739 channel = ucontrol->id.index - 1;
3741 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3744 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3746 spin_lock_irq(&hdspm->lock);
3748 gain != hdspm_read_pb_gain(hdspm, channel,
3751 hdspm_write_pb_gain(hdspm, channel, channel,
3753 spin_unlock_irq(&hdspm->lock);
3757 #define HDSPM_SYNC_CHECK(xname, xindex) \
3758 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3760 .private_value = xindex, \
3761 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3762 .info = snd_hdspm_info_sync_check, \
3763 .get = snd_hdspm_get_sync_check \
3767 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3768 struct snd_ctl_elem_info *uinfo)
3770 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3771 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3773 uinfo->value.enumerated.items = 4;
3774 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3775 uinfo->value.enumerated.item =
3776 uinfo->value.enumerated.items - 1;
3777 strcpy(uinfo->value.enumerated.name,
3778 texts[uinfo->value.enumerated.item]);
3782 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3784 int status, status2;
3786 switch (hdspm->io_type) {
3788 status = hdspm_read(hdspm, HDSPM_statusRegister);
3789 if (status & HDSPM_wcSync)
3791 else if (status & HDSPM_wcLock)
3797 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3798 if (status2 & HDSPM_wcLock) {
3799 if (status2 & HDSPM_wcSync)
3809 status = hdspm_read(hdspm, HDSPM_statusRegister);
3811 if (status & 0x2000000)
3813 else if (status & 0x1000000)
3828 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3830 int status = hdspm_read(hdspm, HDSPM_statusRegister);
3831 if (status & HDSPM_madiLock) {
3832 if (status & HDSPM_madiSync)
3841 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3843 int status, lock, sync;
3845 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3847 lock = (status & (0x1<<idx)) ? 1 : 0;
3848 sync = (status & (0x100<<idx)) ? 1 : 0;
3858 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3860 int status, lock = 0, sync = 0;
3862 switch (hdspm->io_type) {
3865 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3866 lock = (status & 0x400) ? 1 : 0;
3867 sync = (status & 0x800) ? 1 : 0;
3872 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3873 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3874 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3889 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3891 int status2, lock, sync;
3892 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3894 lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3895 sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3905 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3910 switch (hdspm->io_type) {
3913 status = hdspm_read(hdspm, HDSPM_statusRegister);
3914 if (status & HDSPM_tcoLock) {
3915 if (status & HDSPM_tcoSync)
3926 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3928 if (status & 0x8000000)
3929 return 2; /* Sync */
3930 if (status & 0x4000000)
3931 return 1; /* Lock */
3932 return 0; /* No signal */
3944 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3945 struct snd_ctl_elem_value *ucontrol)
3947 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3950 switch (hdspm->io_type) {
3952 switch (kcontrol->private_value) {
3954 val = hdspm_wc_sync_check(hdspm); break;
3956 val = hdspm_tco_sync_check(hdspm); break;
3957 case 8: /* SYNC IN */
3958 val = hdspm_sync_in_sync_check(hdspm); break;
3960 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3965 switch (kcontrol->private_value) {
3967 val = hdspm_wc_sync_check(hdspm); break;
3969 val = hdspm_tco_sync_check(hdspm); break;
3970 case 5: /* SYNC IN */
3971 val = hdspm_sync_in_sync_check(hdspm); break;
3973 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3978 switch (kcontrol->private_value) {
3980 val = hdspm_wc_sync_check(hdspm); break;
3982 val = hdspm_madi_sync_check(hdspm); break;
3984 val = hdspm_tco_sync_check(hdspm); break;
3985 case 3: /* SYNC_IN */
3986 val = hdspm_sync_in_sync_check(hdspm); break;
3991 val = hdspm_madi_sync_check(hdspm); /* MADI */
3995 switch (kcontrol->private_value) {
3997 val = hdspm_wc_sync_check(hdspm); break;
3999 val = hdspm_tco_sync_check(hdspm); break;
4000 case 10 /* SYNC IN */:
4001 val = hdspm_sync_in_sync_check(hdspm); break;
4002 default: /* AES1 to AES8 */
4003 val = hdspm_aes_sync_check(hdspm,
4004 kcontrol->private_value-1);
4013 ucontrol->value.enumerated.item[0] = val;
4022 static void hdspm_tco_write(struct hdspm *hdspm)
4024 unsigned int tc[4] = { 0, 0, 0, 0};
4026 switch (hdspm->tco->input) {
4028 tc[2] |= HDSPM_TCO2_set_input_MSB;
4031 tc[2] |= HDSPM_TCO2_set_input_LSB;
4037 switch (hdspm->tco->framerate) {
4039 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4042 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4045 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4046 HDSPM_TCO1_set_drop_frame_flag;
4049 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4050 HDSPM_TCO1_LTC_Format_MSB;
4053 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4054 HDSPM_TCO1_LTC_Format_MSB +
4055 HDSPM_TCO1_set_drop_frame_flag;
4061 switch (hdspm->tco->wordclock) {
4063 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4066 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4072 switch (hdspm->tco->samplerate) {
4074 tc[2] |= HDSPM_TCO2_set_freq;
4077 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4083 switch (hdspm->tco->pull) {
4085 tc[2] |= HDSPM_TCO2_set_pull_up;
4088 tc[2] |= HDSPM_TCO2_set_pull_down;
4091 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4094 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4100 if (1 == hdspm->tco->term) {
4101 tc[2] |= HDSPM_TCO2_set_term_75R;
4104 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4105 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4106 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4107 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4111 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4112 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4115 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4116 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4117 .info = snd_hdspm_info_tco_sample_rate, \
4118 .get = snd_hdspm_get_tco_sample_rate, \
4119 .put = snd_hdspm_put_tco_sample_rate \
4122 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4123 struct snd_ctl_elem_info *uinfo)
4125 static char *texts[] = { "44.1 kHz", "48 kHz" };
4126 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4128 uinfo->value.enumerated.items = 2;
4130 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4131 uinfo->value.enumerated.item =
4132 uinfo->value.enumerated.items - 1;
4134 strcpy(uinfo->value.enumerated.name,
4135 texts[uinfo->value.enumerated.item]);
4140 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4141 struct snd_ctl_elem_value *ucontrol)
4143 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4145 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4150 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4151 struct snd_ctl_elem_value *ucontrol)
4153 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4155 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4156 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4158 hdspm_tco_write(hdspm);
4167 #define HDSPM_TCO_PULL(xname, xindex) \
4168 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4171 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4172 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4173 .info = snd_hdspm_info_tco_pull, \
4174 .get = snd_hdspm_get_tco_pull, \
4175 .put = snd_hdspm_put_tco_pull \
4178 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4179 struct snd_ctl_elem_info *uinfo)
4181 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4182 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4184 uinfo->value.enumerated.items = 5;
4186 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4187 uinfo->value.enumerated.item =
4188 uinfo->value.enumerated.items - 1;
4190 strcpy(uinfo->value.enumerated.name,
4191 texts[uinfo->value.enumerated.item]);
4196 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4197 struct snd_ctl_elem_value *ucontrol)
4199 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4201 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4206 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4207 struct snd_ctl_elem_value *ucontrol)
4209 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4211 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4212 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4214 hdspm_tco_write(hdspm);
4222 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4223 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4226 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4227 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4228 .info = snd_hdspm_info_tco_wck_conversion, \
4229 .get = snd_hdspm_get_tco_wck_conversion, \
4230 .put = snd_hdspm_put_tco_wck_conversion \
4233 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4234 struct snd_ctl_elem_info *uinfo)
4236 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4237 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4239 uinfo->value.enumerated.items = 3;
4241 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4242 uinfo->value.enumerated.item =
4243 uinfo->value.enumerated.items - 1;
4245 strcpy(uinfo->value.enumerated.name,
4246 texts[uinfo->value.enumerated.item]);
4251 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4252 struct snd_ctl_elem_value *ucontrol)
4254 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4256 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4261 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4262 struct snd_ctl_elem_value *ucontrol)
4264 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4266 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4267 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4269 hdspm_tco_write(hdspm);
4278 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4279 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4282 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4283 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4284 .info = snd_hdspm_info_tco_frame_rate, \
4285 .get = snd_hdspm_get_tco_frame_rate, \
4286 .put = snd_hdspm_put_tco_frame_rate \
4289 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4290 struct snd_ctl_elem_info *uinfo)
4292 static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4293 "29.97 dfps", "30 fps", "30 dfps" };
4294 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4296 uinfo->value.enumerated.items = 6;
4298 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4299 uinfo->value.enumerated.item =
4300 uinfo->value.enumerated.items - 1;
4302 strcpy(uinfo->value.enumerated.name,
4303 texts[uinfo->value.enumerated.item]);
4308 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4309 struct snd_ctl_elem_value *ucontrol)
4311 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4313 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4318 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4319 struct snd_ctl_elem_value *ucontrol)
4321 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4323 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4324 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4326 hdspm_tco_write(hdspm);
4335 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4336 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4339 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4340 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4341 .info = snd_hdspm_info_tco_sync_source, \
4342 .get = snd_hdspm_get_tco_sync_source, \
4343 .put = snd_hdspm_put_tco_sync_source \
4346 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4347 struct snd_ctl_elem_info *uinfo)
4349 static char *texts[] = { "LTC", "Video", "WCK" };
4350 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4352 uinfo->value.enumerated.items = 3;
4354 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4355 uinfo->value.enumerated.item =
4356 uinfo->value.enumerated.items - 1;
4358 strcpy(uinfo->value.enumerated.name,
4359 texts[uinfo->value.enumerated.item]);
4364 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4365 struct snd_ctl_elem_value *ucontrol)
4367 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4369 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4374 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4375 struct snd_ctl_elem_value *ucontrol)
4377 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4379 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4380 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4382 hdspm_tco_write(hdspm);
4391 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4392 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4395 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4396 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4397 .info = snd_hdspm_info_tco_word_term, \
4398 .get = snd_hdspm_get_tco_word_term, \
4399 .put = snd_hdspm_put_tco_word_term \
4402 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4403 struct snd_ctl_elem_info *uinfo)
4405 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4407 uinfo->value.integer.min = 0;
4408 uinfo->value.integer.max = 1;
4414 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4415 struct snd_ctl_elem_value *ucontrol)
4417 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4419 ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4425 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4426 struct snd_ctl_elem_value *ucontrol)
4428 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4430 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4431 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4433 hdspm_tco_write(hdspm);
4444 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4445 HDSPM_MIXER("Mixer", 0),
4446 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4447 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4448 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4449 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4450 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4451 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4452 HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4453 HDSPM_SYNC_CHECK("TCO SyncCHeck", 2),
4454 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4455 HDSPM_LINE_OUT("Line Out", 0),
4456 HDSPM_TX_64("TX 64 channels mode", 0),
4457 HDSPM_C_TMS("Clear Track Marker", 0),
4458 HDSPM_SAFE_MODE("Safe Mode", 0),
4459 HDSPM_INPUT_SELECT("Input Select", 0),
4460 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4464 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4465 HDSPM_MIXER("Mixer", 0),
4466 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4467 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4468 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4469 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4470 HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4471 HDSPM_TX_64("TX 64 channels mode", 0),
4472 HDSPM_C_TMS("Clear Track Marker", 0),
4473 HDSPM_SAFE_MODE("Safe Mode", 0),
4474 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4477 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4478 HDSPM_MIXER("Mixer", 0),
4479 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4480 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4481 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4482 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4483 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4484 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4485 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4486 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4487 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4488 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4489 HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4490 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4491 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4492 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4493 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4494 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4495 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4496 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4499 HDSPM_INPUT_SELECT("Input Select", 0),
4500 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4501 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4502 HDSPM_SPDIF_IN("SPDIF In", 0);
4503 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4504 HDSPM_INPUT_LEVEL("Input Level", 0);
4505 HDSPM_OUTPUT_LEVEL("Output Level", 0);
4506 HDSPM_PHONES("Phones", 0);
4510 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4511 HDSPM_MIXER("Mixer", 0),
4512 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4513 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4514 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4515 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4516 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4517 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4518 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4519 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4520 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4521 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4522 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4523 HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4524 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4525 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4526 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4527 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4528 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4529 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4530 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4531 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4532 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4533 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4536 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4537 HDSPM_MIXER("Mixer", 0),
4538 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4539 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4540 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4541 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4542 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4543 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4544 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4545 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4546 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4547 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4548 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4549 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4550 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4551 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4552 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4553 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4554 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4555 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4556 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4557 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4558 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4559 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4560 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4561 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4562 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4563 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4564 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4565 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4566 HDSPM_LINE_OUT("Line Out", 0),
4567 HDSPM_EMPHASIS("Emphasis", 0),
4568 HDSPM_DOLBY("Non Audio", 0),
4569 HDSPM_PROFESSIONAL("Professional", 0),
4570 HDSPM_C_TMS("Clear Track Marker", 0),
4571 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4572 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4577 /* Control elements for the optional TCO module */
4578 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4579 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4580 HDSPM_TCO_PULL("TCO Pull", 0),
4581 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4582 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4583 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4584 HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
4588 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4591 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4595 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4596 if (hdspm->system_sample_rate > 48000) {
4597 hdspm->playback_mixer_ctls[i]->vd[0].access =
4598 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4599 SNDRV_CTL_ELEM_ACCESS_READ |
4600 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4602 hdspm->playback_mixer_ctls[i]->vd[0].access =
4603 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4604 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4606 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4607 SNDRV_CTL_EVENT_MASK_INFO,
4608 &hdspm->playback_mixer_ctls[i]->id);
4615 static int snd_hdspm_create_controls(struct snd_card *card,
4616 struct hdspm *hdspm)
4618 unsigned int idx, limit;
4620 struct snd_kcontrol *kctl;
4621 struct snd_kcontrol_new *list = NULL;
4623 switch (hdspm->io_type) {
4625 list = snd_hdspm_controls_madi;
4626 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4629 list = snd_hdspm_controls_madiface;
4630 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4633 list = snd_hdspm_controls_aio;
4634 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4637 list = snd_hdspm_controls_raydat;
4638 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4641 list = snd_hdspm_controls_aes32;
4642 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4647 for (idx = 0; idx < limit; idx++) {
4648 err = snd_ctl_add(card,
4649 snd_ctl_new1(&list[idx], hdspm));
4656 /* create simple 1:1 playback mixer controls */
4657 snd_hdspm_playback_mixer.name = "Chn";
4658 if (hdspm->system_sample_rate >= 128000) {
4659 limit = hdspm->qs_out_channels;
4660 } else if (hdspm->system_sample_rate >= 64000) {
4661 limit = hdspm->ds_out_channels;
4663 limit = hdspm->ss_out_channels;
4665 for (idx = 0; idx < limit; ++idx) {
4666 snd_hdspm_playback_mixer.index = idx + 1;
4667 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4668 err = snd_ctl_add(card, kctl);
4671 hdspm->playback_mixer_ctls[idx] = kctl;
4676 /* add tco control elements */
4677 list = snd_hdspm_controls_tco;
4678 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4679 for (idx = 0; idx < limit; idx++) {
4680 err = snd_ctl_add(card,
4681 snd_ctl_new1(&list[idx], hdspm));
4690 /*------------------------------------------------------------
4692 ------------------------------------------------------------*/
4695 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4696 struct snd_info_buffer *buffer)
4698 struct hdspm *hdspm = entry->private_data;
4699 unsigned int status, status2, control, freq;
4701 char *pref_sync_ref;
4703 char *system_clock_mode;
4708 int a, ltc, frames, seconds, minutes, hours;
4709 unsigned int period;
4713 status = hdspm_read(hdspm, HDSPM_statusRegister);
4714 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4715 control = hdspm->control_register;
4716 freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4718 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4719 hdspm->card_name, hdspm->card->number + 1,
4720 hdspm->firmware_rev,
4721 (status2 & HDSPM_version0) |
4722 (status2 & HDSPM_version1) | (status2 &
4725 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4726 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4729 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4730 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4732 snd_iprintf(buffer, "--- System ---\n");
4735 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4736 status & HDSPM_audioIRQPending,
4737 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4738 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4741 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4742 "estimated= %ld (bytes)\n",
4743 ((status & HDSPM_BufferID) ? 1 : 0),
4744 (status & HDSPM_BufferPositionMask),
4745 (status & HDSPM_BufferPositionMask) %
4746 (2 * (int)hdspm->period_bytes),
4747 ((status & HDSPM_BufferPositionMask) - 64) %
4748 (2 * (int)hdspm->period_bytes),
4749 (long) hdspm_hw_pointer(hdspm) * 4);
4752 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4753 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4754 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4755 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4756 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4758 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4759 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4760 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4762 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4764 hdspm->control_register, hdspm->control2_register,
4766 if (status & HDSPM_tco_detect) {
4767 snd_iprintf(buffer, "TCO module detected.\n");
4768 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4769 if (a & HDSPM_TCO1_LTC_Input_valid) {
4770 snd_iprintf(buffer, " LTC valid, ");
4771 switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4772 HDSPM_TCO1_LTC_Format_MSB)) {
4774 snd_iprintf(buffer, "24 fps, ");
4776 case HDSPM_TCO1_LTC_Format_LSB:
4777 snd_iprintf(buffer, "25 fps, ");
4779 case HDSPM_TCO1_LTC_Format_MSB:
4780 snd_iprintf(buffer, "29.97 fps, ");
4783 snd_iprintf(buffer, "30 fps, ");
4786 if (a & HDSPM_TCO1_set_drop_frame_flag) {
4787 snd_iprintf(buffer, "drop frame\n");
4789 snd_iprintf(buffer, "full frame\n");
4792 snd_iprintf(buffer, " no LTC\n");
4794 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4795 snd_iprintf(buffer, " Video: NTSC\n");
4796 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4797 snd_iprintf(buffer, " Video: PAL\n");
4799 snd_iprintf(buffer, " No video\n");
4801 if (a & HDSPM_TCO1_TCO_lock) {
4802 snd_iprintf(buffer, " Sync: lock\n");
4804 snd_iprintf(buffer, " Sync: no lock\n");
4807 switch (hdspm->io_type) {
4810 freq_const = 110069313433624ULL;
4814 freq_const = 104857600000000ULL;
4817 break; /* no TCO possible */
4820 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4821 snd_iprintf(buffer, " period: %u\n", period);
4824 /* rate = freq_const/period; */
4825 rate = div_u64(freq_const, period);
4827 if (control & HDSPM_QuadSpeed) {
4829 } else if (control & HDSPM_DoubleSpeed) {
4833 snd_iprintf(buffer, " Frequency: %u Hz\n",
4834 (unsigned int) rate);
4836 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4839 frames += (ltc & 0x3) * 10;
4841 seconds = ltc & 0xF;
4843 seconds += (ltc & 0x7) * 10;
4845 minutes = ltc & 0xF;
4847 minutes += (ltc & 0x7) * 10;
4851 hours += (ltc & 0x3) * 10;
4853 " LTC In: %02d:%02d:%02d:%02d\n",
4854 hours, minutes, seconds, frames);
4857 snd_iprintf(buffer, "No TCO module detected.\n");
4860 snd_iprintf(buffer, "--- Settings ---\n");
4862 x = hdspm_get_latency(hdspm);
4865 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4866 x, (unsigned long) hdspm->period_bytes);
4868 snd_iprintf(buffer, "Line out: %s\n",
4869 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4871 switch (hdspm->control_register & HDSPM_InputMask) {
4872 case HDSPM_InputOptical:
4875 case HDSPM_InputCoaxial:
4883 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4885 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4886 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4887 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4890 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4891 system_clock_mode = "AutoSync";
4893 system_clock_mode = "Master";
4894 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4896 switch (hdspm_pref_sync_ref(hdspm)) {
4897 case HDSPM_SYNC_FROM_WORD:
4898 pref_sync_ref = "Word Clock";
4900 case HDSPM_SYNC_FROM_MADI:
4901 pref_sync_ref = "MADI Sync";
4903 case HDSPM_SYNC_FROM_TCO:
4904 pref_sync_ref = "TCO";
4906 case HDSPM_SYNC_FROM_SYNC_IN:
4907 pref_sync_ref = "Sync In";
4910 pref_sync_ref = "XXXX Clock";
4913 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4916 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4917 hdspm->system_sample_rate);
4920 snd_iprintf(buffer, "--- Status:\n");
4922 x = status & HDSPM_madiSync;
4923 x2 = status2 & HDSPM_wcSync;
4925 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4926 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4928 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4931 switch (hdspm_autosync_ref(hdspm)) {
4932 case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4933 autosync_ref = "Sync In";
4935 case HDSPM_AUTOSYNC_FROM_TCO:
4936 autosync_ref = "TCO";
4938 case HDSPM_AUTOSYNC_FROM_WORD:
4939 autosync_ref = "Word Clock";
4941 case HDSPM_AUTOSYNC_FROM_MADI:
4942 autosync_ref = "MADI Sync";
4944 case HDSPM_AUTOSYNC_FROM_NONE:
4945 autosync_ref = "Input not valid";
4948 autosync_ref = "---";
4952 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4953 autosync_ref, hdspm_external_sample_rate(hdspm),
4954 (status & HDSPM_madiFreqMask) >> 22,
4955 (status2 & HDSPM_wcFreqMask) >> 5);
4957 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4958 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4959 (status & HDSPM_RX_64ch) ? "64 channels" :
4962 snd_iprintf(buffer, "\n");
4966 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4967 struct snd_info_buffer *buffer)
4969 struct hdspm *hdspm = entry->private_data;
4970 unsigned int status;
4971 unsigned int status2;
4972 unsigned int timecode;
4977 status = hdspm_read(hdspm, HDSPM_statusRegister);
4978 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4979 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4981 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4982 hdspm->card_name, hdspm->card->number + 1,
4983 hdspm->firmware_rev);
4985 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4986 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4988 snd_iprintf(buffer, "--- System ---\n");
4991 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4992 status & HDSPM_audioIRQPending,
4993 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4994 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4997 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4998 "estimated= %ld (bytes)\n",
4999 ((status & HDSPM_BufferID) ? 1 : 0),
5000 (status & HDSPM_BufferPositionMask),
5001 (status & HDSPM_BufferPositionMask) %
5002 (2 * (int)hdspm->period_bytes),
5003 ((status & HDSPM_BufferPositionMask) - 64) %
5004 (2 * (int)hdspm->period_bytes),
5005 (long) hdspm_hw_pointer(hdspm) * 4);
5008 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5009 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5010 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5011 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5012 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5014 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5015 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5016 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5018 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5020 hdspm->control_register, hdspm->control2_register,
5023 snd_iprintf(buffer, "--- Settings ---\n");
5025 x = hdspm_get_latency(hdspm);
5028 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5029 x, (unsigned long) hdspm->period_bytes);
5031 snd_iprintf(buffer, "Line out: %s\n",
5033 control_register & HDSPM_LineOut) ? "on " : "off");
5036 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5038 control_register & HDSPM_clr_tms) ? "on" : "off",
5040 control_register & HDSPM_Emphasis) ? "on" : "off",
5042 control_register & HDSPM_Dolby) ? "on" : "off");
5045 pref_syncref = hdspm_pref_sync_ref(hdspm);
5046 if (pref_syncref == 0)
5047 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5049 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5052 snd_iprintf(buffer, "System Clock Frequency: %d\n",
5053 hdspm->system_sample_rate);
5055 snd_iprintf(buffer, "Double speed: %s\n",
5056 hdspm->control_register & HDSPM_DS_DoubleWire?
5057 "Double wire" : "Single wire");
5058 snd_iprintf(buffer, "Quad speed: %s\n",
5059 hdspm->control_register & HDSPM_QS_DoubleWire?
5061 hdspm->control_register & HDSPM_QS_QuadWire?
5062 "Quad wire" : "Single wire");
5064 snd_iprintf(buffer, "--- Status:\n");
5066 snd_iprintf(buffer, "Word: %s Frequency: %d\n",
5067 (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock",
5068 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5070 for (x = 0; x < 8; x++) {
5071 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
5073 (status2 & (HDSPM_LockAES >> x)) ?
5074 "Sync " : "No Lock",
5075 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5078 switch (hdspm_autosync_ref(hdspm)) {
5079 case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5080 autosync_ref = "None"; break;
5081 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5082 autosync_ref = "Word Clock"; break;
5083 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5084 autosync_ref = "AES1"; break;
5085 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5086 autosync_ref = "AES2"; break;
5087 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5088 autosync_ref = "AES3"; break;
5089 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5090 autosync_ref = "AES4"; break;
5091 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5092 autosync_ref = "AES5"; break;
5093 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5094 autosync_ref = "AES6"; break;
5095 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5096 autosync_ref = "AES7"; break;
5097 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5098 autosync_ref = "AES8"; break;
5100 autosync_ref = "---"; break;
5102 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5104 snd_iprintf(buffer, "\n");
5108 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5109 struct snd_info_buffer *buffer)
5111 struct hdspm *hdspm = entry->private_data;
5112 unsigned int status1, status2, status3, control, i;
5113 unsigned int lock, sync;
5115 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5116 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5117 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5119 control = hdspm->control_register;
5121 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5122 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5123 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5126 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5128 snd_iprintf(buffer, "Clock mode : %s\n",
5129 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5130 snd_iprintf(buffer, "System frequency: %d Hz\n",
5131 hdspm_get_system_sample_rate(hdspm));
5133 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5138 for (i = 0; i < 8; i++) {
5139 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5141 (status1 & lock) ? 1 : 0,
5142 (status1 & sync) ? 1 : 0,
5143 texts_freq[(status2 >> (i * 4)) & 0xF]);
5149 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5150 (status1 & 0x1000000) ? 1 : 0,
5151 (status1 & 0x2000000) ? 1 : 0,
5152 texts_freq[(status1 >> 16) & 0xF]);
5154 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5155 (status1 & 0x4000000) ? 1 : 0,
5156 (status1 & 0x8000000) ? 1 : 0,
5157 texts_freq[(status1 >> 20) & 0xF]);
5159 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5160 (status3 & 0x400) ? 1 : 0,
5161 (status3 & 0x800) ? 1 : 0,
5162 texts_freq[(status2 >> 12) & 0xF]);
5166 #ifdef CONFIG_SND_DEBUG
5168 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5169 struct snd_info_buffer *buffer)
5171 struct hdspm *hdspm = entry->private_data;
5175 for (i = 0; i < 256 /* 1024*64 */; i += j) {
5176 snd_iprintf(buffer, "0x%08X: ", i);
5177 for (j = 0; j < 16; j += 4)
5178 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5179 snd_iprintf(buffer, "\n");
5185 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5186 struct snd_info_buffer *buffer)
5188 struct hdspm *hdspm = entry->private_data;
5191 snd_iprintf(buffer, "# generated by hdspm\n");
5193 for (i = 0; i < hdspm->max_channels_in; i++) {
5194 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5198 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5199 struct snd_info_buffer *buffer)
5201 struct hdspm *hdspm = entry->private_data;
5204 snd_iprintf(buffer, "# generated by hdspm\n");
5206 for (i = 0; i < hdspm->max_channels_out; i++) {
5207 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5212 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
5214 struct snd_info_entry *entry;
5216 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5217 switch (hdspm->io_type) {
5219 snd_info_set_text_ops(entry, hdspm,
5220 snd_hdspm_proc_read_aes32);
5223 snd_info_set_text_ops(entry, hdspm,
5224 snd_hdspm_proc_read_madi);
5227 /* snd_info_set_text_ops(entry, hdspm,
5228 snd_hdspm_proc_read_madiface); */
5231 snd_info_set_text_ops(entry, hdspm,
5232 snd_hdspm_proc_read_raydat);
5239 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5240 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5243 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5244 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5247 #ifdef CONFIG_SND_DEBUG
5248 /* debug file to read all hdspm registers */
5249 if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5250 snd_info_set_text_ops(entry, hdspm,
5251 snd_hdspm_proc_read_debug);
5255 /*------------------------------------------------------------
5257 ------------------------------------------------------------*/
5259 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5261 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5262 hold it (e.g. during module initialization).
5267 hdspm->settings_register = 0;
5269 switch (hdspm->io_type) {
5272 hdspm->control_register =
5273 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5278 hdspm->settings_register = 0x1 + 0x1000;
5279 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5281 hdspm->control_register =
5282 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5286 hdspm->control_register =
5287 HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5288 hdspm_encode_latency(7) | /* latency max=8192samples */
5289 HDSPM_SyncRef0 | /* AES1 is syncclock */
5290 HDSPM_LineOut | /* Analog output in */
5291 HDSPM_Professional; /* Professional mode */
5295 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5297 if (AES32 == hdspm->io_type) {
5298 /* No control2 register for AES32 */
5299 #ifdef SNDRV_BIG_ENDIAN
5300 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5302 hdspm->control2_register = 0;
5305 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5307 hdspm_compute_period_size(hdspm);
5309 /* silence everything */
5311 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5313 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5314 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5317 /* set a default rate so that the channel map is set up. */
5318 hdspm_set_rate(hdspm, 48000, 1);
5324 /*------------------------------------------------------------
5326 ------------------------------------------------------------*/
5328 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5330 struct hdspm *hdspm = (struct hdspm *) dev_id;
5331 unsigned int status;
5332 int i, audio, midi, schedule = 0;
5335 status = hdspm_read(hdspm, HDSPM_statusRegister);
5337 audio = status & HDSPM_audioIRQPending;
5338 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5339 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5341 /* now = get_cycles(); */
5343 * LAT_2..LAT_0 period counter (win) counter (mac)
5344 * 6 4096 ~256053425 ~514672358
5345 * 5 2048 ~128024983 ~257373821
5346 * 4 1024 ~64023706 ~128718089
5347 * 3 512 ~32005945 ~64385999
5348 * 2 256 ~16003039 ~32260176
5349 * 1 128 ~7998738 ~16194507
5350 * 0 64 ~3998231 ~8191558
5353 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5354 now-hdspm->last_interrupt, status & 0xFFC0);
5355 hdspm->last_interrupt = now;
5358 if (!audio && !midi)
5361 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5366 if (hdspm->capture_substream)
5367 snd_pcm_period_elapsed(hdspm->capture_substream);
5369 if (hdspm->playback_substream)
5370 snd_pcm_period_elapsed(hdspm->playback_substream);
5375 while (i < hdspm->midiPorts) {
5376 if ((hdspm_read(hdspm,
5377 hdspm->midi[i].statusIn) & 0xff) &&
5378 (status & hdspm->midi[i].irq)) {
5379 /* we disable interrupts for this input until
5380 * processing is done
5382 hdspm->control_register &= ~hdspm->midi[i].ie;
5383 hdspm_write(hdspm, HDSPM_controlRegister,
5384 hdspm->control_register);
5385 hdspm->midi[i].pending = 1;
5393 tasklet_hi_schedule(&hdspm->midi_tasklet);
5399 /*------------------------------------------------------------
5401 ------------------------------------------------------------*/
5404 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5407 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5408 return hdspm_hw_pointer(hdspm);
5412 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5414 struct snd_pcm_runtime *runtime = substream->runtime;
5415 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5416 struct snd_pcm_substream *other;
5418 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5419 other = hdspm->capture_substream;
5421 other = hdspm->playback_substream;
5424 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5426 runtime->status->hw_ptr = 0;
5428 struct snd_pcm_substream *s;
5429 struct snd_pcm_runtime *oruntime = other->runtime;
5430 snd_pcm_group_for_each_entry(s, substream) {
5432 oruntime->status->hw_ptr =
5433 runtime->status->hw_ptr;
5441 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5442 struct snd_pcm_hw_params *params)
5444 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5450 spin_lock_irq(&hdspm->lock);
5452 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5453 this_pid = hdspm->playback_pid;
5454 other_pid = hdspm->capture_pid;
5456 this_pid = hdspm->capture_pid;
5457 other_pid = hdspm->playback_pid;
5460 if (other_pid > 0 && this_pid != other_pid) {
5462 /* The other stream is open, and not by the same
5463 task as this one. Make sure that the parameters
5464 that matter are the same.
5467 if (params_rate(params) != hdspm->system_sample_rate) {
5468 spin_unlock_irq(&hdspm->lock);
5469 _snd_pcm_hw_param_setempty(params,
5470 SNDRV_PCM_HW_PARAM_RATE);
5474 if (params_period_size(params) != hdspm->period_bytes / 4) {
5475 spin_unlock_irq(&hdspm->lock);
5476 _snd_pcm_hw_param_setempty(params,
5477 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5483 spin_unlock_irq(&hdspm->lock);
5485 /* how to make sure that the rate matches an externally-set one ? */
5487 spin_lock_irq(&hdspm->lock);
5488 err = hdspm_set_rate(hdspm, params_rate(params), 0);
5490 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5491 spin_unlock_irq(&hdspm->lock);
5492 _snd_pcm_hw_param_setempty(params,
5493 SNDRV_PCM_HW_PARAM_RATE);
5496 spin_unlock_irq(&hdspm->lock);
5498 err = hdspm_set_interrupt_interval(hdspm,
5499 params_period_size(params));
5501 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5502 _snd_pcm_hw_param_setempty(params,
5503 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5507 /* Memory allocation, takashi's method, dont know if we should
5510 /* malloc all buffer even if not enabled to get sure */
5511 /* Update for MADI rev 204: we need to allocate for all channels,
5512 * otherwise it doesn't work at 96kHz */
5515 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5517 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5521 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5523 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5524 params_channels(params));
5526 for (i = 0; i < params_channels(params); ++i)
5527 snd_hdspm_enable_out(hdspm, i, 1);
5529 hdspm->playback_buffer =
5530 (unsigned char *) substream->runtime->dma_area;
5531 snd_printdd("Allocated sample buffer for playback at %p\n",
5532 hdspm->playback_buffer);
5534 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5535 params_channels(params));
5537 for (i = 0; i < params_channels(params); ++i)
5538 snd_hdspm_enable_in(hdspm, i, 1);
5540 hdspm->capture_buffer =
5541 (unsigned char *) substream->runtime->dma_area;
5542 snd_printdd("Allocated sample buffer for capture at %p\n",
5543 hdspm->capture_buffer);
5547 snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5548 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5549 "playback" : "capture",
5550 snd_pcm_sgbuf_get_addr(substream, 0));
5553 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5554 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5555 "playback" : "capture",
5556 params_rate(params), params_channels(params),
5557 params_buffer_size(params));
5561 /* Switch to native float format if requested */
5562 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5563 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5564 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5566 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5567 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5568 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5569 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5571 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5573 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5578 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5581 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5583 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5585 /* params_channels(params) should be enough,
5586 but to get sure in case of error */
5587 for (i = 0; i < hdspm->max_channels_out; ++i)
5588 snd_hdspm_enable_out(hdspm, i, 0);
5590 hdspm->playback_buffer = NULL;
5592 for (i = 0; i < hdspm->max_channels_in; ++i)
5593 snd_hdspm_enable_in(hdspm, i, 0);
5595 hdspm->capture_buffer = NULL;
5599 snd_pcm_lib_free_pages(substream);
5605 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5606 struct snd_pcm_channel_info *info)
5608 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5610 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5611 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5612 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5616 if (hdspm->channel_map_out[info->channel] < 0) {
5617 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5621 info->offset = hdspm->channel_map_out[info->channel] *
5622 HDSPM_CHANNEL_BUFFER_BYTES;
5624 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5625 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5629 if (hdspm->channel_map_in[info->channel] < 0) {
5630 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5634 info->offset = hdspm->channel_map_in[info->channel] *
5635 HDSPM_CHANNEL_BUFFER_BYTES;
5644 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5645 unsigned int cmd, void *arg)
5648 case SNDRV_PCM_IOCTL1_RESET:
5649 return snd_hdspm_reset(substream);
5651 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5653 struct snd_pcm_channel_info *info = arg;
5654 return snd_hdspm_channel_info(substream, info);
5660 return snd_pcm_lib_ioctl(substream, cmd, arg);
5663 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5665 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5666 struct snd_pcm_substream *other;
5669 spin_lock(&hdspm->lock);
5670 running = hdspm->running;
5672 case SNDRV_PCM_TRIGGER_START:
5673 running |= 1 << substream->stream;
5675 case SNDRV_PCM_TRIGGER_STOP:
5676 running &= ~(1 << substream->stream);
5680 spin_unlock(&hdspm->lock);
5683 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5684 other = hdspm->capture_substream;
5686 other = hdspm->playback_substream;
5689 struct snd_pcm_substream *s;
5690 snd_pcm_group_for_each_entry(s, substream) {
5692 snd_pcm_trigger_done(s, substream);
5693 if (cmd == SNDRV_PCM_TRIGGER_START)
5694 running |= 1 << s->stream;
5696 running &= ~(1 << s->stream);
5700 if (cmd == SNDRV_PCM_TRIGGER_START) {
5701 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5702 && substream->stream ==
5703 SNDRV_PCM_STREAM_CAPTURE)
5704 hdspm_silence_playback(hdspm);
5707 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5708 hdspm_silence_playback(hdspm);
5711 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5712 hdspm_silence_playback(hdspm);
5715 snd_pcm_trigger_done(substream, substream);
5716 if (!hdspm->running && running)
5717 hdspm_start_audio(hdspm);
5718 else if (hdspm->running && !running)
5719 hdspm_stop_audio(hdspm);
5720 hdspm->running = running;
5721 spin_unlock(&hdspm->lock);
5726 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5731 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5732 .info = (SNDRV_PCM_INFO_MMAP |
5733 SNDRV_PCM_INFO_MMAP_VALID |
5734 SNDRV_PCM_INFO_NONINTERLEAVED |
5735 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5736 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5737 .rates = (SNDRV_PCM_RATE_32000 |
5738 SNDRV_PCM_RATE_44100 |
5739 SNDRV_PCM_RATE_48000 |
5740 SNDRV_PCM_RATE_64000 |
5741 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5742 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5746 .channels_max = HDSPM_MAX_CHANNELS,
5748 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5749 .period_bytes_min = (32 * 4),
5750 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5756 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5757 .info = (SNDRV_PCM_INFO_MMAP |
5758 SNDRV_PCM_INFO_MMAP_VALID |
5759 SNDRV_PCM_INFO_NONINTERLEAVED |
5760 SNDRV_PCM_INFO_SYNC_START),
5761 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5762 .rates = (SNDRV_PCM_RATE_32000 |
5763 SNDRV_PCM_RATE_44100 |
5764 SNDRV_PCM_RATE_48000 |
5765 SNDRV_PCM_RATE_64000 |
5766 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5767 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5771 .channels_max = HDSPM_MAX_CHANNELS,
5773 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5774 .period_bytes_min = (32 * 4),
5775 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5781 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5782 struct snd_pcm_hw_rule *rule)
5784 struct hdspm *hdspm = rule->private;
5785 struct snd_interval *c =
5786 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5787 struct snd_interval *r =
5788 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5790 if (r->min > 96000 && r->max <= 192000) {
5791 struct snd_interval t = {
5792 .min = hdspm->qs_in_channels,
5793 .max = hdspm->qs_in_channels,
5796 return snd_interval_refine(c, &t);
5797 } else if (r->min > 48000 && r->max <= 96000) {
5798 struct snd_interval t = {
5799 .min = hdspm->ds_in_channels,
5800 .max = hdspm->ds_in_channels,
5803 return snd_interval_refine(c, &t);
5804 } else if (r->max < 64000) {
5805 struct snd_interval t = {
5806 .min = hdspm->ss_in_channels,
5807 .max = hdspm->ss_in_channels,
5810 return snd_interval_refine(c, &t);
5816 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5817 struct snd_pcm_hw_rule * rule)
5819 struct hdspm *hdspm = rule->private;
5820 struct snd_interval *c =
5821 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5822 struct snd_interval *r =
5823 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5825 if (r->min > 96000 && r->max <= 192000) {
5826 struct snd_interval t = {
5827 .min = hdspm->qs_out_channels,
5828 .max = hdspm->qs_out_channels,
5831 return snd_interval_refine(c, &t);
5832 } else if (r->min > 48000 && r->max <= 96000) {
5833 struct snd_interval t = {
5834 .min = hdspm->ds_out_channels,
5835 .max = hdspm->ds_out_channels,
5838 return snd_interval_refine(c, &t);
5839 } else if (r->max < 64000) {
5840 struct snd_interval t = {
5841 .min = hdspm->ss_out_channels,
5842 .max = hdspm->ss_out_channels,
5845 return snd_interval_refine(c, &t);
5851 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5852 struct snd_pcm_hw_rule * rule)
5854 struct hdspm *hdspm = rule->private;
5855 struct snd_interval *c =
5856 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5857 struct snd_interval *r =
5858 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5860 if (c->min >= hdspm->ss_in_channels) {
5861 struct snd_interval t = {
5866 return snd_interval_refine(r, &t);
5867 } else if (c->max <= hdspm->qs_in_channels) {
5868 struct snd_interval t = {
5873 return snd_interval_refine(r, &t);
5874 } else if (c->max <= hdspm->ds_in_channels) {
5875 struct snd_interval t = {
5880 return snd_interval_refine(r, &t);
5885 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5886 struct snd_pcm_hw_rule *rule)
5888 struct hdspm *hdspm = rule->private;
5889 struct snd_interval *c =
5890 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5891 struct snd_interval *r =
5892 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5894 if (c->min >= hdspm->ss_out_channels) {
5895 struct snd_interval t = {
5900 return snd_interval_refine(r, &t);
5901 } else if (c->max <= hdspm->qs_out_channels) {
5902 struct snd_interval t = {
5907 return snd_interval_refine(r, &t);
5908 } else if (c->max <= hdspm->ds_out_channels) {
5909 struct snd_interval t = {
5914 return snd_interval_refine(r, &t);
5920 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5921 struct snd_pcm_hw_rule *rule)
5923 unsigned int list[3];
5924 struct hdspm *hdspm = rule->private;
5925 struct snd_interval *c = hw_param_interval(params,
5926 SNDRV_PCM_HW_PARAM_CHANNELS);
5928 list[0] = hdspm->qs_in_channels;
5929 list[1] = hdspm->ds_in_channels;
5930 list[2] = hdspm->ss_in_channels;
5931 return snd_interval_list(c, 3, list, 0);
5934 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5935 struct snd_pcm_hw_rule *rule)
5937 unsigned int list[3];
5938 struct hdspm *hdspm = rule->private;
5939 struct snd_interval *c = hw_param_interval(params,
5940 SNDRV_PCM_HW_PARAM_CHANNELS);
5942 list[0] = hdspm->qs_out_channels;
5943 list[1] = hdspm->ds_out_channels;
5944 list[2] = hdspm->ss_out_channels;
5945 return snd_interval_list(c, 3, list, 0);
5949 static unsigned int hdspm_aes32_sample_rates[] = {
5950 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5953 static struct snd_pcm_hw_constraint_list
5954 hdspm_hw_constraints_aes32_sample_rates = {
5955 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5956 .list = hdspm_aes32_sample_rates,
5960 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5962 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5963 struct snd_pcm_runtime *runtime = substream->runtime;
5965 spin_lock_irq(&hdspm->lock);
5967 snd_pcm_set_sync(substream);
5970 runtime->hw = snd_hdspm_playback_subinfo;
5972 if (hdspm->capture_substream == NULL)
5973 hdspm_stop_audio(hdspm);
5975 hdspm->playback_pid = current->pid;
5976 hdspm->playback_substream = substream;
5978 spin_unlock_irq(&hdspm->lock);
5980 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5981 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5983 switch (hdspm->io_type) {
5986 snd_pcm_hw_constraint_minmax(runtime,
5987 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5989 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
5990 snd_pcm_hw_constraint_minmax(runtime,
5991 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5996 snd_pcm_hw_constraint_minmax(runtime,
5997 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6002 if (AES32 == hdspm->io_type) {
6003 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6004 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6005 &hdspm_hw_constraints_aes32_sample_rates);
6007 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6008 snd_hdspm_hw_rule_rate_out_channels, hdspm,
6009 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6012 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6013 snd_hdspm_hw_rule_out_channels, hdspm,
6014 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6016 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6017 snd_hdspm_hw_rule_out_channels_rate, hdspm,
6018 SNDRV_PCM_HW_PARAM_RATE, -1);
6023 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
6025 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6027 spin_lock_irq(&hdspm->lock);
6029 hdspm->playback_pid = -1;
6030 hdspm->playback_substream = NULL;
6032 spin_unlock_irq(&hdspm->lock);
6038 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6040 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6041 struct snd_pcm_runtime *runtime = substream->runtime;
6043 spin_lock_irq(&hdspm->lock);
6044 snd_pcm_set_sync(substream);
6045 runtime->hw = snd_hdspm_capture_subinfo;
6047 if (hdspm->playback_substream == NULL)
6048 hdspm_stop_audio(hdspm);
6050 hdspm->capture_pid = current->pid;
6051 hdspm->capture_substream = substream;
6053 spin_unlock_irq(&hdspm->lock);
6055 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6056 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6058 switch (hdspm->io_type) {
6061 snd_pcm_hw_constraint_minmax(runtime,
6062 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6064 snd_pcm_hw_constraint_minmax(runtime,
6065 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6070 snd_pcm_hw_constraint_minmax(runtime,
6071 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6076 if (AES32 == hdspm->io_type) {
6077 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6078 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6079 &hdspm_hw_constraints_aes32_sample_rates);
6081 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6082 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6083 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6086 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6087 snd_hdspm_hw_rule_in_channels, hdspm,
6088 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6090 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6091 snd_hdspm_hw_rule_in_channels_rate, hdspm,
6092 SNDRV_PCM_HW_PARAM_RATE, -1);
6097 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6099 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6101 spin_lock_irq(&hdspm->lock);
6103 hdspm->capture_pid = -1;
6104 hdspm->capture_substream = NULL;
6106 spin_unlock_irq(&hdspm->lock);
6110 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6112 /* we have nothing to initialize but the call is required */
6116 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6118 u32 val = readl(src);
6119 return copy_to_user(dest, &val, 4);
6122 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6123 unsigned int cmd, unsigned long arg)
6125 void __user *argp = (void __user *)arg;
6126 struct hdspm *hdspm = hw->private_data;
6127 struct hdspm_mixer_ioctl mixer;
6128 struct hdspm_config info;
6129 struct hdspm_status status;
6130 struct hdspm_version hdspm_version;
6131 struct hdspm_peak_rms *levels;
6132 struct hdspm_ltc ltc;
6133 unsigned int statusregister;
6134 long unsigned int s;
6139 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6140 levels = &hdspm->peak_rms;
6141 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6142 levels->input_peaks[i] =
6143 readl(hdspm->iobase +
6144 HDSPM_MADI_INPUT_PEAK + i*4);
6145 levels->playback_peaks[i] =
6146 readl(hdspm->iobase +
6147 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6148 levels->output_peaks[i] =
6149 readl(hdspm->iobase +
6150 HDSPM_MADI_OUTPUT_PEAK + i*4);
6152 levels->input_rms[i] =
6153 ((uint64_t) readl(hdspm->iobase +
6154 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6155 (uint64_t) readl(hdspm->iobase +
6156 HDSPM_MADI_INPUT_RMS_L + i*4);
6157 levels->playback_rms[i] =
6158 ((uint64_t)readl(hdspm->iobase +
6159 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6160 (uint64_t)readl(hdspm->iobase +
6161 HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6162 levels->output_rms[i] =
6163 ((uint64_t)readl(hdspm->iobase +
6164 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6165 (uint64_t)readl(hdspm->iobase +
6166 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6169 if (hdspm->system_sample_rate > 96000) {
6171 } else if (hdspm->system_sample_rate > 48000) {
6176 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6178 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6180 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6181 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6187 case SNDRV_HDSPM_IOCTL_GET_LTC:
6188 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6189 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6190 if (i & HDSPM_TCO1_LTC_Input_valid) {
6191 switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6192 HDSPM_TCO1_LTC_Format_MSB)) {
6194 ltc.format = fps_24;
6196 case HDSPM_TCO1_LTC_Format_LSB:
6197 ltc.format = fps_25;
6199 case HDSPM_TCO1_LTC_Format_MSB:
6200 ltc.format = fps_2997;
6206 if (i & HDSPM_TCO1_set_drop_frame_flag) {
6207 ltc.frame = drop_frame;
6209 ltc.frame = full_frame;
6212 ltc.format = format_invalid;
6213 ltc.frame = frame_invalid;
6215 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6216 ltc.input_format = ntsc;
6217 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6218 ltc.input_format = pal;
6220 ltc.input_format = no_video;
6223 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc));
6226 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6232 case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6234 memset(&info, 0, sizeof(info));
6235 spin_lock_irq(&hdspm->lock);
6236 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6237 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6239 info.system_sample_rate = hdspm->system_sample_rate;
6240 info.autosync_sample_rate =
6241 hdspm_external_sample_rate(hdspm);
6242 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6243 info.clock_source = hdspm_clock_source(hdspm);
6244 info.autosync_ref = hdspm_autosync_ref(hdspm);
6245 info.line_out = hdspm_line_out(hdspm);
6247 spin_unlock_irq(&hdspm->lock);
6248 if (copy_to_user(argp, &info, sizeof(info)))
6252 case SNDRV_HDSPM_IOCTL_GET_STATUS:
6253 memset(&status, 0, sizeof(status));
6255 status.card_type = hdspm->io_type;
6257 status.autosync_source = hdspm_autosync_ref(hdspm);
6259 status.card_clock = 110069313433624ULL;
6260 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6262 switch (hdspm->io_type) {
6265 status.card_specific.madi.sync_wc =
6266 hdspm_wc_sync_check(hdspm);
6267 status.card_specific.madi.sync_madi =
6268 hdspm_madi_sync_check(hdspm);
6269 status.card_specific.madi.sync_tco =
6270 hdspm_tco_sync_check(hdspm);
6271 status.card_specific.madi.sync_in =
6272 hdspm_sync_in_sync_check(hdspm);
6275 hdspm_read(hdspm, HDSPM_statusRegister);
6276 status.card_specific.madi.madi_input =
6277 (statusregister & HDSPM_AB_int) ? 1 : 0;
6278 status.card_specific.madi.channel_format =
6279 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6280 /* TODO: Mac driver sets it when f_s>48kHz */
6281 status.card_specific.madi.frame_format = 0;
6287 if (copy_to_user(argp, &status, sizeof(status)))
6293 case SNDRV_HDSPM_IOCTL_GET_VERSION:
6294 memset(&hdspm_version, 0, sizeof(hdspm_version));
6296 hdspm_version.card_type = hdspm->io_type;
6297 strncpy(hdspm_version.cardname, hdspm->card_name,
6298 sizeof(hdspm_version.cardname));
6299 hdspm_version.serial = hdspm->serial;
6300 hdspm_version.firmware_rev = hdspm->firmware_rev;
6301 hdspm_version.addons = 0;
6303 hdspm_version.addons |= HDSPM_ADDON_TCO;
6305 if (copy_to_user(argp, &hdspm_version,
6306 sizeof(hdspm_version)))
6310 case SNDRV_HDSPM_IOCTL_GET_MIXER:
6311 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6313 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6314 sizeof(struct hdspm_mixer)))
6324 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6325 .open = snd_hdspm_playback_open,
6326 .close = snd_hdspm_playback_release,
6327 .ioctl = snd_hdspm_ioctl,
6328 .hw_params = snd_hdspm_hw_params,
6329 .hw_free = snd_hdspm_hw_free,
6330 .prepare = snd_hdspm_prepare,
6331 .trigger = snd_hdspm_trigger,
6332 .pointer = snd_hdspm_hw_pointer,
6333 .page = snd_pcm_sgbuf_ops_page,
6336 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6337 .open = snd_hdspm_capture_open,
6338 .close = snd_hdspm_capture_release,
6339 .ioctl = snd_hdspm_ioctl,
6340 .hw_params = snd_hdspm_hw_params,
6341 .hw_free = snd_hdspm_hw_free,
6342 .prepare = snd_hdspm_prepare,
6343 .trigger = snd_hdspm_trigger,
6344 .pointer = snd_hdspm_hw_pointer,
6345 .page = snd_pcm_sgbuf_ops_page,
6348 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
6349 struct hdspm * hdspm)
6351 struct snd_hwdep *hw;
6354 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6359 hw->private_data = hdspm;
6360 strcpy(hw->name, "HDSPM hwdep interface");
6362 hw->ops.open = snd_hdspm_hwdep_dummy_op;
6363 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6364 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6365 hw->ops.release = snd_hdspm_hwdep_dummy_op;
6371 /*------------------------------------------------------------
6373 ------------------------------------------------------------*/
6374 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6377 struct snd_pcm *pcm;
6382 wanted = HDSPM_DMA_AREA_BYTES;
6385 snd_pcm_lib_preallocate_pages_for_all(pcm,
6386 SNDRV_DMA_TYPE_DEV_SG,
6387 snd_dma_pci_data(hdspm->pci),
6391 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6395 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6401 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6402 struct snd_pcm_substream *substream,
6403 unsigned int reg, int channels)
6407 /* continuous memory segment */
6408 for (i = 0; i < (channels * 16); i++)
6409 hdspm_write(hdspm, reg + 4 * i,
6410 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6414 /* ------------- ALSA Devices ---------------------------- */
6415 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
6416 struct hdspm *hdspm)
6418 struct snd_pcm *pcm;
6421 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6426 pcm->private_data = hdspm;
6427 strcpy(pcm->name, hdspm->card_name);
6429 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6430 &snd_hdspm_playback_ops);
6431 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6432 &snd_hdspm_capture_ops);
6434 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6436 err = snd_hdspm_preallocate_memory(hdspm);
6443 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6447 for (i = 0; i < hdspm->midiPorts; i++)
6448 snd_hdspm_flush_midi_input(hdspm, i);
6451 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
6452 struct hdspm * hdspm)
6456 snd_printdd("Create card...\n");
6457 err = snd_hdspm_create_pcm(card, hdspm);
6462 while (i < hdspm->midiPorts) {
6463 err = snd_hdspm_create_midi(card, hdspm, i);
6470 err = snd_hdspm_create_controls(card, hdspm);
6474 err = snd_hdspm_create_hwdep(card, hdspm);
6478 snd_printdd("proc init...\n");
6479 snd_hdspm_proc_init(hdspm);
6481 hdspm->system_sample_rate = -1;
6482 hdspm->last_external_sample_rate = -1;
6483 hdspm->last_internal_sample_rate = -1;
6484 hdspm->playback_pid = -1;
6485 hdspm->capture_pid = -1;
6486 hdspm->capture_substream = NULL;
6487 hdspm->playback_substream = NULL;
6489 snd_printdd("Set defaults...\n");
6490 err = snd_hdspm_set_defaults(hdspm);
6494 snd_printdd("Update mixer controls...\n");
6495 hdspm_update_simple_mixer_controls(hdspm);
6497 snd_printdd("Initializeing complete ???\n");
6499 err = snd_card_register(card);
6501 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6505 snd_printdd("... yes now\n");
6510 static int __devinit snd_hdspm_create(struct snd_card *card,
6511 struct hdspm *hdspm) {
6513 struct pci_dev *pci = hdspm->pci;
6515 unsigned long io_extent;
6520 spin_lock_init(&hdspm->lock);
6522 pci_read_config_word(hdspm->pci,
6523 PCI_CLASS_REVISION, &hdspm->firmware_rev);
6525 strcpy(card->mixername, "Xilinx FPGA");
6526 strcpy(card->driver, "HDSPM");
6528 switch (hdspm->firmware_rev) {
6529 case HDSPM_RAYDAT_REV:
6530 hdspm->io_type = RayDAT;
6531 hdspm->card_name = "RME RayDAT";
6532 hdspm->midiPorts = 2;
6535 hdspm->io_type = AIO;
6536 hdspm->card_name = "RME AIO";
6537 hdspm->midiPorts = 1;
6539 case HDSPM_MADIFACE_REV:
6540 hdspm->io_type = MADIface;
6541 hdspm->card_name = "RME MADIface";
6542 hdspm->midiPorts = 1;
6545 if ((hdspm->firmware_rev == 0xf0) ||
6546 ((hdspm->firmware_rev >= 0xe6) &&
6547 (hdspm->firmware_rev <= 0xea))) {
6548 hdspm->io_type = AES32;
6549 hdspm->card_name = "RME AES32";
6550 hdspm->midiPorts = 2;
6551 } else if ((hdspm->firmware_rev == 0xd2) ||
6552 ((hdspm->firmware_rev >= 0xc8) &&
6553 (hdspm->firmware_rev <= 0xcf))) {
6554 hdspm->io_type = MADI;
6555 hdspm->card_name = "RME MADI";
6556 hdspm->midiPorts = 3;
6559 "HDSPM: unknown firmware revision %x\n",
6560 hdspm->firmware_rev);
6565 err = pci_enable_device(pci);
6569 pci_set_master(hdspm->pci);
6571 err = pci_request_regions(pci, "hdspm");
6575 hdspm->port = pci_resource_start(pci, 0);
6576 io_extent = pci_resource_len(pci, 0);
6578 snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6579 hdspm->port, hdspm->port + io_extent - 1);
6581 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6582 if (!hdspm->iobase) {
6583 snd_printk(KERN_ERR "HDSPM: "
6584 "unable to remap region 0x%lx-0x%lx\n",
6585 hdspm->port, hdspm->port + io_extent - 1);
6588 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6589 (unsigned long)hdspm->iobase, hdspm->port,
6590 hdspm->port + io_extent - 1);
6592 if (request_irq(pci->irq, snd_hdspm_interrupt,
6593 IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6594 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6598 snd_printdd("use IRQ %d\n", pci->irq);
6600 hdspm->irq = pci->irq;
6602 snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6603 sizeof(struct hdspm_mixer));
6604 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6605 if (!hdspm->mixer) {
6606 snd_printk(KERN_ERR "HDSPM: "
6607 "unable to kmalloc Mixer memory of %d Bytes\n",
6608 (int)sizeof(struct hdspm_mixer));
6612 hdspm->port_names_in = NULL;
6613 hdspm->port_names_out = NULL;
6615 switch (hdspm->io_type) {
6617 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6618 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6619 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6621 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6623 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6625 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6627 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6629 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6631 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6634 hdspm->max_channels_out = hdspm->max_channels_in =
6636 hdspm->port_names_in = hdspm->port_names_out =
6638 hdspm->channel_map_in = hdspm->channel_map_out =
6645 hdspm->ss_in_channels = hdspm->ss_out_channels =
6647 hdspm->ds_in_channels = hdspm->ds_out_channels =
6649 hdspm->qs_in_channels = hdspm->qs_out_channels =
6652 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6653 channel_map_unity_ss;
6654 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6655 channel_map_unity_ss;
6656 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6657 channel_map_unity_ss;
6659 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6661 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6663 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6668 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6669 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6672 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6673 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6674 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6675 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6676 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6677 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6679 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6680 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6681 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6683 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6684 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6685 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6687 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6688 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6689 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6690 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6691 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6692 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6697 hdspm->ss_in_channels = hdspm->ss_out_channels =
6699 hdspm->ds_in_channels = hdspm->ds_out_channels =
6701 hdspm->qs_in_channels = hdspm->qs_out_channels =
6704 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6705 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6707 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6708 channel_map_raydat_ss;
6709 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6710 channel_map_raydat_ds;
6711 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6712 channel_map_raydat_qs;
6713 hdspm->channel_map_in = hdspm->channel_map_out =
6714 channel_map_raydat_ss;
6716 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6717 texts_ports_raydat_ss;
6718 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6719 texts_ports_raydat_ds;
6720 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6721 texts_ports_raydat_qs;
6729 switch (hdspm->io_type) {
6732 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6733 HDSPM_s2_tco_detect) {
6735 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6737 if (NULL != hdspm->tco) {
6738 hdspm_tco_write(hdspm);
6740 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6747 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6749 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6751 if (NULL != hdspm->tco) {
6752 hdspm_tco_write(hdspm);
6754 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6765 switch (hdspm->io_type) {
6768 hdspm->texts_autosync = texts_autosync_aes_tco;
6769 hdspm->texts_autosync_items = 10;
6771 hdspm->texts_autosync = texts_autosync_aes;
6772 hdspm->texts_autosync_items = 9;
6778 hdspm->texts_autosync = texts_autosync_madi_tco;
6779 hdspm->texts_autosync_items = 4;
6781 hdspm->texts_autosync = texts_autosync_madi;
6782 hdspm->texts_autosync_items = 3;
6792 hdspm->texts_autosync = texts_autosync_raydat_tco;
6793 hdspm->texts_autosync_items = 9;
6795 hdspm->texts_autosync = texts_autosync_raydat;
6796 hdspm->texts_autosync_items = 8;
6802 hdspm->texts_autosync = texts_autosync_aio_tco;
6803 hdspm->texts_autosync_items = 6;
6805 hdspm->texts_autosync = texts_autosync_aio;
6806 hdspm->texts_autosync_items = 5;
6812 tasklet_init(&hdspm->midi_tasklet,
6813 hdspm_midi_tasklet, (unsigned long) hdspm);
6816 if (hdspm->io_type != MADIface) {
6817 hdspm->serial = (hdspm_read(hdspm,
6818 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6819 /* id contains either a user-provided value or the default
6820 * NULL. If it's the default, we're safe to
6821 * fill card->id with the serial number.
6823 * If the serial number is 0xFFFFFF, then we're dealing with
6824 * an old PCI revision that comes without a sane number. In
6825 * this case, we don't set card->id to avoid collisions
6826 * when running with multiple cards.
6828 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6829 sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6830 snd_card_set_id(card, card->id);
6834 snd_printdd("create alsa devices.\n");
6835 err = snd_hdspm_create_alsa_devices(card, hdspm);
6839 snd_hdspm_initialize_midi_flush(hdspm);
6845 static int snd_hdspm_free(struct hdspm * hdspm)
6850 /* stop th audio, and cancel all interrupts */
6851 hdspm->control_register &=
6852 ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6853 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6854 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6855 hdspm_write(hdspm, HDSPM_controlRegister,
6856 hdspm->control_register);
6859 if (hdspm->irq >= 0)
6860 free_irq(hdspm->irq, (void *) hdspm);
6862 kfree(hdspm->mixer);
6865 iounmap(hdspm->iobase);
6868 pci_release_regions(hdspm->pci);
6870 pci_disable_device(hdspm->pci);
6875 static void snd_hdspm_card_free(struct snd_card *card)
6877 struct hdspm *hdspm = card->private_data;
6880 snd_hdspm_free(hdspm);
6884 static int __devinit snd_hdspm_probe(struct pci_dev *pci,
6885 const struct pci_device_id *pci_id)
6888 struct hdspm *hdspm;
6889 struct snd_card *card;
6892 if (dev >= SNDRV_CARDS)
6899 err = snd_card_create(index[dev], id[dev],
6900 THIS_MODULE, sizeof(struct hdspm), &card);
6904 hdspm = card->private_data;
6905 card->private_free = snd_hdspm_card_free;
6909 snd_card_set_dev(card, &pci->dev);
6911 err = snd_hdspm_create(card, hdspm);
6913 snd_card_free(card);
6917 if (hdspm->io_type != MADIface) {
6918 sprintf(card->shortname, "%s_%x",
6921 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6924 hdspm->port, hdspm->irq);
6926 sprintf(card->shortname, "%s", hdspm->card_name);
6927 sprintf(card->longname, "%s at 0x%lx, irq %d",
6928 hdspm->card_name, hdspm->port, hdspm->irq);
6931 err = snd_card_register(card);
6933 snd_card_free(card);
6937 pci_set_drvdata(pci, card);
6943 static void __devexit snd_hdspm_remove(struct pci_dev *pci)
6945 snd_card_free(pci_get_drvdata(pci));
6946 pci_set_drvdata(pci, NULL);
6949 static struct pci_driver hdspm_driver = {
6950 .name = KBUILD_MODNAME,
6951 .id_table = snd_hdspm_ids,
6952 .probe = snd_hdspm_probe,
6953 .remove = __devexit_p(snd_hdspm_remove),
6956 module_pci_driver(hdspm_driver);