ALSA: hdspm - Fix sync check reporting on all RME HDSPM cards
[linux-block.git] / sound / pci / rme9652 / hdspm.c
1 /*
2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
3  *
4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
5  *      code based on hdsp.c   Paul Davis
6  *                             Marcus Andersson
7  *                             Thomas Charbonnel
8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
9  *                                               <remy.bruno@trinnov.com>
10  *
11  *      Modified 2009-04-13 for proper metering by Florian Faber
12  *                                               <faber@faberman.de>
13  *
14  *      Modified 2009-04-14 for native float support by Florian Faber
15  *                                               <faber@faberman.de>
16  *
17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
18  *                                               <faber@faberman.de>
19  *
20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
21  *
22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
23  *
24  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
25  *
26  *   This program is free software; you can redistribute it and/or modify
27  *   it under the terms of the GNU General Public License as published by
28  *   the Free Software Foundation; either version 2 of the License, or
29  *   (at your option) any later version.
30  *
31  *   This program is distributed in the hope that it will be useful,
32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
34  *   GNU General Public License for more details.
35  *
36  *   You should have received a copy of the GNU General Public License
37  *   along with this program; if not, write to the Free Software
38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
39  *
40  */
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/module.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/math64.h>
48 #include <asm/io.h>
49
50 #include <sound/core.h>
51 #include <sound/control.h>
52 #include <sound/pcm.h>
53 #include <sound/pcm_params.h>
54 #include <sound/info.h>
55 #include <sound/asoundef.h>
56 #include <sound/rawmidi.h>
57 #include <sound/hwdep.h>
58 #include <sound/initval.h>
59
60 #include <sound/hdspm.h>
61
62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
65
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
68
69 module_param_array(id, charp, NULL, 0444);
70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
71
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
74
75
76 MODULE_AUTHOR
77 (
78         "Winfried Ritsch <ritsch_AT_iem.at>, "
79         "Paul Davis <paul@linuxaudiosystems.com>, "
80         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
81         "Remy Bruno <remy.bruno@trinnov.com>, "
82         "Florian Faber <faberman@linuxproaudio.org>, "
83         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
84 );
85 MODULE_DESCRIPTION("RME HDSPM");
86 MODULE_LICENSE("GPL");
87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
88
89 /* --- Write registers. ---
90   These are defined as byte-offsets from the iobase value.  */
91
92 #define HDSPM_WR_SETTINGS             0
93 #define HDSPM_outputBufferAddress    32
94 #define HDSPM_inputBufferAddress     36
95 #define HDSPM_controlRegister        64
96 #define HDSPM_interruptConfirmation  96
97 #define HDSPM_control2Reg            256  /* not in specs ???????? */
98 #define HDSPM_freqReg                256  /* for AES32 */
99 #define HDSPM_midiDataOut0           352  /* just believe in old code */
100 #define HDSPM_midiDataOut1           356
101 #define HDSPM_eeprom_wr              384  /* for AES32 */
102
103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
105 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
106
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut       8192
110 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
111
112 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
113
114 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
115
116 /* --- Read registers. ---
117    These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister    0
119 /*#define HDSPM_statusRegister2  96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121  * offset 192, for AES32 *and* MADI
122  * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2  192
124 #define HDSPM_timecodeRegister 128
125
126 /* AIO, RayDAT */
127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192
131
132 #define HDSPM_RD_TCO           256
133 #define HDSPM_RD_PLL_FREQ      512
134 #define HDSPM_WR_TCO           128
135
136 #define HDSPM_TCO1_TCO_lock                     0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
143
144 #define HDSPM_TCO1_set_TC                       0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
148
149 #define HDSPM_TCO2_TC_run                       0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
154 #define HDSPM_TCO2_set_jam_sync                 0x00200000
155 #define HDSPM_TCO2_set_flywheel                 0x00400000
156
157 #define HDSPM_TCO2_set_01_4                     0x01000000
158 #define HDSPM_TCO2_set_pull_down                0x02000000
159 #define HDSPM_TCO2_set_pull_up                  0x04000000
160 #define HDSPM_TCO2_set_freq                     0x08000000
161 #define HDSPM_TCO2_set_term_75R                 0x10000000
162 #define HDSPM_TCO2_set_input_LSB                0x20000000
163 #define HDSPM_TCO2_set_input_MSB                0x40000000
164 #define HDSPM_TCO2_set_freq_from_app            0x80000000
165
166
167 #define HDSPM_midiDataOut0    352
168 #define HDSPM_midiDataOut1    356
169 #define HDSPM_midiDataOut2    368
170
171 #define HDSPM_midiDataIn0     360
172 #define HDSPM_midiDataIn1     364
173 #define HDSPM_midiDataIn2     372
174 #define HDSPM_midiDataIn3     376
175
176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0  384
178 #define HDSPM_midiStatusOut1  388
179 #define HDSPM_midiStatusOut2  400
180
181 #define HDSPM_midiStatusIn0   392
182 #define HDSPM_midiStatusIn1   396
183 #define HDSPM_midiStatusIn2   404
184 #define HDSPM_midiStatusIn3   408
185
186
187 /* the meters are regular i/o-mapped registers, but offset
188    considerably from the rest. the peak registers are reset
189    when read; the least-significant 4 bits are full-scale counters;
190    the actual peak value is in the most-significant 24 bits.
191 */
192
193 #define HDSPM_MADI_INPUT_PEAK           4096
194 #define HDSPM_MADI_PLAYBACK_PEAK        4352
195 #define HDSPM_MADI_OUTPUT_PEAK          4608
196
197 #define HDSPM_MADI_INPUT_RMS_L          6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
199 #define HDSPM_MADI_OUTPUT_RMS_L         6656
200
201 #define HDSPM_MADI_INPUT_RMS_H          7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
203 #define HDSPM_MADI_OUTPUT_RMS_H         7680
204
205 /* --- Control Register bits --------- */
206 #define HDSPM_Start                (1<<0) /* start engine */
207
208 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1             (1<<2) /* where n is defined */
210 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
211
212 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
214                                           register [RayDAT, AIO] */
215
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
217
218 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
222
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
225                                      56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
227
228 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
229                                      0=off, 1=on  */ /* MADI ONLY */
230 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
231
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
233                                     * -- MADI ONLY
234                                     */
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
236
237 #define HDSPM_SyncRef2     (1<<13)
238 #define HDSPM_SyncRef3     (1<<25)
239
240 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
242                                       AES additional bits in
243                                       lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
246
247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000
251
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT         0x2000000
254
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
258
259 #define HDSPM_wclk_sel (1<<30)
260
261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
264                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical   0
267 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269                               HDSPM_SyncRef2|HDSPM_SyncRef3)
270
271 #define HDSPM_c0_SyncRef0      0x2
272 #define HDSPM_c0_SyncRef1      0x4
273 #define HDSPM_c0_SyncRef2      0x8
274 #define HDSPM_c0_SyncRef3      0x10
275 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
277
278 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO     2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3
282
283 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
289                                 HDSPM_Frequency0)
290 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
293                                  HDSPM_Frequency0)
294
295
296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK    1
299 #define HDSPM_SYNC_CHECK_SYNC    2
300
301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD      0
303 #define HDSPM_AUTOSYNC_FROM_MADI      1
304 #define HDSPM_AUTOSYNC_FROM_TCO       2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
306 #define HDSPM_AUTOSYNC_FROM_NONE      4
307
308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0         /* optical   */
310 #define HDSPM_COAXIAL 1         /* BNC */
311
312 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
314
315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
317
318 /* --- control2 register bits --- */
319 #define HDSPM_TMS             (1<<0)
320 #define HDSPM_TCK             (1<<1)
321 #define HDSPM_TDI             (1<<2)
322 #define HDSPM_JTAG            (1<<3)
323 #define HDSPM_PWDN            (1<<4)
324 #define HDSPM_PROGRAM         (1<<5)
325 #define HDSPM_CONFIG_MODE_0   (1<<6)
326 #define HDSPM_CONFIG_MODE_1   (1<<7)
327 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE  (1<<9)
329 #define HDSPM_RD_MULTIPLE     (1<<10)
330
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332      that do not conflict with specific bits for AES32 seem to be valid also
333      for the AES32
334  */
335 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
338                                          * (like inp0)
339                                          */
340
341 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
343
344 #define HDSPM_tcoLock    0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status */
346
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
349
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351                         /* since 64byte accurate, last 6 bits are not used */
352
353
354
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
356
357 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
361
362 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
363                                          * Interrupt
364                                          */
365 #define HDSPM_tco_detect         0x08000000
366 #define HDSPM_tco_lock           0x20000000
367
368 #define HDSPM_s2_tco_detect      0x00000040
369 #define HDSPM_s2_AEBO_D          0x00000080
370 #define HDSPM_s2_AEBI_D          0x00000100
371
372
373 #define HDSPM_midi0IRQPending    0x40000000
374 #define HDSPM_midi1IRQPending    0x80000000
375 #define HDSPM_midi2IRQPending    0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending    0x00200000
378
379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381                              HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
391
392 /* Status2 Register bits */ /* MADI ONLY */
393
394 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
395 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2)
397
398 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
400
401 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
402 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, */
404 /* missing Bit   for               111=128, 1000=176.4, 1001=192 */
405
406 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000
408
409 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
412
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
414
415 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
417 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
418 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
419 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
420 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
421 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
422
423 #define HDSPM_status1_F_0 0x0400000
424 #define HDSPM_status1_F_1 0x0800000
425 #define HDSPM_status1_F_2 0x1000000
426 #define HDSPM_status1_F_3 0x2000000
427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
428
429
430 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
431                                     HDSPM_SelSyncRef2)
432 #define HDSPM_SelSyncRef_WORD      0
433 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
434 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
435 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
437                                     HDSPM_SelSyncRef2)
438
439 /*
440    For AES32, bits for status, status2 and timecode are different
441 */
442 /* status */
443 #define HDSPM_AES32_wcLock      0x0200000
444 #define HDSPM_AES32_wcFreq_bit  22
445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
446   HDSPM_bit2freq */
447 #define HDSPM_AES32_syncref_bit  16
448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
449
450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
460
461 /*  status2 */
462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
463 #define HDSPM_LockAES   0x80
464 #define HDSPM_LockAES1  0x80
465 #define HDSPM_LockAES2  0x40
466 #define HDSPM_LockAES3  0x20
467 #define HDSPM_LockAES4  0x10
468 #define HDSPM_LockAES5  0x8
469 #define HDSPM_LockAES6  0x4
470 #define HDSPM_LockAES7  0x2
471 #define HDSPM_LockAES8  0x1
472 /*
473    Timecode
474    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
475    AES i+1
476  bits 3210
477       0001  32kHz
478       0010  44.1kHz
479       0011  48kHz
480       0100  64kHz
481       0101  88.2kHz
482       0110  96kHz
483       0111  128kHz
484       1000  176.4kHz
485       1001  192kHz
486   NB: Timecode register doesn't seem to work on AES32 card revision 230
487 */
488
489 /* Mixer Values */
490 #define UNITY_GAIN          32768       /* = 65536/2 */
491 #define MINUS_INFINITY_GAIN 0
492
493 /* Number of channels for different Speed Modes */
494 #define MADI_SS_CHANNELS       64
495 #define MADI_DS_CHANNELS       32
496 #define MADI_QS_CHANNELS       16
497
498 #define RAYDAT_SS_CHANNELS     36
499 #define RAYDAT_DS_CHANNELS     20
500 #define RAYDAT_QS_CHANNELS     12
501
502 #define AIO_IN_SS_CHANNELS        14
503 #define AIO_IN_DS_CHANNELS        10
504 #define AIO_IN_QS_CHANNELS        8
505 #define AIO_OUT_SS_CHANNELS        16
506 #define AIO_OUT_DS_CHANNELS        12
507 #define AIO_OUT_QS_CHANNELS        10
508
509 #define AES32_CHANNELS          16
510
511 /* the size of a substream (1 mono data stream) */
512 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
513 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
514
515 /* the size of the area we need to allocate for DMA transfers. the
516    size is the same regardless of the number of channels, and
517    also the latency to use.
518    for one direction !!!
519 */
520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
522
523 #define HDSPM_RAYDAT_REV        211
524 #define HDSPM_AIO_REV           212
525 #define HDSPM_MADIFACE_REV      213
526
527 /* speed factor modes */
528 #define HDSPM_SPEED_SINGLE 0
529 #define HDSPM_SPEED_DOUBLE 1
530 #define HDSPM_SPEED_QUAD   2
531
532 /* names for speed modes */
533 static char *hdspm_speed_names[] = { "single", "double", "quad" };
534
535 static char *texts_autosync_aes_tco[] = { "Word Clock",
536                                           "AES1", "AES2", "AES3", "AES4",
537                                           "AES5", "AES6", "AES7", "AES8",
538                                           "TCO" };
539 static char *texts_autosync_aes[] = { "Word Clock",
540                                       "AES1", "AES2", "AES3", "AES4",
541                                       "AES5", "AES6", "AES7", "AES8" };
542 static char *texts_autosync_madi_tco[] = { "Word Clock",
543                                            "MADI", "TCO", "Sync In" };
544 static char *texts_autosync_madi[] = { "Word Clock",
545                                        "MADI", "Sync In" };
546
547 static char *texts_autosync_raydat_tco[] = {
548         "Word Clock",
549         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
550         "AES", "SPDIF", "TCO", "Sync In"
551 };
552 static char *texts_autosync_raydat[] = {
553         "Word Clock",
554         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
555         "AES", "SPDIF", "Sync In"
556 };
557 static char *texts_autosync_aio_tco[] = {
558         "Word Clock",
559         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
560 };
561 static char *texts_autosync_aio[] = { "Word Clock",
562                                       "ADAT", "AES", "SPDIF", "Sync In" };
563
564 static char *texts_freq[] = {
565         "No Lock",
566         "32 kHz",
567         "44.1 kHz",
568         "48 kHz",
569         "64 kHz",
570         "88.2 kHz",
571         "96 kHz",
572         "128 kHz",
573         "176.4 kHz",
574         "192 kHz"
575 };
576
577 static char *texts_ports_madi[] = {
578         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
579         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
580         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
581         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
582         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
583         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
584         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
585         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
586         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
587         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
588         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
589 };
590
591
592 static char *texts_ports_raydat_ss[] = {
593         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
594         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
595         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
596         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
597         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
598         "ADAT4.7", "ADAT4.8",
599         "AES.L", "AES.R",
600         "SPDIF.L", "SPDIF.R"
601 };
602
603 static char *texts_ports_raydat_ds[] = {
604         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
605         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
606         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
607         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
608         "AES.L", "AES.R",
609         "SPDIF.L", "SPDIF.R"
610 };
611
612 static char *texts_ports_raydat_qs[] = {
613         "ADAT1.1", "ADAT1.2",
614         "ADAT2.1", "ADAT2.2",
615         "ADAT3.1", "ADAT3.2",
616         "ADAT4.1", "ADAT4.2",
617         "AES.L", "AES.R",
618         "SPDIF.L", "SPDIF.R"
619 };
620
621
622 static char *texts_ports_aio_in_ss[] = {
623         "Analogue.L", "Analogue.R",
624         "AES.L", "AES.R",
625         "SPDIF.L", "SPDIF.R",
626         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
627         "ADAT.7", "ADAT.8"
628 };
629
630 static char *texts_ports_aio_out_ss[] = {
631         "Analogue.L", "Analogue.R",
632         "AES.L", "AES.R",
633         "SPDIF.L", "SPDIF.R",
634         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
635         "ADAT.7", "ADAT.8",
636         "Phone.L", "Phone.R"
637 };
638
639 static char *texts_ports_aio_in_ds[] = {
640         "Analogue.L", "Analogue.R",
641         "AES.L", "AES.R",
642         "SPDIF.L", "SPDIF.R",
643         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
644 };
645
646 static char *texts_ports_aio_out_ds[] = {
647         "Analogue.L", "Analogue.R",
648         "AES.L", "AES.R",
649         "SPDIF.L", "SPDIF.R",
650         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
651         "Phone.L", "Phone.R"
652 };
653
654 static char *texts_ports_aio_in_qs[] = {
655         "Analogue.L", "Analogue.R",
656         "AES.L", "AES.R",
657         "SPDIF.L", "SPDIF.R",
658         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
659 };
660
661 static char *texts_ports_aio_out_qs[] = {
662         "Analogue.L", "Analogue.R",
663         "AES.L", "AES.R",
664         "SPDIF.L", "SPDIF.R",
665         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
666         "Phone.L", "Phone.R"
667 };
668
669 static char *texts_ports_aes32[] = {
670         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
671         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
672         "AES.15", "AES.16"
673 };
674
675 /* These tables map the ALSA channels 1..N to the channels that we
676    need to use in order to find the relevant channel buffer. RME
677    refers to this kind of mapping as between "the ADAT channel and
678    the DMA channel." We index it using the logical audio channel,
679    and the value is the DMA channel (i.e. channel buffer number)
680    where the data for that channel can be read/written from/to.
681 */
682
683 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
684         0, 1, 2, 3, 4, 5, 6, 7,
685         8, 9, 10, 11, 12, 13, 14, 15,
686         16, 17, 18, 19, 20, 21, 22, 23,
687         24, 25, 26, 27, 28, 29, 30, 31,
688         32, 33, 34, 35, 36, 37, 38, 39,
689         40, 41, 42, 43, 44, 45, 46, 47,
690         48, 49, 50, 51, 52, 53, 54, 55,
691         56, 57, 58, 59, 60, 61, 62, 63
692 };
693
694 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
695         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
696         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
697         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
698         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
699         0, 1,                   /* AES */
700         2, 3,                   /* SPDIF */
701         -1, -1, -1, -1,
702         -1, -1, -1, -1, -1, -1, -1, -1,
703         -1, -1, -1, -1, -1, -1, -1, -1,
704         -1, -1, -1, -1, -1, -1, -1, -1,
705 };
706
707 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
708         4, 5, 6, 7,             /* ADAT 1 */
709         8, 9, 10, 11,           /* ADAT 2 */
710         12, 13, 14, 15,         /* ADAT 3 */
711         16, 17, 18, 19,         /* ADAT 4 */
712         0, 1,                   /* AES */
713         2, 3,                   /* SPDIF */
714         -1, -1, -1, -1,
715         -1, -1, -1, -1, -1, -1, -1, -1,
716         -1, -1, -1, -1, -1, -1, -1, -1,
717         -1, -1, -1, -1, -1, -1, -1, -1,
718         -1, -1, -1, -1, -1, -1, -1, -1,
719         -1, -1, -1, -1, -1, -1, -1, -1,
720 };
721
722 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
723         4, 5,                   /* ADAT 1 */
724         6, 7,                   /* ADAT 2 */
725         8, 9,                   /* ADAT 3 */
726         10, 11,                 /* ADAT 4 */
727         0, 1,                   /* AES */
728         2, 3,                   /* SPDIF */
729         -1, -1, -1, -1,
730         -1, -1, -1, -1, -1, -1, -1, -1,
731         -1, -1, -1, -1, -1, -1, -1, -1,
732         -1, -1, -1, -1, -1, -1, -1, -1,
733         -1, -1, -1, -1, -1, -1, -1, -1,
734         -1, -1, -1, -1, -1, -1, -1, -1,
735         -1, -1, -1, -1, -1, -1, -1, -1,
736 };
737
738 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
739         0, 1,                   /* line in */
740         8, 9,                   /* aes in, */
741         10, 11,                 /* spdif in */
742         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
743         -1, -1,
744         -1, -1, -1, -1, -1, -1, -1, -1,
745         -1, -1, -1, -1, -1, -1, -1, -1,
746         -1, -1, -1, -1, -1, -1, -1, -1,
747         -1, -1, -1, -1, -1, -1, -1, -1,
748         -1, -1, -1, -1, -1, -1, -1, -1,
749         -1, -1, -1, -1, -1, -1, -1, -1,
750 };
751
752 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
753         0, 1,                   /* line out */
754         8, 9,                   /* aes out */
755         10, 11,                 /* spdif out */
756         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
757         6, 7,                   /* phone out */
758         -1, -1, -1, -1, -1, -1, -1, -1,
759         -1, -1, -1, -1, -1, -1, -1, -1,
760         -1, -1, -1, -1, -1, -1, -1, -1,
761         -1, -1, -1, -1, -1, -1, -1, -1,
762         -1, -1, -1, -1, -1, -1, -1, -1,
763         -1, -1, -1, -1, -1, -1, -1, -1,
764 };
765
766 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
767         0, 1,                   /* line in */
768         8, 9,                   /* aes in */
769         10, 11,                 /* spdif in */
770         12, 14, 16, 18,         /* adat in */
771         -1, -1, -1, -1, -1, -1,
772         -1, -1, -1, -1, -1, -1, -1, -1,
773         -1, -1, -1, -1, -1, -1, -1, -1,
774         -1, -1, -1, -1, -1, -1, -1, -1,
775         -1, -1, -1, -1, -1, -1, -1, -1,
776         -1, -1, -1, -1, -1, -1, -1, -1,
777         -1, -1, -1, -1, -1, -1, -1, -1
778 };
779
780 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
781         0, 1,                   /* line out */
782         8, 9,                   /* aes out */
783         10, 11,                 /* spdif out */
784         12, 14, 16, 18,         /* adat out */
785         6, 7,                   /* phone out */
786         -1, -1, -1, -1,
787         -1, -1, -1, -1, -1, -1, -1, -1,
788         -1, -1, -1, -1, -1, -1, -1, -1,
789         -1, -1, -1, -1, -1, -1, -1, -1,
790         -1, -1, -1, -1, -1, -1, -1, -1,
791         -1, -1, -1, -1, -1, -1, -1, -1,
792         -1, -1, -1, -1, -1, -1, -1, -1
793 };
794
795 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
796         0, 1,                   /* line in */
797         8, 9,                   /* aes in */
798         10, 11,                 /* spdif in */
799         12, 16,                 /* adat in */
800         -1, -1, -1, -1, -1, -1, -1, -1,
801         -1, -1, -1, -1, -1, -1, -1, -1,
802         -1, -1, -1, -1, -1, -1, -1, -1,
803         -1, -1, -1, -1, -1, -1, -1, -1,
804         -1, -1, -1, -1, -1, -1, -1, -1,
805         -1, -1, -1, -1, -1, -1, -1, -1,
806         -1, -1, -1, -1, -1, -1, -1, -1
807 };
808
809 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
810         0, 1,                   /* line out */
811         8, 9,                   /* aes out */
812         10, 11,                 /* spdif out */
813         12, 16,                 /* adat out */
814         6, 7,                   /* phone out */
815         -1, -1, -1, -1, -1, -1,
816         -1, -1, -1, -1, -1, -1, -1, -1,
817         -1, -1, -1, -1, -1, -1, -1, -1,
818         -1, -1, -1, -1, -1, -1, -1, -1,
819         -1, -1, -1, -1, -1, -1, -1, -1,
820         -1, -1, -1, -1, -1, -1, -1, -1,
821         -1, -1, -1, -1, -1, -1, -1, -1
822 };
823
824 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
825         0, 1, 2, 3, 4, 5, 6, 7,
826         8, 9, 10, 11, 12, 13, 14, 15,
827         -1, -1, -1, -1, -1, -1, -1, -1,
828         -1, -1, -1, -1, -1, -1, -1, -1,
829         -1, -1, -1, -1, -1, -1, -1, -1,
830         -1, -1, -1, -1, -1, -1, -1, -1,
831         -1, -1, -1, -1, -1, -1, -1, -1,
832         -1, -1, -1, -1, -1, -1, -1, -1
833 };
834
835 struct hdspm_midi {
836         struct hdspm *hdspm;
837         int id;
838         struct snd_rawmidi *rmidi;
839         struct snd_rawmidi_substream *input;
840         struct snd_rawmidi_substream *output;
841         char istimer;           /* timer in use */
842         struct timer_list timer;
843         spinlock_t lock;
844         int pending;
845         int dataIn;
846         int statusIn;
847         int dataOut;
848         int statusOut;
849         int ie;
850         int irq;
851 };
852
853 struct hdspm_tco {
854         int input;
855         int framerate;
856         int wordclock;
857         int samplerate;
858         int pull;
859         int term; /* 0 = off, 1 = on */
860 };
861
862 struct hdspm {
863         spinlock_t lock;
864         /* only one playback and/or capture stream */
865         struct snd_pcm_substream *capture_substream;
866         struct snd_pcm_substream *playback_substream;
867
868         char *card_name;             /* for procinfo */
869         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
870
871         uint8_t io_type;
872
873         int monitor_outs;       /* set up monitoring outs init flag */
874
875         u32 control_register;   /* cached value */
876         u32 control2_register;  /* cached value */
877         u32 settings_register;
878
879         struct hdspm_midi midi[4];
880         struct tasklet_struct midi_tasklet;
881
882         size_t period_bytes;
883         unsigned char ss_in_channels;
884         unsigned char ds_in_channels;
885         unsigned char qs_in_channels;
886         unsigned char ss_out_channels;
887         unsigned char ds_out_channels;
888         unsigned char qs_out_channels;
889
890         unsigned char max_channels_in;
891         unsigned char max_channels_out;
892
893         signed char *channel_map_in;
894         signed char *channel_map_out;
895
896         signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
897         signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
898
899         char **port_names_in;
900         char **port_names_out;
901
902         char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
903         char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
904
905         unsigned char *playback_buffer; /* suitably aligned address */
906         unsigned char *capture_buffer;  /* suitably aligned address */
907
908         pid_t capture_pid;      /* process id which uses capture */
909         pid_t playback_pid;     /* process id which uses capture */
910         int running;            /* running status */
911
912         int last_external_sample_rate;  /* samplerate mystic ... */
913         int last_internal_sample_rate;
914         int system_sample_rate;
915
916         int dev;                /* Hardware vars... */
917         int irq;
918         unsigned long port;
919         void __iomem *iobase;
920
921         int irq_count;          /* for debug */
922         int midiPorts;
923
924         struct snd_card *card;  /* one card */
925         struct snd_pcm *pcm;            /* has one pcm */
926         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
927         struct pci_dev *pci;    /* and an pci info */
928
929         /* Mixer vars */
930         /* fast alsa mixer */
931         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
932         /* but input to much, so not used */
933         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
934         /* full mixer accessible over mixer ioctl or hwdep-device */
935         struct hdspm_mixer *mixer;
936
937         struct hdspm_tco *tco;  /* NULL if no TCO detected */
938
939         char **texts_autosync;
940         int texts_autosync_items;
941
942         cycles_t last_interrupt;
943
944         unsigned int serial;
945
946         struct hdspm_peak_rms peak_rms;
947 };
948
949
950 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
951         {
952          .vendor = PCI_VENDOR_ID_XILINX,
953          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
954          .subvendor = PCI_ANY_ID,
955          .subdevice = PCI_ANY_ID,
956          .class = 0,
957          .class_mask = 0,
958          .driver_data = 0},
959         {0,}
960 };
961
962 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
963
964 /* prototypes */
965 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
966                                                    struct hdspm * hdspm);
967 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
968                                           struct hdspm * hdspm);
969
970 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
971 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
972 static int hdspm_autosync_ref(struct hdspm *hdspm);
973 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
974 static int hdspm_system_clock_mode(struct hdspm *hdspm);
975 static void hdspm_set_sgbuf(struct hdspm *hdspm,
976                             struct snd_pcm_substream *substream,
977                              unsigned int reg, int channels);
978
979 static inline int HDSPM_bit2freq(int n)
980 {
981         static const int bit2freq_tab[] = {
982                 0, 32000, 44100, 48000, 64000, 88200,
983                 96000, 128000, 176400, 192000 };
984         if (n < 1 || n > 9)
985                 return 0;
986         return bit2freq_tab[n];
987 }
988
989 /* Write/read to/from HDSPM with Adresses in Bytes
990    not words but only 32Bit writes are allowed */
991
992 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
993                                unsigned int val)
994 {
995         writel(val, hdspm->iobase + reg);
996 }
997
998 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
999 {
1000         return readl(hdspm->iobase + reg);
1001 }
1002
1003 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1004    mixer is write only on hardware so we have to cache him for read
1005    each fader is a u32, but uses only the first 16 bit */
1006
1007 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1008                                      unsigned int in)
1009 {
1010         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1011                 return 0;
1012
1013         return hdspm->mixer->ch[chan].in[in];
1014 }
1015
1016 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1017                                      unsigned int pb)
1018 {
1019         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1020                 return 0;
1021         return hdspm->mixer->ch[chan].pb[pb];
1022 }
1023
1024 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1025                                       unsigned int in, unsigned short data)
1026 {
1027         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1028                 return -1;
1029
1030         hdspm_write(hdspm,
1031                     HDSPM_MADI_mixerBase +
1032                     ((in + 128 * chan) * sizeof(u32)),
1033                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1034         return 0;
1035 }
1036
1037 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1038                                       unsigned int pb, unsigned short data)
1039 {
1040         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1041                 return -1;
1042
1043         hdspm_write(hdspm,
1044                     HDSPM_MADI_mixerBase +
1045                     ((64 + pb + 128 * chan) * sizeof(u32)),
1046                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1047         return 0;
1048 }
1049
1050
1051 /* enable DMA for specific channels, now available for DSP-MADI */
1052 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1053 {
1054         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1055 }
1056
1057 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1058 {
1059         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1060 }
1061
1062 /* check if same process is writing and reading */
1063 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1064 {
1065         unsigned long flags;
1066         int ret = 1;
1067
1068         spin_lock_irqsave(&hdspm->lock, flags);
1069         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1070             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1071                 ret = 0;
1072         }
1073         spin_unlock_irqrestore(&hdspm->lock, flags);
1074         return ret;
1075 }
1076
1077 /* check for external sample rate */
1078 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1079 {
1080         unsigned int status, status2, timecode;
1081         int syncref, rate = 0, rate_bits;
1082
1083         switch (hdspm->io_type) {
1084         case AES32:
1085                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1086                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1087                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1088
1089                 syncref = hdspm_autosync_ref(hdspm);
1090
1091                 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1092                                 status & HDSPM_AES32_wcLock)
1093                         return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1094
1095                 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1096                                 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1097                                 status2 & (HDSPM_LockAES >>
1098                                 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1099                         return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1100                 return 0;
1101                 break;
1102
1103         case MADIface:
1104                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1105
1106                 if (!(status & HDSPM_madiLock)) {
1107                         rate = 0;  /* no lock */
1108                 } else {
1109                         switch (status & (HDSPM_status1_freqMask)) {
1110                         case HDSPM_status1_F_0*1:
1111                                 rate = 32000; break;
1112                         case HDSPM_status1_F_0*2:
1113                                 rate = 44100; break;
1114                         case HDSPM_status1_F_0*3:
1115                                 rate = 48000; break;
1116                         case HDSPM_status1_F_0*4:
1117                                 rate = 64000; break;
1118                         case HDSPM_status1_F_0*5:
1119                                 rate = 88200; break;
1120                         case HDSPM_status1_F_0*6:
1121                                 rate = 96000; break;
1122                         case HDSPM_status1_F_0*7:
1123                                 rate = 128000; break;
1124                         case HDSPM_status1_F_0*8:
1125                                 rate = 176400; break;
1126                         case HDSPM_status1_F_0*9:
1127                                 rate = 192000; break;
1128                         default:
1129                                 rate = 0; break;
1130                         }
1131                 }
1132
1133                 break;
1134
1135         case MADI:
1136         case AIO:
1137         case RayDAT:
1138                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1139                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1140                 rate = 0;
1141
1142                 /* if wordclock has synced freq and wordclock is valid */
1143                 if ((status2 & HDSPM_wcLock) != 0 &&
1144                                 (status2 & HDSPM_SelSyncRef0) == 0) {
1145
1146                         rate_bits = status2 & HDSPM_wcFreqMask;
1147
1148
1149                         switch (rate_bits) {
1150                         case HDSPM_wcFreq32:
1151                                 rate = 32000;
1152                                 break;
1153                         case HDSPM_wcFreq44_1:
1154                                 rate = 44100;
1155                                 break;
1156                         case HDSPM_wcFreq48:
1157                                 rate = 48000;
1158                                 break;
1159                         case HDSPM_wcFreq64:
1160                                 rate = 64000;
1161                                 break;
1162                         case HDSPM_wcFreq88_2:
1163                                 rate = 88200;
1164                                 break;
1165                         case HDSPM_wcFreq96:
1166                                 rate = 96000;
1167                                 break;
1168                         default:
1169                                 rate = 0;
1170                                 break;
1171                         }
1172                 }
1173
1174                 /* if rate detected and Syncref is Word than have it,
1175                  * word has priority to MADI
1176                  */
1177                 if (rate != 0 &&
1178                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1179                         return rate;
1180
1181                 /* maybe a madi input (which is taken if sel sync is madi) */
1182                 if (status & HDSPM_madiLock) {
1183                         rate_bits = status & HDSPM_madiFreqMask;
1184
1185                         switch (rate_bits) {
1186                         case HDSPM_madiFreq32:
1187                                 rate = 32000;
1188                                 break;
1189                         case HDSPM_madiFreq44_1:
1190                                 rate = 44100;
1191                                 break;
1192                         case HDSPM_madiFreq48:
1193                                 rate = 48000;
1194                                 break;
1195                         case HDSPM_madiFreq64:
1196                                 rate = 64000;
1197                                 break;
1198                         case HDSPM_madiFreq88_2:
1199                                 rate = 88200;
1200                                 break;
1201                         case HDSPM_madiFreq96:
1202                                 rate = 96000;
1203                                 break;
1204                         case HDSPM_madiFreq128:
1205                                 rate = 128000;
1206                                 break;
1207                         case HDSPM_madiFreq176_4:
1208                                 rate = 176400;
1209                                 break;
1210                         case HDSPM_madiFreq192:
1211                                 rate = 192000;
1212                                 break;
1213                         default:
1214                                 rate = 0;
1215                                 break;
1216                         }
1217
1218                         /* QS and DS rates normally can not be detected
1219                          * automatically by the card. Only exception is MADI
1220                          * in 96k frame mode.
1221                          *
1222                          * So if we read SS values (32 .. 48k), check for
1223                          * user-provided DS/QS bits in the control register
1224                          * and multiply the base frequency accordingly.
1225                          */
1226                         if (rate <= 48000) {
1227                                 if (hdspm->control_register & HDSPM_QuadSpeed)
1228                                         rate *= 4;
1229                                 else if (hdspm->control_register &
1230                                                 HDSPM_DoubleSpeed)
1231                                         rate *= 2;
1232                         }
1233                 }
1234                 break;
1235         }
1236
1237         return rate;
1238 }
1239
1240 /* return latency in samples per period */
1241 static int hdspm_get_latency(struct hdspm *hdspm)
1242 {
1243         int n;
1244
1245         n = hdspm_decode_latency(hdspm->control_register);
1246
1247         /* Special case for new RME cards with 32 samples period size.
1248          * The three latency bits in the control register
1249          * (HDSP_LatencyMask) encode latency values of 64 samples as
1250          * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1251          * denotes 8192 samples, but on new cards like RayDAT or AIO,
1252          * it corresponds to 32 samples.
1253          */
1254         if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1255                 n = -1;
1256
1257         return 1 << (n + 6);
1258 }
1259
1260 /* Latency function */
1261 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1262 {
1263         hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1264 }
1265
1266
1267 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1268 {
1269         int position;
1270
1271         position = hdspm_read(hdspm, HDSPM_statusRegister);
1272
1273         switch (hdspm->io_type) {
1274         case RayDAT:
1275         case AIO:
1276                 position &= HDSPM_BufferPositionMask;
1277                 position /= 4; /* Bytes per sample */
1278                 break;
1279         default:
1280                 position = (position & HDSPM_BufferID) ?
1281                         (hdspm->period_bytes / 4) : 0;
1282         }
1283
1284         return position;
1285 }
1286
1287
1288 static inline void hdspm_start_audio(struct hdspm * s)
1289 {
1290         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1291         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1292 }
1293
1294 static inline void hdspm_stop_audio(struct hdspm * s)
1295 {
1296         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1297         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1298 }
1299
1300 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1301 static void hdspm_silence_playback(struct hdspm *hdspm)
1302 {
1303         int i;
1304         int n = hdspm->period_bytes;
1305         void *buf = hdspm->playback_buffer;
1306
1307         if (buf == NULL)
1308                 return;
1309
1310         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1311                 memset(buf, 0, n);
1312                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1313         }
1314 }
1315
1316 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1317 {
1318         int n;
1319
1320         spin_lock_irq(&s->lock);
1321
1322         if (32 == frames) {
1323                 /* Special case for new RME cards like RayDAT/AIO which
1324                  * support period sizes of 32 samples. Since latency is
1325                  * encoded in the three bits of HDSP_LatencyMask, we can only
1326                  * have values from 0 .. 7. While 0 still means 64 samples and
1327                  * 6 represents 4096 samples on all cards, 7 represents 8192
1328                  * on older cards and 32 samples on new cards.
1329                  *
1330                  * In other words, period size in samples is calculated by
1331                  * 2^(n+6) with n ranging from 0 .. 7.
1332                  */
1333                 n = 7;
1334         } else {
1335                 frames >>= 7;
1336                 n = 0;
1337                 while (frames) {
1338                         n++;
1339                         frames >>= 1;
1340                 }
1341         }
1342
1343         s->control_register &= ~HDSPM_LatencyMask;
1344         s->control_register |= hdspm_encode_latency(n);
1345
1346         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1347
1348         hdspm_compute_period_size(s);
1349
1350         spin_unlock_irq(&s->lock);
1351
1352         return 0;
1353 }
1354
1355 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1356 {
1357         u64 freq_const;
1358
1359         if (period == 0)
1360                 return 0;
1361
1362         switch (hdspm->io_type) {
1363         case MADI:
1364         case AES32:
1365                 freq_const = 110069313433624ULL;
1366                 break;
1367         case RayDAT:
1368         case AIO:
1369                 freq_const = 104857600000000ULL;
1370                 break;
1371         case MADIface:
1372                 freq_const = 131072000000000ULL;
1373                 break;
1374         default:
1375                 snd_BUG();
1376                 return 0;
1377         }
1378
1379         return div_u64(freq_const, period);
1380 }
1381
1382
1383 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1384 {
1385         u64 n;
1386
1387         if (rate >= 112000)
1388                 rate /= 4;
1389         else if (rate >= 56000)
1390                 rate /= 2;
1391
1392         switch (hdspm->io_type) {
1393         case MADIface:
1394                 n = 131072000000000ULL;  /* 125 MHz */
1395                 break;
1396         case MADI:
1397         case AES32:
1398                 n = 110069313433624ULL;  /* 105 MHz */
1399                 break;
1400         case RayDAT:
1401         case AIO:
1402                 n = 104857600000000ULL;  /* 100 MHz */
1403                 break;
1404         default:
1405                 snd_BUG();
1406                 return;
1407         }
1408
1409         n = div_u64(n, rate);
1410         /* n should be less than 2^32 for being written to FREQ register */
1411         snd_BUG_ON(n >> 32);
1412         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1413 }
1414
1415 /* dummy set rate lets see what happens */
1416 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1417 {
1418         int current_rate;
1419         int rate_bits;
1420         int not_set = 0;
1421         int current_speed, target_speed;
1422
1423         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1424            it (e.g. during module initialization).
1425          */
1426
1427         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1428
1429                 /* SLAVE --- */
1430                 if (called_internally) {
1431
1432                         /* request from ctl or card initialization
1433                            just make a warning an remember setting
1434                            for future master mode switching */
1435
1436                         snd_printk(KERN_WARNING "HDSPM: "
1437                                    "Warning: device is not running "
1438                                    "as a clock master.\n");
1439                         not_set = 1;
1440                 } else {
1441
1442                         /* hw_param request while in AutoSync mode */
1443                         int external_freq =
1444                             hdspm_external_sample_rate(hdspm);
1445
1446                         if (hdspm_autosync_ref(hdspm) ==
1447                             HDSPM_AUTOSYNC_FROM_NONE) {
1448
1449                                 snd_printk(KERN_WARNING "HDSPM: "
1450                                            "Detected no Externel Sync \n");
1451                                 not_set = 1;
1452
1453                         } else if (rate != external_freq) {
1454
1455                                 snd_printk(KERN_WARNING "HDSPM: "
1456                                            "Warning: No AutoSync source for "
1457                                            "requested rate\n");
1458                                 not_set = 1;
1459                         }
1460                 }
1461         }
1462
1463         current_rate = hdspm->system_sample_rate;
1464
1465         /* Changing between Singe, Double and Quad speed is not
1466            allowed if any substreams are open. This is because such a change
1467            causes a shift in the location of the DMA buffers and a reduction
1468            in the number of available buffers.
1469
1470            Note that a similar but essentially insoluble problem exists for
1471            externally-driven rate changes. All we can do is to flag rate
1472            changes in the read/write routines.
1473          */
1474
1475         if (current_rate <= 48000)
1476                 current_speed = HDSPM_SPEED_SINGLE;
1477         else if (current_rate <= 96000)
1478                 current_speed = HDSPM_SPEED_DOUBLE;
1479         else
1480                 current_speed = HDSPM_SPEED_QUAD;
1481
1482         if (rate <= 48000)
1483                 target_speed = HDSPM_SPEED_SINGLE;
1484         else if (rate <= 96000)
1485                 target_speed = HDSPM_SPEED_DOUBLE;
1486         else
1487                 target_speed = HDSPM_SPEED_QUAD;
1488
1489         switch (rate) {
1490         case 32000:
1491                 rate_bits = HDSPM_Frequency32KHz;
1492                 break;
1493         case 44100:
1494                 rate_bits = HDSPM_Frequency44_1KHz;
1495                 break;
1496         case 48000:
1497                 rate_bits = HDSPM_Frequency48KHz;
1498                 break;
1499         case 64000:
1500                 rate_bits = HDSPM_Frequency64KHz;
1501                 break;
1502         case 88200:
1503                 rate_bits = HDSPM_Frequency88_2KHz;
1504                 break;
1505         case 96000:
1506                 rate_bits = HDSPM_Frequency96KHz;
1507                 break;
1508         case 128000:
1509                 rate_bits = HDSPM_Frequency128KHz;
1510                 break;
1511         case 176400:
1512                 rate_bits = HDSPM_Frequency176_4KHz;
1513                 break;
1514         case 192000:
1515                 rate_bits = HDSPM_Frequency192KHz;
1516                 break;
1517         default:
1518                 return -EINVAL;
1519         }
1520
1521         if (current_speed != target_speed
1522             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1523                 snd_printk
1524                     (KERN_ERR "HDSPM: "
1525                      "cannot change from %s speed to %s speed mode "
1526                      "(capture PID = %d, playback PID = %d)\n",
1527                      hdspm_speed_names[current_speed],
1528                      hdspm_speed_names[target_speed],
1529                      hdspm->capture_pid, hdspm->playback_pid);
1530                 return -EBUSY;
1531         }
1532
1533         hdspm->control_register &= ~HDSPM_FrequencyMask;
1534         hdspm->control_register |= rate_bits;
1535         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1536
1537         /* For AES32, need to set DDS value in FREQ register
1538            For MADI, also apparently */
1539         hdspm_set_dds_value(hdspm, rate);
1540
1541         if (AES32 == hdspm->io_type && rate != current_rate)
1542                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1543
1544         hdspm->system_sample_rate = rate;
1545
1546         if (rate <= 48000) {
1547                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1548                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1549                 hdspm->max_channels_in = hdspm->ss_in_channels;
1550                 hdspm->max_channels_out = hdspm->ss_out_channels;
1551                 hdspm->port_names_in = hdspm->port_names_in_ss;
1552                 hdspm->port_names_out = hdspm->port_names_out_ss;
1553         } else if (rate <= 96000) {
1554                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1555                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1556                 hdspm->max_channels_in = hdspm->ds_in_channels;
1557                 hdspm->max_channels_out = hdspm->ds_out_channels;
1558                 hdspm->port_names_in = hdspm->port_names_in_ds;
1559                 hdspm->port_names_out = hdspm->port_names_out_ds;
1560         } else {
1561                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1562                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1563                 hdspm->max_channels_in = hdspm->qs_in_channels;
1564                 hdspm->max_channels_out = hdspm->qs_out_channels;
1565                 hdspm->port_names_in = hdspm->port_names_in_qs;
1566                 hdspm->port_names_out = hdspm->port_names_out_qs;
1567         }
1568
1569         if (not_set != 0)
1570                 return -1;
1571
1572         return 0;
1573 }
1574
1575 /* mainly for init to 0 on load */
1576 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1577 {
1578         int i, j;
1579         unsigned int gain;
1580
1581         if (sgain > UNITY_GAIN)
1582                 gain = UNITY_GAIN;
1583         else if (sgain < 0)
1584                 gain = 0;
1585         else
1586                 gain = sgain;
1587
1588         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1589                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1590                         hdspm_write_in_gain(hdspm, i, j, gain);
1591                         hdspm_write_pb_gain(hdspm, i, j, gain);
1592                 }
1593 }
1594
1595 /*----------------------------------------------------------------------------
1596    MIDI
1597   ----------------------------------------------------------------------------*/
1598
1599 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1600                                                       int id)
1601 {
1602         /* the hardware already does the relevant bit-mask with 0xff */
1603         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1604 }
1605
1606 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1607                                               int val)
1608 {
1609         /* the hardware already does the relevant bit-mask with 0xff */
1610         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1611 }
1612
1613 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1614 {
1615         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1616 }
1617
1618 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1619 {
1620         int fifo_bytes_used;
1621
1622         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1623
1624         if (fifo_bytes_used < 128)
1625                 return  128 - fifo_bytes_used;
1626         else
1627                 return 0;
1628 }
1629
1630 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1631 {
1632         while (snd_hdspm_midi_input_available (hdspm, id))
1633                 snd_hdspm_midi_read_byte (hdspm, id);
1634 }
1635
1636 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1637 {
1638         unsigned long flags;
1639         int n_pending;
1640         int to_write;
1641         int i;
1642         unsigned char buf[128];
1643
1644         /* Output is not interrupt driven */
1645
1646         spin_lock_irqsave (&hmidi->lock, flags);
1647         if (hmidi->output &&
1648             !snd_rawmidi_transmit_empty (hmidi->output)) {
1649                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1650                                                             hmidi->id);
1651                 if (n_pending > 0) {
1652                         if (n_pending > (int)sizeof (buf))
1653                                 n_pending = sizeof (buf);
1654
1655                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1656                                                          n_pending);
1657                         if (to_write > 0) {
1658                                 for (i = 0; i < to_write; ++i)
1659                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1660                                                                    hmidi->id,
1661                                                                    buf[i]);
1662                         }
1663                 }
1664         }
1665         spin_unlock_irqrestore (&hmidi->lock, flags);
1666         return 0;
1667 }
1668
1669 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1670 {
1671         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1672                                  * input FIFO size
1673                                  */
1674         unsigned long flags;
1675         int n_pending;
1676         int i;
1677
1678         spin_lock_irqsave (&hmidi->lock, flags);
1679         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1680         if (n_pending > 0) {
1681                 if (hmidi->input) {
1682                         if (n_pending > (int)sizeof (buf))
1683                                 n_pending = sizeof (buf);
1684                         for (i = 0; i < n_pending; ++i)
1685                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1686                                                                    hmidi->id);
1687                         if (n_pending)
1688                                 snd_rawmidi_receive (hmidi->input, buf,
1689                                                      n_pending);
1690                 } else {
1691                         /* flush the MIDI input FIFO */
1692                         while (n_pending--)
1693                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1694                                                           hmidi->id);
1695                 }
1696         }
1697         hmidi->pending = 0;
1698         spin_unlock_irqrestore(&hmidi->lock, flags);
1699
1700         spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1701         hmidi->hdspm->control_register |= hmidi->ie;
1702         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1703                     hmidi->hdspm->control_register);
1704         spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1705
1706         return snd_hdspm_midi_output_write (hmidi);
1707 }
1708
1709 static void
1710 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1711 {
1712         struct hdspm *hdspm;
1713         struct hdspm_midi *hmidi;
1714         unsigned long flags;
1715
1716         hmidi = substream->rmidi->private_data;
1717         hdspm = hmidi->hdspm;
1718
1719         spin_lock_irqsave (&hdspm->lock, flags);
1720         if (up) {
1721                 if (!(hdspm->control_register & hmidi->ie)) {
1722                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1723                         hdspm->control_register |= hmidi->ie;
1724                 }
1725         } else {
1726                 hdspm->control_register &= ~hmidi->ie;
1727         }
1728
1729         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1730         spin_unlock_irqrestore (&hdspm->lock, flags);
1731 }
1732
1733 static void snd_hdspm_midi_output_timer(unsigned long data)
1734 {
1735         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1736         unsigned long flags;
1737
1738         snd_hdspm_midi_output_write(hmidi);
1739         spin_lock_irqsave (&hmidi->lock, flags);
1740
1741         /* this does not bump hmidi->istimer, because the
1742            kernel automatically removed the timer when it
1743            expired, and we are now adding it back, thus
1744            leaving istimer wherever it was set before.
1745         */
1746
1747         if (hmidi->istimer) {
1748                 hmidi->timer.expires = 1 + jiffies;
1749                 add_timer(&hmidi->timer);
1750         }
1751
1752         spin_unlock_irqrestore (&hmidi->lock, flags);
1753 }
1754
1755 static void
1756 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1757 {
1758         struct hdspm_midi *hmidi;
1759         unsigned long flags;
1760
1761         hmidi = substream->rmidi->private_data;
1762         spin_lock_irqsave (&hmidi->lock, flags);
1763         if (up) {
1764                 if (!hmidi->istimer) {
1765                         init_timer(&hmidi->timer);
1766                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1767                         hmidi->timer.data = (unsigned long) hmidi;
1768                         hmidi->timer.expires = 1 + jiffies;
1769                         add_timer(&hmidi->timer);
1770                         hmidi->istimer++;
1771                 }
1772         } else {
1773                 if (hmidi->istimer && --hmidi->istimer <= 0)
1774                         del_timer (&hmidi->timer);
1775         }
1776         spin_unlock_irqrestore (&hmidi->lock, flags);
1777         if (up)
1778                 snd_hdspm_midi_output_write(hmidi);
1779 }
1780
1781 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1782 {
1783         struct hdspm_midi *hmidi;
1784
1785         hmidi = substream->rmidi->private_data;
1786         spin_lock_irq (&hmidi->lock);
1787         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1788         hmidi->input = substream;
1789         spin_unlock_irq (&hmidi->lock);
1790
1791         return 0;
1792 }
1793
1794 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1795 {
1796         struct hdspm_midi *hmidi;
1797
1798         hmidi = substream->rmidi->private_data;
1799         spin_lock_irq (&hmidi->lock);
1800         hmidi->output = substream;
1801         spin_unlock_irq (&hmidi->lock);
1802
1803         return 0;
1804 }
1805
1806 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1807 {
1808         struct hdspm_midi *hmidi;
1809
1810         snd_hdspm_midi_input_trigger (substream, 0);
1811
1812         hmidi = substream->rmidi->private_data;
1813         spin_lock_irq (&hmidi->lock);
1814         hmidi->input = NULL;
1815         spin_unlock_irq (&hmidi->lock);
1816
1817         return 0;
1818 }
1819
1820 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1821 {
1822         struct hdspm_midi *hmidi;
1823
1824         snd_hdspm_midi_output_trigger (substream, 0);
1825
1826         hmidi = substream->rmidi->private_data;
1827         spin_lock_irq (&hmidi->lock);
1828         hmidi->output = NULL;
1829         spin_unlock_irq (&hmidi->lock);
1830
1831         return 0;
1832 }
1833
1834 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1835 {
1836         .open =         snd_hdspm_midi_output_open,
1837         .close =        snd_hdspm_midi_output_close,
1838         .trigger =      snd_hdspm_midi_output_trigger,
1839 };
1840
1841 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1842 {
1843         .open =         snd_hdspm_midi_input_open,
1844         .close =        snd_hdspm_midi_input_close,
1845         .trigger =      snd_hdspm_midi_input_trigger,
1846 };
1847
1848 static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1849                                             struct hdspm *hdspm, int id)
1850 {
1851         int err;
1852         char buf[32];
1853
1854         hdspm->midi[id].id = id;
1855         hdspm->midi[id].hdspm = hdspm;
1856         spin_lock_init (&hdspm->midi[id].lock);
1857
1858         if (0 == id) {
1859                 if (MADIface == hdspm->io_type) {
1860                         /* MIDI-over-MADI on HDSPe MADIface */
1861                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1862                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1863                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1864                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1865                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1866                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1867                 } else {
1868                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1869                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1870                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1871                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1872                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1873                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1874                 }
1875         } else if (1 == id) {
1876                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1877                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1878                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1879                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1880                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1881                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1882         } else if ((2 == id) && (MADI == hdspm->io_type)) {
1883                 /* MIDI-over-MADI on HDSPe MADI */
1884                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1885                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1886                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1887                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1888                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1889                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1890         } else if (2 == id) {
1891                 /* TCO MTC, read only */
1892                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1893                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1894                 hdspm->midi[2].dataOut = -1;
1895                 hdspm->midi[2].statusOut = -1;
1896                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1897                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1898         } else if (3 == id) {
1899                 /* TCO MTC on HDSPe MADI */
1900                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1901                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1902                 hdspm->midi[3].dataOut = -1;
1903                 hdspm->midi[3].statusOut = -1;
1904                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1905                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1906         }
1907
1908         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1909                                         (MADIface == hdspm->io_type)))) {
1910                 if ((id == 0) && (MADIface == hdspm->io_type)) {
1911                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1912                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1913                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1914                 } else {
1915                         sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1916                 }
1917                 err = snd_rawmidi_new(card, buf, id, 1, 1,
1918                                 &hdspm->midi[id].rmidi);
1919                 if (err < 0)
1920                         return err;
1921
1922                 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1923                                 card->id, id+1);
1924                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1925
1926                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1927                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
1928                                 &snd_hdspm_midi_output);
1929                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1930                                 SNDRV_RAWMIDI_STREAM_INPUT,
1931                                 &snd_hdspm_midi_input);
1932
1933                 hdspm->midi[id].rmidi->info_flags |=
1934                         SNDRV_RAWMIDI_INFO_OUTPUT |
1935                         SNDRV_RAWMIDI_INFO_INPUT |
1936                         SNDRV_RAWMIDI_INFO_DUPLEX;
1937         } else {
1938                 /* TCO MTC, read only */
1939                 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1940                 err = snd_rawmidi_new(card, buf, id, 1, 1,
1941                                 &hdspm->midi[id].rmidi);
1942                 if (err < 0)
1943                         return err;
1944
1945                 sprintf(hdspm->midi[id].rmidi->name,
1946                                 "%s MTC %d", card->id, id+1);
1947                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1948
1949                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1950                                 SNDRV_RAWMIDI_STREAM_INPUT,
1951                                 &snd_hdspm_midi_input);
1952
1953                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1954         }
1955
1956         return 0;
1957 }
1958
1959
1960 static void hdspm_midi_tasklet(unsigned long arg)
1961 {
1962         struct hdspm *hdspm = (struct hdspm *)arg;
1963         int i = 0;
1964
1965         while (i < hdspm->midiPorts) {
1966                 if (hdspm->midi[i].pending)
1967                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
1968
1969                 i++;
1970         }
1971 }
1972
1973
1974 /*-----------------------------------------------------------------------------
1975   Status Interface
1976   ----------------------------------------------------------------------------*/
1977
1978 /* get the system sample rate which is set */
1979
1980
1981 /**
1982  * Calculate the real sample rate from the
1983  * current DDS value.
1984  **/
1985 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
1986 {
1987         unsigned int period, rate;
1988
1989         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
1990         rate = hdspm_calc_dds_value(hdspm, period);
1991
1992         if (rate > 207000) {
1993                 /* Unreasonable high sample rate as seen on PCI MADI cards. */
1994                 if (0 == hdspm_system_clock_mode(hdspm)) {
1995                         /* master mode, return internal sample rate */
1996                         rate = hdspm->system_sample_rate;
1997                 } else {
1998                         /* slave mode, return external sample rate */
1999                         rate = hdspm_external_sample_rate(hdspm);
2000                 }
2001         }
2002
2003         return rate;
2004 }
2005
2006
2007 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2008 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2009   .name = xname, \
2010   .index = xindex, \
2011   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2012         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2013   .info = snd_hdspm_info_system_sample_rate, \
2014   .put = snd_hdspm_put_system_sample_rate, \
2015   .get = snd_hdspm_get_system_sample_rate \
2016 }
2017
2018 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2019                                              struct snd_ctl_elem_info *uinfo)
2020 {
2021         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2022         uinfo->count = 1;
2023         uinfo->value.integer.min = 27000;
2024         uinfo->value.integer.max = 207000;
2025         uinfo->value.integer.step = 1;
2026         return 0;
2027 }
2028
2029
2030 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2031                                             struct snd_ctl_elem_value *
2032                                             ucontrol)
2033 {
2034         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2035
2036         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2037         return 0;
2038 }
2039
2040 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2041                                             struct snd_ctl_elem_value *
2042                                             ucontrol)
2043 {
2044         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2045
2046         hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]);
2047         return 0;
2048 }
2049
2050
2051 /**
2052  * Returns the WordClock sample rate class for the given card.
2053  **/
2054 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2055 {
2056         int status;
2057
2058         switch (hdspm->io_type) {
2059         case RayDAT:
2060         case AIO:
2061                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2062                 return (status >> 16) & 0xF;
2063                 break;
2064         default:
2065                 break;
2066         }
2067
2068
2069         return 0;
2070 }
2071
2072
2073 /**
2074  * Returns the TCO sample rate class for the given card.
2075  **/
2076 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2077 {
2078         int status;
2079
2080         if (hdspm->tco) {
2081                 switch (hdspm->io_type) {
2082                 case RayDAT:
2083                 case AIO:
2084                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2085                         return (status >> 20) & 0xF;
2086                         break;
2087                 default:
2088                         break;
2089                 }
2090         }
2091
2092         return 0;
2093 }
2094
2095
2096 /**
2097  * Returns the SYNC_IN sample rate class for the given card.
2098  **/
2099 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2100 {
2101         int status;
2102
2103         if (hdspm->tco) {
2104                 switch (hdspm->io_type) {
2105                 case RayDAT:
2106                 case AIO:
2107                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2108                         return (status >> 12) & 0xF;
2109                         break;
2110                 default:
2111                         break;
2112                 }
2113         }
2114
2115         return 0;
2116 }
2117
2118
2119 /**
2120  * Returns the sample rate class for input source <idx> for
2121  * 'new style' cards like the AIO and RayDAT.
2122  **/
2123 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2124 {
2125         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2126
2127         return (status >> (idx*4)) & 0xF;
2128 }
2129
2130
2131
2132 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2133 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2134         .name = xname, \
2135         .private_value = xindex, \
2136         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2137         .info = snd_hdspm_info_autosync_sample_rate, \
2138         .get = snd_hdspm_get_autosync_sample_rate \
2139 }
2140
2141
2142 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2143                                                struct snd_ctl_elem_info *uinfo)
2144 {
2145         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2146         uinfo->count = 1;
2147         uinfo->value.enumerated.items = 10;
2148
2149         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2150                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2151         strcpy(uinfo->value.enumerated.name,
2152                         texts_freq[uinfo->value.enumerated.item]);
2153         return 0;
2154 }
2155
2156
2157 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2158                                               struct snd_ctl_elem_value *
2159                                               ucontrol)
2160 {
2161         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2162
2163         switch (hdspm->io_type) {
2164         case RayDAT:
2165                 switch (kcontrol->private_value) {
2166                 case 0:
2167                         ucontrol->value.enumerated.item[0] =
2168                                 hdspm_get_wc_sample_rate(hdspm);
2169                         break;
2170                 case 7:
2171                         ucontrol->value.enumerated.item[0] =
2172                                 hdspm_get_tco_sample_rate(hdspm);
2173                         break;
2174                 case 8:
2175                         ucontrol->value.enumerated.item[0] =
2176                                 hdspm_get_sync_in_sample_rate(hdspm);
2177                         break;
2178                 default:
2179                         ucontrol->value.enumerated.item[0] =
2180                                 hdspm_get_s1_sample_rate(hdspm,
2181                                                 kcontrol->private_value-1);
2182                 }
2183
2184         case AIO:
2185                 switch (kcontrol->private_value) {
2186                 case 0: /* WC */
2187                         ucontrol->value.enumerated.item[0] =
2188                                 hdspm_get_wc_sample_rate(hdspm);
2189                         break;
2190                 case 4: /* TCO */
2191                         ucontrol->value.enumerated.item[0] =
2192                                 hdspm_get_tco_sample_rate(hdspm);
2193                         break;
2194                 case 5: /* SYNC_IN */
2195                         ucontrol->value.enumerated.item[0] =
2196                                 hdspm_get_sync_in_sample_rate(hdspm);
2197                         break;
2198                 default:
2199                         ucontrol->value.enumerated.item[0] =
2200                                 hdspm_get_s1_sample_rate(hdspm,
2201                                                 ucontrol->id.index-1);
2202                 }
2203
2204         case AES32:
2205
2206                 switch (kcontrol->private_value) {
2207                 case 0: /* WC */
2208                         ucontrol->value.enumerated.item[0] =
2209                                 hdspm_get_wc_sample_rate(hdspm);
2210                         break;
2211                 case 9: /* TCO */
2212                         ucontrol->value.enumerated.item[0] =
2213                                 hdspm_get_tco_sample_rate(hdspm);
2214                         break;
2215                 case 10: /* SYNC_IN */
2216                         ucontrol->value.enumerated.item[0] =
2217                                 hdspm_get_sync_in_sample_rate(hdspm);
2218                         break;
2219                 default: /* AES1 to AES8 */
2220                         ucontrol->value.enumerated.item[0] =
2221                                 hdspm_get_s1_sample_rate(hdspm,
2222                                                 kcontrol->private_value-1);
2223                         break;
2224
2225                 }
2226         default:
2227                 break;
2228         }
2229
2230         return 0;
2231 }
2232
2233
2234 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2235 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2236         .name = xname, \
2237         .index = xindex, \
2238         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2239                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2240         .info = snd_hdspm_info_system_clock_mode, \
2241         .get = snd_hdspm_get_system_clock_mode, \
2242         .put = snd_hdspm_put_system_clock_mode, \
2243 }
2244
2245
2246 /**
2247  * Returns the system clock mode for the given card.
2248  * @returns 0 - master, 1 - slave
2249  **/
2250 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2251 {
2252         switch (hdspm->io_type) {
2253         case AIO:
2254         case RayDAT:
2255                 if (hdspm->settings_register & HDSPM_c0Master)
2256                         return 0;
2257                 break;
2258
2259         default:
2260                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2261                         return 0;
2262         }
2263
2264         return 1;
2265 }
2266
2267
2268 /**
2269  * Sets the system clock mode.
2270  * @param mode 0 - master, 1 - slave
2271  **/
2272 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2273 {
2274         switch (hdspm->io_type) {
2275         case AIO:
2276         case RayDAT:
2277                 if (0 == mode)
2278                         hdspm->settings_register |= HDSPM_c0Master;
2279                 else
2280                         hdspm->settings_register &= ~HDSPM_c0Master;
2281
2282                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2283                 break;
2284
2285         default:
2286                 if (0 == mode)
2287                         hdspm->control_register |= HDSPM_ClockModeMaster;
2288                 else
2289                         hdspm->control_register &= ~HDSPM_ClockModeMaster;
2290
2291                 hdspm_write(hdspm, HDSPM_controlRegister,
2292                                 hdspm->control_register);
2293         }
2294 }
2295
2296
2297 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2298                                             struct snd_ctl_elem_info *uinfo)
2299 {
2300         static char *texts[] = { "Master", "AutoSync" };
2301
2302         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2303         uinfo->count = 1;
2304         uinfo->value.enumerated.items = 2;
2305         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2306                 uinfo->value.enumerated.item =
2307                     uinfo->value.enumerated.items - 1;
2308         strcpy(uinfo->value.enumerated.name,
2309                texts[uinfo->value.enumerated.item]);
2310         return 0;
2311 }
2312
2313 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2314                                            struct snd_ctl_elem_value *ucontrol)
2315 {
2316         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2317
2318         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2319         return 0;
2320 }
2321
2322 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2323                                            struct snd_ctl_elem_value *ucontrol)
2324 {
2325         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2326         int val;
2327
2328         if (!snd_hdspm_use_is_exclusive(hdspm))
2329                 return -EBUSY;
2330
2331         val = ucontrol->value.enumerated.item[0];
2332         if (val < 0)
2333                 val = 0;
2334         else if (val > 1)
2335                 val = 1;
2336
2337         hdspm_set_system_clock_mode(hdspm, val);
2338
2339         return 0;
2340 }
2341
2342
2343 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2344 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2345         .name = xname, \
2346         .index = xindex, \
2347         .info = snd_hdspm_info_clock_source, \
2348         .get = snd_hdspm_get_clock_source, \
2349         .put = snd_hdspm_put_clock_source \
2350 }
2351
2352
2353 static int hdspm_clock_source(struct hdspm * hdspm)
2354 {
2355         switch (hdspm->system_sample_rate) {
2356         case 32000: return 0;
2357         case 44100: return 1;
2358         case 48000: return 2;
2359         case 64000: return 3;
2360         case 88200: return 4;
2361         case 96000: return 5;
2362         case 128000: return 6;
2363         case 176400: return 7;
2364         case 192000: return 8;
2365         }
2366
2367         return -1;
2368 }
2369
2370 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2371 {
2372         int rate;
2373         switch (mode) {
2374         case 0:
2375                 rate = 32000; break;
2376         case 1:
2377                 rate = 44100; break;
2378         case 2:
2379                 rate = 48000; break;
2380         case 3:
2381                 rate = 64000; break;
2382         case 4:
2383                 rate = 88200; break;
2384         case 5:
2385                 rate = 96000; break;
2386         case 6:
2387                 rate = 128000; break;
2388         case 7:
2389                 rate = 176400; break;
2390         case 8:
2391                 rate = 192000; break;
2392         default:
2393                 rate = 48000;
2394         }
2395         hdspm_set_rate(hdspm, rate, 1);
2396         return 0;
2397 }
2398
2399 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2400                                        struct snd_ctl_elem_info *uinfo)
2401 {
2402         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2403         uinfo->count = 1;
2404         uinfo->value.enumerated.items = 9;
2405
2406         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2407                 uinfo->value.enumerated.item =
2408                     uinfo->value.enumerated.items - 1;
2409
2410         strcpy(uinfo->value.enumerated.name,
2411                texts_freq[uinfo->value.enumerated.item+1]);
2412
2413         return 0;
2414 }
2415
2416 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2417                                       struct snd_ctl_elem_value *ucontrol)
2418 {
2419         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2420
2421         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2422         return 0;
2423 }
2424
2425 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2426                                       struct snd_ctl_elem_value *ucontrol)
2427 {
2428         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2429         int change;
2430         int val;
2431
2432         if (!snd_hdspm_use_is_exclusive(hdspm))
2433                 return -EBUSY;
2434         val = ucontrol->value.enumerated.item[0];
2435         if (val < 0)
2436                 val = 0;
2437         if (val > 9)
2438                 val = 9;
2439         spin_lock_irq(&hdspm->lock);
2440         if (val != hdspm_clock_source(hdspm))
2441                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2442         else
2443                 change = 0;
2444         spin_unlock_irq(&hdspm->lock);
2445         return change;
2446 }
2447
2448
2449 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2450 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2451         .name = xname, \
2452         .index = xindex, \
2453         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2454                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2455         .info = snd_hdspm_info_pref_sync_ref, \
2456         .get = snd_hdspm_get_pref_sync_ref, \
2457         .put = snd_hdspm_put_pref_sync_ref \
2458 }
2459
2460
2461 /**
2462  * Returns the current preferred sync reference setting.
2463  * The semantics of the return value are depending on the
2464  * card, please see the comments for clarification.
2465  **/
2466 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2467 {
2468         switch (hdspm->io_type) {
2469         case AES32:
2470                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2471                 case 0: return 0;  /* WC */
2472                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2473                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2474                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2475                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2476                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2477                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2478                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2479                                                     return 7; /* AES 7 */
2480                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2481                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2482                 }
2483                 break;
2484
2485         case MADI:
2486         case MADIface:
2487                 if (hdspm->tco) {
2488                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2489                         case 0: return 0;  /* WC */
2490                         case HDSPM_SyncRef0: return 1;  /* MADI */
2491                         case HDSPM_SyncRef1: return 2;  /* TCO */
2492                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2493                                              return 3;  /* SYNC_IN */
2494                         }
2495                 } else {
2496                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2497                         case 0: return 0;  /* WC */
2498                         case HDSPM_SyncRef0: return 1;  /* MADI */
2499                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2500                                              return 2;  /* SYNC_IN */
2501                         }
2502                 }
2503                 break;
2504
2505         case RayDAT:
2506                 if (hdspm->tco) {
2507                         switch ((hdspm->settings_register &
2508                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2509                         case 0: return 0;  /* WC */
2510                         case 3: return 1;  /* ADAT 1 */
2511                         case 4: return 2;  /* ADAT 2 */
2512                         case 5: return 3;  /* ADAT 3 */
2513                         case 6: return 4;  /* ADAT 4 */
2514                         case 1: return 5;  /* AES */
2515                         case 2: return 6;  /* SPDIF */
2516                         case 9: return 7;  /* TCO */
2517                         case 10: return 8; /* SYNC_IN */
2518                         }
2519                 } else {
2520                         switch ((hdspm->settings_register &
2521                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2522                         case 0: return 0;  /* WC */
2523                         case 3: return 1;  /* ADAT 1 */
2524                         case 4: return 2;  /* ADAT 2 */
2525                         case 5: return 3;  /* ADAT 3 */
2526                         case 6: return 4;  /* ADAT 4 */
2527                         case 1: return 5;  /* AES */
2528                         case 2: return 6;  /* SPDIF */
2529                         case 10: return 7; /* SYNC_IN */
2530                         }
2531                 }
2532
2533                 break;
2534
2535         case AIO:
2536                 if (hdspm->tco) {
2537                         switch ((hdspm->settings_register &
2538                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2539                         case 0: return 0;  /* WC */
2540                         case 3: return 1;  /* ADAT */
2541                         case 1: return 2;  /* AES */
2542                         case 2: return 3;  /* SPDIF */
2543                         case 9: return 4;  /* TCO */
2544                         case 10: return 5; /* SYNC_IN */
2545                         }
2546                 } else {
2547                         switch ((hdspm->settings_register &
2548                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2549                         case 0: return 0;  /* WC */
2550                         case 3: return 1;  /* ADAT */
2551                         case 1: return 2;  /* AES */
2552                         case 2: return 3;  /* SPDIF */
2553                         case 10: return 4; /* SYNC_IN */
2554                         }
2555                 }
2556
2557                 break;
2558         }
2559
2560         return -1;
2561 }
2562
2563
2564 /**
2565  * Set the preferred sync reference to <pref>. The semantics
2566  * of <pref> are depending on the card type, see the comments
2567  * for clarification.
2568  **/
2569 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2570 {
2571         int p = 0;
2572
2573         switch (hdspm->io_type) {
2574         case AES32:
2575                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2576                 switch (pref) {
2577                 case 0: /* WC  */
2578                         break;
2579                 case 1: /* AES 1 */
2580                         hdspm->control_register |= HDSPM_SyncRef0;
2581                         break;
2582                 case 2: /* AES 2 */
2583                         hdspm->control_register |= HDSPM_SyncRef1;
2584                         break;
2585                 case 3: /* AES 3 */
2586                         hdspm->control_register |=
2587                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2588                         break;
2589                 case 4: /* AES 4 */
2590                         hdspm->control_register |= HDSPM_SyncRef2;
2591                         break;
2592                 case 5: /* AES 5 */
2593                         hdspm->control_register |=
2594                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2595                         break;
2596                 case 6: /* AES 6 */
2597                         hdspm->control_register |=
2598                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2599                         break;
2600                 case 7: /* AES 7 */
2601                         hdspm->control_register |=
2602                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2603                         break;
2604                 case 8: /* AES 8 */
2605                         hdspm->control_register |= HDSPM_SyncRef3;
2606                         break;
2607                 case 9: /* TCO */
2608                         hdspm->control_register |=
2609                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2610                         break;
2611                 default:
2612                         return -1;
2613                 }
2614
2615                 break;
2616
2617         case MADI:
2618         case MADIface:
2619                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2620                 if (hdspm->tco) {
2621                         switch (pref) {
2622                         case 0: /* WC */
2623                                 break;
2624                         case 1: /* MADI */
2625                                 hdspm->control_register |= HDSPM_SyncRef0;
2626                                 break;
2627                         case 2: /* TCO */
2628                                 hdspm->control_register |= HDSPM_SyncRef1;
2629                                 break;
2630                         case 3: /* SYNC_IN */
2631                                 hdspm->control_register |=
2632                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2633                                 break;
2634                         default:
2635                                 return -1;
2636                         }
2637                 } else {
2638                         switch (pref) {
2639                         case 0: /* WC */
2640                                 break;
2641                         case 1: /* MADI */
2642                                 hdspm->control_register |= HDSPM_SyncRef0;
2643                                 break;
2644                         case 2: /* SYNC_IN */
2645                                 hdspm->control_register |=
2646                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2647                                 break;
2648                         default:
2649                                 return -1;
2650                         }
2651                 }
2652
2653                 break;
2654
2655         case RayDAT:
2656                 if (hdspm->tco) {
2657                         switch (pref) {
2658                         case 0: p = 0; break;  /* WC */
2659                         case 1: p = 3; break;  /* ADAT 1 */
2660                         case 2: p = 4; break;  /* ADAT 2 */
2661                         case 3: p = 5; break;  /* ADAT 3 */
2662                         case 4: p = 6; break;  /* ADAT 4 */
2663                         case 5: p = 1; break;  /* AES */
2664                         case 6: p = 2; break;  /* SPDIF */
2665                         case 7: p = 9; break;  /* TCO */
2666                         case 8: p = 10; break; /* SYNC_IN */
2667                         default: return -1;
2668                         }
2669                 } else {
2670                         switch (pref) {
2671                         case 0: p = 0; break;  /* WC */
2672                         case 1: p = 3; break;  /* ADAT 1 */
2673                         case 2: p = 4; break;  /* ADAT 2 */
2674                         case 3: p = 5; break;  /* ADAT 3 */
2675                         case 4: p = 6; break;  /* ADAT 4 */
2676                         case 5: p = 1; break;  /* AES */
2677                         case 6: p = 2; break;  /* SPDIF */
2678                         case 7: p = 10; break; /* SYNC_IN */
2679                         default: return -1;
2680                         }
2681                 }
2682                 break;
2683
2684         case AIO:
2685                 if (hdspm->tco) {
2686                         switch (pref) {
2687                         case 0: p = 0; break;  /* WC */
2688                         case 1: p = 3; break;  /* ADAT */
2689                         case 2: p = 1; break;  /* AES */
2690                         case 3: p = 2; break;  /* SPDIF */
2691                         case 4: p = 9; break;  /* TCO */
2692                         case 5: p = 10; break; /* SYNC_IN */
2693                         default: return -1;
2694                         }
2695                 } else {
2696                         switch (pref) {
2697                         case 0: p = 0; break;  /* WC */
2698                         case 1: p = 3; break;  /* ADAT */
2699                         case 2: p = 1; break;  /* AES */
2700                         case 3: p = 2; break;  /* SPDIF */
2701                         case 4: p = 10; break; /* SYNC_IN */
2702                         default: return -1;
2703                         }
2704                 }
2705                 break;
2706         }
2707
2708         switch (hdspm->io_type) {
2709         case RayDAT:
2710         case AIO:
2711                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2712                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2713                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2714                 break;
2715
2716         case MADI:
2717         case MADIface:
2718         case AES32:
2719                 hdspm_write(hdspm, HDSPM_controlRegister,
2720                                 hdspm->control_register);
2721         }
2722
2723         return 0;
2724 }
2725
2726
2727 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2728                                         struct snd_ctl_elem_info *uinfo)
2729 {
2730         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2731
2732         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2733         uinfo->count = 1;
2734         uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2735
2736         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2737                 uinfo->value.enumerated.item =
2738                         uinfo->value.enumerated.items - 1;
2739
2740         strcpy(uinfo->value.enumerated.name,
2741                         hdspm->texts_autosync[uinfo->value.enumerated.item]);
2742
2743         return 0;
2744 }
2745
2746 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2747                                        struct snd_ctl_elem_value *ucontrol)
2748 {
2749         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2750         int psf = hdspm_pref_sync_ref(hdspm);
2751
2752         if (psf >= 0) {
2753                 ucontrol->value.enumerated.item[0] = psf;
2754                 return 0;
2755         }
2756
2757         return -1;
2758 }
2759
2760 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2761                                        struct snd_ctl_elem_value *ucontrol)
2762 {
2763         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2764         int val, change = 0;
2765
2766         if (!snd_hdspm_use_is_exclusive(hdspm))
2767                 return -EBUSY;
2768
2769         val = ucontrol->value.enumerated.item[0];
2770
2771         if (val < 0)
2772                 val = 0;
2773         else if (val >= hdspm->texts_autosync_items)
2774                 val = hdspm->texts_autosync_items-1;
2775
2776         spin_lock_irq(&hdspm->lock);
2777         if (val != hdspm_pref_sync_ref(hdspm))
2778                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2779
2780         spin_unlock_irq(&hdspm->lock);
2781         return change;
2782 }
2783
2784
2785 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2786 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2787   .name = xname, \
2788   .index = xindex, \
2789   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2790   .info = snd_hdspm_info_autosync_ref, \
2791   .get = snd_hdspm_get_autosync_ref, \
2792 }
2793
2794 static int hdspm_autosync_ref(struct hdspm *hdspm)
2795 {
2796         if (AES32 == hdspm->io_type) {
2797                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2798                 unsigned int syncref =
2799                         (status >> HDSPM_AES32_syncref_bit) & 0xF;
2800                 if (syncref == 0)
2801                         return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2802                 if (syncref <= 8)
2803                         return syncref;
2804                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2805         } else if (MADI == hdspm->io_type) {
2806                 /* This looks at the autosync selected sync reference */
2807                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2808
2809                 switch (status2 & HDSPM_SelSyncRefMask) {
2810                 case HDSPM_SelSyncRef_WORD:
2811                         return HDSPM_AUTOSYNC_FROM_WORD;
2812                 case HDSPM_SelSyncRef_MADI:
2813                         return HDSPM_AUTOSYNC_FROM_MADI;
2814                 case HDSPM_SelSyncRef_TCO:
2815                         return HDSPM_AUTOSYNC_FROM_TCO;
2816                 case HDSPM_SelSyncRef_SyncIn:
2817                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2818                 case HDSPM_SelSyncRef_NVALID:
2819                         return HDSPM_AUTOSYNC_FROM_NONE;
2820                 default:
2821                         return 0;
2822                 }
2823
2824         }
2825         return 0;
2826 }
2827
2828
2829 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2830                                        struct snd_ctl_elem_info *uinfo)
2831 {
2832         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2833
2834         if (AES32 == hdspm->io_type) {
2835                 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2836                         "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2837
2838                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2839                 uinfo->count = 1;
2840                 uinfo->value.enumerated.items = 10;
2841                 if (uinfo->value.enumerated.item >=
2842                     uinfo->value.enumerated.items)
2843                         uinfo->value.enumerated.item =
2844                                 uinfo->value.enumerated.items - 1;
2845                 strcpy(uinfo->value.enumerated.name,
2846                                 texts[uinfo->value.enumerated.item]);
2847         } else if (MADI == hdspm->io_type) {
2848                 static char *texts[] = {"Word Clock", "MADI", "TCO",
2849                         "Sync In", "None" };
2850
2851                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2852                 uinfo->count = 1;
2853                 uinfo->value.enumerated.items = 5;
2854                 if (uinfo->value.enumerated.item >=
2855                                 uinfo->value.enumerated.items)
2856                         uinfo->value.enumerated.item =
2857                                 uinfo->value.enumerated.items - 1;
2858                 strcpy(uinfo->value.enumerated.name,
2859                                 texts[uinfo->value.enumerated.item]);
2860         }
2861         return 0;
2862 }
2863
2864 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2865                                       struct snd_ctl_elem_value *ucontrol)
2866 {
2867         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2868
2869         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2870         return 0;
2871 }
2872
2873
2874 #define HDSPM_LINE_OUT(xname, xindex) \
2875 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2876   .name = xname, \
2877   .index = xindex, \
2878   .info = snd_hdspm_info_line_out, \
2879   .get = snd_hdspm_get_line_out, \
2880   .put = snd_hdspm_put_line_out \
2881 }
2882
2883 static int hdspm_line_out(struct hdspm * hdspm)
2884 {
2885         return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
2886 }
2887
2888
2889 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
2890 {
2891         if (out)
2892                 hdspm->control_register |= HDSPM_LineOut;
2893         else
2894                 hdspm->control_register &= ~HDSPM_LineOut;
2895         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2896
2897         return 0;
2898 }
2899
2900 #define snd_hdspm_info_line_out         snd_ctl_boolean_mono_info
2901
2902 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
2903                                   struct snd_ctl_elem_value *ucontrol)
2904 {
2905         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2906
2907         spin_lock_irq(&hdspm->lock);
2908         ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
2909         spin_unlock_irq(&hdspm->lock);
2910         return 0;
2911 }
2912
2913 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
2914                                   struct snd_ctl_elem_value *ucontrol)
2915 {
2916         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2917         int change;
2918         unsigned int val;
2919
2920         if (!snd_hdspm_use_is_exclusive(hdspm))
2921                 return -EBUSY;
2922         val = ucontrol->value.integer.value[0] & 1;
2923         spin_lock_irq(&hdspm->lock);
2924         change = (int) val != hdspm_line_out(hdspm);
2925         hdspm_set_line_output(hdspm, val);
2926         spin_unlock_irq(&hdspm->lock);
2927         return change;
2928 }
2929
2930
2931 #define HDSPM_TX_64(xname, xindex) \
2932 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2933   .name = xname, \
2934   .index = xindex, \
2935   .info = snd_hdspm_info_tx_64, \
2936   .get = snd_hdspm_get_tx_64, \
2937   .put = snd_hdspm_put_tx_64 \
2938 }
2939
2940 static int hdspm_tx_64(struct hdspm * hdspm)
2941 {
2942         return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
2943 }
2944
2945 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
2946 {
2947         if (out)
2948                 hdspm->control_register |= HDSPM_TX_64ch;
2949         else
2950                 hdspm->control_register &= ~HDSPM_TX_64ch;
2951         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2952
2953         return 0;
2954 }
2955
2956 #define snd_hdspm_info_tx_64            snd_ctl_boolean_mono_info
2957
2958 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
2959                                struct snd_ctl_elem_value *ucontrol)
2960 {
2961         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2962
2963         spin_lock_irq(&hdspm->lock);
2964         ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
2965         spin_unlock_irq(&hdspm->lock);
2966         return 0;
2967 }
2968
2969 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
2970                                struct snd_ctl_elem_value *ucontrol)
2971 {
2972         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2973         int change;
2974         unsigned int val;
2975
2976         if (!snd_hdspm_use_is_exclusive(hdspm))
2977                 return -EBUSY;
2978         val = ucontrol->value.integer.value[0] & 1;
2979         spin_lock_irq(&hdspm->lock);
2980         change = (int) val != hdspm_tx_64(hdspm);
2981         hdspm_set_tx_64(hdspm, val);
2982         spin_unlock_irq(&hdspm->lock);
2983         return change;
2984 }
2985
2986
2987 #define HDSPM_C_TMS(xname, xindex) \
2988 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2989   .name = xname, \
2990   .index = xindex, \
2991   .info = snd_hdspm_info_c_tms, \
2992   .get = snd_hdspm_get_c_tms, \
2993   .put = snd_hdspm_put_c_tms \
2994 }
2995
2996 static int hdspm_c_tms(struct hdspm * hdspm)
2997 {
2998         return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
2999 }
3000
3001 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
3002 {
3003         if (out)
3004                 hdspm->control_register |= HDSPM_clr_tms;
3005         else
3006                 hdspm->control_register &= ~HDSPM_clr_tms;
3007         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3008
3009         return 0;
3010 }
3011
3012 #define snd_hdspm_info_c_tms            snd_ctl_boolean_mono_info
3013
3014 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
3015                                struct snd_ctl_elem_value *ucontrol)
3016 {
3017         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3018
3019         spin_lock_irq(&hdspm->lock);
3020         ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
3021         spin_unlock_irq(&hdspm->lock);
3022         return 0;
3023 }
3024
3025 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
3026                                struct snd_ctl_elem_value *ucontrol)
3027 {
3028         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3029         int change;
3030         unsigned int val;
3031
3032         if (!snd_hdspm_use_is_exclusive(hdspm))
3033                 return -EBUSY;
3034         val = ucontrol->value.integer.value[0] & 1;
3035         spin_lock_irq(&hdspm->lock);
3036         change = (int) val != hdspm_c_tms(hdspm);
3037         hdspm_set_c_tms(hdspm, val);
3038         spin_unlock_irq(&hdspm->lock);
3039         return change;
3040 }
3041
3042
3043 #define HDSPM_SAFE_MODE(xname, xindex) \
3044 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3045   .name = xname, \
3046   .index = xindex, \
3047   .info = snd_hdspm_info_safe_mode, \
3048   .get = snd_hdspm_get_safe_mode, \
3049   .put = snd_hdspm_put_safe_mode \
3050 }
3051
3052 static int hdspm_safe_mode(struct hdspm * hdspm)
3053 {
3054         return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
3055 }
3056
3057 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
3058 {
3059         if (out)
3060                 hdspm->control_register |= HDSPM_AutoInp;
3061         else
3062                 hdspm->control_register &= ~HDSPM_AutoInp;
3063         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3064
3065         return 0;
3066 }
3067
3068 #define snd_hdspm_info_safe_mode        snd_ctl_boolean_mono_info
3069
3070 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
3071                                    struct snd_ctl_elem_value *ucontrol)
3072 {
3073         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3074
3075         spin_lock_irq(&hdspm->lock);
3076         ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
3077         spin_unlock_irq(&hdspm->lock);
3078         return 0;
3079 }
3080
3081 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
3082                                    struct snd_ctl_elem_value *ucontrol)
3083 {
3084         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3085         int change;
3086         unsigned int val;
3087
3088         if (!snd_hdspm_use_is_exclusive(hdspm))
3089                 return -EBUSY;
3090         val = ucontrol->value.integer.value[0] & 1;
3091         spin_lock_irq(&hdspm->lock);
3092         change = (int) val != hdspm_safe_mode(hdspm);
3093         hdspm_set_safe_mode(hdspm, val);
3094         spin_unlock_irq(&hdspm->lock);
3095         return change;
3096 }
3097
3098
3099 #define HDSPM_EMPHASIS(xname, xindex) \
3100 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3101   .name = xname, \
3102   .index = xindex, \
3103   .info = snd_hdspm_info_emphasis, \
3104   .get = snd_hdspm_get_emphasis, \
3105   .put = snd_hdspm_put_emphasis \
3106 }
3107
3108 static int hdspm_emphasis(struct hdspm * hdspm)
3109 {
3110         return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
3111 }
3112
3113 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
3114 {
3115         if (emp)
3116                 hdspm->control_register |= HDSPM_Emphasis;
3117         else
3118                 hdspm->control_register &= ~HDSPM_Emphasis;
3119         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3120
3121         return 0;
3122 }
3123
3124 #define snd_hdspm_info_emphasis         snd_ctl_boolean_mono_info
3125
3126 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
3127                                   struct snd_ctl_elem_value *ucontrol)
3128 {
3129         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3130
3131         spin_lock_irq(&hdspm->lock);
3132         ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
3133         spin_unlock_irq(&hdspm->lock);
3134         return 0;
3135 }
3136
3137 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
3138                                   struct snd_ctl_elem_value *ucontrol)
3139 {
3140         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3141         int change;
3142         unsigned int val;
3143
3144         if (!snd_hdspm_use_is_exclusive(hdspm))
3145                 return -EBUSY;
3146         val = ucontrol->value.integer.value[0] & 1;
3147         spin_lock_irq(&hdspm->lock);
3148         change = (int) val != hdspm_emphasis(hdspm);
3149         hdspm_set_emphasis(hdspm, val);
3150         spin_unlock_irq(&hdspm->lock);
3151         return change;
3152 }
3153
3154
3155 #define HDSPM_DOLBY(xname, xindex) \
3156 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3157   .name = xname, \
3158   .index = xindex, \
3159   .info = snd_hdspm_info_dolby, \
3160   .get = snd_hdspm_get_dolby, \
3161   .put = snd_hdspm_put_dolby \
3162 }
3163
3164 static int hdspm_dolby(struct hdspm * hdspm)
3165 {
3166         return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
3167 }
3168
3169 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
3170 {
3171         if (dol)
3172                 hdspm->control_register |= HDSPM_Dolby;
3173         else
3174                 hdspm->control_register &= ~HDSPM_Dolby;
3175         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3176
3177         return 0;
3178 }
3179
3180 #define snd_hdspm_info_dolby            snd_ctl_boolean_mono_info
3181
3182 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
3183                                struct snd_ctl_elem_value *ucontrol)
3184 {
3185         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3186
3187         spin_lock_irq(&hdspm->lock);
3188         ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
3189         spin_unlock_irq(&hdspm->lock);
3190         return 0;
3191 }
3192
3193 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
3194                                struct snd_ctl_elem_value *ucontrol)
3195 {
3196         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3197         int change;
3198         unsigned int val;
3199
3200         if (!snd_hdspm_use_is_exclusive(hdspm))
3201                 return -EBUSY;
3202         val = ucontrol->value.integer.value[0] & 1;
3203         spin_lock_irq(&hdspm->lock);
3204         change = (int) val != hdspm_dolby(hdspm);
3205         hdspm_set_dolby(hdspm, val);
3206         spin_unlock_irq(&hdspm->lock);
3207         return change;
3208 }
3209
3210
3211 #define HDSPM_PROFESSIONAL(xname, xindex) \
3212 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3213   .name = xname, \
3214   .index = xindex, \
3215   .info = snd_hdspm_info_professional, \
3216   .get = snd_hdspm_get_professional, \
3217   .put = snd_hdspm_put_professional \
3218 }
3219
3220 static int hdspm_professional(struct hdspm * hdspm)
3221 {
3222         return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
3223 }
3224
3225 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
3226 {
3227         if (dol)
3228                 hdspm->control_register |= HDSPM_Professional;
3229         else
3230                 hdspm->control_register &= ~HDSPM_Professional;
3231         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3232
3233         return 0;
3234 }
3235
3236 #define snd_hdspm_info_professional     snd_ctl_boolean_mono_info
3237
3238 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
3239                                       struct snd_ctl_elem_value *ucontrol)
3240 {
3241         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3242
3243         spin_lock_irq(&hdspm->lock);
3244         ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
3245         spin_unlock_irq(&hdspm->lock);
3246         return 0;
3247 }
3248
3249 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
3250                                       struct snd_ctl_elem_value *ucontrol)
3251 {
3252         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3253         int change;
3254         unsigned int val;
3255
3256         if (!snd_hdspm_use_is_exclusive(hdspm))
3257                 return -EBUSY;
3258         val = ucontrol->value.integer.value[0] & 1;
3259         spin_lock_irq(&hdspm->lock);
3260         change = (int) val != hdspm_professional(hdspm);
3261         hdspm_set_professional(hdspm, val);
3262         spin_unlock_irq(&hdspm->lock);
3263         return change;
3264 }
3265
3266 #define HDSPM_INPUT_SELECT(xname, xindex) \
3267 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3268   .name = xname, \
3269   .index = xindex, \
3270   .info = snd_hdspm_info_input_select, \
3271   .get = snd_hdspm_get_input_select, \
3272   .put = snd_hdspm_put_input_select \
3273 }
3274
3275 static int hdspm_input_select(struct hdspm * hdspm)
3276 {
3277         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3278 }
3279
3280 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3281 {
3282         if (out)
3283                 hdspm->control_register |= HDSPM_InputSelect0;
3284         else
3285                 hdspm->control_register &= ~HDSPM_InputSelect0;
3286         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3287
3288         return 0;
3289 }
3290
3291 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3292                                        struct snd_ctl_elem_info *uinfo)
3293 {
3294         static char *texts[] = { "optical", "coaxial" };
3295
3296         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3297         uinfo->count = 1;
3298         uinfo->value.enumerated.items = 2;
3299
3300         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3301                 uinfo->value.enumerated.item =
3302                     uinfo->value.enumerated.items - 1;
3303         strcpy(uinfo->value.enumerated.name,
3304                texts[uinfo->value.enumerated.item]);
3305
3306         return 0;
3307 }
3308
3309 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3310                                       struct snd_ctl_elem_value *ucontrol)
3311 {
3312         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3313
3314         spin_lock_irq(&hdspm->lock);
3315         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3316         spin_unlock_irq(&hdspm->lock);
3317         return 0;
3318 }
3319
3320 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3321                                       struct snd_ctl_elem_value *ucontrol)
3322 {
3323         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3324         int change;
3325         unsigned int val;
3326
3327         if (!snd_hdspm_use_is_exclusive(hdspm))
3328                 return -EBUSY;
3329         val = ucontrol->value.integer.value[0] & 1;
3330         spin_lock_irq(&hdspm->lock);
3331         change = (int) val != hdspm_input_select(hdspm);
3332         hdspm_set_input_select(hdspm, val);
3333         spin_unlock_irq(&hdspm->lock);
3334         return change;
3335 }
3336
3337
3338 #define HDSPM_DS_WIRE(xname, xindex) \
3339 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3340   .name = xname, \
3341   .index = xindex, \
3342   .info = snd_hdspm_info_ds_wire, \
3343   .get = snd_hdspm_get_ds_wire, \
3344   .put = snd_hdspm_put_ds_wire \
3345 }
3346
3347 static int hdspm_ds_wire(struct hdspm * hdspm)
3348 {
3349         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3350 }
3351
3352 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3353 {
3354         if (ds)
3355                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3356         else
3357                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3358         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3359
3360         return 0;
3361 }
3362
3363 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3364                                   struct snd_ctl_elem_info *uinfo)
3365 {
3366         static char *texts[] = { "Single", "Double" };
3367
3368         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3369         uinfo->count = 1;
3370         uinfo->value.enumerated.items = 2;
3371
3372         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3373                 uinfo->value.enumerated.item =
3374                     uinfo->value.enumerated.items - 1;
3375         strcpy(uinfo->value.enumerated.name,
3376                texts[uinfo->value.enumerated.item]);
3377
3378         return 0;
3379 }
3380
3381 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3382                                  struct snd_ctl_elem_value *ucontrol)
3383 {
3384         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3385
3386         spin_lock_irq(&hdspm->lock);
3387         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3388         spin_unlock_irq(&hdspm->lock);
3389         return 0;
3390 }
3391
3392 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3393                                  struct snd_ctl_elem_value *ucontrol)
3394 {
3395         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3396         int change;
3397         unsigned int val;
3398
3399         if (!snd_hdspm_use_is_exclusive(hdspm))
3400                 return -EBUSY;
3401         val = ucontrol->value.integer.value[0] & 1;
3402         spin_lock_irq(&hdspm->lock);
3403         change = (int) val != hdspm_ds_wire(hdspm);
3404         hdspm_set_ds_wire(hdspm, val);
3405         spin_unlock_irq(&hdspm->lock);
3406         return change;
3407 }
3408
3409
3410 #define HDSPM_QS_WIRE(xname, xindex) \
3411 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3412   .name = xname, \
3413   .index = xindex, \
3414   .info = snd_hdspm_info_qs_wire, \
3415   .get = snd_hdspm_get_qs_wire, \
3416   .put = snd_hdspm_put_qs_wire \
3417 }
3418
3419 static int hdspm_qs_wire(struct hdspm * hdspm)
3420 {
3421         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3422                 return 1;
3423         if (hdspm->control_register & HDSPM_QS_QuadWire)
3424                 return 2;
3425         return 0;
3426 }
3427
3428 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3429 {
3430         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3431         switch (mode) {
3432         case 0:
3433                 break;
3434         case 1:
3435                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3436                 break;
3437         case 2:
3438                 hdspm->control_register |= HDSPM_QS_QuadWire;
3439                 break;
3440         }
3441         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3442
3443         return 0;
3444 }
3445
3446 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3447                                        struct snd_ctl_elem_info *uinfo)
3448 {
3449         static char *texts[] = { "Single", "Double", "Quad" };
3450
3451         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3452         uinfo->count = 1;
3453         uinfo->value.enumerated.items = 3;
3454
3455         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3456                 uinfo->value.enumerated.item =
3457                     uinfo->value.enumerated.items - 1;
3458         strcpy(uinfo->value.enumerated.name,
3459                texts[uinfo->value.enumerated.item]);
3460
3461         return 0;
3462 }
3463
3464 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3465                                       struct snd_ctl_elem_value *ucontrol)
3466 {
3467         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3468
3469         spin_lock_irq(&hdspm->lock);
3470         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3471         spin_unlock_irq(&hdspm->lock);
3472         return 0;
3473 }
3474
3475 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3476                                       struct snd_ctl_elem_value *ucontrol)
3477 {
3478         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3479         int change;
3480         int val;
3481
3482         if (!snd_hdspm_use_is_exclusive(hdspm))
3483                 return -EBUSY;
3484         val = ucontrol->value.integer.value[0];
3485         if (val < 0)
3486                 val = 0;
3487         if (val > 2)
3488                 val = 2;
3489         spin_lock_irq(&hdspm->lock);
3490         change = val != hdspm_qs_wire(hdspm);
3491         hdspm_set_qs_wire(hdspm, val);
3492         spin_unlock_irq(&hdspm->lock);
3493         return change;
3494 }
3495
3496 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3497 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3498         .name = xname, \
3499         .index = xindex, \
3500         .info = snd_hdspm_info_madi_speedmode, \
3501         .get = snd_hdspm_get_madi_speedmode, \
3502         .put = snd_hdspm_put_madi_speedmode \
3503 }
3504
3505 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3506 {
3507         if (hdspm->control_register & HDSPM_QuadSpeed)
3508                 return 2;
3509         if (hdspm->control_register & HDSPM_DoubleSpeed)
3510                 return 1;
3511         return 0;
3512 }
3513
3514 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3515 {
3516         hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3517         switch (mode) {
3518         case 0:
3519                 break;
3520         case 1:
3521                 hdspm->control_register |= HDSPM_DoubleSpeed;
3522                 break;
3523         case 2:
3524                 hdspm->control_register |= HDSPM_QuadSpeed;
3525                 break;
3526         }
3527         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3528
3529         return 0;
3530 }
3531
3532 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3533                                        struct snd_ctl_elem_info *uinfo)
3534 {
3535         static char *texts[] = { "Single", "Double", "Quad" };
3536
3537         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3538         uinfo->count = 1;
3539         uinfo->value.enumerated.items = 3;
3540
3541         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3542                 uinfo->value.enumerated.item =
3543                     uinfo->value.enumerated.items - 1;
3544         strcpy(uinfo->value.enumerated.name,
3545                texts[uinfo->value.enumerated.item]);
3546
3547         return 0;
3548 }
3549
3550 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3551                                       struct snd_ctl_elem_value *ucontrol)
3552 {
3553         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3554
3555         spin_lock_irq(&hdspm->lock);
3556         ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3557         spin_unlock_irq(&hdspm->lock);
3558         return 0;
3559 }
3560
3561 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3562                                       struct snd_ctl_elem_value *ucontrol)
3563 {
3564         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3565         int change;
3566         int val;
3567
3568         if (!snd_hdspm_use_is_exclusive(hdspm))
3569                 return -EBUSY;
3570         val = ucontrol->value.integer.value[0];
3571         if (val < 0)
3572                 val = 0;
3573         if (val > 2)
3574                 val = 2;
3575         spin_lock_irq(&hdspm->lock);
3576         change = val != hdspm_madi_speedmode(hdspm);
3577         hdspm_set_madi_speedmode(hdspm, val);
3578         spin_unlock_irq(&hdspm->lock);
3579         return change;
3580 }
3581
3582 #define HDSPM_MIXER(xname, xindex) \
3583 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3584   .name = xname, \
3585   .index = xindex, \
3586   .device = 0, \
3587   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3588                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3589   .info = snd_hdspm_info_mixer, \
3590   .get = snd_hdspm_get_mixer, \
3591   .put = snd_hdspm_put_mixer \
3592 }
3593
3594 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3595                                 struct snd_ctl_elem_info *uinfo)
3596 {
3597         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3598         uinfo->count = 3;
3599         uinfo->value.integer.min = 0;
3600         uinfo->value.integer.max = 65535;
3601         uinfo->value.integer.step = 1;
3602         return 0;
3603 }
3604
3605 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3606                                struct snd_ctl_elem_value *ucontrol)
3607 {
3608         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3609         int source;
3610         int destination;
3611
3612         source = ucontrol->value.integer.value[0];
3613         if (source < 0)
3614                 source = 0;
3615         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3616                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3617
3618         destination = ucontrol->value.integer.value[1];
3619         if (destination < 0)
3620                 destination = 0;
3621         else if (destination >= HDSPM_MAX_CHANNELS)
3622                 destination = HDSPM_MAX_CHANNELS - 1;
3623
3624         spin_lock_irq(&hdspm->lock);
3625         if (source >= HDSPM_MAX_CHANNELS)
3626                 ucontrol->value.integer.value[2] =
3627                     hdspm_read_pb_gain(hdspm, destination,
3628                                        source - HDSPM_MAX_CHANNELS);
3629         else
3630                 ucontrol->value.integer.value[2] =
3631                     hdspm_read_in_gain(hdspm, destination, source);
3632
3633         spin_unlock_irq(&hdspm->lock);
3634
3635         return 0;
3636 }
3637
3638 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3639                                struct snd_ctl_elem_value *ucontrol)
3640 {
3641         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3642         int change;
3643         int source;
3644         int destination;
3645         int gain;
3646
3647         if (!snd_hdspm_use_is_exclusive(hdspm))
3648                 return -EBUSY;
3649
3650         source = ucontrol->value.integer.value[0];
3651         destination = ucontrol->value.integer.value[1];
3652
3653         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3654                 return -1;
3655         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3656                 return -1;
3657
3658         gain = ucontrol->value.integer.value[2];
3659
3660         spin_lock_irq(&hdspm->lock);
3661
3662         if (source >= HDSPM_MAX_CHANNELS)
3663                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3664                                                     source -
3665                                                     HDSPM_MAX_CHANNELS);
3666         else
3667                 change = gain != hdspm_read_in_gain(hdspm, destination,
3668                                                     source);
3669
3670         if (change) {
3671                 if (source >= HDSPM_MAX_CHANNELS)
3672                         hdspm_write_pb_gain(hdspm, destination,
3673                                             source - HDSPM_MAX_CHANNELS,
3674                                             gain);
3675                 else
3676                         hdspm_write_in_gain(hdspm, destination, source,
3677                                             gain);
3678         }
3679         spin_unlock_irq(&hdspm->lock);
3680
3681         return change;
3682 }
3683
3684 /* The simple mixer control(s) provide gain control for the
3685    basic 1:1 mappings of playback streams to output
3686    streams.
3687 */
3688
3689 #define HDSPM_PLAYBACK_MIXER \
3690 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3691   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3692                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3693   .info = snd_hdspm_info_playback_mixer, \
3694   .get = snd_hdspm_get_playback_mixer, \
3695   .put = snd_hdspm_put_playback_mixer \
3696 }
3697
3698 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3699                                          struct snd_ctl_elem_info *uinfo)
3700 {
3701         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3702         uinfo->count = 1;
3703         uinfo->value.integer.min = 0;
3704         uinfo->value.integer.max = 64;
3705         uinfo->value.integer.step = 1;
3706         return 0;
3707 }
3708
3709 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3710                                         struct snd_ctl_elem_value *ucontrol)
3711 {
3712         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3713         int channel;
3714
3715         channel = ucontrol->id.index - 1;
3716
3717         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3718                 return -EINVAL;
3719
3720         spin_lock_irq(&hdspm->lock);
3721         ucontrol->value.integer.value[0] =
3722           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3723         spin_unlock_irq(&hdspm->lock);
3724
3725         return 0;
3726 }
3727
3728 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3729                                         struct snd_ctl_elem_value *ucontrol)
3730 {
3731         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3732         int change;
3733         int channel;
3734         int gain;
3735
3736         if (!snd_hdspm_use_is_exclusive(hdspm))
3737                 return -EBUSY;
3738
3739         channel = ucontrol->id.index - 1;
3740
3741         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3742                 return -EINVAL;
3743
3744         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3745
3746         spin_lock_irq(&hdspm->lock);
3747         change =
3748             gain != hdspm_read_pb_gain(hdspm, channel,
3749                                        channel);
3750         if (change)
3751                 hdspm_write_pb_gain(hdspm, channel, channel,
3752                                     gain);
3753         spin_unlock_irq(&hdspm->lock);
3754         return change;
3755 }
3756
3757 #define HDSPM_SYNC_CHECK(xname, xindex) \
3758 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3759         .name = xname, \
3760         .private_value = xindex, \
3761         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3762         .info = snd_hdspm_info_sync_check, \
3763         .get = snd_hdspm_get_sync_check \
3764 }
3765
3766
3767 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3768                                      struct snd_ctl_elem_info *uinfo)
3769 {
3770         static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3771         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3772         uinfo->count = 1;
3773         uinfo->value.enumerated.items = 4;
3774         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3775                 uinfo->value.enumerated.item =
3776                         uinfo->value.enumerated.items - 1;
3777         strcpy(uinfo->value.enumerated.name,
3778                         texts[uinfo->value.enumerated.item]);
3779         return 0;
3780 }
3781
3782 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3783 {
3784         int status, status2;
3785
3786         switch (hdspm->io_type) {
3787         case AES32:
3788                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3789                 if (status & HDSPM_wcSync)
3790                         return 2;
3791                 else if (status & HDSPM_wcLock)
3792                         return 1;
3793                 return 0;
3794                 break;
3795
3796         case MADI:
3797                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3798                 if (status2 & HDSPM_wcLock) {
3799                         if (status2 & HDSPM_wcSync)
3800                                 return 2;
3801                         else
3802                                 return 1;
3803                 }
3804                 return 0;
3805                 break;
3806
3807         case RayDAT:
3808         case AIO:
3809                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3810
3811                 if (status & 0x2000000)
3812                         return 2;
3813                 else if (status & 0x1000000)
3814                         return 1;
3815                 return 0;
3816
3817                 break;
3818
3819         case MADIface:
3820                 break;
3821         }
3822
3823
3824         return 3;
3825 }
3826
3827
3828 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3829 {
3830         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3831         if (status & HDSPM_madiLock) {
3832                 if (status & HDSPM_madiSync)
3833                         return 2;
3834                 else
3835                         return 1;
3836         }
3837         return 0;
3838 }
3839
3840
3841 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3842 {
3843         int status, lock, sync;
3844
3845         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3846
3847         lock = (status & (0x1<<idx)) ? 1 : 0;
3848         sync = (status & (0x100<<idx)) ? 1 : 0;
3849
3850         if (lock && sync)
3851                 return 2;
3852         else if (lock)
3853                 return 1;
3854         return 0;
3855 }
3856
3857
3858 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3859 {
3860         int status, lock = 0, sync = 0;
3861
3862         switch (hdspm->io_type) {
3863         case RayDAT:
3864         case AIO:
3865                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3866                 lock = (status & 0x400) ? 1 : 0;
3867                 sync = (status & 0x800) ? 1 : 0;
3868                 break;
3869
3870         case MADI:
3871         case AES32:
3872                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3873                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3874                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3875                 break;
3876
3877         case MADIface:
3878                 break;
3879         }
3880
3881         if (lock && sync)
3882                 return 2;
3883         else if (lock)
3884                 return 1;
3885
3886         return 0;
3887 }
3888
3889 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3890 {
3891         int status2, lock, sync;
3892         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3893
3894         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3895         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3896
3897         if (sync)
3898                 return 2;
3899         else if (lock)
3900                 return 1;
3901         return 0;
3902 }
3903
3904
3905 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3906 {
3907         int status;
3908
3909         if (hdspm->tco) {
3910                 switch (hdspm->io_type) {
3911                 case MADI:
3912                 case AES32:
3913                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3914                         if (status & HDSPM_tcoLock) {
3915                                 if (status & HDSPM_tcoSync)
3916                                         return 2;
3917                                 else
3918                                         return 1;
3919                         }
3920                         return 0;
3921
3922                         break;
3923
3924                 case RayDAT:
3925                 case AIO:
3926                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3927
3928                         if (status & 0x8000000)
3929                                 return 2; /* Sync */
3930                         if (status & 0x4000000)
3931                                 return 1; /* Lock */
3932                         return 0; /* No signal */
3933                         break;
3934
3935                 default:
3936                         break;
3937                 }
3938         }
3939
3940         return 3; /* N/A */
3941 }
3942
3943
3944 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3945                                     struct snd_ctl_elem_value *ucontrol)
3946 {
3947         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3948         int val = -1;
3949
3950         switch (hdspm->io_type) {
3951         case RayDAT:
3952                 switch (kcontrol->private_value) {
3953                 case 0: /* WC */
3954                         val = hdspm_wc_sync_check(hdspm); break;
3955                 case 7: /* TCO */
3956                         val = hdspm_tco_sync_check(hdspm); break;
3957                 case 8: /* SYNC IN */
3958                         val = hdspm_sync_in_sync_check(hdspm); break;
3959                 default:
3960                         val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3961                 }
3962                 break;
3963
3964         case AIO:
3965                 switch (kcontrol->private_value) {
3966                 case 0: /* WC */
3967                         val = hdspm_wc_sync_check(hdspm); break;
3968                 case 4: /* TCO */
3969                         val = hdspm_tco_sync_check(hdspm); break;
3970                 case 5: /* SYNC IN */
3971                         val = hdspm_sync_in_sync_check(hdspm); break;
3972                 default:
3973                         val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3974                 }
3975                 break;
3976
3977         case MADI:
3978                 switch (kcontrol->private_value) {
3979                 case 0: /* WC */
3980                         val = hdspm_wc_sync_check(hdspm); break;
3981                 case 1: /* MADI */
3982                         val = hdspm_madi_sync_check(hdspm); break;
3983                 case 2: /* TCO */
3984                         val = hdspm_tco_sync_check(hdspm); break;
3985                 case 3: /* SYNC_IN */
3986                         val = hdspm_sync_in_sync_check(hdspm); break;
3987                 }
3988                 break;
3989
3990         case MADIface:
3991                 val = hdspm_madi_sync_check(hdspm); /* MADI */
3992                 break;
3993
3994         case AES32:
3995                 switch (kcontrol->private_value) {
3996                 case 0: /* WC */
3997                         val = hdspm_wc_sync_check(hdspm); break;
3998                 case 9: /* TCO */
3999                         val = hdspm_tco_sync_check(hdspm); break;
4000                 case 10 /* SYNC IN */:
4001                         val = hdspm_sync_in_sync_check(hdspm); break;
4002                 default: /* AES1 to AES8 */
4003                          val = hdspm_aes_sync_check(hdspm,
4004                                          kcontrol->private_value-1);
4005                 }
4006                 break;
4007
4008         }
4009
4010         if (-1 == val)
4011                 val = 3;
4012
4013         ucontrol->value.enumerated.item[0] = val;
4014         return 0;
4015 }
4016
4017
4018
4019 /**
4020  * TCO controls
4021  **/
4022 static void hdspm_tco_write(struct hdspm *hdspm)
4023 {
4024         unsigned int tc[4] = { 0, 0, 0, 0};
4025
4026         switch (hdspm->tco->input) {
4027         case 0:
4028                 tc[2] |= HDSPM_TCO2_set_input_MSB;
4029                 break;
4030         case 1:
4031                 tc[2] |= HDSPM_TCO2_set_input_LSB;
4032                 break;
4033         default:
4034                 break;
4035         }
4036
4037         switch (hdspm->tco->framerate) {
4038         case 1:
4039                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4040                 break;
4041         case 2:
4042                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4043                 break;
4044         case 3:
4045                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4046                         HDSPM_TCO1_set_drop_frame_flag;
4047                 break;
4048         case 4:
4049                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4050                         HDSPM_TCO1_LTC_Format_MSB;
4051                 break;
4052         case 5:
4053                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4054                         HDSPM_TCO1_LTC_Format_MSB +
4055                         HDSPM_TCO1_set_drop_frame_flag;
4056                 break;
4057         default:
4058                 break;
4059         }
4060
4061         switch (hdspm->tco->wordclock) {
4062         case 1:
4063                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4064                 break;
4065         case 2:
4066                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4067                 break;
4068         default:
4069                 break;
4070         }
4071
4072         switch (hdspm->tco->samplerate) {
4073         case 1:
4074                 tc[2] |= HDSPM_TCO2_set_freq;
4075                 break;
4076         case 2:
4077                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4078                 break;
4079         default:
4080                 break;
4081         }
4082
4083         switch (hdspm->tco->pull) {
4084         case 1:
4085                 tc[2] |= HDSPM_TCO2_set_pull_up;
4086                 break;
4087         case 2:
4088                 tc[2] |= HDSPM_TCO2_set_pull_down;
4089                 break;
4090         case 3:
4091                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4092                 break;
4093         case 4:
4094                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4095                 break;
4096         default:
4097                 break;
4098         }
4099
4100         if (1 == hdspm->tco->term) {
4101                 tc[2] |= HDSPM_TCO2_set_term_75R;
4102         }
4103
4104         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4105         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4106         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4107         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4108 }
4109
4110
4111 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4112 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4113         .name = xname, \
4114         .index = xindex, \
4115         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4116                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4117         .info = snd_hdspm_info_tco_sample_rate, \
4118         .get = snd_hdspm_get_tco_sample_rate, \
4119         .put = snd_hdspm_put_tco_sample_rate \
4120 }
4121
4122 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4123                                           struct snd_ctl_elem_info *uinfo)
4124 {
4125         static char *texts[] = { "44.1 kHz", "48 kHz" };
4126         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4127         uinfo->count = 1;
4128         uinfo->value.enumerated.items = 2;
4129
4130         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4131                 uinfo->value.enumerated.item =
4132                         uinfo->value.enumerated.items - 1;
4133
4134         strcpy(uinfo->value.enumerated.name,
4135                         texts[uinfo->value.enumerated.item]);
4136
4137         return 0;
4138 }
4139
4140 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4141                                       struct snd_ctl_elem_value *ucontrol)
4142 {
4143         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4144
4145         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4146
4147         return 0;
4148 }
4149
4150 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4151                                          struct snd_ctl_elem_value *ucontrol)
4152 {
4153         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4154
4155         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4156                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4157
4158                 hdspm_tco_write(hdspm);
4159
4160                 return 1;
4161         }
4162
4163         return 0;
4164 }
4165
4166
4167 #define HDSPM_TCO_PULL(xname, xindex) \
4168 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4169         .name = xname, \
4170         .index = xindex, \
4171         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4172                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4173         .info = snd_hdspm_info_tco_pull, \
4174         .get = snd_hdspm_get_tco_pull, \
4175         .put = snd_hdspm_put_tco_pull \
4176 }
4177
4178 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4179                                    struct snd_ctl_elem_info *uinfo)
4180 {
4181         static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4182         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4183         uinfo->count = 1;
4184         uinfo->value.enumerated.items = 5;
4185
4186         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4187                 uinfo->value.enumerated.item =
4188                         uinfo->value.enumerated.items - 1;
4189
4190         strcpy(uinfo->value.enumerated.name,
4191                         texts[uinfo->value.enumerated.item]);
4192
4193         return 0;
4194 }
4195
4196 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4197                                   struct snd_ctl_elem_value *ucontrol)
4198 {
4199         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4200
4201         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4202
4203         return 0;
4204 }
4205
4206 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4207                                   struct snd_ctl_elem_value *ucontrol)
4208 {
4209         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4210
4211         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4212                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4213
4214                 hdspm_tco_write(hdspm);
4215
4216                 return 1;
4217         }
4218
4219         return 0;
4220 }
4221
4222 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4223 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4224         .name = xname, \
4225         .index = xindex, \
4226         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4227                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4228         .info = snd_hdspm_info_tco_wck_conversion, \
4229         .get = snd_hdspm_get_tco_wck_conversion, \
4230         .put = snd_hdspm_put_tco_wck_conversion \
4231 }
4232
4233 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4234                                              struct snd_ctl_elem_info *uinfo)
4235 {
4236         static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4237         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4238         uinfo->count = 1;
4239         uinfo->value.enumerated.items = 3;
4240
4241         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4242                 uinfo->value.enumerated.item =
4243                         uinfo->value.enumerated.items - 1;
4244
4245         strcpy(uinfo->value.enumerated.name,
4246                         texts[uinfo->value.enumerated.item]);
4247
4248         return 0;
4249 }
4250
4251 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4252                                             struct snd_ctl_elem_value *ucontrol)
4253 {
4254         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4255
4256         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4257
4258         return 0;
4259 }
4260
4261 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4262                                             struct snd_ctl_elem_value *ucontrol)
4263 {
4264         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4265
4266         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4267                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4268
4269                 hdspm_tco_write(hdspm);
4270
4271                 return 1;
4272         }
4273
4274         return 0;
4275 }
4276
4277
4278 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4279 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4280         .name = xname, \
4281         .index = xindex, \
4282         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4283                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4284         .info = snd_hdspm_info_tco_frame_rate, \
4285         .get = snd_hdspm_get_tco_frame_rate, \
4286         .put = snd_hdspm_put_tco_frame_rate \
4287 }
4288
4289 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4290                                           struct snd_ctl_elem_info *uinfo)
4291 {
4292         static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4293                 "29.97 dfps", "30 fps", "30 dfps" };
4294         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4295         uinfo->count = 1;
4296         uinfo->value.enumerated.items = 6;
4297
4298         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4299                 uinfo->value.enumerated.item =
4300                         uinfo->value.enumerated.items - 1;
4301
4302         strcpy(uinfo->value.enumerated.name,
4303                         texts[uinfo->value.enumerated.item]);
4304
4305         return 0;
4306 }
4307
4308 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4309                                         struct snd_ctl_elem_value *ucontrol)
4310 {
4311         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4312
4313         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4314
4315         return 0;
4316 }
4317
4318 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4319                                         struct snd_ctl_elem_value *ucontrol)
4320 {
4321         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4322
4323         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4324                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4325
4326                 hdspm_tco_write(hdspm);
4327
4328                 return 1;
4329         }
4330
4331         return 0;
4332 }
4333
4334
4335 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4336 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4337         .name = xname, \
4338         .index = xindex, \
4339         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4340                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4341         .info = snd_hdspm_info_tco_sync_source, \
4342         .get = snd_hdspm_get_tco_sync_source, \
4343         .put = snd_hdspm_put_tco_sync_source \
4344 }
4345
4346 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4347                                           struct snd_ctl_elem_info *uinfo)
4348 {
4349         static char *texts[] = { "LTC", "Video", "WCK" };
4350         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4351         uinfo->count = 1;
4352         uinfo->value.enumerated.items = 3;
4353
4354         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4355                 uinfo->value.enumerated.item =
4356                         uinfo->value.enumerated.items - 1;
4357
4358         strcpy(uinfo->value.enumerated.name,
4359                         texts[uinfo->value.enumerated.item]);
4360
4361         return 0;
4362 }
4363
4364 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4365                                          struct snd_ctl_elem_value *ucontrol)
4366 {
4367         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4368
4369         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4370
4371         return 0;
4372 }
4373
4374 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4375                                          struct snd_ctl_elem_value *ucontrol)
4376 {
4377         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4378
4379         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4380                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4381
4382                 hdspm_tco_write(hdspm);
4383
4384                 return 1;
4385         }
4386
4387         return 0;
4388 }
4389
4390
4391 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4392 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4393         .name = xname, \
4394         .index = xindex, \
4395         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4396                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4397         .info = snd_hdspm_info_tco_word_term, \
4398         .get = snd_hdspm_get_tco_word_term, \
4399         .put = snd_hdspm_put_tco_word_term \
4400 }
4401
4402 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4403                                         struct snd_ctl_elem_info *uinfo)
4404 {
4405         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4406         uinfo->count = 1;
4407         uinfo->value.integer.min = 0;
4408         uinfo->value.integer.max = 1;
4409
4410         return 0;
4411 }
4412
4413
4414 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4415                                        struct snd_ctl_elem_value *ucontrol)
4416 {
4417         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4418
4419         ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4420
4421         return 0;
4422 }
4423
4424
4425 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4426                                        struct snd_ctl_elem_value *ucontrol)
4427 {
4428         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4429
4430         if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4431                 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4432
4433                 hdspm_tco_write(hdspm);
4434
4435                 return 1;
4436         }
4437
4438         return 0;
4439 }
4440
4441
4442
4443
4444 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4445         HDSPM_MIXER("Mixer", 0),
4446         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4447         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4448         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4449         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4450         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4451         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4452         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4453         HDSPM_SYNC_CHECK("TCO SyncCHeck", 2),
4454         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4455         HDSPM_LINE_OUT("Line Out", 0),
4456         HDSPM_TX_64("TX 64 channels mode", 0),
4457         HDSPM_C_TMS("Clear Track Marker", 0),
4458         HDSPM_SAFE_MODE("Safe Mode", 0),
4459         HDSPM_INPUT_SELECT("Input Select", 0),
4460         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4461 };
4462
4463
4464 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4465         HDSPM_MIXER("Mixer", 0),
4466         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4467         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4468         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4469         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4470         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4471         HDSPM_TX_64("TX 64 channels mode", 0),
4472         HDSPM_C_TMS("Clear Track Marker", 0),
4473         HDSPM_SAFE_MODE("Safe Mode", 0),
4474         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4475 };
4476
4477 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4478         HDSPM_MIXER("Mixer", 0),
4479         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4480         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4481         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4482         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4483         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4484         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4485         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4486         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4487         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4488         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4489         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4490         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4491         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4492         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4493         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4494         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4495         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4496         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4497
4498                 /*
4499                    HDSPM_INPUT_SELECT("Input Select", 0),
4500                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4501                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4502                    HDSPM_SPDIF_IN("SPDIF In", 0);
4503                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4504                    HDSPM_INPUT_LEVEL("Input Level", 0);
4505                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4506                    HDSPM_PHONES("Phones", 0);
4507                    */
4508 };
4509
4510 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4511         HDSPM_MIXER("Mixer", 0),
4512         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4513         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4514         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4515         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4516         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4517         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4518         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4519         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4520         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4521         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4522         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4523         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4524         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4525         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4526         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4527         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4528         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4529         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4530         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4531         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4532         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4533         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4534 };
4535
4536 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4537         HDSPM_MIXER("Mixer", 0),
4538         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4539         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4540         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4541         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4542         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4543         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4544         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4545         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4546         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4547         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4548         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4549         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4550         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4551         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4552         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4553         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4554         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4555         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4556         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4557         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4558         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4559         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4560         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4561         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4562         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4563         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4564         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4565         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4566         HDSPM_LINE_OUT("Line Out", 0),
4567         HDSPM_EMPHASIS("Emphasis", 0),
4568         HDSPM_DOLBY("Non Audio", 0),
4569         HDSPM_PROFESSIONAL("Professional", 0),
4570         HDSPM_C_TMS("Clear Track Marker", 0),
4571         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4572         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4573 };
4574
4575
4576
4577 /* Control elements for the optional TCO module */
4578 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4579         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4580         HDSPM_TCO_PULL("TCO Pull", 0),
4581         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4582         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4583         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4584         HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
4585 };
4586
4587
4588 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4589
4590
4591 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4592 {
4593         int i;
4594
4595         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4596                 if (hdspm->system_sample_rate > 48000) {
4597                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4598                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4599                                 SNDRV_CTL_ELEM_ACCESS_READ |
4600                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4601                 } else {
4602                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4603                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4604                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4605                 }
4606                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4607                                 SNDRV_CTL_EVENT_MASK_INFO,
4608                                 &hdspm->playback_mixer_ctls[i]->id);
4609         }
4610
4611         return 0;
4612 }
4613
4614
4615 static int snd_hdspm_create_controls(struct snd_card *card,
4616                                         struct hdspm *hdspm)
4617 {
4618         unsigned int idx, limit;
4619         int err;
4620         struct snd_kcontrol *kctl;
4621         struct snd_kcontrol_new *list = NULL;
4622
4623         switch (hdspm->io_type) {
4624         case MADI:
4625                 list = snd_hdspm_controls_madi;
4626                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4627                 break;
4628         case MADIface:
4629                 list = snd_hdspm_controls_madiface;
4630                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4631                 break;
4632         case AIO:
4633                 list = snd_hdspm_controls_aio;
4634                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4635                 break;
4636         case RayDAT:
4637                 list = snd_hdspm_controls_raydat;
4638                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4639                 break;
4640         case AES32:
4641                 list = snd_hdspm_controls_aes32;
4642                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4643                 break;
4644         }
4645
4646         if (NULL != list) {
4647                 for (idx = 0; idx < limit; idx++) {
4648                         err = snd_ctl_add(card,
4649                                         snd_ctl_new1(&list[idx], hdspm));
4650                         if (err < 0)
4651                                 return err;
4652                 }
4653         }
4654
4655
4656         /* create simple 1:1 playback mixer controls */
4657         snd_hdspm_playback_mixer.name = "Chn";
4658         if (hdspm->system_sample_rate >= 128000) {
4659                 limit = hdspm->qs_out_channels;
4660         } else if (hdspm->system_sample_rate >= 64000) {
4661                 limit = hdspm->ds_out_channels;
4662         } else {
4663                 limit = hdspm->ss_out_channels;
4664         }
4665         for (idx = 0; idx < limit; ++idx) {
4666                 snd_hdspm_playback_mixer.index = idx + 1;
4667                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4668                 err = snd_ctl_add(card, kctl);
4669                 if (err < 0)
4670                         return err;
4671                 hdspm->playback_mixer_ctls[idx] = kctl;
4672         }
4673
4674
4675         if (hdspm->tco) {
4676                 /* add tco control elements */
4677                 list = snd_hdspm_controls_tco;
4678                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4679                 for (idx = 0; idx < limit; idx++) {
4680                         err = snd_ctl_add(card,
4681                                         snd_ctl_new1(&list[idx], hdspm));
4682                         if (err < 0)
4683                                 return err;
4684                 }
4685         }
4686
4687         return 0;
4688 }
4689
4690 /*------------------------------------------------------------
4691    /proc interface
4692  ------------------------------------------------------------*/
4693
4694 static void
4695 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4696                          struct snd_info_buffer *buffer)
4697 {
4698         struct hdspm *hdspm = entry->private_data;
4699         unsigned int status, status2, control, freq;
4700
4701         char *pref_sync_ref;
4702         char *autosync_ref;
4703         char *system_clock_mode;
4704         char *insel;
4705         int x, x2;
4706
4707         /* TCO stuff */
4708         int a, ltc, frames, seconds, minutes, hours;
4709         unsigned int period;
4710         u64 freq_const = 0;
4711         u32 rate;
4712
4713         status = hdspm_read(hdspm, HDSPM_statusRegister);
4714         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4715         control = hdspm->control_register;
4716         freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4717
4718         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4719                         hdspm->card_name, hdspm->card->number + 1,
4720                         hdspm->firmware_rev,
4721                         (status2 & HDSPM_version0) |
4722                         (status2 & HDSPM_version1) | (status2 &
4723                                 HDSPM_version2));
4724
4725         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4726                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4727                         hdspm->serial);
4728
4729         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4730                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4731
4732         snd_iprintf(buffer, "--- System ---\n");
4733
4734         snd_iprintf(buffer,
4735                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4736                 status & HDSPM_audioIRQPending,
4737                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4738                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4739                 hdspm->irq_count);
4740         snd_iprintf(buffer,
4741                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4742                 "estimated= %ld (bytes)\n",
4743                 ((status & HDSPM_BufferID) ? 1 : 0),
4744                 (status & HDSPM_BufferPositionMask),
4745                 (status & HDSPM_BufferPositionMask) %
4746                 (2 * (int)hdspm->period_bytes),
4747                 ((status & HDSPM_BufferPositionMask) - 64) %
4748                 (2 * (int)hdspm->period_bytes),
4749                 (long) hdspm_hw_pointer(hdspm) * 4);
4750
4751         snd_iprintf(buffer,
4752                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4753                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4754                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4755                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4756                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4757         snd_iprintf(buffer,
4758                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4759                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4760                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4761         snd_iprintf(buffer,
4762                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4763                 "status2=0x%x\n",
4764                 hdspm->control_register, hdspm->control2_register,
4765                 status, status2);
4766         if (status & HDSPM_tco_detect) {
4767                 snd_iprintf(buffer, "TCO module detected.\n");
4768                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4769                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4770                         snd_iprintf(buffer, "  LTC valid, ");
4771                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4772                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4773                         case 0:
4774                                 snd_iprintf(buffer, "24 fps, ");
4775                                 break;
4776                         case HDSPM_TCO1_LTC_Format_LSB:
4777                                 snd_iprintf(buffer, "25 fps, ");
4778                                 break;
4779                         case HDSPM_TCO1_LTC_Format_MSB:
4780                                 snd_iprintf(buffer, "29.97 fps, ");
4781                                 break;
4782                         default:
4783                                 snd_iprintf(buffer, "30 fps, ");
4784                                 break;
4785                         }
4786                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4787                                 snd_iprintf(buffer, "drop frame\n");
4788                         } else {
4789                                 snd_iprintf(buffer, "full frame\n");
4790                         }
4791                 } else {
4792                         snd_iprintf(buffer, "  no LTC\n");
4793                 }
4794                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4795                         snd_iprintf(buffer, "  Video: NTSC\n");
4796                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4797                         snd_iprintf(buffer, "  Video: PAL\n");
4798                 } else {
4799                         snd_iprintf(buffer, "  No video\n");
4800                 }
4801                 if (a & HDSPM_TCO1_TCO_lock) {
4802                         snd_iprintf(buffer, "  Sync: lock\n");
4803                 } else {
4804                         snd_iprintf(buffer, "  Sync: no lock\n");
4805                 }
4806
4807                 switch (hdspm->io_type) {
4808                 case MADI:
4809                 case AES32:
4810                         freq_const = 110069313433624ULL;
4811                         break;
4812                 case RayDAT:
4813                 case AIO:
4814                         freq_const = 104857600000000ULL;
4815                         break;
4816                 case MADIface:
4817                         break; /* no TCO possible */
4818                 }
4819
4820                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4821                 snd_iprintf(buffer, "    period: %u\n", period);
4822
4823
4824                 /* rate = freq_const/period; */
4825                 rate = div_u64(freq_const, period);
4826
4827                 if (control & HDSPM_QuadSpeed) {
4828                         rate *= 4;
4829                 } else if (control & HDSPM_DoubleSpeed) {
4830                         rate *= 2;
4831                 }
4832
4833                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4834                                 (unsigned int) rate);
4835
4836                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4837                 frames = ltc & 0xF;
4838                 ltc >>= 4;
4839                 frames += (ltc & 0x3) * 10;
4840                 ltc >>= 4;
4841                 seconds = ltc & 0xF;
4842                 ltc >>= 4;
4843                 seconds += (ltc & 0x7) * 10;
4844                 ltc >>= 4;
4845                 minutes = ltc & 0xF;
4846                 ltc >>= 4;
4847                 minutes += (ltc & 0x7) * 10;
4848                 ltc >>= 4;
4849                 hours = ltc & 0xF;
4850                 ltc >>= 4;
4851                 hours += (ltc & 0x3) * 10;
4852                 snd_iprintf(buffer,
4853                         "  LTC In: %02d:%02d:%02d:%02d\n",
4854                         hours, minutes, seconds, frames);
4855
4856         } else {
4857                 snd_iprintf(buffer, "No TCO module detected.\n");
4858         }
4859
4860         snd_iprintf(buffer, "--- Settings ---\n");
4861
4862         x = hdspm_get_latency(hdspm);
4863
4864         snd_iprintf(buffer,
4865                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4866                 x, (unsigned long) hdspm->period_bytes);
4867
4868         snd_iprintf(buffer, "Line out: %s\n",
4869                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4870
4871         switch (hdspm->control_register & HDSPM_InputMask) {
4872         case HDSPM_InputOptical:
4873                 insel = "Optical";
4874                 break;
4875         case HDSPM_InputCoaxial:
4876                 insel = "Coaxial";
4877                 break;
4878         default:
4879                 insel = "Unkown";
4880         }
4881
4882         snd_iprintf(buffer,
4883                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4884                 "Auto Input %s\n",
4885                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4886                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4887                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4888
4889
4890         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4891                 system_clock_mode = "AutoSync";
4892         else
4893                 system_clock_mode = "Master";
4894         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4895
4896         switch (hdspm_pref_sync_ref(hdspm)) {
4897         case HDSPM_SYNC_FROM_WORD:
4898                 pref_sync_ref = "Word Clock";
4899                 break;
4900         case HDSPM_SYNC_FROM_MADI:
4901                 pref_sync_ref = "MADI Sync";
4902                 break;
4903         case HDSPM_SYNC_FROM_TCO:
4904                 pref_sync_ref = "TCO";
4905                 break;
4906         case HDSPM_SYNC_FROM_SYNC_IN:
4907                 pref_sync_ref = "Sync In";
4908                 break;
4909         default:
4910                 pref_sync_ref = "XXXX Clock";
4911                 break;
4912         }
4913         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4914                         pref_sync_ref);
4915
4916         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4917                         hdspm->system_sample_rate);
4918
4919
4920         snd_iprintf(buffer, "--- Status:\n");
4921
4922         x = status & HDSPM_madiSync;
4923         x2 = status2 & HDSPM_wcSync;
4924
4925         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4926                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4927                         "NoLock",
4928                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4929                         "NoLock");
4930
4931         switch (hdspm_autosync_ref(hdspm)) {
4932         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4933                 autosync_ref = "Sync In";
4934                 break;
4935         case HDSPM_AUTOSYNC_FROM_TCO:
4936                 autosync_ref = "TCO";
4937                 break;
4938         case HDSPM_AUTOSYNC_FROM_WORD:
4939                 autosync_ref = "Word Clock";
4940                 break;
4941         case HDSPM_AUTOSYNC_FROM_MADI:
4942                 autosync_ref = "MADI Sync";
4943                 break;
4944         case HDSPM_AUTOSYNC_FROM_NONE:
4945                 autosync_ref = "Input not valid";
4946                 break;
4947         default:
4948                 autosync_ref = "---";
4949                 break;
4950         }
4951         snd_iprintf(buffer,
4952                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4953                 autosync_ref, hdspm_external_sample_rate(hdspm),
4954                 (status & HDSPM_madiFreqMask) >> 22,
4955                 (status2 & HDSPM_wcFreqMask) >> 5);
4956
4957         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4958                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4959                 (status & HDSPM_RX_64ch) ? "64 channels" :
4960                 "56 channels");
4961
4962         snd_iprintf(buffer, "\n");
4963 }
4964
4965 static void
4966 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4967                           struct snd_info_buffer *buffer)
4968 {
4969         struct hdspm *hdspm = entry->private_data;
4970         unsigned int status;
4971         unsigned int status2;
4972         unsigned int timecode;
4973         int pref_syncref;
4974         char *autosync_ref;
4975         int x;
4976
4977         status = hdspm_read(hdspm, HDSPM_statusRegister);
4978         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4979         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4980
4981         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4982                     hdspm->card_name, hdspm->card->number + 1,
4983                     hdspm->firmware_rev);
4984
4985         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4986                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4987
4988         snd_iprintf(buffer, "--- System ---\n");
4989
4990         snd_iprintf(buffer,
4991                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4992                     status & HDSPM_audioIRQPending,
4993                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
4994                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
4995                     hdspm->irq_count);
4996         snd_iprintf(buffer,
4997                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
4998                     "estimated= %ld (bytes)\n",
4999                     ((status & HDSPM_BufferID) ? 1 : 0),
5000                     (status & HDSPM_BufferPositionMask),
5001                     (status & HDSPM_BufferPositionMask) %
5002                     (2 * (int)hdspm->period_bytes),
5003                     ((status & HDSPM_BufferPositionMask) - 64) %
5004                     (2 * (int)hdspm->period_bytes),
5005                     (long) hdspm_hw_pointer(hdspm) * 4);
5006
5007         snd_iprintf(buffer,
5008                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5009                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5010                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5011                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5012                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5013         snd_iprintf(buffer,
5014                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5015                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5016                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5017         snd_iprintf(buffer,
5018                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5019                     "status2=0x%x\n",
5020                     hdspm->control_register, hdspm->control2_register,
5021                     status, status2);
5022
5023         snd_iprintf(buffer, "--- Settings ---\n");
5024
5025         x = hdspm_get_latency(hdspm);
5026
5027         snd_iprintf(buffer,
5028                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5029                     x, (unsigned long) hdspm->period_bytes);
5030
5031         snd_iprintf(buffer, "Line out: %s\n",
5032                     (hdspm->
5033                      control_register & HDSPM_LineOut) ? "on " : "off");
5034
5035         snd_iprintf(buffer,
5036                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5037                     (hdspm->
5038                      control_register & HDSPM_clr_tms) ? "on" : "off",
5039                     (hdspm->
5040                      control_register & HDSPM_Emphasis) ? "on" : "off",
5041                     (hdspm->
5042                      control_register & HDSPM_Dolby) ? "on" : "off");
5043
5044
5045         pref_syncref = hdspm_pref_sync_ref(hdspm);
5046         if (pref_syncref == 0)
5047                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5048         else
5049                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5050                                 pref_syncref);
5051
5052         snd_iprintf(buffer, "System Clock Frequency: %d\n",
5053                     hdspm->system_sample_rate);
5054
5055         snd_iprintf(buffer, "Double speed: %s\n",
5056                         hdspm->control_register & HDSPM_DS_DoubleWire?
5057                         "Double wire" : "Single wire");
5058         snd_iprintf(buffer, "Quad speed: %s\n",
5059                         hdspm->control_register & HDSPM_QS_DoubleWire?
5060                         "Double wire" :
5061                         hdspm->control_register & HDSPM_QS_QuadWire?
5062                         "Quad wire" : "Single wire");
5063
5064         snd_iprintf(buffer, "--- Status:\n");
5065
5066         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
5067                     (status & HDSPM_AES32_wcLock) ? "Sync   " : "No Lock",
5068                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5069
5070         for (x = 0; x < 8; x++) {
5071                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
5072                             x+1,
5073                             (status2 & (HDSPM_LockAES >> x)) ?
5074                             "Sync   " : "No Lock",
5075                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5076         }
5077
5078         switch (hdspm_autosync_ref(hdspm)) {
5079         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5080                 autosync_ref = "None"; break;
5081         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5082                 autosync_ref = "Word Clock"; break;
5083         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5084                 autosync_ref = "AES1"; break;
5085         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5086                 autosync_ref = "AES2"; break;
5087         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5088                 autosync_ref = "AES3"; break;
5089         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5090                 autosync_ref = "AES4"; break;
5091         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5092                 autosync_ref = "AES5"; break;
5093         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5094                 autosync_ref = "AES6"; break;
5095         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5096                 autosync_ref = "AES7"; break;
5097         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5098                 autosync_ref = "AES8"; break;
5099         default:
5100                 autosync_ref = "---"; break;
5101         }
5102         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5103
5104         snd_iprintf(buffer, "\n");
5105 }
5106
5107 static void
5108 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5109                          struct snd_info_buffer *buffer)
5110 {
5111         struct hdspm *hdspm = entry->private_data;
5112         unsigned int status1, status2, status3, control, i;
5113         unsigned int lock, sync;
5114
5115         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5116         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5117         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5118
5119         control = hdspm->control_register;
5120
5121         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5122         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5123         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5124
5125
5126         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5127
5128         snd_iprintf(buffer, "Clock mode      : %s\n",
5129                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5130         snd_iprintf(buffer, "System frequency: %d Hz\n",
5131                 hdspm_get_system_sample_rate(hdspm));
5132
5133         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5134
5135         lock = 0x1;
5136         sync = 0x100;
5137
5138         for (i = 0; i < 8; i++) {
5139                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5140                                 i,
5141                                 (status1 & lock) ? 1 : 0,
5142                                 (status1 & sync) ? 1 : 0,
5143                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
5144
5145                 lock = lock<<1;
5146                 sync = sync<<1;
5147         }
5148
5149         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5150                         (status1 & 0x1000000) ? 1 : 0,
5151                         (status1 & 0x2000000) ? 1 : 0,
5152                         texts_freq[(status1 >> 16) & 0xF]);
5153
5154         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5155                         (status1 & 0x4000000) ? 1 : 0,
5156                         (status1 & 0x8000000) ? 1 : 0,
5157                         texts_freq[(status1 >> 20) & 0xF]);
5158
5159         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5160                         (status3 & 0x400) ? 1 : 0,
5161                         (status3 & 0x800) ? 1 : 0,
5162                         texts_freq[(status2 >> 12) & 0xF]);
5163
5164 }
5165
5166 #ifdef CONFIG_SND_DEBUG
5167 static void
5168 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5169                           struct snd_info_buffer *buffer)
5170 {
5171         struct hdspm *hdspm = entry->private_data;
5172
5173         int j,i;
5174
5175         for (i = 0; i < 256 /* 1024*64 */; i += j) {
5176                 snd_iprintf(buffer, "0x%08X: ", i);
5177                 for (j = 0; j < 16; j += 4)
5178                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5179                 snd_iprintf(buffer, "\n");
5180         }
5181 }
5182 #endif
5183
5184
5185 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5186                           struct snd_info_buffer *buffer)
5187 {
5188         struct hdspm *hdspm = entry->private_data;
5189         int i;
5190
5191         snd_iprintf(buffer, "# generated by hdspm\n");
5192
5193         for (i = 0; i < hdspm->max_channels_in; i++) {
5194                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5195         }
5196 }
5197
5198 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5199                           struct snd_info_buffer *buffer)
5200 {
5201         struct hdspm *hdspm = entry->private_data;
5202         int i;
5203
5204         snd_iprintf(buffer, "# generated by hdspm\n");
5205
5206         for (i = 0; i < hdspm->max_channels_out; i++) {
5207                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5208         }
5209 }
5210
5211
5212 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
5213 {
5214         struct snd_info_entry *entry;
5215
5216         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5217                 switch (hdspm->io_type) {
5218                 case AES32:
5219                         snd_info_set_text_ops(entry, hdspm,
5220                                         snd_hdspm_proc_read_aes32);
5221                         break;
5222                 case MADI:
5223                         snd_info_set_text_ops(entry, hdspm,
5224                                         snd_hdspm_proc_read_madi);
5225                         break;
5226                 case MADIface:
5227                         /* snd_info_set_text_ops(entry, hdspm,
5228                          snd_hdspm_proc_read_madiface); */
5229                         break;
5230                 case RayDAT:
5231                         snd_info_set_text_ops(entry, hdspm,
5232                                         snd_hdspm_proc_read_raydat);
5233                         break;
5234                 case AIO:
5235                         break;
5236                 }
5237         }
5238
5239         if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5240                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5241         }
5242
5243         if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5244                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5245         }
5246
5247 #ifdef CONFIG_SND_DEBUG
5248         /* debug file to read all hdspm registers */
5249         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5250                 snd_info_set_text_ops(entry, hdspm,
5251                                 snd_hdspm_proc_read_debug);
5252 #endif
5253 }
5254
5255 /*------------------------------------------------------------
5256    hdspm intitialize
5257  ------------------------------------------------------------*/
5258
5259 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5260 {
5261         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5262            hold it (e.g. during module initialization).
5263            */
5264
5265         /* set defaults:       */
5266
5267         hdspm->settings_register = 0;
5268
5269         switch (hdspm->io_type) {
5270         case MADI:
5271         case MADIface:
5272                 hdspm->control_register =
5273                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5274                 break;
5275
5276         case RayDAT:
5277         case AIO:
5278                 hdspm->settings_register = 0x1 + 0x1000;
5279                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5280                  * line_out */
5281                 hdspm->control_register =
5282                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5283                 break;
5284
5285         case AES32:
5286                 hdspm->control_register =
5287                         HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5288                         hdspm_encode_latency(7) | /* latency max=8192samples */
5289                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5290                         HDSPM_LineOut | /* Analog output in */
5291                         HDSPM_Professional;  /* Professional mode */
5292                 break;
5293         }
5294
5295         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5296
5297         if (AES32 == hdspm->io_type) {
5298                 /* No control2 register for AES32 */
5299 #ifdef SNDRV_BIG_ENDIAN
5300                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5301 #else
5302                 hdspm->control2_register = 0;
5303 #endif
5304
5305                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5306         }
5307         hdspm_compute_period_size(hdspm);
5308
5309         /* silence everything */
5310
5311         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5312
5313         if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5314                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5315         }
5316
5317         /* set a default rate so that the channel map is set up. */
5318         hdspm_set_rate(hdspm, 48000, 1);
5319
5320         return 0;
5321 }
5322
5323
5324 /*------------------------------------------------------------
5325    interrupt
5326  ------------------------------------------------------------*/
5327
5328 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5329 {
5330         struct hdspm *hdspm = (struct hdspm *) dev_id;
5331         unsigned int status;
5332         int i, audio, midi, schedule = 0;
5333         /* cycles_t now; */
5334
5335         status = hdspm_read(hdspm, HDSPM_statusRegister);
5336
5337         audio = status & HDSPM_audioIRQPending;
5338         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5339                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5340
5341         /* now = get_cycles(); */
5342         /**
5343          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5344          *          6       4096   ~256053425     ~514672358
5345          *          5       2048   ~128024983     ~257373821
5346          *          4       1024    ~64023706     ~128718089
5347          *          3        512    ~32005945      ~64385999
5348          *          2        256    ~16003039      ~32260176
5349          *          1        128     ~7998738      ~16194507
5350          *          0         64     ~3998231       ~8191558
5351          **/
5352         /*
5353            snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5354            now-hdspm->last_interrupt, status & 0xFFC0);
5355            hdspm->last_interrupt = now;
5356         */
5357
5358         if (!audio && !midi)
5359                 return IRQ_NONE;
5360
5361         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5362         hdspm->irq_count++;
5363
5364
5365         if (audio) {
5366                 if (hdspm->capture_substream)
5367                         snd_pcm_period_elapsed(hdspm->capture_substream);
5368
5369                 if (hdspm->playback_substream)
5370                         snd_pcm_period_elapsed(hdspm->playback_substream);
5371         }
5372
5373         if (midi) {
5374                 i = 0;
5375                 while (i < hdspm->midiPorts) {
5376                         if ((hdspm_read(hdspm,
5377                                 hdspm->midi[i].statusIn) & 0xff) &&
5378                                         (status & hdspm->midi[i].irq)) {
5379                                 /* we disable interrupts for this input until
5380                                  * processing is done
5381                                  */
5382                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5383                                 hdspm_write(hdspm, HDSPM_controlRegister,
5384                                                 hdspm->control_register);
5385                                 hdspm->midi[i].pending = 1;
5386                                 schedule = 1;
5387                         }
5388
5389                         i++;
5390                 }
5391
5392                 if (schedule)
5393                         tasklet_hi_schedule(&hdspm->midi_tasklet);
5394         }
5395
5396         return IRQ_HANDLED;
5397 }
5398
5399 /*------------------------------------------------------------
5400    pcm interface
5401   ------------------------------------------------------------*/
5402
5403
5404 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5405                                               *substream)
5406 {
5407         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5408         return hdspm_hw_pointer(hdspm);
5409 }
5410
5411
5412 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5413 {
5414         struct snd_pcm_runtime *runtime = substream->runtime;
5415         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5416         struct snd_pcm_substream *other;
5417
5418         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5419                 other = hdspm->capture_substream;
5420         else
5421                 other = hdspm->playback_substream;
5422
5423         if (hdspm->running)
5424                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5425         else
5426                 runtime->status->hw_ptr = 0;
5427         if (other) {
5428                 struct snd_pcm_substream *s;
5429                 struct snd_pcm_runtime *oruntime = other->runtime;
5430                 snd_pcm_group_for_each_entry(s, substream) {
5431                         if (s == other) {
5432                                 oruntime->status->hw_ptr =
5433                                         runtime->status->hw_ptr;
5434                                 break;
5435                         }
5436                 }
5437         }
5438         return 0;
5439 }
5440
5441 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5442                                struct snd_pcm_hw_params *params)
5443 {
5444         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5445         int err;
5446         int i;
5447         pid_t this_pid;
5448         pid_t other_pid;
5449
5450         spin_lock_irq(&hdspm->lock);
5451
5452         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5453                 this_pid = hdspm->playback_pid;
5454                 other_pid = hdspm->capture_pid;
5455         } else {
5456                 this_pid = hdspm->capture_pid;
5457                 other_pid = hdspm->playback_pid;
5458         }
5459
5460         if (other_pid > 0 && this_pid != other_pid) {
5461
5462                 /* The other stream is open, and not by the same
5463                    task as this one. Make sure that the parameters
5464                    that matter are the same.
5465                    */
5466
5467                 if (params_rate(params) != hdspm->system_sample_rate) {
5468                         spin_unlock_irq(&hdspm->lock);
5469                         _snd_pcm_hw_param_setempty(params,
5470                                         SNDRV_PCM_HW_PARAM_RATE);
5471                         return -EBUSY;
5472                 }
5473
5474                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5475                         spin_unlock_irq(&hdspm->lock);
5476                         _snd_pcm_hw_param_setempty(params,
5477                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5478                         return -EBUSY;
5479                 }
5480
5481         }
5482         /* We're fine. */
5483         spin_unlock_irq(&hdspm->lock);
5484
5485         /* how to make sure that the rate matches an externally-set one ?   */
5486
5487         spin_lock_irq(&hdspm->lock);
5488         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5489         if (err < 0) {
5490                 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5491                 spin_unlock_irq(&hdspm->lock);
5492                 _snd_pcm_hw_param_setempty(params,
5493                                 SNDRV_PCM_HW_PARAM_RATE);
5494                 return err;
5495         }
5496         spin_unlock_irq(&hdspm->lock);
5497
5498         err = hdspm_set_interrupt_interval(hdspm,
5499                         params_period_size(params));
5500         if (err < 0) {
5501                 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5502                 _snd_pcm_hw_param_setempty(params,
5503                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5504                 return err;
5505         }
5506
5507         /* Memory allocation, takashi's method, dont know if we should
5508          * spinlock
5509          */
5510         /* malloc all buffer even if not enabled to get sure */
5511         /* Update for MADI rev 204: we need to allocate for all channels,
5512          * otherwise it doesn't work at 96kHz */
5513
5514         err =
5515                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5516         if (err < 0) {
5517                 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5518                 return err;
5519         }
5520
5521         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5522
5523                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5524                                 params_channels(params));
5525
5526                 for (i = 0; i < params_channels(params); ++i)
5527                         snd_hdspm_enable_out(hdspm, i, 1);
5528
5529                 hdspm->playback_buffer =
5530                         (unsigned char *) substream->runtime->dma_area;
5531                 snd_printdd("Allocated sample buffer for playback at %p\n",
5532                                 hdspm->playback_buffer);
5533         } else {
5534                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5535                                 params_channels(params));
5536
5537                 for (i = 0; i < params_channels(params); ++i)
5538                         snd_hdspm_enable_in(hdspm, i, 1);
5539
5540                 hdspm->capture_buffer =
5541                         (unsigned char *) substream->runtime->dma_area;
5542                 snd_printdd("Allocated sample buffer for capture at %p\n",
5543                                 hdspm->capture_buffer);
5544         }
5545
5546         /*
5547            snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5548            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5549            "playback" : "capture",
5550            snd_pcm_sgbuf_get_addr(substream, 0));
5551            */
5552         /*
5553            snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5554            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5555            "playback" : "capture",
5556            params_rate(params), params_channels(params),
5557            params_buffer_size(params));
5558            */
5559
5560
5561         /* Switch to native float format if requested */
5562         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5563                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5564                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5565
5566                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5567         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5568                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5569                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5570
5571                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5572         }
5573         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5574
5575         return 0;
5576 }
5577
5578 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5579 {
5580         int i;
5581         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5582
5583         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5584
5585                 /* params_channels(params) should be enough,
5586                    but to get sure in case of error */
5587                 for (i = 0; i < hdspm->max_channels_out; ++i)
5588                         snd_hdspm_enable_out(hdspm, i, 0);
5589
5590                 hdspm->playback_buffer = NULL;
5591         } else {
5592                 for (i = 0; i < hdspm->max_channels_in; ++i)
5593                         snd_hdspm_enable_in(hdspm, i, 0);
5594
5595                 hdspm->capture_buffer = NULL;
5596
5597         }
5598
5599         snd_pcm_lib_free_pages(substream);
5600
5601         return 0;
5602 }
5603
5604
5605 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5606                 struct snd_pcm_channel_info *info)
5607 {
5608         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5609
5610         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5611                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5612                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5613                         return -EINVAL;
5614                 }
5615
5616                 if (hdspm->channel_map_out[info->channel] < 0) {
5617                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5618                         return -EINVAL;
5619                 }
5620
5621                 info->offset = hdspm->channel_map_out[info->channel] *
5622                         HDSPM_CHANNEL_BUFFER_BYTES;
5623         } else {
5624                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5625                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5626                         return -EINVAL;
5627                 }
5628
5629                 if (hdspm->channel_map_in[info->channel] < 0) {
5630                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5631                         return -EINVAL;
5632                 }
5633
5634                 info->offset = hdspm->channel_map_in[info->channel] *
5635                         HDSPM_CHANNEL_BUFFER_BYTES;
5636         }
5637
5638         info->first = 0;
5639         info->step = 32;
5640         return 0;
5641 }
5642
5643
5644 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5645                 unsigned int cmd, void *arg)
5646 {
5647         switch (cmd) {
5648         case SNDRV_PCM_IOCTL1_RESET:
5649                 return snd_hdspm_reset(substream);
5650
5651         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5652                 {
5653                         struct snd_pcm_channel_info *info = arg;
5654                         return snd_hdspm_channel_info(substream, info);
5655                 }
5656         default:
5657                 break;
5658         }
5659
5660         return snd_pcm_lib_ioctl(substream, cmd, arg);
5661 }
5662
5663 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5664 {
5665         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5666         struct snd_pcm_substream *other;
5667         int running;
5668
5669         spin_lock(&hdspm->lock);
5670         running = hdspm->running;
5671         switch (cmd) {
5672         case SNDRV_PCM_TRIGGER_START:
5673                 running |= 1 << substream->stream;
5674                 break;
5675         case SNDRV_PCM_TRIGGER_STOP:
5676                 running &= ~(1 << substream->stream);
5677                 break;
5678         default:
5679                 snd_BUG();
5680                 spin_unlock(&hdspm->lock);
5681                 return -EINVAL;
5682         }
5683         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5684                 other = hdspm->capture_substream;
5685         else
5686                 other = hdspm->playback_substream;
5687
5688         if (other) {
5689                 struct snd_pcm_substream *s;
5690                 snd_pcm_group_for_each_entry(s, substream) {
5691                         if (s == other) {
5692                                 snd_pcm_trigger_done(s, substream);
5693                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5694                                         running |= 1 << s->stream;
5695                                 else
5696                                         running &= ~(1 << s->stream);
5697                                 goto _ok;
5698                         }
5699                 }
5700                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5701                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5702                                         && substream->stream ==
5703                                         SNDRV_PCM_STREAM_CAPTURE)
5704                                 hdspm_silence_playback(hdspm);
5705                 } else {
5706                         if (running &&
5707                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5708                                 hdspm_silence_playback(hdspm);
5709                 }
5710         } else {
5711                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5712                         hdspm_silence_playback(hdspm);
5713         }
5714 _ok:
5715         snd_pcm_trigger_done(substream, substream);
5716         if (!hdspm->running && running)
5717                 hdspm_start_audio(hdspm);
5718         else if (hdspm->running && !running)
5719                 hdspm_stop_audio(hdspm);
5720         hdspm->running = running;
5721         spin_unlock(&hdspm->lock);
5722
5723         return 0;
5724 }
5725
5726 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5727 {
5728         return 0;
5729 }
5730
5731 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5732         .info = (SNDRV_PCM_INFO_MMAP |
5733                  SNDRV_PCM_INFO_MMAP_VALID |
5734                  SNDRV_PCM_INFO_NONINTERLEAVED |
5735                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5736         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5737         .rates = (SNDRV_PCM_RATE_32000 |
5738                   SNDRV_PCM_RATE_44100 |
5739                   SNDRV_PCM_RATE_48000 |
5740                   SNDRV_PCM_RATE_64000 |
5741                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5742                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5743         .rate_min = 32000,
5744         .rate_max = 192000,
5745         .channels_min = 1,
5746         .channels_max = HDSPM_MAX_CHANNELS,
5747         .buffer_bytes_max =
5748             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5749         .period_bytes_min = (32 * 4),
5750         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5751         .periods_min = 2,
5752         .periods_max = 512,
5753         .fifo_size = 0
5754 };
5755
5756 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5757         .info = (SNDRV_PCM_INFO_MMAP |
5758                  SNDRV_PCM_INFO_MMAP_VALID |
5759                  SNDRV_PCM_INFO_NONINTERLEAVED |
5760                  SNDRV_PCM_INFO_SYNC_START),
5761         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5762         .rates = (SNDRV_PCM_RATE_32000 |
5763                   SNDRV_PCM_RATE_44100 |
5764                   SNDRV_PCM_RATE_48000 |
5765                   SNDRV_PCM_RATE_64000 |
5766                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5767                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5768         .rate_min = 32000,
5769         .rate_max = 192000,
5770         .channels_min = 1,
5771         .channels_max = HDSPM_MAX_CHANNELS,
5772         .buffer_bytes_max =
5773             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5774         .period_bytes_min = (32 * 4),
5775         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5776         .periods_min = 2,
5777         .periods_max = 512,
5778         .fifo_size = 0
5779 };
5780
5781 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5782                                            struct snd_pcm_hw_rule *rule)
5783 {
5784         struct hdspm *hdspm = rule->private;
5785         struct snd_interval *c =
5786             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5787         struct snd_interval *r =
5788             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5789
5790         if (r->min > 96000 && r->max <= 192000) {
5791                 struct snd_interval t = {
5792                         .min = hdspm->qs_in_channels,
5793                         .max = hdspm->qs_in_channels,
5794                         .integer = 1,
5795                 };
5796                 return snd_interval_refine(c, &t);
5797         } else if (r->min > 48000 && r->max <= 96000) {
5798                 struct snd_interval t = {
5799                         .min = hdspm->ds_in_channels,
5800                         .max = hdspm->ds_in_channels,
5801                         .integer = 1,
5802                 };
5803                 return snd_interval_refine(c, &t);
5804         } else if (r->max < 64000) {
5805                 struct snd_interval t = {
5806                         .min = hdspm->ss_in_channels,
5807                         .max = hdspm->ss_in_channels,
5808                         .integer = 1,
5809                 };
5810                 return snd_interval_refine(c, &t);
5811         }
5812
5813         return 0;
5814 }
5815
5816 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5817                                            struct snd_pcm_hw_rule * rule)
5818 {
5819         struct hdspm *hdspm = rule->private;
5820         struct snd_interval *c =
5821             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5822         struct snd_interval *r =
5823             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5824
5825         if (r->min > 96000 && r->max <= 192000) {
5826                 struct snd_interval t = {
5827                         .min = hdspm->qs_out_channels,
5828                         .max = hdspm->qs_out_channels,
5829                         .integer = 1,
5830                 };
5831                 return snd_interval_refine(c, &t);
5832         } else if (r->min > 48000 && r->max <= 96000) {
5833                 struct snd_interval t = {
5834                         .min = hdspm->ds_out_channels,
5835                         .max = hdspm->ds_out_channels,
5836                         .integer = 1,
5837                 };
5838                 return snd_interval_refine(c, &t);
5839         } else if (r->max < 64000) {
5840                 struct snd_interval t = {
5841                         .min = hdspm->ss_out_channels,
5842                         .max = hdspm->ss_out_channels,
5843                         .integer = 1,
5844                 };
5845                 return snd_interval_refine(c, &t);
5846         } else {
5847         }
5848         return 0;
5849 }
5850
5851 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5852                                            struct snd_pcm_hw_rule * rule)
5853 {
5854         struct hdspm *hdspm = rule->private;
5855         struct snd_interval *c =
5856             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5857         struct snd_interval *r =
5858             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5859
5860         if (c->min >= hdspm->ss_in_channels) {
5861                 struct snd_interval t = {
5862                         .min = 32000,
5863                         .max = 48000,
5864                         .integer = 1,
5865                 };
5866                 return snd_interval_refine(r, &t);
5867         } else if (c->max <= hdspm->qs_in_channels) {
5868                 struct snd_interval t = {
5869                         .min = 128000,
5870                         .max = 192000,
5871                         .integer = 1,
5872                 };
5873                 return snd_interval_refine(r, &t);
5874         } else if (c->max <= hdspm->ds_in_channels) {
5875                 struct snd_interval t = {
5876                         .min = 64000,
5877                         .max = 96000,
5878                         .integer = 1,
5879                 };
5880                 return snd_interval_refine(r, &t);
5881         }
5882
5883         return 0;
5884 }
5885 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5886                                            struct snd_pcm_hw_rule *rule)
5887 {
5888         struct hdspm *hdspm = rule->private;
5889         struct snd_interval *c =
5890             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5891         struct snd_interval *r =
5892             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5893
5894         if (c->min >= hdspm->ss_out_channels) {
5895                 struct snd_interval t = {
5896                         .min = 32000,
5897                         .max = 48000,
5898                         .integer = 1,
5899                 };
5900                 return snd_interval_refine(r, &t);
5901         } else if (c->max <= hdspm->qs_out_channels) {
5902                 struct snd_interval t = {
5903                         .min = 128000,
5904                         .max = 192000,
5905                         .integer = 1,
5906                 };
5907                 return snd_interval_refine(r, &t);
5908         } else if (c->max <= hdspm->ds_out_channels) {
5909                 struct snd_interval t = {
5910                         .min = 64000,
5911                         .max = 96000,
5912                         .integer = 1,
5913                 };
5914                 return snd_interval_refine(r, &t);
5915         }
5916
5917         return 0;
5918 }
5919
5920 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5921                                       struct snd_pcm_hw_rule *rule)
5922 {
5923         unsigned int list[3];
5924         struct hdspm *hdspm = rule->private;
5925         struct snd_interval *c = hw_param_interval(params,
5926                         SNDRV_PCM_HW_PARAM_CHANNELS);
5927
5928         list[0] = hdspm->qs_in_channels;
5929         list[1] = hdspm->ds_in_channels;
5930         list[2] = hdspm->ss_in_channels;
5931         return snd_interval_list(c, 3, list, 0);
5932 }
5933
5934 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5935                                       struct snd_pcm_hw_rule *rule)
5936 {
5937         unsigned int list[3];
5938         struct hdspm *hdspm = rule->private;
5939         struct snd_interval *c = hw_param_interval(params,
5940                         SNDRV_PCM_HW_PARAM_CHANNELS);
5941
5942         list[0] = hdspm->qs_out_channels;
5943         list[1] = hdspm->ds_out_channels;
5944         list[2] = hdspm->ss_out_channels;
5945         return snd_interval_list(c, 3, list, 0);
5946 }
5947
5948
5949 static unsigned int hdspm_aes32_sample_rates[] = {
5950         32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5951 };
5952
5953 static struct snd_pcm_hw_constraint_list
5954 hdspm_hw_constraints_aes32_sample_rates = {
5955         .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5956         .list = hdspm_aes32_sample_rates,
5957         .mask = 0
5958 };
5959
5960 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5961 {
5962         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5963         struct snd_pcm_runtime *runtime = substream->runtime;
5964
5965         spin_lock_irq(&hdspm->lock);
5966
5967         snd_pcm_set_sync(substream);
5968
5969
5970         runtime->hw = snd_hdspm_playback_subinfo;
5971
5972         if (hdspm->capture_substream == NULL)
5973                 hdspm_stop_audio(hdspm);
5974
5975         hdspm->playback_pid = current->pid;
5976         hdspm->playback_substream = substream;
5977
5978         spin_unlock_irq(&hdspm->lock);
5979
5980         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5981         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5982
5983         switch (hdspm->io_type) {
5984         case AIO:
5985         case RayDAT:
5986                 snd_pcm_hw_constraint_minmax(runtime,
5987                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5988                                              32, 4096);
5989                 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
5990                 snd_pcm_hw_constraint_minmax(runtime,
5991                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5992                                              16384, 16384);
5993                 break;
5994
5995         default:
5996                 snd_pcm_hw_constraint_minmax(runtime,
5997                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5998                                              64, 8192);
5999                 break;
6000         }
6001
6002         if (AES32 == hdspm->io_type) {
6003                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6004                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6005                                 &hdspm_hw_constraints_aes32_sample_rates);
6006         } else {
6007                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6008                                 snd_hdspm_hw_rule_rate_out_channels, hdspm,
6009                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6010         }
6011
6012         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6013                         snd_hdspm_hw_rule_out_channels, hdspm,
6014                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6015
6016         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6017                         snd_hdspm_hw_rule_out_channels_rate, hdspm,
6018                         SNDRV_PCM_HW_PARAM_RATE, -1);
6019
6020         return 0;
6021 }
6022
6023 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
6024 {
6025         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6026
6027         spin_lock_irq(&hdspm->lock);
6028
6029         hdspm->playback_pid = -1;
6030         hdspm->playback_substream = NULL;
6031
6032         spin_unlock_irq(&hdspm->lock);
6033
6034         return 0;
6035 }
6036
6037
6038 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6039 {
6040         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6041         struct snd_pcm_runtime *runtime = substream->runtime;
6042
6043         spin_lock_irq(&hdspm->lock);
6044         snd_pcm_set_sync(substream);
6045         runtime->hw = snd_hdspm_capture_subinfo;
6046
6047         if (hdspm->playback_substream == NULL)
6048                 hdspm_stop_audio(hdspm);
6049
6050         hdspm->capture_pid = current->pid;
6051         hdspm->capture_substream = substream;
6052
6053         spin_unlock_irq(&hdspm->lock);
6054
6055         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6056         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6057
6058         switch (hdspm->io_type) {
6059         case AIO:
6060         case RayDAT:
6061                 snd_pcm_hw_constraint_minmax(runtime,
6062                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6063                                              32, 4096);
6064                 snd_pcm_hw_constraint_minmax(runtime,
6065                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6066                                              16384, 16384);
6067                 break;
6068
6069         default:
6070                 snd_pcm_hw_constraint_minmax(runtime,
6071                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6072                                              64, 8192);
6073                 break;
6074         }
6075
6076         if (AES32 == hdspm->io_type) {
6077                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6078                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6079                                 &hdspm_hw_constraints_aes32_sample_rates);
6080         } else {
6081                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6082                                 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6083                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6084         }
6085
6086         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6087                         snd_hdspm_hw_rule_in_channels, hdspm,
6088                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6089
6090         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6091                         snd_hdspm_hw_rule_in_channels_rate, hdspm,
6092                         SNDRV_PCM_HW_PARAM_RATE, -1);
6093
6094         return 0;
6095 }
6096
6097 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6098 {
6099         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6100
6101         spin_lock_irq(&hdspm->lock);
6102
6103         hdspm->capture_pid = -1;
6104         hdspm->capture_substream = NULL;
6105
6106         spin_unlock_irq(&hdspm->lock);
6107         return 0;
6108 }
6109
6110 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6111 {
6112         /* we have nothing to initialize but the call is required */
6113         return 0;
6114 }
6115
6116 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6117 {
6118         u32 val = readl(src);
6119         return copy_to_user(dest, &val, 4);
6120 }
6121
6122 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6123                 unsigned int cmd, unsigned long arg)
6124 {
6125         void __user *argp = (void __user *)arg;
6126         struct hdspm *hdspm = hw->private_data;
6127         struct hdspm_mixer_ioctl mixer;
6128         struct hdspm_config info;
6129         struct hdspm_status status;
6130         struct hdspm_version hdspm_version;
6131         struct hdspm_peak_rms *levels;
6132         struct hdspm_ltc ltc;
6133         unsigned int statusregister;
6134         long unsigned int s;
6135         int i = 0;
6136
6137         switch (cmd) {
6138
6139         case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6140                 levels = &hdspm->peak_rms;
6141                 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6142                         levels->input_peaks[i] =
6143                                 readl(hdspm->iobase +
6144                                                 HDSPM_MADI_INPUT_PEAK + i*4);
6145                         levels->playback_peaks[i] =
6146                                 readl(hdspm->iobase +
6147                                                 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6148                         levels->output_peaks[i] =
6149                                 readl(hdspm->iobase +
6150                                                 HDSPM_MADI_OUTPUT_PEAK + i*4);
6151
6152                         levels->input_rms[i] =
6153                                 ((uint64_t) readl(hdspm->iobase +
6154                                         HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6155                                 (uint64_t) readl(hdspm->iobase +
6156                                                 HDSPM_MADI_INPUT_RMS_L + i*4);
6157                         levels->playback_rms[i] =
6158                                 ((uint64_t)readl(hdspm->iobase +
6159                                         HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6160                                 (uint64_t)readl(hdspm->iobase +
6161                                         HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6162                         levels->output_rms[i] =
6163                                 ((uint64_t)readl(hdspm->iobase +
6164                                         HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6165                                 (uint64_t)readl(hdspm->iobase +
6166                                                 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6167                 }
6168
6169                 if (hdspm->system_sample_rate > 96000) {
6170                         levels->speed = qs;
6171                 } else if (hdspm->system_sample_rate > 48000) {
6172                         levels->speed = ds;
6173                 } else {
6174                         levels->speed = ss;
6175                 }
6176                 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6177
6178                 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6179                 if (0 != s) {
6180                         /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6181                          [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6182                          */
6183                         return -EFAULT;
6184                 }
6185                 break;
6186
6187         case SNDRV_HDSPM_IOCTL_GET_LTC:
6188                 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6189                 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6190                 if (i & HDSPM_TCO1_LTC_Input_valid) {
6191                         switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6192                                 HDSPM_TCO1_LTC_Format_MSB)) {
6193                         case 0:
6194                                 ltc.format = fps_24;
6195                                 break;
6196                         case HDSPM_TCO1_LTC_Format_LSB:
6197                                 ltc.format = fps_25;
6198                                 break;
6199                         case HDSPM_TCO1_LTC_Format_MSB:
6200                                 ltc.format = fps_2997;
6201                                 break;
6202                         default:
6203                                 ltc.format = 30;
6204                                 break;
6205                         }
6206                         if (i & HDSPM_TCO1_set_drop_frame_flag) {
6207                                 ltc.frame = drop_frame;
6208                         } else {
6209                                 ltc.frame = full_frame;
6210                         }
6211                 } else {
6212                         ltc.format = format_invalid;
6213                         ltc.frame = frame_invalid;
6214                 }
6215                 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6216                         ltc.input_format = ntsc;
6217                 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6218                         ltc.input_format = pal;
6219                 } else {
6220                         ltc.input_format = no_video;
6221                 }
6222
6223                 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6224                 if (0 != s) {
6225                         /*
6226                          snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6227                         return -EFAULT;
6228                 }
6229
6230                 break;
6231
6232         case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6233
6234                 memset(&info, 0, sizeof(info));
6235                 spin_lock_irq(&hdspm->lock);
6236                 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6237                 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6238
6239                 info.system_sample_rate = hdspm->system_sample_rate;
6240                 info.autosync_sample_rate =
6241                         hdspm_external_sample_rate(hdspm);
6242                 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6243                 info.clock_source = hdspm_clock_source(hdspm);
6244                 info.autosync_ref = hdspm_autosync_ref(hdspm);
6245                 info.line_out = hdspm_line_out(hdspm);
6246                 info.passthru = 0;
6247                 spin_unlock_irq(&hdspm->lock);
6248                 if (copy_to_user(argp, &info, sizeof(info)))
6249                         return -EFAULT;
6250                 break;
6251
6252         case SNDRV_HDSPM_IOCTL_GET_STATUS:
6253                 memset(&status, 0, sizeof(status));
6254
6255                 status.card_type = hdspm->io_type;
6256
6257                 status.autosync_source = hdspm_autosync_ref(hdspm);
6258
6259                 status.card_clock = 110069313433624ULL;
6260                 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6261
6262                 switch (hdspm->io_type) {
6263                 case MADI:
6264                 case MADIface:
6265                         status.card_specific.madi.sync_wc =
6266                                 hdspm_wc_sync_check(hdspm);
6267                         status.card_specific.madi.sync_madi =
6268                                 hdspm_madi_sync_check(hdspm);
6269                         status.card_specific.madi.sync_tco =
6270                                 hdspm_tco_sync_check(hdspm);
6271                         status.card_specific.madi.sync_in =
6272                                 hdspm_sync_in_sync_check(hdspm);
6273
6274                         statusregister =
6275                                 hdspm_read(hdspm, HDSPM_statusRegister);
6276                         status.card_specific.madi.madi_input =
6277                                 (statusregister & HDSPM_AB_int) ? 1 : 0;
6278                         status.card_specific.madi.channel_format =
6279                                 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6280                         /* TODO: Mac driver sets it when f_s>48kHz */
6281                         status.card_specific.madi.frame_format = 0;
6282
6283                 default:
6284                         break;
6285                 }
6286
6287                 if (copy_to_user(argp, &status, sizeof(status)))
6288                         return -EFAULT;
6289
6290
6291                 break;
6292
6293         case SNDRV_HDSPM_IOCTL_GET_VERSION:
6294                 memset(&hdspm_version, 0, sizeof(hdspm_version));
6295
6296                 hdspm_version.card_type = hdspm->io_type;
6297                 strncpy(hdspm_version.cardname, hdspm->card_name,
6298                                 sizeof(hdspm_version.cardname));
6299                 hdspm_version.serial = hdspm->serial;
6300                 hdspm_version.firmware_rev = hdspm->firmware_rev;
6301                 hdspm_version.addons = 0;
6302                 if (hdspm->tco)
6303                         hdspm_version.addons |= HDSPM_ADDON_TCO;
6304
6305                 if (copy_to_user(argp, &hdspm_version,
6306                                         sizeof(hdspm_version)))
6307                         return -EFAULT;
6308                 break;
6309
6310         case SNDRV_HDSPM_IOCTL_GET_MIXER:
6311                 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6312                         return -EFAULT;
6313                 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6314                                         sizeof(struct hdspm_mixer)))
6315                         return -EFAULT;
6316                 break;
6317
6318         default:
6319                 return -EINVAL;
6320         }
6321         return 0;
6322 }
6323
6324 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6325         .open = snd_hdspm_playback_open,
6326         .close = snd_hdspm_playback_release,
6327         .ioctl = snd_hdspm_ioctl,
6328         .hw_params = snd_hdspm_hw_params,
6329         .hw_free = snd_hdspm_hw_free,
6330         .prepare = snd_hdspm_prepare,
6331         .trigger = snd_hdspm_trigger,
6332         .pointer = snd_hdspm_hw_pointer,
6333         .page = snd_pcm_sgbuf_ops_page,
6334 };
6335
6336 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6337         .open = snd_hdspm_capture_open,
6338         .close = snd_hdspm_capture_release,
6339         .ioctl = snd_hdspm_ioctl,
6340         .hw_params = snd_hdspm_hw_params,
6341         .hw_free = snd_hdspm_hw_free,
6342         .prepare = snd_hdspm_prepare,
6343         .trigger = snd_hdspm_trigger,
6344         .pointer = snd_hdspm_hw_pointer,
6345         .page = snd_pcm_sgbuf_ops_page,
6346 };
6347
6348 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
6349                                             struct hdspm * hdspm)
6350 {
6351         struct snd_hwdep *hw;
6352         int err;
6353
6354         err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6355         if (err < 0)
6356                 return err;
6357
6358         hdspm->hwdep = hw;
6359         hw->private_data = hdspm;
6360         strcpy(hw->name, "HDSPM hwdep interface");
6361
6362         hw->ops.open = snd_hdspm_hwdep_dummy_op;
6363         hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6364         hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6365         hw->ops.release = snd_hdspm_hwdep_dummy_op;
6366
6367         return 0;
6368 }
6369
6370
6371 /*------------------------------------------------------------
6372    memory interface
6373  ------------------------------------------------------------*/
6374 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6375 {
6376         int err;
6377         struct snd_pcm *pcm;
6378         size_t wanted;
6379
6380         pcm = hdspm->pcm;
6381
6382         wanted = HDSPM_DMA_AREA_BYTES;
6383
6384         err =
6385              snd_pcm_lib_preallocate_pages_for_all(pcm,
6386                                                    SNDRV_DMA_TYPE_DEV_SG,
6387                                                    snd_dma_pci_data(hdspm->pci),
6388                                                    wanted,
6389                                                    wanted);
6390         if (err < 0) {
6391                 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6392
6393                 return err;
6394         } else
6395                 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6396
6397         return 0;
6398 }
6399
6400
6401 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6402                             struct snd_pcm_substream *substream,
6403                              unsigned int reg, int channels)
6404 {
6405         int i;
6406
6407         /* continuous memory segment */
6408         for (i = 0; i < (channels * 16); i++)
6409                 hdspm_write(hdspm, reg + 4 * i,
6410                                 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6411 }
6412
6413
6414 /* ------------- ALSA Devices ---------------------------- */
6415 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
6416                                           struct hdspm *hdspm)
6417 {
6418         struct snd_pcm *pcm;
6419         int err;
6420
6421         err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6422         if (err < 0)
6423                 return err;
6424
6425         hdspm->pcm = pcm;
6426         pcm->private_data = hdspm;
6427         strcpy(pcm->name, hdspm->card_name);
6428
6429         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6430                         &snd_hdspm_playback_ops);
6431         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6432                         &snd_hdspm_capture_ops);
6433
6434         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6435
6436         err = snd_hdspm_preallocate_memory(hdspm);
6437         if (err < 0)
6438                 return err;
6439
6440         return 0;
6441 }
6442
6443 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6444 {
6445         int i;
6446
6447         for (i = 0; i < hdspm->midiPorts; i++)
6448                 snd_hdspm_flush_midi_input(hdspm, i);
6449 }
6450
6451 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
6452                                                    struct hdspm * hdspm)
6453 {
6454         int err, i;
6455
6456         snd_printdd("Create card...\n");
6457         err = snd_hdspm_create_pcm(card, hdspm);
6458         if (err < 0)
6459                 return err;
6460
6461         i = 0;
6462         while (i < hdspm->midiPorts) {
6463                 err = snd_hdspm_create_midi(card, hdspm, i);
6464                 if (err < 0) {
6465                         return err;
6466                 }
6467                 i++;
6468         }
6469
6470         err = snd_hdspm_create_controls(card, hdspm);
6471         if (err < 0)
6472                 return err;
6473
6474         err = snd_hdspm_create_hwdep(card, hdspm);
6475         if (err < 0)
6476                 return err;
6477
6478         snd_printdd("proc init...\n");
6479         snd_hdspm_proc_init(hdspm);
6480
6481         hdspm->system_sample_rate = -1;
6482         hdspm->last_external_sample_rate = -1;
6483         hdspm->last_internal_sample_rate = -1;
6484         hdspm->playback_pid = -1;
6485         hdspm->capture_pid = -1;
6486         hdspm->capture_substream = NULL;
6487         hdspm->playback_substream = NULL;
6488
6489         snd_printdd("Set defaults...\n");
6490         err = snd_hdspm_set_defaults(hdspm);
6491         if (err < 0)
6492                 return err;
6493
6494         snd_printdd("Update mixer controls...\n");
6495         hdspm_update_simple_mixer_controls(hdspm);
6496
6497         snd_printdd("Initializeing complete ???\n");
6498
6499         err = snd_card_register(card);
6500         if (err < 0) {
6501                 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6502                 return err;
6503         }
6504
6505         snd_printdd("... yes now\n");
6506
6507         return 0;
6508 }
6509
6510 static int __devinit snd_hdspm_create(struct snd_card *card,
6511                 struct hdspm *hdspm) {
6512
6513         struct pci_dev *pci = hdspm->pci;
6514         int err;
6515         unsigned long io_extent;
6516
6517         hdspm->irq = -1;
6518         hdspm->card = card;
6519
6520         spin_lock_init(&hdspm->lock);
6521
6522         pci_read_config_word(hdspm->pci,
6523                         PCI_CLASS_REVISION, &hdspm->firmware_rev);
6524
6525         strcpy(card->mixername, "Xilinx FPGA");
6526         strcpy(card->driver, "HDSPM");
6527
6528         switch (hdspm->firmware_rev) {
6529         case HDSPM_RAYDAT_REV:
6530                 hdspm->io_type = RayDAT;
6531                 hdspm->card_name = "RME RayDAT";
6532                 hdspm->midiPorts = 2;
6533                 break;
6534         case HDSPM_AIO_REV:
6535                 hdspm->io_type = AIO;
6536                 hdspm->card_name = "RME AIO";
6537                 hdspm->midiPorts = 1;
6538                 break;
6539         case HDSPM_MADIFACE_REV:
6540                 hdspm->io_type = MADIface;
6541                 hdspm->card_name = "RME MADIface";
6542                 hdspm->midiPorts = 1;
6543                 break;
6544         default:
6545                 if ((hdspm->firmware_rev == 0xf0) ||
6546                         ((hdspm->firmware_rev >= 0xe6) &&
6547                                         (hdspm->firmware_rev <= 0xea))) {
6548                         hdspm->io_type = AES32;
6549                         hdspm->card_name = "RME AES32";
6550                         hdspm->midiPorts = 2;
6551                 } else if ((hdspm->firmware_rev == 0xd2) ||
6552                         ((hdspm->firmware_rev >= 0xc8)  &&
6553                                 (hdspm->firmware_rev <= 0xcf))) {
6554                         hdspm->io_type = MADI;
6555                         hdspm->card_name = "RME MADI";
6556                         hdspm->midiPorts = 3;
6557                 } else {
6558                         snd_printk(KERN_ERR
6559                                 "HDSPM: unknown firmware revision %x\n",
6560                                 hdspm->firmware_rev);
6561                         return -ENODEV;
6562                 }
6563         }
6564
6565         err = pci_enable_device(pci);
6566         if (err < 0)
6567                 return err;
6568
6569         pci_set_master(hdspm->pci);
6570
6571         err = pci_request_regions(pci, "hdspm");
6572         if (err < 0)
6573                 return err;
6574
6575         hdspm->port = pci_resource_start(pci, 0);
6576         io_extent = pci_resource_len(pci, 0);
6577
6578         snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6579                         hdspm->port, hdspm->port + io_extent - 1);
6580
6581         hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6582         if (!hdspm->iobase) {
6583                 snd_printk(KERN_ERR "HDSPM: "
6584                                 "unable to remap region 0x%lx-0x%lx\n",
6585                                 hdspm->port, hdspm->port + io_extent - 1);
6586                 return -EBUSY;
6587         }
6588         snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6589                         (unsigned long)hdspm->iobase, hdspm->port,
6590                         hdspm->port + io_extent - 1);
6591
6592         if (request_irq(pci->irq, snd_hdspm_interrupt,
6593                         IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6594                 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6595                 return -EBUSY;
6596         }
6597
6598         snd_printdd("use IRQ %d\n", pci->irq);
6599
6600         hdspm->irq = pci->irq;
6601
6602         snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6603                         sizeof(struct hdspm_mixer));
6604         hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6605         if (!hdspm->mixer) {
6606                 snd_printk(KERN_ERR "HDSPM: "
6607                                 "unable to kmalloc Mixer memory of %d Bytes\n",
6608                                 (int)sizeof(struct hdspm_mixer));
6609                 return -ENOMEM;
6610         }
6611
6612         hdspm->port_names_in = NULL;
6613         hdspm->port_names_out = NULL;
6614
6615         switch (hdspm->io_type) {
6616         case AES32:
6617                 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6618                 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6619                 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6620
6621                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6622                         channel_map_aes32;
6623                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6624                         channel_map_aes32;
6625                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6626                         channel_map_aes32;
6627                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6628                         texts_ports_aes32;
6629                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6630                         texts_ports_aes32;
6631                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6632                         texts_ports_aes32;
6633
6634                 hdspm->max_channels_out = hdspm->max_channels_in =
6635                         AES32_CHANNELS;
6636                 hdspm->port_names_in = hdspm->port_names_out =
6637                         texts_ports_aes32;
6638                 hdspm->channel_map_in = hdspm->channel_map_out =
6639                         channel_map_aes32;
6640
6641                 break;
6642
6643         case MADI:
6644         case MADIface:
6645                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6646                         MADI_SS_CHANNELS;
6647                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6648                         MADI_DS_CHANNELS;
6649                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6650                         MADI_QS_CHANNELS;
6651
6652                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6653                         channel_map_unity_ss;
6654                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6655                         channel_map_unity_ss;
6656                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6657                         channel_map_unity_ss;
6658
6659                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6660                         texts_ports_madi;
6661                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6662                         texts_ports_madi;
6663                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6664                         texts_ports_madi;
6665                 break;
6666
6667         case AIO:
6668                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6669                         snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6670                 }
6671
6672                 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6673                 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6674                 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6675                 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6676                 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6677                 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6678
6679                 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6680                 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6681                 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6682
6683                 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6684                 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6685                 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6686
6687                 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6688                 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6689                 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6690                 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6691                 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6692                 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6693
6694                 break;
6695
6696         case RayDAT:
6697                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6698                         RAYDAT_SS_CHANNELS;
6699                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6700                         RAYDAT_DS_CHANNELS;
6701                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6702                         RAYDAT_QS_CHANNELS;
6703
6704                 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6705                 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6706
6707                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6708                         channel_map_raydat_ss;
6709                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6710                         channel_map_raydat_ds;
6711                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6712                         channel_map_raydat_qs;
6713                 hdspm->channel_map_in = hdspm->channel_map_out =
6714                         channel_map_raydat_ss;
6715
6716                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6717                         texts_ports_raydat_ss;
6718                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6719                         texts_ports_raydat_ds;
6720                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6721                         texts_ports_raydat_qs;
6722
6723
6724                 break;
6725
6726         }
6727
6728         /* TCO detection */
6729         switch (hdspm->io_type) {
6730         case AIO:
6731         case RayDAT:
6732                 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6733                                 HDSPM_s2_tco_detect) {
6734                         hdspm->midiPorts++;
6735                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6736                                         GFP_KERNEL);
6737                         if (NULL != hdspm->tco) {
6738                                 hdspm_tco_write(hdspm);
6739                         }
6740                         snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6741                 } else {
6742                         hdspm->tco = NULL;
6743                 }
6744                 break;
6745
6746         case MADI:
6747                 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6748                         hdspm->midiPorts++;
6749                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6750                                         GFP_KERNEL);
6751                         if (NULL != hdspm->tco) {
6752                                 hdspm_tco_write(hdspm);
6753                         }
6754                         snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6755                 } else {
6756                         hdspm->tco = NULL;
6757                 }
6758                 break;
6759
6760         default:
6761                 hdspm->tco = NULL;
6762         }
6763
6764         /* texts */
6765         switch (hdspm->io_type) {
6766         case AES32:
6767                 if (hdspm->tco) {
6768                         hdspm->texts_autosync = texts_autosync_aes_tco;
6769                         hdspm->texts_autosync_items = 10;
6770                 } else {
6771                         hdspm->texts_autosync = texts_autosync_aes;
6772                         hdspm->texts_autosync_items = 9;
6773                 }
6774                 break;
6775
6776         case MADI:
6777                 if (hdspm->tco) {
6778                         hdspm->texts_autosync = texts_autosync_madi_tco;
6779                         hdspm->texts_autosync_items = 4;
6780                 } else {
6781                         hdspm->texts_autosync = texts_autosync_madi;
6782                         hdspm->texts_autosync_items = 3;
6783                 }
6784                 break;
6785
6786         case MADIface:
6787
6788                 break;
6789
6790         case RayDAT:
6791                 if (hdspm->tco) {
6792                         hdspm->texts_autosync = texts_autosync_raydat_tco;
6793                         hdspm->texts_autosync_items = 9;
6794                 } else {
6795                         hdspm->texts_autosync = texts_autosync_raydat;
6796                         hdspm->texts_autosync_items = 8;
6797                 }
6798                 break;
6799
6800         case AIO:
6801                 if (hdspm->tco) {
6802                         hdspm->texts_autosync = texts_autosync_aio_tco;
6803                         hdspm->texts_autosync_items = 6;
6804                 } else {
6805                         hdspm->texts_autosync = texts_autosync_aio;
6806                         hdspm->texts_autosync_items = 5;
6807                 }
6808                 break;
6809
6810         }
6811
6812         tasklet_init(&hdspm->midi_tasklet,
6813                         hdspm_midi_tasklet, (unsigned long) hdspm);
6814
6815
6816         if (hdspm->io_type != MADIface) {
6817                 hdspm->serial = (hdspm_read(hdspm,
6818                                 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6819                 /* id contains either a user-provided value or the default
6820                  * NULL. If it's the default, we're safe to
6821                  * fill card->id with the serial number.
6822                  *
6823                  * If the serial number is 0xFFFFFF, then we're dealing with
6824                  * an old PCI revision that comes without a sane number. In
6825                  * this case, we don't set card->id to avoid collisions
6826                  * when running with multiple cards.
6827                  */
6828                 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6829                         sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6830                         snd_card_set_id(card, card->id);
6831                 }
6832         }
6833
6834         snd_printdd("create alsa devices.\n");
6835         err = snd_hdspm_create_alsa_devices(card, hdspm);
6836         if (err < 0)
6837                 return err;
6838
6839         snd_hdspm_initialize_midi_flush(hdspm);
6840
6841         return 0;
6842 }
6843
6844
6845 static int snd_hdspm_free(struct hdspm * hdspm)
6846 {
6847
6848         if (hdspm->port) {
6849
6850                 /* stop th audio, and cancel all interrupts */
6851                 hdspm->control_register &=
6852                     ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6853                       HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6854                       HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6855                 hdspm_write(hdspm, HDSPM_controlRegister,
6856                             hdspm->control_register);
6857         }
6858
6859         if (hdspm->irq >= 0)
6860                 free_irq(hdspm->irq, (void *) hdspm);
6861
6862         kfree(hdspm->mixer);
6863
6864         if (hdspm->iobase)
6865                 iounmap(hdspm->iobase);
6866
6867         if (hdspm->port)
6868                 pci_release_regions(hdspm->pci);
6869
6870         pci_disable_device(hdspm->pci);
6871         return 0;
6872 }
6873
6874
6875 static void snd_hdspm_card_free(struct snd_card *card)
6876 {
6877         struct hdspm *hdspm = card->private_data;
6878
6879         if (hdspm)
6880                 snd_hdspm_free(hdspm);
6881 }
6882
6883
6884 static int __devinit snd_hdspm_probe(struct pci_dev *pci,
6885                                      const struct pci_device_id *pci_id)
6886 {
6887         static int dev;
6888         struct hdspm *hdspm;
6889         struct snd_card *card;
6890         int err;
6891
6892         if (dev >= SNDRV_CARDS)
6893                 return -ENODEV;
6894         if (!enable[dev]) {
6895                 dev++;
6896                 return -ENOENT;
6897         }
6898
6899         err = snd_card_create(index[dev], id[dev],
6900                         THIS_MODULE, sizeof(struct hdspm), &card);
6901         if (err < 0)
6902                 return err;
6903
6904         hdspm = card->private_data;
6905         card->private_free = snd_hdspm_card_free;
6906         hdspm->dev = dev;
6907         hdspm->pci = pci;
6908
6909         snd_card_set_dev(card, &pci->dev);
6910
6911         err = snd_hdspm_create(card, hdspm);
6912         if (err < 0) {
6913                 snd_card_free(card);
6914                 return err;
6915         }
6916
6917         if (hdspm->io_type != MADIface) {
6918                 sprintf(card->shortname, "%s_%x",
6919                         hdspm->card_name,
6920                         hdspm->serial);
6921                 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6922                         hdspm->card_name,
6923                         hdspm->serial,
6924                         hdspm->port, hdspm->irq);
6925         } else {
6926                 sprintf(card->shortname, "%s", hdspm->card_name);
6927                 sprintf(card->longname, "%s at 0x%lx, irq %d",
6928                                 hdspm->card_name, hdspm->port, hdspm->irq);
6929         }
6930
6931         err = snd_card_register(card);
6932         if (err < 0) {
6933                 snd_card_free(card);
6934                 return err;
6935         }
6936
6937         pci_set_drvdata(pci, card);
6938
6939         dev++;
6940         return 0;
6941 }
6942
6943 static void __devexit snd_hdspm_remove(struct pci_dev *pci)
6944 {
6945         snd_card_free(pci_get_drvdata(pci));
6946         pci_set_drvdata(pci, NULL);
6947 }
6948
6949 static struct pci_driver hdspm_driver = {
6950         .name = KBUILD_MODNAME,
6951         .id_table = snd_hdspm_ids,
6952         .probe = snd_hdspm_probe,
6953         .remove = __devexit_p(snd_hdspm_remove),
6954 };
6955
6956 module_pci_driver(hdspm_driver);