1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ALSA driver for RME Hammerfall DSP audio interface(s)
5 * Copyright (c) 2002 Paul Davis
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/pci.h>
14 #include <linux/firmware.h>
15 #include <linux/module.h>
16 #include <linux/math64.h>
17 #include <linux/vmalloc.h>
19 #include <linux/nospec.h>
21 #include <sound/core.h>
22 #include <sound/control.h>
23 #include <sound/pcm.h>
24 #include <sound/info.h>
25 #include <sound/asoundef.h>
26 #include <sound/rawmidi.h>
27 #include <sound/hwdep.h>
28 #include <sound/initval.h>
29 #include <sound/hdsp.h>
31 #include <asm/byteorder.h>
32 #include <asm/current.h>
34 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
35 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
36 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
38 module_param_array(index, int, NULL, 0444);
39 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
40 module_param_array(id, charp, NULL, 0444);
41 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
42 module_param_array(enable, bool, NULL, 0444);
43 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
44 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
45 MODULE_DESCRIPTION("RME Hammerfall DSP");
46 MODULE_LICENSE("GPL");
47 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
50 MODULE_FIRMWARE("rpm_firmware.bin");
51 MODULE_FIRMWARE("multiface_firmware.bin");
52 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
53 MODULE_FIRMWARE("digiface_firmware.bin");
54 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
56 #define HDSP_MAX_CHANNELS 26
57 #define HDSP_MAX_DS_CHANNELS 14
58 #define HDSP_MAX_QS_CHANNELS 8
59 #define DIGIFACE_SS_CHANNELS 26
60 #define DIGIFACE_DS_CHANNELS 14
61 #define MULTIFACE_SS_CHANNELS 18
62 #define MULTIFACE_DS_CHANNELS 14
63 #define H9652_SS_CHANNELS 26
64 #define H9652_DS_CHANNELS 14
65 /* This does not include possible Analog Extension Boards
66 AEBs are detected at card initialization
68 #define H9632_SS_CHANNELS 12
69 #define H9632_DS_CHANNELS 8
70 #define H9632_QS_CHANNELS 4
71 #define RPM_CHANNELS 6
73 /* Write registers. These are defined as byte-offsets from the iobase value.
75 #define HDSP_resetPointer 0
76 #define HDSP_freqReg 0
77 #define HDSP_outputBufferAddress 32
78 #define HDSP_inputBufferAddress 36
79 #define HDSP_controlRegister 64
80 #define HDSP_interruptConfirmation 96
81 #define HDSP_outputEnable 128
82 #define HDSP_control2Reg 256
83 #define HDSP_midiDataOut0 352
84 #define HDSP_midiDataOut1 356
85 #define HDSP_fifoData 368
86 #define HDSP_inputEnable 384
88 /* Read registers. These are defined as byte-offsets from the iobase value
91 #define HDSP_statusRegister 0
92 #define HDSP_timecode 128
93 #define HDSP_status2Register 192
94 #define HDSP_midiDataIn0 360
95 #define HDSP_midiDataIn1 364
96 #define HDSP_midiStatusOut0 384
97 #define HDSP_midiStatusOut1 388
98 #define HDSP_midiStatusIn0 392
99 #define HDSP_midiStatusIn1 396
100 #define HDSP_fifoStatus 400
102 /* the meters are regular i/o-mapped registers, but offset
103 considerably from the rest. the peak registers are reset
104 when read; the least-significant 4 bits are full-scale counters;
105 the actual peak value is in the most-significant 24 bits.
108 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
109 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
110 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
111 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
112 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
115 /* This is for H9652 cards
116 Peak values are read downward from the base
117 Rms values are read upward
118 There are rms values for the outputs too
119 26*3 values are read in ss mode
120 14*3 in ds mode, with no gap between values
122 #define HDSP_9652_peakBase 7164
123 #define HDSP_9652_rmsBase 4096
125 /* c.f. the hdsp_9632_meters_t struct */
126 #define HDSP_9632_metersBase 4096
128 #define HDSP_IO_EXTENT 7168
130 /* control2 register bits */
132 #define HDSP_TMS 0x01
133 #define HDSP_TCK 0x02
134 #define HDSP_TDI 0x04
135 #define HDSP_JTAG 0x08
136 #define HDSP_PWDN 0x10
137 #define HDSP_PROGRAM 0x020
138 #define HDSP_CONFIG_MODE_0 0x040
139 #define HDSP_CONFIG_MODE_1 0x080
140 #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
141 #define HDSP_BIGENDIAN_MODE 0x200
142 #define HDSP_RD_MULTIPLE 0x400
143 #define HDSP_9652_ENABLE_MIXER 0x800
144 #define HDSP_S200 0x800
145 #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
146 #define HDSP_CYCLIC_MODE 0x1000
147 #define HDSP_TDO 0x10000000
149 #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
150 #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
152 /* Control Register bits */
154 #define HDSP_Start (1<<0) /* start engine */
155 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
156 #define HDSP_Latency1 (1<<2) /* [ see above ] */
157 #define HDSP_Latency2 (1<<3) /* [ see above ] */
158 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
159 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
160 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
161 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
162 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
163 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
164 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
165 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
166 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
167 #define HDSP_SyncRef2 (1<<13)
168 #define HDSP_SPDIFInputSelect0 (1<<14)
169 #define HDSP_SPDIFInputSelect1 (1<<15)
170 #define HDSP_SyncRef0 (1<<16)
171 #define HDSP_SyncRef1 (1<<17)
172 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
173 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
174 #define HDSP_Midi0InterruptEnable (1<<22)
175 #define HDSP_Midi1InterruptEnable (1<<23)
176 #define HDSP_LineOut (1<<24)
177 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
178 #define HDSP_ADGain1 (1<<26)
179 #define HDSP_DAGain0 (1<<27)
180 #define HDSP_DAGain1 (1<<28)
181 #define HDSP_PhoneGain0 (1<<29)
182 #define HDSP_PhoneGain1 (1<<30)
183 #define HDSP_QuadSpeed (1<<31)
185 /* RPM uses some of the registers for special purposes */
186 #define HDSP_RPM_Inp12 0x04A00
187 #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */
188 #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */
189 #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */
190 #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */
191 #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */
193 #define HDSP_RPM_Inp34 0x32000
194 #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */
195 #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */
196 #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */
197 #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */
198 #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */
200 #define HDSP_RPM_Bypass 0x01000
202 #define HDSP_RPM_Disconnect 0x00001
204 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
205 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
206 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
207 #define HDSP_ADGainLowGain 0
209 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
210 #define HDSP_DAGainHighGain HDSP_DAGainMask
211 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
212 #define HDSP_DAGainMinus10dBV 0
214 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
215 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
216 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
217 #define HDSP_PhoneGainMinus12dB 0
219 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
220 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
222 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
223 #define HDSP_SPDIFInputADAT1 0
224 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
225 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
226 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
228 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
229 #define HDSP_SyncRef_ADAT1 0
230 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
231 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
232 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
233 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
234 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
236 /* Sample Clock Sources */
238 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
239 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
240 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
241 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
242 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
243 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
244 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
245 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
246 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
247 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
249 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
251 #define HDSP_SYNC_FROM_WORD 0
252 #define HDSP_SYNC_FROM_SPDIF 1
253 #define HDSP_SYNC_FROM_ADAT1 2
254 #define HDSP_SYNC_FROM_ADAT_SYNC 3
255 #define HDSP_SYNC_FROM_ADAT2 4
256 #define HDSP_SYNC_FROM_ADAT3 5
258 /* SyncCheck status */
260 #define HDSP_SYNC_CHECK_NO_LOCK 0
261 #define HDSP_SYNC_CHECK_LOCK 1
262 #define HDSP_SYNC_CHECK_SYNC 2
264 /* AutoSync references - used by "autosync_ref" control switch */
266 #define HDSP_AUTOSYNC_FROM_WORD 0
267 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
268 #define HDSP_AUTOSYNC_FROM_SPDIF 2
269 #define HDSP_AUTOSYNC_FROM_NONE 3
270 #define HDSP_AUTOSYNC_FROM_ADAT1 4
271 #define HDSP_AUTOSYNC_FROM_ADAT2 5
272 #define HDSP_AUTOSYNC_FROM_ADAT3 6
274 /* Possible sources of S/PDIF input */
276 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
277 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
278 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
279 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
281 #define HDSP_Frequency32KHz HDSP_Frequency0
282 #define HDSP_Frequency44_1KHz HDSP_Frequency1
283 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
284 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
285 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
286 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
287 /* For H9632 cards */
288 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
289 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
290 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
291 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
292 return 104857600000000 / rate; // 100 MHz
293 return 110100480000000 / rate; // 105 MHz
295 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
297 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
298 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
300 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
301 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
303 /* Status Register bits */
305 #define HDSP_audioIRQPending (1<<0)
306 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
307 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
308 #define HDSP_Lock1 (1<<2)
309 #define HDSP_Lock0 (1<<3)
310 #define HDSP_SPDIFSync (1<<4)
311 #define HDSP_TimecodeLock (1<<5)
312 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
313 #define HDSP_Sync2 (1<<16)
314 #define HDSP_Sync1 (1<<17)
315 #define HDSP_Sync0 (1<<18)
316 #define HDSP_DoubleSpeedStatus (1<<19)
317 #define HDSP_ConfigError (1<<20)
318 #define HDSP_DllError (1<<21)
319 #define HDSP_spdifFrequency0 (1<<22)
320 #define HDSP_spdifFrequency1 (1<<23)
321 #define HDSP_spdifFrequency2 (1<<24)
322 #define HDSP_SPDIFErrorFlag (1<<25)
323 #define HDSP_BufferID (1<<26)
324 #define HDSP_TimecodeSync (1<<27)
325 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
326 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
327 #define HDSP_midi0IRQPending (1<<30)
328 #define HDSP_midi1IRQPending (1<<31)
330 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
331 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
332 HDSP_spdifFrequency1|\
333 HDSP_spdifFrequency2|\
334 HDSP_spdifFrequency3)
336 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
337 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
338 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
340 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
341 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
342 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
344 /* This is for H9632 cards */
345 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
346 HDSP_spdifFrequency1|\
347 HDSP_spdifFrequency2)
348 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
349 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
351 /* Status2 Register bits */
353 #define HDSP_version0 (1<<0)
354 #define HDSP_version1 (1<<1)
355 #define HDSP_version2 (1<<2)
356 #define HDSP_wc_lock (1<<3)
357 #define HDSP_wc_sync (1<<4)
358 #define HDSP_inp_freq0 (1<<5)
359 #define HDSP_inp_freq1 (1<<6)
360 #define HDSP_inp_freq2 (1<<7)
361 #define HDSP_SelSyncRef0 (1<<8)
362 #define HDSP_SelSyncRef1 (1<<9)
363 #define HDSP_SelSyncRef2 (1<<10)
365 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
367 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
368 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
369 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
370 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
371 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
372 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
373 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
374 /* FIXME : more values for 9632 cards ? */
376 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
377 #define HDSP_SelSyncRef_ADAT1 0
378 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
379 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
380 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
381 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
382 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
384 /* Card state flags */
386 #define HDSP_InitializationComplete (1<<0)
387 #define HDSP_FirmwareLoaded (1<<1)
388 #define HDSP_FirmwareCached (1<<2)
390 /* FIFO wait times, defined in terms of 1/10ths of msecs */
392 #define HDSP_LONG_WAIT 5000
393 #define HDSP_SHORT_WAIT 30
395 #define UNITY_GAIN 32768
396 #define MINUS_INFINITY_GAIN 0
398 /* the size of a substream (1 mono data stream) */
400 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
401 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
403 /* the size of the area we need to allocate for DMA transfers. the
404 size is the same regardless of the number of channels - the
405 Multiface still uses the same memory area.
407 Note that we allocate 1 more channel than is apparently needed
408 because the h/w seems to write 1 byte beyond the end of the last
412 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
413 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
415 #define HDSP_FIRMWARE_SIZE (24413 * 4)
417 struct hdsp_9632_meters {
419 u32 playback_peak[16];
423 u32 input_rms_low[16];
424 u32 playback_rms_low[16];
425 u32 output_rms_low[16];
427 u32 input_rms_high[16];
428 u32 playback_rms_high[16];
429 u32 output_rms_high[16];
430 u32 xxx_rms_high[16];
436 struct snd_rawmidi *rmidi;
437 struct snd_rawmidi_substream *input;
438 struct snd_rawmidi_substream *output;
439 char istimer; /* timer in use */
440 struct timer_list timer;
447 struct snd_pcm_substream *capture_substream;
448 struct snd_pcm_substream *playback_substream;
449 struct hdsp_midi midi[2];
450 struct tasklet_struct midi_tasklet;
451 int use_midi_tasklet;
453 u32 control_register; /* cached value */
454 u32 control2_register; /* cached value */
456 u32 creg_spdif_stream;
457 int clock_source_locked;
458 char *card_name; /* digiface/multiface/rpm */
459 enum HDSP_IO_Type io_type; /* ditto, but for code use */
460 unsigned short firmware_rev;
461 unsigned short state; /* stores state bits */
462 const struct firmware *firmware;
464 size_t period_bytes; /* guess what this is */
465 unsigned char max_channels;
466 unsigned char qs_in_channels; /* quad speed mode for H9632 */
467 unsigned char ds_in_channels;
468 unsigned char ss_in_channels; /* different for multiface/digiface */
469 unsigned char qs_out_channels;
470 unsigned char ds_out_channels;
471 unsigned char ss_out_channels;
473 struct snd_dma_buffer capture_dma_buf;
474 struct snd_dma_buffer playback_dma_buf;
475 unsigned char *capture_buffer; /* suitably aligned address */
476 unsigned char *playback_buffer; /* suitably aligned address */
481 int system_sample_rate;
486 void __iomem *iobase;
487 struct snd_card *card;
489 struct snd_hwdep *hwdep;
491 struct snd_kcontrol *spdif_ctl;
492 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
493 unsigned int dds_value; /* last value written to freq register */
496 /* These tables map the ALSA channels 1..N to the channels that we
497 need to use in order to find the relevant channel buffer. RME
498 refer to this kind of mapping as between "the ADAT channel and
499 the DMA channel." We index it using the logical audio channel,
500 and the value is the DMA channel (i.e. channel buffer number)
501 where the data for that channel can be read/written from/to.
504 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
505 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
506 18, 19, 20, 21, 22, 23, 24, 25
509 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
511 0, 1, 2, 3, 4, 5, 6, 7,
513 16, 17, 18, 19, 20, 21, 22, 23,
516 -1, -1, -1, -1, -1, -1, -1, -1
519 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
520 /* ADAT channels are remapped */
521 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
522 /* channels 12 and 13 are S/PDIF */
524 /* others don't exist */
525 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
528 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
530 0, 1, 2, 3, 4, 5, 6, 7,
535 /* AO4S-192 and AI4S-192 extension boards */
537 /* others don't exist */
538 -1, -1, -1, -1, -1, -1, -1, -1,
542 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
549 /* AO4S-192 and AI4S-192 extension boards */
551 /* others don't exist */
552 -1, -1, -1, -1, -1, -1, -1, -1,
553 -1, -1, -1, -1, -1, -1
556 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
557 /* ADAT is disabled in this mode */
562 /* AO4S-192 and AI4S-192 extension boards */
564 /* others don't exist */
565 -1, -1, -1, -1, -1, -1, -1, -1,
566 -1, -1, -1, -1, -1, -1, -1, -1,
570 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
572 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
573 dmab->dev.dev = snd_dma_pci_data(pci);
574 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
580 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
583 snd_dma_free_pages(dmab);
587 static const struct pci_device_id snd_hdsp_ids[] = {
589 .vendor = PCI_VENDOR_ID_XILINX,
590 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
591 .subvendor = PCI_ANY_ID,
592 .subdevice = PCI_ANY_ID,
593 }, /* RME Hammerfall-DSP */
597 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
600 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
601 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
602 static int snd_hdsp_enable_io (struct hdsp *hdsp);
603 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
604 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
605 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
606 static int hdsp_autosync_ref(struct hdsp *hdsp);
607 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
608 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
610 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
612 switch (hdsp->io_type) {
617 if (hdsp->firmware_rev == 0xa)
618 return (64 * out) + (32 + (in));
620 return (52 * out) + (26 + (in));
622 return (32 * out) + (16 + (in));
624 return (52 * out) + (26 + (in));
628 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
630 switch (hdsp->io_type) {
635 if (hdsp->firmware_rev == 0xa)
636 return (64 * out) + in;
638 return (52 * out) + in;
640 return (32 * out) + in;
642 return (52 * out) + in;
646 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
648 writel(val, hdsp->iobase + reg);
651 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
653 return readl (hdsp->iobase + reg);
656 static int hdsp_check_for_iobox (struct hdsp *hdsp)
660 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
661 for (i = 0; i < 500; i++) {
662 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
665 dev_dbg(hdsp->card->dev,
666 "IO box found after %d ms\n",
673 dev_err(hdsp->card->dev, "no IO box connected!\n");
674 hdsp->state &= ~HDSP_FirmwareLoaded;
678 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
683 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
686 for (i = 0; i != loops; ++i) {
687 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
690 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
696 dev_info(hdsp->card->dev, "no IO box connected!\n");
697 hdsp->state &= ~HDSP_FirmwareLoaded;
701 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
707 if (hdsp->fw_uploaded)
708 cache = hdsp->fw_uploaded;
712 cache = (u32 *)hdsp->firmware->data;
717 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
719 dev_info(hdsp->card->dev, "loading firmware\n");
721 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
722 hdsp_write (hdsp, HDSP_fifoData, 0);
724 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
725 dev_info(hdsp->card->dev,
726 "timeout waiting for download preparation\n");
727 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
731 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
733 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
734 hdsp_write(hdsp, HDSP_fifoData, cache[i]);
735 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
736 dev_info(hdsp->card->dev,
737 "timeout during firmware loading\n");
738 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
743 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
744 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
747 #ifdef SNDRV_BIG_ENDIAN
748 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
750 hdsp->control2_register = 0;
752 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
753 dev_info(hdsp->card->dev, "finished firmware loading\n");
756 if (hdsp->state & HDSP_InitializationComplete) {
757 dev_info(hdsp->card->dev,
758 "firmware loaded from cache, restoring defaults\n");
759 spin_lock_irqsave(&hdsp->lock, flags);
760 snd_hdsp_set_defaults(hdsp);
761 spin_unlock_irqrestore(&hdsp->lock, flags);
764 hdsp->state |= HDSP_FirmwareLoaded;
769 static int hdsp_get_iobox_version (struct hdsp *hdsp)
771 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
773 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
774 hdsp_write(hdsp, HDSP_fifoData, 0);
776 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
777 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
778 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
781 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
782 hdsp_write (hdsp, HDSP_fifoData, 0);
783 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
786 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
787 hdsp_write(hdsp, HDSP_fifoData, 0);
788 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
789 hdsp->io_type = Digiface;
790 dev_info(hdsp->card->dev, "Digiface found\n");
794 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
795 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
796 hdsp_write(hdsp, HDSP_fifoData, 0);
797 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
800 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
801 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
802 hdsp_write(hdsp, HDSP_fifoData, 0);
803 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
807 dev_info(hdsp->card->dev, "RPM found\n");
810 /* firmware was already loaded, get iobox type */
811 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
813 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
814 hdsp->io_type = Multiface;
816 hdsp->io_type = Digiface;
821 hdsp->io_type = Multiface;
822 dev_info(hdsp->card->dev, "Multiface found\n");
827 static int hdsp_request_fw_loader(struct hdsp *hdsp);
829 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
831 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
833 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
834 hdsp->state &= ~HDSP_FirmwareLoaded;
835 if (! load_on_demand)
837 dev_err(hdsp->card->dev, "firmware not present.\n");
838 /* try to load firmware */
839 if (! (hdsp->state & HDSP_FirmwareCached)) {
840 if (! hdsp_request_fw_loader(hdsp))
842 dev_err(hdsp->card->dev,
843 "No firmware loaded nor cached, please upload firmware.\n");
846 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
847 dev_err(hdsp->card->dev,
848 "Firmware loading from cache failed, please upload manually.\n");
856 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
860 /* the fifoStatus registers reports on how many words
861 are available in the command FIFO.
864 for (i = 0; i < timeout; i++) {
866 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
869 /* not very friendly, but we only do this during a firmware
870 load and changing the mixer, so we just put up with it.
876 dev_warn(hdsp->card->dev,
877 "wait for FIFO status <= %d failed after %d iterations\n",
882 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
884 if (addr >= HDSP_MATRIX_MIXER_SIZE)
887 return hdsp->mixer_matrix[addr];
890 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
894 if (addr >= HDSP_MATRIX_MIXER_SIZE)
897 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
899 /* from martin bjornsen:
901 "You can only write dwords to the
902 mixer memory which contain two
903 mixer values in the low and high
904 word. So if you want to change
905 value 0 you have to read value 1
906 from the cache and write both to
907 the first dword in the mixer
911 if (hdsp->io_type == H9632 && addr >= 512)
914 if (hdsp->io_type == H9652 && addr >= 1352)
917 hdsp->mixer_matrix[addr] = data;
920 /* `addr' addresses a 16-bit wide address, but
921 the address space accessed via hdsp_write
922 uses byte offsets. put another way, addr
923 varies from 0 to 1351, but to access the
924 corresponding memory location, we need
925 to access 0 to 2703 ...
929 hdsp_write (hdsp, 4096 + (ad*4),
930 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
931 hdsp->mixer_matrix[addr&0x7fe]);
937 ad = (addr << 16) + data;
939 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
942 hdsp_write (hdsp, HDSP_fifoData, ad);
943 hdsp->mixer_matrix[addr] = data;
950 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
955 spin_lock_irqsave(&hdsp->lock, flags);
956 if ((hdsp->playback_pid != hdsp->capture_pid) &&
957 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
959 spin_unlock_irqrestore(&hdsp->lock, flags);
963 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
965 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
966 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
968 /* For the 9632, the mask is different */
969 if (hdsp->io_type == H9632)
970 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
972 if (status & HDSP_SPDIFErrorFlag)
976 case HDSP_spdifFrequency32KHz: return 32000;
977 case HDSP_spdifFrequency44_1KHz: return 44100;
978 case HDSP_spdifFrequency48KHz: return 48000;
979 case HDSP_spdifFrequency64KHz: return 64000;
980 case HDSP_spdifFrequency88_2KHz: return 88200;
981 case HDSP_spdifFrequency96KHz: return 96000;
982 case HDSP_spdifFrequency128KHz:
983 if (hdsp->io_type == H9632) return 128000;
985 case HDSP_spdifFrequency176_4KHz:
986 if (hdsp->io_type == H9632) return 176400;
988 case HDSP_spdifFrequency192KHz:
989 if (hdsp->io_type == H9632) return 192000;
994 dev_warn(hdsp->card->dev,
995 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
1000 static int hdsp_external_sample_rate(struct hdsp *hdsp)
1002 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
1003 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1005 /* For the 9632 card, there seems to be no bit for indicating external
1006 * sample rate greater than 96kHz. The card reports the corresponding
1007 * single speed. So the best means seems to get spdif rate when
1008 * autosync reference is spdif */
1009 if (hdsp->io_type == H9632 &&
1010 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1011 return hdsp_spdif_sample_rate(hdsp);
1013 switch (rate_bits) {
1014 case HDSP_systemFrequency32: return 32000;
1015 case HDSP_systemFrequency44_1: return 44100;
1016 case HDSP_systemFrequency48: return 48000;
1017 case HDSP_systemFrequency64: return 64000;
1018 case HDSP_systemFrequency88_2: return 88200;
1019 case HDSP_systemFrequency96: return 96000;
1025 static void hdsp_compute_period_size(struct hdsp *hdsp)
1027 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1030 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1034 position = hdsp_read(hdsp, HDSP_statusRegister);
1036 if (!hdsp->precise_ptr)
1037 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1039 position &= HDSP_BufferPositionMask;
1041 position &= (hdsp->period_bytes/2) - 1;
1045 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1047 hdsp_write (hdsp, HDSP_resetPointer, 0);
1048 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1049 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1050 * requires (?) to write again DDS value after a reset pointer
1051 * (at least, it works like this) */
1052 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1055 static void hdsp_start_audio(struct hdsp *s)
1057 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1058 hdsp_write(s, HDSP_controlRegister, s->control_register);
1061 static void hdsp_stop_audio(struct hdsp *s)
1063 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1064 hdsp_write(s, HDSP_controlRegister, s->control_register);
1067 static void hdsp_silence_playback(struct hdsp *hdsp)
1069 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1072 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1076 spin_lock_irq(&s->lock);
1085 s->control_register &= ~HDSP_LatencyMask;
1086 s->control_register |= hdsp_encode_latency(n);
1088 hdsp_write(s, HDSP_controlRegister, s->control_register);
1090 hdsp_compute_period_size(s);
1092 spin_unlock_irq(&s->lock);
1097 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1103 else if (rate >= 56000)
1107 n = div_u64(n, rate);
1108 /* n should be less than 2^32 for being written to FREQ register */
1109 snd_BUG_ON(n >> 32);
1110 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1111 value to write it after a reset */
1112 hdsp->dds_value = n;
1113 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1116 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1118 int reject_if_open = 0;
1122 /* ASSUMPTION: hdsp->lock is either held, or
1123 there is no need for it (e.g. during module
1127 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1128 if (called_internally) {
1129 /* request from ctl or card initialization */
1130 dev_err(hdsp->card->dev,
1131 "device is not running as a clock master: cannot set sample rate.\n");
1134 /* hw_param request while in AutoSync mode */
1135 int external_freq = hdsp_external_sample_rate(hdsp);
1136 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1138 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1139 dev_info(hdsp->card->dev,
1140 "Detected ADAT in double speed mode\n");
1141 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1142 dev_info(hdsp->card->dev,
1143 "Detected ADAT in quad speed mode\n");
1144 else if (rate != external_freq) {
1145 dev_info(hdsp->card->dev,
1146 "No AutoSync source for requested rate\n");
1152 current_rate = hdsp->system_sample_rate;
1154 /* Changing from a "single speed" to a "double speed" rate is
1155 not allowed if any substreams are open. This is because
1156 such a change causes a shift in the location of
1157 the DMA buffers and a reduction in the number of available
1160 Note that a similar but essentially insoluble problem
1161 exists for externally-driven rate changes. All we can do
1162 is to flag rate changes in the read/write routines. */
1164 if (rate > 96000 && hdsp->io_type != H9632)
1169 if (current_rate > 48000)
1171 rate_bits = HDSP_Frequency32KHz;
1174 if (current_rate > 48000)
1176 rate_bits = HDSP_Frequency44_1KHz;
1179 if (current_rate > 48000)
1181 rate_bits = HDSP_Frequency48KHz;
1184 if (current_rate <= 48000 || current_rate > 96000)
1186 rate_bits = HDSP_Frequency64KHz;
1189 if (current_rate <= 48000 || current_rate > 96000)
1191 rate_bits = HDSP_Frequency88_2KHz;
1194 if (current_rate <= 48000 || current_rate > 96000)
1196 rate_bits = HDSP_Frequency96KHz;
1199 if (current_rate < 128000)
1201 rate_bits = HDSP_Frequency128KHz;
1204 if (current_rate < 128000)
1206 rate_bits = HDSP_Frequency176_4KHz;
1209 if (current_rate < 128000)
1211 rate_bits = HDSP_Frequency192KHz;
1217 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1218 dev_warn(hdsp->card->dev,
1219 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1221 hdsp->playback_pid);
1225 hdsp->control_register &= ~HDSP_FrequencyMask;
1226 hdsp->control_register |= rate_bits;
1227 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1229 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1230 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1231 hdsp_set_dds_value(hdsp, rate);
1233 if (rate >= 128000) {
1234 hdsp->channel_map = channel_map_H9632_qs;
1235 } else if (rate > 48000) {
1236 if (hdsp->io_type == H9632)
1237 hdsp->channel_map = channel_map_H9632_ds;
1239 hdsp->channel_map = channel_map_ds;
1241 switch (hdsp->io_type) {
1244 hdsp->channel_map = channel_map_mf_ss;
1248 hdsp->channel_map = channel_map_df_ss;
1251 hdsp->channel_map = channel_map_H9632_ss;
1254 /* should never happen */
1259 hdsp->system_sample_rate = rate;
1264 /*----------------------------------------------------------------------------
1266 ----------------------------------------------------------------------------*/
1268 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1270 /* the hardware already does the relevant bit-mask with 0xff */
1272 return hdsp_read(hdsp, HDSP_midiDataIn1);
1274 return hdsp_read(hdsp, HDSP_midiDataIn0);
1277 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1279 /* the hardware already does the relevant bit-mask with 0xff */
1281 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1283 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1286 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1289 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1291 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1294 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1296 int fifo_bytes_used;
1299 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1301 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1303 if (fifo_bytes_used < 128)
1304 return 128 - fifo_bytes_used;
1309 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1311 while (snd_hdsp_midi_input_available (hdsp, id))
1312 snd_hdsp_midi_read_byte (hdsp, id);
1315 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1317 unsigned long flags;
1321 unsigned char buf[128];
1323 /* Output is not interrupt driven */
1325 spin_lock_irqsave (&hmidi->lock, flags);
1326 if (hmidi->output) {
1327 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1328 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1329 if (n_pending > (int)sizeof (buf))
1330 n_pending = sizeof (buf);
1332 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1333 for (i = 0; i < to_write; ++i)
1334 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1339 spin_unlock_irqrestore (&hmidi->lock, flags);
1343 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1345 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1346 unsigned long flags;
1350 spin_lock_irqsave (&hmidi->lock, flags);
1351 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1353 if (n_pending > (int)sizeof (buf))
1354 n_pending = sizeof (buf);
1355 for (i = 0; i < n_pending; ++i)
1356 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1358 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1360 /* flush the MIDI input FIFO */
1362 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1367 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1369 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1370 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1371 spin_unlock_irqrestore (&hmidi->lock, flags);
1372 return snd_hdsp_midi_output_write (hmidi);
1375 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1378 struct hdsp_midi *hmidi;
1379 unsigned long flags;
1382 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1384 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1385 spin_lock_irqsave (&hdsp->lock, flags);
1387 if (!(hdsp->control_register & ie)) {
1388 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1389 hdsp->control_register |= ie;
1392 hdsp->control_register &= ~ie;
1393 tasklet_kill(&hdsp->midi_tasklet);
1396 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1397 spin_unlock_irqrestore (&hdsp->lock, flags);
1400 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1402 struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1403 unsigned long flags;
1405 snd_hdsp_midi_output_write(hmidi);
1406 spin_lock_irqsave (&hmidi->lock, flags);
1408 /* this does not bump hmidi->istimer, because the
1409 kernel automatically removed the timer when it
1410 expired, and we are now adding it back, thus
1411 leaving istimer wherever it was set before.
1415 mod_timer(&hmidi->timer, 1 + jiffies);
1417 spin_unlock_irqrestore (&hmidi->lock, flags);
1420 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1422 struct hdsp_midi *hmidi;
1423 unsigned long flags;
1425 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1426 spin_lock_irqsave (&hmidi->lock, flags);
1428 if (!hmidi->istimer) {
1429 timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1431 mod_timer(&hmidi->timer, 1 + jiffies);
1435 if (hmidi->istimer && --hmidi->istimer <= 0)
1436 del_timer (&hmidi->timer);
1438 spin_unlock_irqrestore (&hmidi->lock, flags);
1440 snd_hdsp_midi_output_write(hmidi);
1443 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1445 struct hdsp_midi *hmidi;
1447 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1448 spin_lock_irq (&hmidi->lock);
1449 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1450 hmidi->input = substream;
1451 spin_unlock_irq (&hmidi->lock);
1456 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1458 struct hdsp_midi *hmidi;
1460 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1461 spin_lock_irq (&hmidi->lock);
1462 hmidi->output = substream;
1463 spin_unlock_irq (&hmidi->lock);
1468 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1470 struct hdsp_midi *hmidi;
1472 snd_hdsp_midi_input_trigger (substream, 0);
1474 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1475 spin_lock_irq (&hmidi->lock);
1476 hmidi->input = NULL;
1477 spin_unlock_irq (&hmidi->lock);
1482 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1484 struct hdsp_midi *hmidi;
1486 snd_hdsp_midi_output_trigger (substream, 0);
1488 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1489 spin_lock_irq (&hmidi->lock);
1490 hmidi->output = NULL;
1491 spin_unlock_irq (&hmidi->lock);
1496 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1498 .open = snd_hdsp_midi_output_open,
1499 .close = snd_hdsp_midi_output_close,
1500 .trigger = snd_hdsp_midi_output_trigger,
1503 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1505 .open = snd_hdsp_midi_input_open,
1506 .close = snd_hdsp_midi_input_close,
1507 .trigger = snd_hdsp_midi_input_trigger,
1510 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1514 hdsp->midi[id].id = id;
1515 hdsp->midi[id].rmidi = NULL;
1516 hdsp->midi[id].input = NULL;
1517 hdsp->midi[id].output = NULL;
1518 hdsp->midi[id].hdsp = hdsp;
1519 hdsp->midi[id].istimer = 0;
1520 hdsp->midi[id].pending = 0;
1521 spin_lock_init (&hdsp->midi[id].lock);
1523 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1524 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1527 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1528 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1530 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1531 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1533 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1534 SNDRV_RAWMIDI_INFO_INPUT |
1535 SNDRV_RAWMIDI_INFO_DUPLEX;
1540 /*-----------------------------------------------------------------------------
1542 ----------------------------------------------------------------------------*/
1544 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1547 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1548 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1549 if (val & HDSP_SPDIFProfessional)
1550 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1552 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1556 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1558 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1559 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1560 if (val & HDSP_SPDIFProfessional)
1561 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1563 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1566 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1568 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1573 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1575 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1577 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1581 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1583 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1587 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1588 spin_lock_irq(&hdsp->lock);
1589 change = val != hdsp->creg_spdif;
1590 hdsp->creg_spdif = val;
1591 spin_unlock_irq(&hdsp->lock);
1595 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1597 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1602 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1604 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1606 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1610 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1612 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1616 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1617 spin_lock_irq(&hdsp->lock);
1618 change = val != hdsp->creg_spdif_stream;
1619 hdsp->creg_spdif_stream = val;
1620 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1621 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1622 spin_unlock_irq(&hdsp->lock);
1626 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1628 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1633 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1635 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1639 #define HDSP_SPDIF_IN(xname, xindex) \
1640 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1643 .info = snd_hdsp_info_spdif_in, \
1644 .get = snd_hdsp_get_spdif_in, \
1645 .put = snd_hdsp_put_spdif_in }
1647 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1649 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1652 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1654 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1655 hdsp->control_register |= hdsp_encode_spdif_in(in);
1656 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1660 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1662 static const char * const texts[4] = {
1663 "Optical", "Coaxial", "Internal", "AES"
1665 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1667 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1671 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1673 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1675 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1679 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1681 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1685 if (!snd_hdsp_use_is_exclusive(hdsp))
1687 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1688 spin_lock_irq(&hdsp->lock);
1689 change = val != hdsp_spdif_in(hdsp);
1691 hdsp_set_spdif_input(hdsp, val);
1692 spin_unlock_irq(&hdsp->lock);
1696 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1697 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1699 .private_value = xindex, \
1700 .info = snd_hdsp_info_toggle_setting, \
1701 .get = snd_hdsp_get_toggle_setting, \
1702 .put = snd_hdsp_put_toggle_setting \
1705 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1707 return (hdsp->control_register & regmask) ? 1 : 0;
1710 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1713 hdsp->control_register |= regmask;
1715 hdsp->control_register &= ~regmask;
1716 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1721 #define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info
1723 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1724 struct snd_ctl_elem_value *ucontrol)
1726 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1727 u32 regmask = kcontrol->private_value;
1729 spin_lock_irq(&hdsp->lock);
1730 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1731 spin_unlock_irq(&hdsp->lock);
1735 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1736 struct snd_ctl_elem_value *ucontrol)
1738 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1739 u32 regmask = kcontrol->private_value;
1743 if (!snd_hdsp_use_is_exclusive(hdsp))
1745 val = ucontrol->value.integer.value[0] & 1;
1746 spin_lock_irq(&hdsp->lock);
1747 change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1749 hdsp_set_toggle_setting(hdsp, regmask, val);
1750 spin_unlock_irq(&hdsp->lock);
1754 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1755 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1758 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1759 .info = snd_hdsp_info_spdif_sample_rate, \
1760 .get = snd_hdsp_get_spdif_sample_rate \
1763 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1765 static const char * const texts[] = {
1766 "32000", "44100", "48000", "64000", "88200", "96000",
1767 "None", "128000", "176400", "192000"
1769 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1771 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1775 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1777 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1779 switch (hdsp_spdif_sample_rate(hdsp)) {
1781 ucontrol->value.enumerated.item[0] = 0;
1784 ucontrol->value.enumerated.item[0] = 1;
1787 ucontrol->value.enumerated.item[0] = 2;
1790 ucontrol->value.enumerated.item[0] = 3;
1793 ucontrol->value.enumerated.item[0] = 4;
1796 ucontrol->value.enumerated.item[0] = 5;
1799 ucontrol->value.enumerated.item[0] = 7;
1802 ucontrol->value.enumerated.item[0] = 8;
1805 ucontrol->value.enumerated.item[0] = 9;
1808 ucontrol->value.enumerated.item[0] = 6;
1813 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1814 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1817 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1818 .info = snd_hdsp_info_system_sample_rate, \
1819 .get = snd_hdsp_get_system_sample_rate \
1822 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1824 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1829 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1831 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1833 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1837 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1838 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1841 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1842 .info = snd_hdsp_info_autosync_sample_rate, \
1843 .get = snd_hdsp_get_autosync_sample_rate \
1846 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1848 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1849 static const char * const texts[] = {
1850 "32000", "44100", "48000", "64000", "88200", "96000",
1851 "None", "128000", "176400", "192000"
1854 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1858 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1860 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1862 switch (hdsp_external_sample_rate(hdsp)) {
1864 ucontrol->value.enumerated.item[0] = 0;
1867 ucontrol->value.enumerated.item[0] = 1;
1870 ucontrol->value.enumerated.item[0] = 2;
1873 ucontrol->value.enumerated.item[0] = 3;
1876 ucontrol->value.enumerated.item[0] = 4;
1879 ucontrol->value.enumerated.item[0] = 5;
1882 ucontrol->value.enumerated.item[0] = 7;
1885 ucontrol->value.enumerated.item[0] = 8;
1888 ucontrol->value.enumerated.item[0] = 9;
1891 ucontrol->value.enumerated.item[0] = 6;
1896 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1897 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1900 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1901 .info = snd_hdsp_info_system_clock_mode, \
1902 .get = snd_hdsp_get_system_clock_mode \
1905 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1907 if (hdsp->control_register & HDSP_ClockModeMaster)
1909 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1914 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1916 static const char * const texts[] = {"Master", "Slave" };
1918 return snd_ctl_enum_info(uinfo, 1, 2, texts);
1921 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1923 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1925 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1929 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1930 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1933 .info = snd_hdsp_info_clock_source, \
1934 .get = snd_hdsp_get_clock_source, \
1935 .put = snd_hdsp_put_clock_source \
1938 static int hdsp_clock_source(struct hdsp *hdsp)
1940 if (hdsp->control_register & HDSP_ClockModeMaster) {
1941 switch (hdsp->system_sample_rate) {
1968 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1972 case HDSP_CLOCK_SOURCE_AUTOSYNC:
1973 if (hdsp_external_sample_rate(hdsp) != 0) {
1974 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1975 hdsp->control_register &= ~HDSP_ClockModeMaster;
1976 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1981 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1984 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1987 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1990 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
1993 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1996 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
1999 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2002 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2005 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2011 hdsp->control_register |= HDSP_ClockModeMaster;
2012 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2013 hdsp_set_rate(hdsp, rate, 1);
2017 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2019 static const char * const texts[] = {
2020 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2021 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2022 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2023 "Internal 192.0 KHz"
2025 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2027 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2031 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2033 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2035 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2039 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2041 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2045 if (!snd_hdsp_use_is_exclusive(hdsp))
2047 val = ucontrol->value.enumerated.item[0];
2048 if (val < 0) val = 0;
2049 if (hdsp->io_type == H9632) {
2056 spin_lock_irq(&hdsp->lock);
2057 if (val != hdsp_clock_source(hdsp))
2058 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2061 spin_unlock_irq(&hdsp->lock);
2065 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2067 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2069 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2071 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2075 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2077 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2080 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2082 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2086 #define HDSP_DA_GAIN(xname, xindex) \
2087 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2090 .info = snd_hdsp_info_da_gain, \
2091 .get = snd_hdsp_get_da_gain, \
2092 .put = snd_hdsp_put_da_gain \
2095 static int hdsp_da_gain(struct hdsp *hdsp)
2097 switch (hdsp->control_register & HDSP_DAGainMask) {
2098 case HDSP_DAGainHighGain:
2100 case HDSP_DAGainPlus4dBu:
2102 case HDSP_DAGainMinus10dBV:
2109 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2111 hdsp->control_register &= ~HDSP_DAGainMask;
2114 hdsp->control_register |= HDSP_DAGainHighGain;
2117 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2120 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2126 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2130 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2132 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2134 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2137 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2139 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2141 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2145 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2147 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2151 if (!snd_hdsp_use_is_exclusive(hdsp))
2153 val = ucontrol->value.enumerated.item[0];
2154 if (val < 0) val = 0;
2155 if (val > 2) val = 2;
2156 spin_lock_irq(&hdsp->lock);
2157 if (val != hdsp_da_gain(hdsp))
2158 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2161 spin_unlock_irq(&hdsp->lock);
2165 #define HDSP_AD_GAIN(xname, xindex) \
2166 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2169 .info = snd_hdsp_info_ad_gain, \
2170 .get = snd_hdsp_get_ad_gain, \
2171 .put = snd_hdsp_put_ad_gain \
2174 static int hdsp_ad_gain(struct hdsp *hdsp)
2176 switch (hdsp->control_register & HDSP_ADGainMask) {
2177 case HDSP_ADGainMinus10dBV:
2179 case HDSP_ADGainPlus4dBu:
2181 case HDSP_ADGainLowGain:
2188 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2190 hdsp->control_register &= ~HDSP_ADGainMask;
2193 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2196 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2199 hdsp->control_register |= HDSP_ADGainLowGain;
2205 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2209 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2211 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2213 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2216 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2218 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2220 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2224 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2226 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2230 if (!snd_hdsp_use_is_exclusive(hdsp))
2232 val = ucontrol->value.enumerated.item[0];
2233 if (val < 0) val = 0;
2234 if (val > 2) val = 2;
2235 spin_lock_irq(&hdsp->lock);
2236 if (val != hdsp_ad_gain(hdsp))
2237 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2240 spin_unlock_irq(&hdsp->lock);
2244 #define HDSP_PHONE_GAIN(xname, xindex) \
2245 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2248 .info = snd_hdsp_info_phone_gain, \
2249 .get = snd_hdsp_get_phone_gain, \
2250 .put = snd_hdsp_put_phone_gain \
2253 static int hdsp_phone_gain(struct hdsp *hdsp)
2255 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2256 case HDSP_PhoneGain0dB:
2258 case HDSP_PhoneGainMinus6dB:
2260 case HDSP_PhoneGainMinus12dB:
2267 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2269 hdsp->control_register &= ~HDSP_PhoneGainMask;
2272 hdsp->control_register |= HDSP_PhoneGain0dB;
2275 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2278 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2284 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2288 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2290 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2292 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2295 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2297 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2299 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2303 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2305 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2309 if (!snd_hdsp_use_is_exclusive(hdsp))
2311 val = ucontrol->value.enumerated.item[0];
2312 if (val < 0) val = 0;
2313 if (val > 2) val = 2;
2314 spin_lock_irq(&hdsp->lock);
2315 if (val != hdsp_phone_gain(hdsp))
2316 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2319 spin_unlock_irq(&hdsp->lock);
2323 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2324 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2327 .info = snd_hdsp_info_pref_sync_ref, \
2328 .get = snd_hdsp_get_pref_sync_ref, \
2329 .put = snd_hdsp_put_pref_sync_ref \
2332 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2334 /* Notice that this looks at the requested sync source,
2335 not the one actually in use.
2338 switch (hdsp->control_register & HDSP_SyncRefMask) {
2339 case HDSP_SyncRef_ADAT1:
2340 return HDSP_SYNC_FROM_ADAT1;
2341 case HDSP_SyncRef_ADAT2:
2342 return HDSP_SYNC_FROM_ADAT2;
2343 case HDSP_SyncRef_ADAT3:
2344 return HDSP_SYNC_FROM_ADAT3;
2345 case HDSP_SyncRef_SPDIF:
2346 return HDSP_SYNC_FROM_SPDIF;
2347 case HDSP_SyncRef_WORD:
2348 return HDSP_SYNC_FROM_WORD;
2349 case HDSP_SyncRef_ADAT_SYNC:
2350 return HDSP_SYNC_FROM_ADAT_SYNC;
2352 return HDSP_SYNC_FROM_WORD;
2357 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2359 hdsp->control_register &= ~HDSP_SyncRefMask;
2361 case HDSP_SYNC_FROM_ADAT1:
2362 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2364 case HDSP_SYNC_FROM_ADAT2:
2365 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2367 case HDSP_SYNC_FROM_ADAT3:
2368 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2370 case HDSP_SYNC_FROM_SPDIF:
2371 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2373 case HDSP_SYNC_FROM_WORD:
2374 hdsp->control_register |= HDSP_SyncRef_WORD;
2376 case HDSP_SYNC_FROM_ADAT_SYNC:
2377 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2382 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2386 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2388 static const char * const texts[] = {
2389 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2391 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2394 switch (hdsp->io_type) {
2409 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2412 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2414 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2416 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2420 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2422 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2426 if (!snd_hdsp_use_is_exclusive(hdsp))
2429 switch (hdsp->io_type) {
2444 val = ucontrol->value.enumerated.item[0] % max;
2445 spin_lock_irq(&hdsp->lock);
2446 change = (int)val != hdsp_pref_sync_ref(hdsp);
2447 hdsp_set_pref_sync_ref(hdsp, val);
2448 spin_unlock_irq(&hdsp->lock);
2452 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2453 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2456 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2457 .info = snd_hdsp_info_autosync_ref, \
2458 .get = snd_hdsp_get_autosync_ref, \
2461 static int hdsp_autosync_ref(struct hdsp *hdsp)
2463 /* This looks at the autosync selected sync reference */
2464 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2466 switch (status2 & HDSP_SelSyncRefMask) {
2467 case HDSP_SelSyncRef_WORD:
2468 return HDSP_AUTOSYNC_FROM_WORD;
2469 case HDSP_SelSyncRef_ADAT_SYNC:
2470 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2471 case HDSP_SelSyncRef_SPDIF:
2472 return HDSP_AUTOSYNC_FROM_SPDIF;
2473 case HDSP_SelSyncRefMask:
2474 return HDSP_AUTOSYNC_FROM_NONE;
2475 case HDSP_SelSyncRef_ADAT1:
2476 return HDSP_AUTOSYNC_FROM_ADAT1;
2477 case HDSP_SelSyncRef_ADAT2:
2478 return HDSP_AUTOSYNC_FROM_ADAT2;
2479 case HDSP_SelSyncRef_ADAT3:
2480 return HDSP_AUTOSYNC_FROM_ADAT3;
2482 return HDSP_AUTOSYNC_FROM_WORD;
2487 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2489 static const char * const texts[] = {
2490 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2493 return snd_ctl_enum_info(uinfo, 1, 7, texts);
2496 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2498 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2500 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2504 #define HDSP_PRECISE_POINTER(xname, xindex) \
2505 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2508 .info = snd_hdsp_info_precise_pointer, \
2509 .get = snd_hdsp_get_precise_pointer, \
2510 .put = snd_hdsp_put_precise_pointer \
2513 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2516 hdsp->precise_ptr = 1;
2518 hdsp->precise_ptr = 0;
2522 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2524 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2526 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2528 spin_lock_irq(&hdsp->lock);
2529 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2530 spin_unlock_irq(&hdsp->lock);
2534 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2536 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2540 if (!snd_hdsp_use_is_exclusive(hdsp))
2542 val = ucontrol->value.integer.value[0] & 1;
2543 spin_lock_irq(&hdsp->lock);
2544 change = (int)val != hdsp->precise_ptr;
2545 hdsp_set_precise_pointer(hdsp, val);
2546 spin_unlock_irq(&hdsp->lock);
2550 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2551 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2554 .info = snd_hdsp_info_use_midi_tasklet, \
2555 .get = snd_hdsp_get_use_midi_tasklet, \
2556 .put = snd_hdsp_put_use_midi_tasklet \
2559 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2562 hdsp->use_midi_tasklet = 1;
2564 hdsp->use_midi_tasklet = 0;
2568 #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info
2570 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2572 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2574 spin_lock_irq(&hdsp->lock);
2575 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2576 spin_unlock_irq(&hdsp->lock);
2580 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2582 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2586 if (!snd_hdsp_use_is_exclusive(hdsp))
2588 val = ucontrol->value.integer.value[0] & 1;
2589 spin_lock_irq(&hdsp->lock);
2590 change = (int)val != hdsp->use_midi_tasklet;
2591 hdsp_set_use_midi_tasklet(hdsp, val);
2592 spin_unlock_irq(&hdsp->lock);
2596 #define HDSP_MIXER(xname, xindex) \
2597 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2601 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2602 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2603 .info = snd_hdsp_info_mixer, \
2604 .get = snd_hdsp_get_mixer, \
2605 .put = snd_hdsp_put_mixer \
2608 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2610 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2612 uinfo->value.integer.min = 0;
2613 uinfo->value.integer.max = 65536;
2614 uinfo->value.integer.step = 1;
2618 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2620 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2625 source = ucontrol->value.integer.value[0];
2626 destination = ucontrol->value.integer.value[1];
2628 if (source >= hdsp->max_channels)
2629 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2631 addr = hdsp_input_to_output_key(hdsp,source, destination);
2633 spin_lock_irq(&hdsp->lock);
2634 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2635 spin_unlock_irq(&hdsp->lock);
2639 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2641 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2648 if (!snd_hdsp_use_is_exclusive(hdsp))
2651 source = ucontrol->value.integer.value[0];
2652 destination = ucontrol->value.integer.value[1];
2654 if (source >= hdsp->max_channels)
2655 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2657 addr = hdsp_input_to_output_key(hdsp,source, destination);
2659 gain = ucontrol->value.integer.value[2];
2661 spin_lock_irq(&hdsp->lock);
2662 change = gain != hdsp_read_gain(hdsp, addr);
2664 hdsp_write_gain(hdsp, addr, gain);
2665 spin_unlock_irq(&hdsp->lock);
2669 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2670 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2673 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2674 .info = snd_hdsp_info_sync_check, \
2675 .get = snd_hdsp_get_wc_sync_check \
2678 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2680 static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2682 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2685 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2687 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2688 if (status2 & HDSP_wc_lock) {
2689 if (status2 & HDSP_wc_sync)
2698 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2700 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2702 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2706 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2707 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2710 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2711 .info = snd_hdsp_info_sync_check, \
2712 .get = snd_hdsp_get_spdif_sync_check \
2715 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2717 int status = hdsp_read(hdsp, HDSP_statusRegister);
2718 if (status & HDSP_SPDIFErrorFlag)
2721 if (status & HDSP_SPDIFSync)
2729 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2731 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2733 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2737 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2738 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2741 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2742 .info = snd_hdsp_info_sync_check, \
2743 .get = snd_hdsp_get_adatsync_sync_check \
2746 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2748 int status = hdsp_read(hdsp, HDSP_statusRegister);
2749 if (status & HDSP_TimecodeLock) {
2750 if (status & HDSP_TimecodeSync)
2758 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2760 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2762 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2766 #define HDSP_ADAT_SYNC_CHECK \
2767 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2768 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2769 .info = snd_hdsp_info_sync_check, \
2770 .get = snd_hdsp_get_adat_sync_check \
2773 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2775 int status = hdsp_read(hdsp, HDSP_statusRegister);
2777 if (status & (HDSP_Lock0>>idx)) {
2778 if (status & (HDSP_Sync0>>idx))
2786 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2789 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2791 offset = ucontrol->id.index - 1;
2792 if (snd_BUG_ON(offset < 0))
2795 switch (hdsp->io_type) {
2810 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2814 #define HDSP_DDS_OFFSET(xname, xindex) \
2815 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2818 .info = snd_hdsp_info_dds_offset, \
2819 .get = snd_hdsp_get_dds_offset, \
2820 .put = snd_hdsp_put_dds_offset \
2823 static int hdsp_dds_offset(struct hdsp *hdsp)
2826 unsigned int dds_value = hdsp->dds_value;
2827 int system_sample_rate = hdsp->system_sample_rate;
2834 * dds_value = n / rate
2835 * rate = n / dds_value
2837 n = div_u64(n, dds_value);
2838 if (system_sample_rate >= 112000)
2840 else if (system_sample_rate >= 56000)
2842 return ((int)n) - system_sample_rate;
2845 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2847 int rate = hdsp->system_sample_rate + offset_hz;
2848 hdsp_set_dds_value(hdsp, rate);
2852 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2854 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2856 uinfo->value.integer.min = -5000;
2857 uinfo->value.integer.max = 5000;
2861 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2863 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2865 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2869 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2871 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2875 if (!snd_hdsp_use_is_exclusive(hdsp))
2877 val = ucontrol->value.integer.value[0];
2878 spin_lock_irq(&hdsp->lock);
2879 if (val != hdsp_dds_offset(hdsp))
2880 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2883 spin_unlock_irq(&hdsp->lock);
2887 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2888 HDSP_DA_GAIN("DA Gain", 0),
2889 HDSP_AD_GAIN("AD Gain", 0),
2890 HDSP_PHONE_GAIN("Phones Gain", 0),
2891 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2892 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2895 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2897 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2898 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2899 .info = snd_hdsp_control_spdif_info,
2900 .get = snd_hdsp_control_spdif_get,
2901 .put = snd_hdsp_control_spdif_put,
2904 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2905 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2906 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2907 .info = snd_hdsp_control_spdif_stream_info,
2908 .get = snd_hdsp_control_spdif_stream_get,
2909 .put = snd_hdsp_control_spdif_stream_put,
2912 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2913 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2914 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2915 .info = snd_hdsp_control_spdif_mask_info,
2916 .get = snd_hdsp_control_spdif_mask_get,
2917 .private_value = IEC958_AES0_NONAUDIO |
2918 IEC958_AES0_PROFESSIONAL |
2919 IEC958_AES0_CON_EMPHASIS,
2922 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2923 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2924 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2925 .info = snd_hdsp_control_spdif_mask_info,
2926 .get = snd_hdsp_control_spdif_mask_get,
2927 .private_value = IEC958_AES0_NONAUDIO |
2928 IEC958_AES0_PROFESSIONAL |
2929 IEC958_AES0_PRO_EMPHASIS,
2931 HDSP_MIXER("Mixer", 0),
2932 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2933 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2934 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2935 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2936 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2937 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2938 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2940 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2941 .name = "Sample Clock Source Locking",
2942 .info = snd_hdsp_info_clock_source_lock,
2943 .get = snd_hdsp_get_clock_source_lock,
2944 .put = snd_hdsp_put_clock_source_lock,
2946 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2947 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2948 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2949 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2950 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2951 /* 'External Rate' complies with the alsa control naming scheme */
2952 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2953 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2954 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2955 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2956 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2957 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2958 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2962 static int hdsp_rpm_input12(struct hdsp *hdsp)
2964 switch (hdsp->control_register & HDSP_RPM_Inp12) {
2965 case HDSP_RPM_Inp12_Phon_6dB:
2967 case HDSP_RPM_Inp12_Phon_n6dB:
2969 case HDSP_RPM_Inp12_Line_0dB:
2971 case HDSP_RPM_Inp12_Line_n6dB:
2978 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2980 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2982 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2987 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2989 hdsp->control_register &= ~HDSP_RPM_Inp12;
2992 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2997 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
3000 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
3003 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3009 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3014 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3016 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3020 if (!snd_hdsp_use_is_exclusive(hdsp))
3022 val = ucontrol->value.enumerated.item[0];
3027 spin_lock_irq(&hdsp->lock);
3028 if (val != hdsp_rpm_input12(hdsp))
3029 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3032 spin_unlock_irq(&hdsp->lock);
3037 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3039 static const char * const texts[] = {
3040 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3043 return snd_ctl_enum_info(uinfo, 1, 5, texts);
3047 static int hdsp_rpm_input34(struct hdsp *hdsp)
3049 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3050 case HDSP_RPM_Inp34_Phon_6dB:
3052 case HDSP_RPM_Inp34_Phon_n6dB:
3054 case HDSP_RPM_Inp34_Line_0dB:
3056 case HDSP_RPM_Inp34_Line_n6dB:
3063 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3065 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3067 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3072 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3074 hdsp->control_register &= ~HDSP_RPM_Inp34;
3077 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3082 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3085 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3088 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3094 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3099 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3101 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3105 if (!snd_hdsp_use_is_exclusive(hdsp))
3107 val = ucontrol->value.enumerated.item[0];
3112 spin_lock_irq(&hdsp->lock);
3113 if (val != hdsp_rpm_input34(hdsp))
3114 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3117 spin_unlock_irq(&hdsp->lock);
3122 /* RPM Bypass switch */
3123 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3125 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3129 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3131 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3133 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3138 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3141 hdsp->control_register |= HDSP_RPM_Bypass;
3143 hdsp->control_register &= ~HDSP_RPM_Bypass;
3144 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3149 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3151 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3155 if (!snd_hdsp_use_is_exclusive(hdsp))
3157 val = ucontrol->value.integer.value[0] & 1;
3158 spin_lock_irq(&hdsp->lock);
3159 change = (int)val != hdsp_rpm_bypass(hdsp);
3160 hdsp_set_rpm_bypass(hdsp, val);
3161 spin_unlock_irq(&hdsp->lock);
3166 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3168 static const char * const texts[] = {"On", "Off"};
3170 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3174 /* RPM Disconnect switch */
3175 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3177 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3181 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3183 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3185 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3190 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3193 hdsp->control_register |= HDSP_RPM_Disconnect;
3195 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3196 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3201 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3203 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3207 if (!snd_hdsp_use_is_exclusive(hdsp))
3209 val = ucontrol->value.integer.value[0] & 1;
3210 spin_lock_irq(&hdsp->lock);
3211 change = (int)val != hdsp_rpm_disconnect(hdsp);
3212 hdsp_set_rpm_disconnect(hdsp, val);
3213 spin_unlock_irq(&hdsp->lock);
3217 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3219 static const char * const texts[] = {"On", "Off"};
3221 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3224 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3226 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3227 .name = "RPM Bypass",
3228 .get = snd_hdsp_get_rpm_bypass,
3229 .put = snd_hdsp_put_rpm_bypass,
3230 .info = snd_hdsp_info_rpm_bypass
3233 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3234 .name = "RPM Disconnect",
3235 .get = snd_hdsp_get_rpm_disconnect,
3236 .put = snd_hdsp_put_rpm_disconnect,
3237 .info = snd_hdsp_info_rpm_disconnect
3240 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3241 .name = "Input 1/2",
3242 .get = snd_hdsp_get_rpm_input12,
3243 .put = snd_hdsp_put_rpm_input12,
3244 .info = snd_hdsp_info_rpm_input
3247 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3248 .name = "Input 3/4",
3249 .get = snd_hdsp_get_rpm_input34,
3250 .put = snd_hdsp_put_rpm_input34,
3251 .info = snd_hdsp_info_rpm_input
3253 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3254 HDSP_MIXER("Mixer", 0)
3257 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3258 HDSP_TOGGLE_SETTING("Analog Extension Board",
3259 HDSP_AnalogExtensionBoard);
3260 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3262 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3266 struct snd_kcontrol *kctl;
3268 if (hdsp->io_type == RPM) {
3269 /* RPM Bypass, Disconnect and Input switches */
3270 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3271 err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3278 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3279 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3281 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3282 hdsp->spdif_ctl = kctl;
3285 /* ADAT SyncCheck status */
3286 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3287 snd_hdsp_adat_sync_check.index = 1;
3288 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3290 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3291 for (idx = 1; idx < 3; ++idx) {
3292 snd_hdsp_adat_sync_check.index = idx+1;
3293 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3298 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3299 if (hdsp->io_type == H9632) {
3300 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3301 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3306 /* AEB control for H96xx card */
3307 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3308 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3315 /*------------------------------------------------------------
3317 ------------------------------------------------------------*/
3320 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3322 struct hdsp *hdsp = entry->private_data;
3323 unsigned int status;
3324 unsigned int status2;
3325 char *pref_sync_ref;
3327 char *system_clock_mode;
3331 status = hdsp_read(hdsp, HDSP_statusRegister);
3332 status2 = hdsp_read(hdsp, HDSP_status2Register);
3334 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3335 hdsp->card->number + 1);
3336 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3337 hdsp->capture_buffer, hdsp->playback_buffer);
3338 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3339 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3340 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3341 snd_iprintf(buffer, "Control2 register: 0x%x\n",
3342 hdsp->control2_register);
3343 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3344 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3346 if (hdsp_check_for_iobox(hdsp)) {
3347 snd_iprintf(buffer, "No I/O box connected.\n"
3348 "Please connect one and upload firmware.\n");
3352 if (hdsp_check_for_firmware(hdsp, 0)) {
3353 if (hdsp->state & HDSP_FirmwareCached) {
3354 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3355 snd_iprintf(buffer, "Firmware loading from "
3357 "please upload manually.\n");
3362 err = hdsp_request_fw_loader(hdsp);
3365 "No firmware loaded nor cached, "
3366 "please upload firmware.\n");
3372 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3373 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3374 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3375 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3376 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3377 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3379 snd_iprintf(buffer, "\n");
3381 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3383 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3384 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3385 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3386 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3388 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3390 snd_iprintf(buffer, "\n");
3392 switch (hdsp_clock_source(hdsp)) {
3393 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3394 clock_source = "AutoSync";
3396 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3397 clock_source = "Internal 32 kHz";
3399 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3400 clock_source = "Internal 44.1 kHz";
3402 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3403 clock_source = "Internal 48 kHz";
3405 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3406 clock_source = "Internal 64 kHz";
3408 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3409 clock_source = "Internal 88.2 kHz";
3411 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3412 clock_source = "Internal 96 kHz";
3414 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3415 clock_source = "Internal 128 kHz";
3417 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3418 clock_source = "Internal 176.4 kHz";
3420 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3421 clock_source = "Internal 192 kHz";
3424 clock_source = "Error";
3426 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3428 if (hdsp_system_clock_mode(hdsp))
3429 system_clock_mode = "Slave";
3431 system_clock_mode = "Master";
3433 switch (hdsp_pref_sync_ref (hdsp)) {
3434 case HDSP_SYNC_FROM_WORD:
3435 pref_sync_ref = "Word Clock";
3437 case HDSP_SYNC_FROM_ADAT_SYNC:
3438 pref_sync_ref = "ADAT Sync";
3440 case HDSP_SYNC_FROM_SPDIF:
3441 pref_sync_ref = "SPDIF";
3443 case HDSP_SYNC_FROM_ADAT1:
3444 pref_sync_ref = "ADAT1";
3446 case HDSP_SYNC_FROM_ADAT2:
3447 pref_sync_ref = "ADAT2";
3449 case HDSP_SYNC_FROM_ADAT3:
3450 pref_sync_ref = "ADAT3";
3453 pref_sync_ref = "Word Clock";
3456 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3458 switch (hdsp_autosync_ref (hdsp)) {
3459 case HDSP_AUTOSYNC_FROM_WORD:
3460 autosync_ref = "Word Clock";
3462 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3463 autosync_ref = "ADAT Sync";
3465 case HDSP_AUTOSYNC_FROM_SPDIF:
3466 autosync_ref = "SPDIF";
3468 case HDSP_AUTOSYNC_FROM_NONE:
3469 autosync_ref = "None";
3471 case HDSP_AUTOSYNC_FROM_ADAT1:
3472 autosync_ref = "ADAT1";
3474 case HDSP_AUTOSYNC_FROM_ADAT2:
3475 autosync_ref = "ADAT2";
3477 case HDSP_AUTOSYNC_FROM_ADAT3:
3478 autosync_ref = "ADAT3";
3481 autosync_ref = "---";
3484 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3486 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3488 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3490 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3491 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3493 snd_iprintf(buffer, "\n");
3495 if (hdsp->io_type != RPM) {
3496 switch (hdsp_spdif_in(hdsp)) {
3497 case HDSP_SPDIFIN_OPTICAL:
3498 snd_iprintf(buffer, "IEC958 input: Optical\n");
3500 case HDSP_SPDIFIN_COAXIAL:
3501 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3503 case HDSP_SPDIFIN_INTERNAL:
3504 snd_iprintf(buffer, "IEC958 input: Internal\n");
3506 case HDSP_SPDIFIN_AES:
3507 snd_iprintf(buffer, "IEC958 input: AES\n");
3510 snd_iprintf(buffer, "IEC958 input: ???\n");
3515 if (RPM == hdsp->io_type) {
3516 if (hdsp->control_register & HDSP_RPM_Bypass)
3517 snd_iprintf(buffer, "RPM Bypass: disabled\n");
3519 snd_iprintf(buffer, "RPM Bypass: enabled\n");
3520 if (hdsp->control_register & HDSP_RPM_Disconnect)
3521 snd_iprintf(buffer, "RPM disconnected\n");
3523 snd_iprintf(buffer, "RPM connected\n");
3525 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3526 case HDSP_RPM_Inp12_Phon_6dB:
3527 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3529 case HDSP_RPM_Inp12_Phon_0dB:
3530 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3532 case HDSP_RPM_Inp12_Phon_n6dB:
3533 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3535 case HDSP_RPM_Inp12_Line_0dB:
3536 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3538 case HDSP_RPM_Inp12_Line_n6dB:
3539 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3542 snd_iprintf(buffer, "Input 1/2: ???\n");
3545 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3546 case HDSP_RPM_Inp34_Phon_6dB:
3547 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3549 case HDSP_RPM_Inp34_Phon_0dB:
3550 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3552 case HDSP_RPM_Inp34_Phon_n6dB:
3553 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3555 case HDSP_RPM_Inp34_Line_0dB:
3556 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3558 case HDSP_RPM_Inp34_Line_n6dB:
3559 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3562 snd_iprintf(buffer, "Input 3/4: ???\n");
3566 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3567 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3569 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3571 if (hdsp->control_register & HDSP_SPDIFProfessional)
3572 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3574 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3576 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3577 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3579 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3581 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3582 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3584 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3585 x = hdsp_spdif_sample_rate(hdsp);
3587 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3589 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3591 snd_iprintf(buffer, "\n");
3594 x = status & HDSP_Sync0;
3595 if (status & HDSP_Lock0)
3596 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3598 snd_iprintf(buffer, "ADAT1: No Lock\n");
3600 switch (hdsp->io_type) {
3603 x = status & HDSP_Sync1;
3604 if (status & HDSP_Lock1)
3605 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3607 snd_iprintf(buffer, "ADAT2: No Lock\n");
3608 x = status & HDSP_Sync2;
3609 if (status & HDSP_Lock2)
3610 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3612 snd_iprintf(buffer, "ADAT3: No Lock\n");
3619 x = status & HDSP_SPDIFSync;
3620 if (status & HDSP_SPDIFErrorFlag)
3621 snd_iprintf (buffer, "SPDIF: No Lock\n");
3623 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3625 x = status2 & HDSP_wc_sync;
3626 if (status2 & HDSP_wc_lock)
3627 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3629 snd_iprintf (buffer, "Word Clock: No Lock\n");
3631 x = status & HDSP_TimecodeSync;
3632 if (status & HDSP_TimecodeLock)
3633 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3635 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3637 snd_iprintf(buffer, "\n");
3639 /* Informations about H9632 specific controls */
3640 if (hdsp->io_type == H9632) {
3643 switch (hdsp_ad_gain(hdsp)) {
3654 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3656 switch (hdsp_da_gain(hdsp)) {
3667 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3669 switch (hdsp_phone_gain(hdsp)) {
3680 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3682 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3683 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3686 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3687 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3689 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3690 snd_iprintf(buffer, "\n");
3695 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3697 snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3700 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3702 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3703 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3706 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3708 unsigned long pb_bus, cb_bus;
3710 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3711 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3712 if (hdsp->capture_dma_buf.area)
3713 snd_dma_free_pages(&hdsp->capture_dma_buf);
3714 dev_err(hdsp->card->dev,
3715 "%s: no buffers available\n", hdsp->card_name);
3719 /* Align to bus-space 64K boundary */
3721 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3722 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3724 /* Tell the card where it is */
3726 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3727 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3729 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3730 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3735 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3739 /* ASSUMPTION: hdsp->lock is either held, or
3740 there is no need to hold it (e.g. during module
3746 SPDIF Input via Coax
3748 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3749 which implies 2 4096 sample, 32Kbyte periods).
3753 hdsp->control_register = HDSP_ClockModeMaster |
3754 HDSP_SPDIFInputCoaxial |
3755 hdsp_encode_latency(7) |
3759 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3761 #ifdef SNDRV_BIG_ENDIAN
3762 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3764 hdsp->control2_register = 0;
3766 if (hdsp->io_type == H9652)
3767 snd_hdsp_9652_enable_mixer (hdsp);
3769 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3771 hdsp_reset_hw_pointer(hdsp);
3772 hdsp_compute_period_size(hdsp);
3774 /* silence everything */
3776 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3777 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3779 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3780 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3784 /* H9632 specific defaults */
3785 if (hdsp->io_type == H9632) {
3786 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3787 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3790 /* set a default rate so that the channel map is set up.
3793 hdsp_set_rate(hdsp, 48000, 1);
3798 static void hdsp_midi_tasklet(unsigned long arg)
3800 struct hdsp *hdsp = (struct hdsp *)arg;
3802 if (hdsp->midi[0].pending)
3803 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3804 if (hdsp->midi[1].pending)
3805 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3808 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3810 struct hdsp *hdsp = (struct hdsp *) dev_id;
3811 unsigned int status;
3815 unsigned int midi0status;
3816 unsigned int midi1status;
3819 status = hdsp_read(hdsp, HDSP_statusRegister);
3821 audio = status & HDSP_audioIRQPending;
3822 midi0 = status & HDSP_midi0IRQPending;
3823 midi1 = status & HDSP_midi1IRQPending;
3825 if (!audio && !midi0 && !midi1)
3828 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3830 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3831 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3833 if (!(hdsp->state & HDSP_InitializationComplete))
3837 if (hdsp->capture_substream)
3838 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3840 if (hdsp->playback_substream)
3841 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3844 if (midi0 && midi0status) {
3845 if (hdsp->use_midi_tasklet) {
3846 /* we disable interrupts for this input until processing is done */
3847 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3848 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3849 hdsp->midi[0].pending = 1;
3852 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3855 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3856 if (hdsp->use_midi_tasklet) {
3857 /* we disable interrupts for this input until processing is done */
3858 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3859 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3860 hdsp->midi[1].pending = 1;
3863 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3866 if (hdsp->use_midi_tasklet && schedule)
3867 tasklet_schedule(&hdsp->midi_tasklet);
3871 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3873 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3874 return hdsp_hw_pointer(hdsp);
3877 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3884 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3887 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3890 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3891 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3893 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3896 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3897 int channel, unsigned long pos,
3898 void __user *src, unsigned long count)
3900 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3903 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3906 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3907 if (snd_BUG_ON(!channel_buf))
3909 if (copy_from_user(channel_buf + pos, src, count))
3914 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3915 int channel, unsigned long pos,
3916 void *src, unsigned long count)
3918 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3921 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3922 if (snd_BUG_ON(!channel_buf))
3924 memcpy(channel_buf + pos, src, count);
3928 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3929 int channel, unsigned long pos,
3930 void __user *dst, unsigned long count)
3932 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3935 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3938 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3939 if (snd_BUG_ON(!channel_buf))
3941 if (copy_to_user(dst, channel_buf + pos, count))
3946 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
3947 int channel, unsigned long pos,
3948 void *dst, unsigned long count)
3950 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3953 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3954 if (snd_BUG_ON(!channel_buf))
3956 memcpy(dst, channel_buf + pos, count);
3960 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
3961 int channel, unsigned long pos,
3962 unsigned long count)
3964 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3967 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3968 if (snd_BUG_ON(!channel_buf))
3970 memset(channel_buf + pos, 0, count);
3974 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3976 struct snd_pcm_runtime *runtime = substream->runtime;
3977 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3978 struct snd_pcm_substream *other;
3979 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3980 other = hdsp->capture_substream;
3982 other = hdsp->playback_substream;
3984 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3986 runtime->status->hw_ptr = 0;
3988 struct snd_pcm_substream *s;
3989 struct snd_pcm_runtime *oruntime = other->runtime;
3990 snd_pcm_group_for_each_entry(s, substream) {
3992 oruntime->status->hw_ptr = runtime->status->hw_ptr;
4000 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4001 struct snd_pcm_hw_params *params)
4003 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4008 if (hdsp_check_for_iobox (hdsp))
4011 if (hdsp_check_for_firmware(hdsp, 1))
4014 spin_lock_irq(&hdsp->lock);
4016 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4017 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4018 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4019 this_pid = hdsp->playback_pid;
4020 other_pid = hdsp->capture_pid;
4022 this_pid = hdsp->capture_pid;
4023 other_pid = hdsp->playback_pid;
4026 if ((other_pid > 0) && (this_pid != other_pid)) {
4028 /* The other stream is open, and not by the same
4029 task as this one. Make sure that the parameters
4030 that matter are the same.
4033 if (params_rate(params) != hdsp->system_sample_rate) {
4034 spin_unlock_irq(&hdsp->lock);
4035 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4039 if (params_period_size(params) != hdsp->period_bytes / 4) {
4040 spin_unlock_irq(&hdsp->lock);
4041 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4047 spin_unlock_irq(&hdsp->lock);
4051 spin_unlock_irq(&hdsp->lock);
4054 /* how to make sure that the rate matches an externally-set one ?
4057 spin_lock_irq(&hdsp->lock);
4058 if (! hdsp->clock_source_locked) {
4059 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4060 spin_unlock_irq(&hdsp->lock);
4061 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4065 spin_unlock_irq(&hdsp->lock);
4067 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4068 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4075 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4076 struct snd_pcm_channel_info *info)
4078 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4079 unsigned int channel = info->channel;
4081 if (snd_BUG_ON(channel >= hdsp->max_channels))
4083 channel = array_index_nospec(channel, hdsp->max_channels);
4085 if (hdsp->channel_map[channel] < 0)
4088 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4094 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4095 unsigned int cmd, void *arg)
4098 case SNDRV_PCM_IOCTL1_RESET:
4099 return snd_hdsp_reset(substream);
4100 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4101 return snd_hdsp_channel_info(substream, arg);
4106 return snd_pcm_lib_ioctl(substream, cmd, arg);
4109 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4111 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4112 struct snd_pcm_substream *other;
4115 if (hdsp_check_for_iobox (hdsp))
4118 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4121 spin_lock(&hdsp->lock);
4122 running = hdsp->running;
4124 case SNDRV_PCM_TRIGGER_START:
4125 running |= 1 << substream->stream;
4127 case SNDRV_PCM_TRIGGER_STOP:
4128 running &= ~(1 << substream->stream);
4132 spin_unlock(&hdsp->lock);
4135 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4136 other = hdsp->capture_substream;
4138 other = hdsp->playback_substream;
4141 struct snd_pcm_substream *s;
4142 snd_pcm_group_for_each_entry(s, substream) {
4144 snd_pcm_trigger_done(s, substream);
4145 if (cmd == SNDRV_PCM_TRIGGER_START)
4146 running |= 1 << s->stream;
4148 running &= ~(1 << s->stream);
4152 if (cmd == SNDRV_PCM_TRIGGER_START) {
4153 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4154 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4155 hdsp_silence_playback(hdsp);
4158 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4159 hdsp_silence_playback(hdsp);
4162 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4163 hdsp_silence_playback(hdsp);
4166 snd_pcm_trigger_done(substream, substream);
4167 if (!hdsp->running && running)
4168 hdsp_start_audio(hdsp);
4169 else if (hdsp->running && !running)
4170 hdsp_stop_audio(hdsp);
4171 hdsp->running = running;
4172 spin_unlock(&hdsp->lock);
4177 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4179 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4182 if (hdsp_check_for_iobox (hdsp))
4185 if (hdsp_check_for_firmware(hdsp, 1))
4188 spin_lock_irq(&hdsp->lock);
4190 hdsp_reset_hw_pointer(hdsp);
4191 spin_unlock_irq(&hdsp->lock);
4195 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4197 .info = (SNDRV_PCM_INFO_MMAP |
4198 SNDRV_PCM_INFO_MMAP_VALID |
4199 SNDRV_PCM_INFO_NONINTERLEAVED |
4200 SNDRV_PCM_INFO_SYNC_START |
4201 SNDRV_PCM_INFO_DOUBLE),
4202 #ifdef SNDRV_BIG_ENDIAN
4203 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4205 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4207 .rates = (SNDRV_PCM_RATE_32000 |
4208 SNDRV_PCM_RATE_44100 |
4209 SNDRV_PCM_RATE_48000 |
4210 SNDRV_PCM_RATE_64000 |
4211 SNDRV_PCM_RATE_88200 |
4212 SNDRV_PCM_RATE_96000),
4216 .channels_max = HDSP_MAX_CHANNELS,
4217 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4218 .period_bytes_min = (64 * 4) * 10,
4219 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4225 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4227 .info = (SNDRV_PCM_INFO_MMAP |
4228 SNDRV_PCM_INFO_MMAP_VALID |
4229 SNDRV_PCM_INFO_NONINTERLEAVED |
4230 SNDRV_PCM_INFO_SYNC_START),
4231 #ifdef SNDRV_BIG_ENDIAN
4232 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4234 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4236 .rates = (SNDRV_PCM_RATE_32000 |
4237 SNDRV_PCM_RATE_44100 |
4238 SNDRV_PCM_RATE_48000 |
4239 SNDRV_PCM_RATE_64000 |
4240 SNDRV_PCM_RATE_88200 |
4241 SNDRV_PCM_RATE_96000),
4245 .channels_max = HDSP_MAX_CHANNELS,
4246 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4247 .period_bytes_min = (64 * 4) * 10,
4248 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4254 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4256 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4257 .count = ARRAY_SIZE(hdsp_period_sizes),
4258 .list = hdsp_period_sizes,
4262 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4264 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4265 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4266 .list = hdsp_9632_sample_rates,
4270 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4271 struct snd_pcm_hw_rule *rule)
4273 struct hdsp *hdsp = rule->private;
4274 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4275 if (hdsp->io_type == H9632) {
4276 unsigned int list[3];
4277 list[0] = hdsp->qs_in_channels;
4278 list[1] = hdsp->ds_in_channels;
4279 list[2] = hdsp->ss_in_channels;
4280 return snd_interval_list(c, 3, list, 0);
4282 unsigned int list[2];
4283 list[0] = hdsp->ds_in_channels;
4284 list[1] = hdsp->ss_in_channels;
4285 return snd_interval_list(c, 2, list, 0);
4289 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4290 struct snd_pcm_hw_rule *rule)
4292 unsigned int list[3];
4293 struct hdsp *hdsp = rule->private;
4294 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4295 if (hdsp->io_type == H9632) {
4296 list[0] = hdsp->qs_out_channels;
4297 list[1] = hdsp->ds_out_channels;
4298 list[2] = hdsp->ss_out_channels;
4299 return snd_interval_list(c, 3, list, 0);
4301 list[0] = hdsp->ds_out_channels;
4302 list[1] = hdsp->ss_out_channels;
4304 return snd_interval_list(c, 2, list, 0);
4307 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4308 struct snd_pcm_hw_rule *rule)
4310 struct hdsp *hdsp = rule->private;
4311 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4312 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4313 if (r->min > 96000 && hdsp->io_type == H9632) {
4314 struct snd_interval t = {
4315 .min = hdsp->qs_in_channels,
4316 .max = hdsp->qs_in_channels,
4319 return snd_interval_refine(c, &t);
4320 } else if (r->min > 48000 && r->max <= 96000) {
4321 struct snd_interval t = {
4322 .min = hdsp->ds_in_channels,
4323 .max = hdsp->ds_in_channels,
4326 return snd_interval_refine(c, &t);
4327 } else if (r->max < 64000) {
4328 struct snd_interval t = {
4329 .min = hdsp->ss_in_channels,
4330 .max = hdsp->ss_in_channels,
4333 return snd_interval_refine(c, &t);
4338 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4339 struct snd_pcm_hw_rule *rule)
4341 struct hdsp *hdsp = rule->private;
4342 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4343 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4344 if (r->min > 96000 && hdsp->io_type == H9632) {
4345 struct snd_interval t = {
4346 .min = hdsp->qs_out_channels,
4347 .max = hdsp->qs_out_channels,
4350 return snd_interval_refine(c, &t);
4351 } else if (r->min > 48000 && r->max <= 96000) {
4352 struct snd_interval t = {
4353 .min = hdsp->ds_out_channels,
4354 .max = hdsp->ds_out_channels,
4357 return snd_interval_refine(c, &t);
4358 } else if (r->max < 64000) {
4359 struct snd_interval t = {
4360 .min = hdsp->ss_out_channels,
4361 .max = hdsp->ss_out_channels,
4364 return snd_interval_refine(c, &t);
4369 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4370 struct snd_pcm_hw_rule *rule)
4372 struct hdsp *hdsp = rule->private;
4373 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4374 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4375 if (c->min >= hdsp->ss_out_channels) {
4376 struct snd_interval t = {
4381 return snd_interval_refine(r, &t);
4382 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4383 struct snd_interval t = {
4388 return snd_interval_refine(r, &t);
4389 } else if (c->max <= hdsp->ds_out_channels) {
4390 struct snd_interval t = {
4395 return snd_interval_refine(r, &t);
4400 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4401 struct snd_pcm_hw_rule *rule)
4403 struct hdsp *hdsp = rule->private;
4404 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4405 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4406 if (c->min >= hdsp->ss_in_channels) {
4407 struct snd_interval t = {
4412 return snd_interval_refine(r, &t);
4413 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4414 struct snd_interval t = {
4419 return snd_interval_refine(r, &t);
4420 } else if (c->max <= hdsp->ds_in_channels) {
4421 struct snd_interval t = {
4426 return snd_interval_refine(r, &t);
4431 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4433 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4434 struct snd_pcm_runtime *runtime = substream->runtime;
4436 if (hdsp_check_for_iobox (hdsp))
4439 if (hdsp_check_for_firmware(hdsp, 1))
4442 spin_lock_irq(&hdsp->lock);
4444 snd_pcm_set_sync(substream);
4446 runtime->hw = snd_hdsp_playback_subinfo;
4447 runtime->dma_area = hdsp->playback_buffer;
4448 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4450 hdsp->playback_pid = current->pid;
4451 hdsp->playback_substream = substream;
4453 spin_unlock_irq(&hdsp->lock);
4455 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4456 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4457 if (hdsp->clock_source_locked) {
4458 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4459 } else if (hdsp->io_type == H9632) {
4460 runtime->hw.rate_max = 192000;
4461 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4462 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4464 if (hdsp->io_type == H9632) {
4465 runtime->hw.channels_min = hdsp->qs_out_channels;
4466 runtime->hw.channels_max = hdsp->ss_out_channels;
4469 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4470 snd_hdsp_hw_rule_out_channels, hdsp,
4471 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4472 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4473 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4474 SNDRV_PCM_HW_PARAM_RATE, -1);
4475 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4476 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4477 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4479 if (RPM != hdsp->io_type) {
4480 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4481 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4482 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4483 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4488 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4490 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4492 spin_lock_irq(&hdsp->lock);
4494 hdsp->playback_pid = -1;
4495 hdsp->playback_substream = NULL;
4497 spin_unlock_irq(&hdsp->lock);
4499 if (RPM != hdsp->io_type) {
4500 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4501 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4502 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4508 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4510 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4511 struct snd_pcm_runtime *runtime = substream->runtime;
4513 if (hdsp_check_for_iobox (hdsp))
4516 if (hdsp_check_for_firmware(hdsp, 1))
4519 spin_lock_irq(&hdsp->lock);
4521 snd_pcm_set_sync(substream);
4523 runtime->hw = snd_hdsp_capture_subinfo;
4524 runtime->dma_area = hdsp->capture_buffer;
4525 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4527 hdsp->capture_pid = current->pid;
4528 hdsp->capture_substream = substream;
4530 spin_unlock_irq(&hdsp->lock);
4532 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4533 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4534 if (hdsp->io_type == H9632) {
4535 runtime->hw.channels_min = hdsp->qs_in_channels;
4536 runtime->hw.channels_max = hdsp->ss_in_channels;
4537 runtime->hw.rate_max = 192000;
4538 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4539 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4541 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4542 snd_hdsp_hw_rule_in_channels, hdsp,
4543 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4544 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4545 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4546 SNDRV_PCM_HW_PARAM_RATE, -1);
4547 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4548 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4549 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4553 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4555 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4557 spin_lock_irq(&hdsp->lock);
4559 hdsp->capture_pid = -1;
4560 hdsp->capture_substream = NULL;
4562 spin_unlock_irq(&hdsp->lock);
4566 /* helper functions for copying meter values */
4567 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4569 u32 val = readl(src);
4570 return copy_to_user(dest, &val, 4);
4573 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4575 u32 rms_low, rms_high;
4577 rms_low = readl(src_low);
4578 rms_high = readl(src_high);
4579 rms = ((u64)rms_high << 32) | rms_low;
4580 return copy_to_user(dest, &rms, 8);
4583 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4585 u32 rms_low, rms_high;
4587 rms_low = readl(src_low) & 0xffffff00;
4588 rms_high = readl(src_high) & 0xffffff00;
4589 rms = ((u64)rms_high << 32) | rms_low;
4590 return copy_to_user(dest, &rms, 8);
4593 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4595 int doublespeed = 0;
4596 int i, j, channels, ofs;
4598 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4600 channels = doublespeed ? 14 : 26;
4601 for (i = 0, j = 0; i < 26; ++i) {
4602 if (doublespeed && (i & 4))
4604 ofs = HDSP_9652_peakBase - j * 4;
4605 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4607 ofs -= channels * 4;
4608 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4610 ofs -= channels * 4;
4611 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4613 ofs = HDSP_9652_rmsBase + j * 8;
4614 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4615 hdsp->iobase + ofs + 4))
4617 ofs += channels * 8;
4618 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4619 hdsp->iobase + ofs + 4))
4621 ofs += channels * 8;
4622 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4623 hdsp->iobase + ofs + 4))
4630 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4633 struct hdsp_9632_meters __iomem *m;
4634 int doublespeed = 0;
4636 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4638 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4639 for (i = 0, j = 0; i < 16; ++i, ++j) {
4640 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4642 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4644 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4646 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4647 &m->input_rms_high[j]))
4649 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4650 &m->playback_rms_high[j]))
4652 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4653 &m->output_rms_high[j]))
4655 if (doublespeed && i == 3) i += 4;
4660 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4664 for (i = 0; i < 26; i++) {
4665 if (copy_u32_le(&peak_rms->playback_peaks[i],
4666 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4668 if (copy_u32_le(&peak_rms->input_peaks[i],
4669 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4672 for (i = 0; i < 28; i++) {
4673 if (copy_u32_le(&peak_rms->output_peaks[i],
4674 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4677 for (i = 0; i < 26; ++i) {
4678 if (copy_u64_le(&peak_rms->playback_rms[i],
4679 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4680 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4682 if (copy_u64_le(&peak_rms->input_rms[i],
4683 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4684 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4690 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4692 struct hdsp *hdsp = hw->private_data;
4693 void __user *argp = (void __user *)arg;
4697 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4698 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4700 err = hdsp_check_for_iobox(hdsp);
4704 err = hdsp_check_for_firmware(hdsp, 1);
4708 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4709 dev_err(hdsp->card->dev,
4710 "firmware needs to be uploaded to the card.\n");
4714 switch (hdsp->io_type) {
4716 return hdsp_9652_get_peak(hdsp, peak_rms);
4718 return hdsp_9632_get_peak(hdsp, peak_rms);
4720 return hdsp_get_peak(hdsp, peak_rms);
4723 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4724 struct hdsp_config_info info;
4725 unsigned long flags;
4728 err = hdsp_check_for_iobox(hdsp);
4732 err = hdsp_check_for_firmware(hdsp, 1);
4736 memset(&info, 0, sizeof(info));
4737 spin_lock_irqsave(&hdsp->lock, flags);
4738 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4739 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4740 if (hdsp->io_type != H9632)
4741 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4742 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4743 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4744 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4745 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4746 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4747 HDSP_SPDIFOpticalOut);
4748 info.spdif_professional = (unsigned char)
4749 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4750 info.spdif_emphasis = (unsigned char)
4751 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4752 info.spdif_nonaudio = (unsigned char)
4753 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4754 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4755 info.system_sample_rate = hdsp->system_sample_rate;
4756 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4757 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4758 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4759 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4760 info.line_out = (unsigned char)
4761 hdsp_toggle_setting(hdsp, HDSP_LineOut);
4762 if (hdsp->io_type == H9632) {
4763 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4764 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4765 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4766 info.xlr_breakout_cable =
4767 (unsigned char)hdsp_toggle_setting(hdsp,
4768 HDSP_XLRBreakoutCable);
4770 } else if (hdsp->io_type == RPM) {
4771 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4772 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4774 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4775 info.analog_extension_board =
4776 (unsigned char)hdsp_toggle_setting(hdsp,
4777 HDSP_AnalogExtensionBoard);
4778 spin_unlock_irqrestore(&hdsp->lock, flags);
4779 if (copy_to_user(argp, &info, sizeof(info)))
4783 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4784 struct hdsp_9632_aeb h9632_aeb;
4786 if (hdsp->io_type != H9632) return -EINVAL;
4787 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4788 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4789 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4793 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4794 struct hdsp_version hdsp_version;
4797 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4798 if (hdsp->io_type == Undefined) {
4799 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4802 memset(&hdsp_version, 0, sizeof(hdsp_version));
4803 hdsp_version.io_type = hdsp->io_type;
4804 hdsp_version.firmware_rev = hdsp->firmware_rev;
4805 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4809 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4810 struct hdsp_firmware __user *firmware;
4811 u32 __user *firmware_data;
4814 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4815 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4816 if (hdsp->io_type == Undefined) return -EINVAL;
4818 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4821 dev_info(hdsp->card->dev,
4822 "initializing firmware upload\n");
4823 firmware = (struct hdsp_firmware __user *)argp;
4825 if (get_user(firmware_data, &firmware->firmware_data))
4828 if (hdsp_check_for_iobox (hdsp))
4831 if (!hdsp->fw_uploaded) {
4832 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4833 if (!hdsp->fw_uploaded)
4837 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4838 HDSP_FIRMWARE_SIZE)) {
4839 vfree(hdsp->fw_uploaded);
4840 hdsp->fw_uploaded = NULL;
4844 hdsp->state |= HDSP_FirmwareCached;
4846 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4849 if (!(hdsp->state & HDSP_InitializationComplete)) {
4850 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4853 snd_hdsp_initialize_channels(hdsp);
4854 snd_hdsp_initialize_midi_flush(hdsp);
4856 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4857 dev_err(hdsp->card->dev,
4858 "error creating alsa devices\n");
4864 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4865 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4866 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4876 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4877 .open = snd_hdsp_playback_open,
4878 .close = snd_hdsp_playback_release,
4879 .ioctl = snd_hdsp_ioctl,
4880 .hw_params = snd_hdsp_hw_params,
4881 .prepare = snd_hdsp_prepare,
4882 .trigger = snd_hdsp_trigger,
4883 .pointer = snd_hdsp_hw_pointer,
4884 .copy_user = snd_hdsp_playback_copy,
4885 .copy_kernel = snd_hdsp_playback_copy_kernel,
4886 .fill_silence = snd_hdsp_hw_silence,
4889 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4890 .open = snd_hdsp_capture_open,
4891 .close = snd_hdsp_capture_release,
4892 .ioctl = snd_hdsp_ioctl,
4893 .hw_params = snd_hdsp_hw_params,
4894 .prepare = snd_hdsp_prepare,
4895 .trigger = snd_hdsp_trigger,
4896 .pointer = snd_hdsp_hw_pointer,
4897 .copy_user = snd_hdsp_capture_copy,
4898 .copy_kernel = snd_hdsp_capture_copy_kernel,
4901 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4903 struct snd_hwdep *hw;
4906 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4910 hw->private_data = hdsp;
4911 strcpy(hw->name, "HDSP hwdep interface");
4913 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4914 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4919 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4921 struct snd_pcm *pcm;
4924 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4928 pcm->private_data = hdsp;
4929 strcpy(pcm->name, hdsp->card_name);
4931 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4932 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4934 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4939 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4941 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4942 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4945 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4949 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4950 dev_err(hdsp->card->dev,
4951 "enable_io fifo_wait failed\n");
4955 for (i = 0; i < hdsp->max_channels; ++i) {
4956 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4957 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4963 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4965 int status, aebi_channels, aebo_channels;
4967 switch (hdsp->io_type) {
4969 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4970 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4971 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4975 hdsp->card_name = "RME Hammerfall HDSP 9652";
4976 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4977 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4981 status = hdsp_read(hdsp, HDSP_statusRegister);
4982 /* HDSP_AEBx bits are low when AEB are connected */
4983 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4984 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4985 hdsp->card_name = "RME Hammerfall HDSP 9632";
4986 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4987 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4988 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4989 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4990 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4991 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4995 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4996 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4997 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5001 hdsp->card_name = "RME Hammerfall DSP + RPM";
5002 hdsp->ss_in_channels = RPM_CHANNELS-1;
5003 hdsp->ss_out_channels = RPM_CHANNELS;
5004 hdsp->ds_in_channels = RPM_CHANNELS-1;
5005 hdsp->ds_out_channels = RPM_CHANNELS;
5009 /* should never get here */
5014 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5016 snd_hdsp_flush_midi_input (hdsp, 0);
5017 snd_hdsp_flush_midi_input (hdsp, 1);
5020 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5024 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5026 "Error creating pcm interface\n");
5031 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5033 "Error creating first midi interface\n");
5037 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5038 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5040 "Error creating second midi interface\n");
5045 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5047 "Error creating ctl interface\n");
5051 snd_hdsp_proc_init(hdsp);
5053 hdsp->system_sample_rate = -1;
5054 hdsp->playback_pid = -1;
5055 hdsp->capture_pid = -1;
5056 hdsp->capture_substream = NULL;
5057 hdsp->playback_substream = NULL;
5059 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5061 "Error setting default values\n");
5065 if (!(hdsp->state & HDSP_InitializationComplete)) {
5066 strcpy(card->shortname, "Hammerfall DSP");
5067 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5068 hdsp->port, hdsp->irq);
5070 if ((err = snd_card_register(card)) < 0) {
5072 "error registering card\n");
5075 hdsp->state |= HDSP_InitializationComplete;
5081 /* load firmware via hotplug fw loader */
5082 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5085 const struct firmware *fw;
5088 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5090 if (hdsp->io_type == Undefined) {
5091 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5093 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5097 /* caution: max length of firmware filename is 30! */
5098 switch (hdsp->io_type) {
5100 fwfile = "rpm_firmware.bin";
5103 if (hdsp->firmware_rev == 0xa)
5104 fwfile = "multiface_firmware.bin";
5106 fwfile = "multiface_firmware_rev11.bin";
5109 if (hdsp->firmware_rev == 0xa)
5110 fwfile = "digiface_firmware.bin";
5112 fwfile = "digiface_firmware_rev11.bin";
5115 dev_err(hdsp->card->dev,
5116 "invalid io_type %d\n", hdsp->io_type);
5120 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5121 dev_err(hdsp->card->dev,
5122 "cannot load firmware %s\n", fwfile);
5125 if (fw->size < HDSP_FIRMWARE_SIZE) {
5126 dev_err(hdsp->card->dev,
5127 "too short firmware size %d (expected %d)\n",
5128 (int)fw->size, HDSP_FIRMWARE_SIZE);
5129 release_firmware(fw);
5133 hdsp->firmware = fw;
5135 hdsp->state |= HDSP_FirmwareCached;
5137 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5140 if (!(hdsp->state & HDSP_InitializationComplete)) {
5141 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5144 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5145 dev_err(hdsp->card->dev,
5146 "error creating hwdep device\n");
5149 snd_hdsp_initialize_channels(hdsp);
5150 snd_hdsp_initialize_midi_flush(hdsp);
5151 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5152 dev_err(hdsp->card->dev,
5153 "error creating alsa devices\n");
5160 static int snd_hdsp_create(struct snd_card *card,
5163 struct pci_dev *pci = hdsp->pci;
5170 hdsp->midi[0].rmidi = NULL;
5171 hdsp->midi[1].rmidi = NULL;
5172 hdsp->midi[0].input = NULL;
5173 hdsp->midi[1].input = NULL;
5174 hdsp->midi[0].output = NULL;
5175 hdsp->midi[1].output = NULL;
5176 hdsp->midi[0].pending = 0;
5177 hdsp->midi[1].pending = 0;
5178 spin_lock_init(&hdsp->midi[0].lock);
5179 spin_lock_init(&hdsp->midi[1].lock);
5180 hdsp->iobase = NULL;
5181 hdsp->control_register = 0;
5182 hdsp->control2_register = 0;
5183 hdsp->io_type = Undefined;
5184 hdsp->max_channels = 26;
5188 spin_lock_init(&hdsp->lock);
5190 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5192 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5193 hdsp->firmware_rev &= 0xff;
5195 /* From Martin Bjoernsen :
5196 "It is important that the card's latency timer register in
5197 the PCI configuration space is set to a value much larger
5198 than 0 by the computer's BIOS or the driver.
5199 The windows driver always sets this 8 bit register [...]
5200 to its maximum 255 to avoid problems with some computers."
5202 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5204 strcpy(card->driver, "H-DSP");
5205 strcpy(card->mixername, "Xilinx FPGA");
5207 if (hdsp->firmware_rev < 0xa)
5209 else if (hdsp->firmware_rev < 0x64)
5210 hdsp->card_name = "RME Hammerfall DSP";
5211 else if (hdsp->firmware_rev < 0x96) {
5212 hdsp->card_name = "RME HDSP 9652";
5215 hdsp->card_name = "RME HDSP 9632";
5216 hdsp->max_channels = 16;
5220 if ((err = pci_enable_device(pci)) < 0)
5223 pci_set_master(hdsp->pci);
5225 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5227 hdsp->port = pci_resource_start(pci, 0);
5228 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5229 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5230 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5234 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5235 KBUILD_MODNAME, hdsp)) {
5236 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5240 hdsp->irq = pci->irq;
5241 hdsp->precise_ptr = 0;
5242 hdsp->use_midi_tasklet = 1;
5243 hdsp->dds_value = 0;
5245 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5248 if (!is_9652 && !is_9632) {
5249 /* we wait a maximum of 10 seconds to let freshly
5250 * inserted cardbus cards do their hardware init */
5251 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5256 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5257 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5258 /* we don't fail as this can happen
5259 if userspace is not ready for
5262 dev_err(hdsp->card->dev,
5263 "couldn't get firmware from userspace. try using hdsploader\n");
5265 /* init is complete, we return */
5267 /* we defer initialization */
5268 dev_info(hdsp->card->dev,
5269 "card initialization pending : waiting for firmware\n");
5270 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5274 dev_info(hdsp->card->dev,
5275 "Firmware already present, initializing card.\n");
5276 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5277 hdsp->io_type = RPM;
5278 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5279 hdsp->io_type = Multiface;
5281 hdsp->io_type = Digiface;
5285 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5289 hdsp->io_type = H9652;
5292 hdsp->io_type = H9632;
5294 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5297 snd_hdsp_initialize_channels(hdsp);
5298 snd_hdsp_initialize_midi_flush(hdsp);
5300 hdsp->state |= HDSP_FirmwareLoaded;
5302 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5308 static int snd_hdsp_free(struct hdsp *hdsp)
5311 /* stop the audio, and cancel all interrupts */
5312 tasklet_kill(&hdsp->midi_tasklet);
5313 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5314 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5318 free_irq(hdsp->irq, (void *)hdsp);
5320 snd_hdsp_free_buffers(hdsp);
5322 release_firmware(hdsp->firmware);
5323 vfree(hdsp->fw_uploaded);
5324 iounmap(hdsp->iobase);
5327 pci_release_regions(hdsp->pci);
5329 pci_disable_device(hdsp->pci);
5333 static void snd_hdsp_card_free(struct snd_card *card)
5335 struct hdsp *hdsp = card->private_data;
5338 snd_hdsp_free(hdsp);
5341 static int snd_hdsp_probe(struct pci_dev *pci,
5342 const struct pci_device_id *pci_id)
5346 struct snd_card *card;
5349 if (dev >= SNDRV_CARDS)
5356 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5357 sizeof(struct hdsp), &card);
5361 hdsp = card->private_data;
5362 card->private_free = snd_hdsp_card_free;
5365 err = snd_hdsp_create(card, hdsp);
5369 strcpy(card->shortname, "Hammerfall DSP");
5370 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5371 hdsp->port, hdsp->irq);
5372 err = snd_card_register(card);
5375 snd_card_free(card);
5378 pci_set_drvdata(pci, card);
5383 static void snd_hdsp_remove(struct pci_dev *pci)
5385 snd_card_free(pci_get_drvdata(pci));
5388 static struct pci_driver hdsp_driver = {
5389 .name = KBUILD_MODNAME,
5390 .id_table = snd_hdsp_ids,
5391 .probe = snd_hdsp_probe,
5392 .remove = snd_hdsp_remove,
5395 module_pci_driver(hdsp_driver);