sound/pci/lx6464es/lx_core.c

   1 /* -*- linux-c -*- *
   2  *
   3  * ALSA driver for the digigram lx6464es interface
   4  * low-level interface
   5  *
   6  * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; see the file COPYING.  If not, write to
  20  * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  21  * Boston, MA 02111-1307, USA.
  22  *
  23  */
  24
  25 /* #define RMH_DEBUG 1 */
  26
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30
  31 #include "lx6464es.h"
  32 #include "lx_core.h"
  33
  34 /* low-level register access */
  35
  36 static const unsigned long dsp_port_offsets[] = {
  37         0,
  38         0x400,
  39         0x401,
  40         0x402,
  41         0x403,
  42         0x404,
  43         0x405,
  44         0x406,
  45         0x407,
  46         0x408,
  47         0x409,
  48         0x40a,
  49         0x40b,
  50         0x40c,
  51
  52         0x410,
  53         0x411,
  54         0x412,
  55         0x413,
  56         0x414,
  57         0x415,
  58         0x416,
  59
  60         0x420,
  61         0x430,
  62         0x431,
  63         0x432,
  64         0x433,
  65         0x434,
  66         0x440
  67 };
  68
  69 static void __iomem *lx_dsp_register(struct lx6464es *chip, int port)
  70 {
  71         void __iomem *base_address = chip->port_dsp_bar;
  72         return base_address + dsp_port_offsets[port]*4;
  73 }
  74
  75 unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port)
  76 {
  77         void __iomem *address = lx_dsp_register(chip, port);
  78         return ioread32(address);
  79 }
  80
  81 void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data, u32 len)
  82 {
  83         void __iomem *address = lx_dsp_register(chip, port);
  84         memcpy_fromio(data, address, len*sizeof(u32));
  85 }
  86
  87
  88 void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data)
  89 {
  90         void __iomem *address = lx_dsp_register(chip, port);
  91         iowrite32(data, address);
  92 }
  93
  94 void lx_dsp_reg_writebuf(struct lx6464es *chip, int port, const u32 *data,
  95                          u32 len)
  96 {
  97         void __iomem *address = lx_dsp_register(chip, port);
  98         memcpy_toio(address, data, len*sizeof(u32));
  99 }
 100
 101
 102 static const unsigned long plx_port_offsets[] = {
 103         0x04,
 104         0x40,
 105         0x44,
 106         0x48,
 107         0x4c,
 108         0x50,
 109         0x54,
 110         0x58,
 111         0x5c,
 112         0x64,
 113         0x68,
 114         0x6C
 115 };
 116
 117 static void __iomem *lx_plx_register(struct lx6464es *chip, int port)
 118 {
 119         void __iomem *base_address = chip->port_plx_remapped;
 120         return base_address + plx_port_offsets[port];
 121 }
 122
 123 unsigned long lx_plx_reg_read(struct lx6464es *chip, int port)
 124 {
 125         void __iomem *address = lx_plx_register(chip, port);
 126         return ioread32(address);
 127 }
 128
 129 void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data)
 130 {
 131         void __iomem *address = lx_plx_register(chip, port);
 132         iowrite32(data, address);
 133 }
 134
 135 u32 lx_plx_mbox_read(struct lx6464es *chip, int mbox_nr)
 136 {
 137         int index;
 138
 139         switch (mbox_nr) {
 140         case 1:
 141                 index = ePLX_MBOX1;    break;
 142         case 2:
 143                 index = ePLX_MBOX2;    break;
 144         case 3:
 145                 index = ePLX_MBOX3;    break;
 146         case 4:
 147                 index = ePLX_MBOX4;    break;
 148         case 5:
 149                 index = ePLX_MBOX5;    break;
 150         case 6:
 151                 index = ePLX_MBOX6;    break;
 152         case 7:
 153                 index = ePLX_MBOX7;    break;
 154         case 0:                 /* reserved for HF flags */
 155                 snd_BUG();
 156         default:
 157                 return 0xdeadbeef;
 158         }
 159
 160         return lx_plx_reg_read(chip, index);
 161 }
 162
 163 int lx_plx_mbox_write(struct lx6464es *chip, int mbox_nr, u32 value)
 164 {
 165         int index = -1;
 166
 167         switch (mbox_nr) {
 168         case 1:
 169                 index = ePLX_MBOX1;    break;
 170         case 3:
 171                 index = ePLX_MBOX3;    break;
 172         case 4:
 173                 index = ePLX_MBOX4;    break;
 174         case 5:
 175                 index = ePLX_MBOX5;    break;
 176         case 6:
 177                 index = ePLX_MBOX6;    break;
 178         case 7:
 179                 index = ePLX_MBOX7;    break;
 180         case 0:                 /* reserved for HF flags */
 181         case 2:                 /* reserved for Pipe States
 182                                  * the DSP keeps an image of it */
 183                 snd_BUG();
 184                 return -EBADRQC;
 185         }
 186
 187         lx_plx_reg_write(chip, index, value);
 188         return 0;
 189 }
 190
 191
 192 /* rmh */
 193
 194 #ifdef CONFIG_SND_DEBUG
 195 #define CMD_NAME(a) a
 196 #else
 197 #define CMD_NAME(a) NULL
 198 #endif
 199
 200 #define Reg_CSM_MR                      0x00000002
 201 #define Reg_CSM_MC                      0x00000001
 202
 203 struct dsp_cmd_info {
 204         u32    dcCodeOp;        /* Op Code of the command (usually 1st 24-bits
 205                                  * word).*/
 206         u16    dcCmdLength;     /* Command length in words of 24 bits.*/
 207         u16    dcStatusType;    /* Status type: 0 for fixed length, 1 for
 208                                  * random. */
 209         u16    dcStatusLength;  /* Status length (if fixed).*/
 210         char  *dcOpName;
 211 };
 212
 213 /*
 214   Initialization and control data for the Microblaze interface
 215   - OpCode:
 216     the opcode field of the command set at the proper offset
 217   - CmdLength
 218     the number of command words
 219   - StatusType
 220     offset in the status registers: 0 means that the return value may be
 221     different from 0, and must be read
 222   - StatusLength
 223     the number of status words (in addition to the return value)
 224 */
 225
 226 static struct dsp_cmd_info dsp_commands[] =
 227 {
 228         { (CMD_00_INFO_DEBUG << OPCODE_OFFSET)                  , 1 /*custom*/
 229           , 1   , 0 /**/                    , CMD_NAME("INFO_DEBUG") },
 230         { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET)                 , 1 /**/
 231           , 1      , 2 /**/                 , CMD_NAME("GET_SYS_CFG") },
 232         { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET)             , 1 /**/
 233           , 1      , 0 /**/                 , CMD_NAME("SET_GRANULARITY") },
 234         { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET)               , 1 /**/
 235           , 1      , 0 /**/                 , CMD_NAME("SET_TIMER_IRQ") },
 236         { (CMD_04_GET_EVENT << OPCODE_OFFSET)                   , 1 /**/
 237           , 1      , 0 /*up to 10*/     , CMD_NAME("GET_EVENT") },
 238         { (CMD_05_GET_PIPES << OPCODE_OFFSET)                   , 1 /**/
 239           , 1      , 2 /*up to 4*/      , CMD_NAME("GET_PIPES") },
 240         { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET)               , 1 /**/
 241           , 0      , 0 /**/                 , CMD_NAME("ALLOCATE_PIPE") },
 242         { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET)                , 1 /**/
 243           , 0      , 0 /**/                 , CMD_NAME("RELEASE_PIPE") },
 244         { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET)                 , 1 /**/
 245           , 1      , MAX_STREAM_BUFFER  , CMD_NAME("ASK_BUFFERS") },
 246         { (CMD_09_STOP_PIPE << OPCODE_OFFSET)                   , 1 /**/
 247           , 0      , 0 /*up to 2*/      , CMD_NAME("STOP_PIPE") },
 248         { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET)          , 1 /**/
 249           , 1      , 1 /*up to 2*/      , CMD_NAME("GET_PIPE_SPL_COUNT") },
 250         { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET)           , 1 /*up to 5*/
 251           , 1      , 0 /**/                 , CMD_NAME("TOGGLE_PIPE_STATE") },
 252         { (CMD_0C_DEF_STREAM << OPCODE_OFFSET)                  , 1 /*up to 4*/
 253           , 1      , 0 /**/                 , CMD_NAME("DEF_STREAM") },
 254         { (CMD_0D_SET_MUTE  << OPCODE_OFFSET)                   , 3 /**/
 255           , 1      , 0 /**/                 , CMD_NAME("SET_MUTE") },
 256         { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET)        , 1/**/
 257           , 1      , 2 /**/                 , CMD_NAME("GET_STREAM_SPL_COUNT") },
 258         { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET)               , 3 /*up to 4*/
 259           , 0      , 1 /**/                 , CMD_NAME("UPDATE_BUFFER") },
 260         { (CMD_10_GET_BUFFER << OPCODE_OFFSET)                  , 1 /**/
 261           , 1      , 4 /**/                 , CMD_NAME("GET_BUFFER") },
 262         { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET)               , 1 /**/
 263           , 1      , 1 /*up to 4*/      , CMD_NAME("CANCEL_BUFFER") },
 264         { (CMD_12_GET_PEAK << OPCODE_OFFSET)                    , 1 /**/
 265           , 1      , 1 /**/                 , CMD_NAME("GET_PEAK") },
 266         { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET)            , 1 /**/
 267           , 1      , 0 /**/                 , CMD_NAME("SET_STREAM_STATE") },
 268 };
 269
 270 static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd)
 271 {
 272         snd_BUG_ON(cmd >= CMD_14_INVALID);
 273
 274         rmh->cmd[0] = dsp_commands[cmd].dcCodeOp;
 275         rmh->cmd_len = dsp_commands[cmd].dcCmdLength;
 276         rmh->stat_len = dsp_commands[cmd].dcStatusLength;
 277         rmh->dsp_stat = dsp_commands[cmd].dcStatusType;
 278         rmh->cmd_idx = cmd;
 279         memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32));
 280
 281 #ifdef CONFIG_SND_DEBUG
 282         memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32));
 283 #endif
 284 #ifdef RMH_DEBUG
 285         rmh->cmd_idx = cmd;
 286 #endif
 287 }
 288
 289 #ifdef RMH_DEBUG
 290 #define LXRMH "lx6464es rmh: "
 291 static void lx_message_dump(struct lx_rmh *rmh)
 292 {
 293         u8 idx = rmh->cmd_idx;
 294         int i;
 295
 296         snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName);
 297
 298         for (i = 0; i != rmh->cmd_len; ++i)
 299                 snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]);
 300
 301         for (i = 0; i != rmh->stat_len; ++i)
 302                 snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]);
 303         snd_printk("\n");
 304 }
 305 #else
 306 static inline void lx_message_dump(struct lx_rmh *rmh)
 307 {}
 308 #endif
 309
 310
 311
 312 /* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */
 313 #define XILINX_TIMEOUT_MS       40
 314 #define XILINX_POLL_NO_SLEEP    100
 315 #define XILINX_POLL_ITERATIONS  150
 316
 317 static int lx_message_send(struct lx6464es *chip, struct lx_rmh *rmh)
 318 {
 319         u32 reg = ED_DSP_TIMED_OUT;
 320         int dwloop;
 321         int answer_received;
 322
 323         if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) {
 324                 snd_printk(KERN_ERR LXP "PIOSendMessage eReg_CSM %x\n", reg);
 325                 return -EBUSY;
 326         }
 327
 328         /* write command */
 329         lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len);
 330
 331         snd_BUG_ON(atomic_read(&chip->send_message_locked) != 0);
 332         atomic_set(&chip->send_message_locked, 1);
 333
 334         /* MicoBlaze gogogo */
 335         lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC);
 336
 337         /* wait for interrupt to answer */
 338         for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS; ++dwloop) {
 339                 answer_received = atomic_read(&chip->send_message_locked);
 340                 if (answer_received == 0)
 341                         break;
 342                 msleep(1);
 343         }
 344
 345         if (answer_received == 0) {
 346                 /* in Debug mode verify Reg_CSM_MR */
 347                 snd_BUG_ON(!(lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR));
 348
 349                 /* command finished, read status */
 350                 if (rmh->dsp_stat == 0)
 351                         reg = lx_dsp_reg_read(chip, eReg_CRM1);
 352                 else
 353                         reg = 0;
 354         } else {
 355                 int i;
 356                 snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send! "
 357                            "Interrupts disabled?\n");
 358
 359                 /* attente bit Reg_CSM_MR */
 360                 for (i = 0; i != XILINX_POLL_ITERATIONS; i++) {
 361                         if ((lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR)) {
 362                                 if (rmh->dsp_stat == 0)
 363                                         reg = lx_dsp_reg_read(chip, eReg_CRM1);
 364                                 else
 365                                         reg = 0;
 366                                 goto polling_successful;
 367                         }
 368
 369                         if (i > XILINX_POLL_NO_SLEEP)
 370                                 msleep(1);
 371                 }
 372                 snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send! "
 373                            "polling failed\n");
 374
 375 polling_successful:
 376                 atomic_set(&chip->send_message_locked, 0);
 377         }
 378
 379         if ((reg & ERROR_VALUE) == 0) {
 380                 /* read response */
 381                 if (rmh->stat_len) {
 382                         snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1));
 383
 384                         lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat,
 385                                            rmh->stat_len);
 386                 }
 387         } else
 388                 snd_printk(KERN_WARNING LXP "lx_message_send: error_value %x\n",
 389                            reg);
 390
 391         /* clear Reg_CSM_MR */
 392         lx_dsp_reg_write(chip, eReg_CSM, 0);
 393
 394         switch (reg) {
 395         case ED_DSP_TIMED_OUT:
 396                 snd_printk(KERN_WARNING LXP "lx_message_send: dsp timeout\n");
 397                 return -ETIMEDOUT;
 398
 399         case ED_DSP_CRASHED:
 400                 snd_printk(KERN_WARNING LXP "lx_message_send: dsp crashed\n");
 401                 return -EAGAIN;
 402         }
 403
 404         lx_message_dump(rmh);
 405         return 0;
 406 }
 407
 408 static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh)
 409 {
 410         u32 reg = ED_DSP_TIMED_OUT;
 411         int dwloop;
 412
 413         if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) {
 414                 snd_printk(KERN_ERR LXP "PIOSendMessage eReg_CSM %x\n", reg);
 415                 return -EBUSY;
 416         }
 417
 418         /* write command */
 419         lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len);
 420
 421         /* MicoBlaze gogogo */
 422         lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC);
 423
 424         /* wait for interrupt to answer */
 425         for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) {
 426                 if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) {
 427                         if (rmh->dsp_stat == 0)
 428                                 reg = lx_dsp_reg_read(chip, eReg_CRM1);
 429                         else
 430                                 reg = 0;
 431                         goto polling_successful;
 432                 } else
 433                         udelay(1);
 434         }
 435         snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send_atomic! "
 436                    "polling failed\n");
 437
 438 polling_successful:
 439         if ((reg & ERROR_VALUE) == 0) {
 440                 /* read response */
 441                 if (rmh->stat_len) {
 442                         snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1));
 443                         lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat,
 444                                            rmh->stat_len);
 445                 }
 446         } else
 447                 snd_printk(LXP "rmh error: %08x\n", reg);
 448
 449         /* clear Reg_CSM_MR */
 450         lx_dsp_reg_write(chip, eReg_CSM, 0);
 451
 452         switch (reg) {
 453         case ED_DSP_TIMED_OUT:
 454                 snd_printk(KERN_WARNING LXP "lx_message_send: dsp timeout\n");
 455                 return -ETIMEDOUT;
 456
 457         case ED_DSP_CRASHED:
 458                 snd_printk(KERN_WARNING LXP "lx_message_send: dsp crashed\n");
 459                 return -EAGAIN;
 460         }
 461
 462         lx_message_dump(rmh);
 463
 464         return reg;
 465 }
 466
 467
 468 /* low-level dsp access */
 469 int __devinit lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version)
 470 {
 471         u16 ret;
 472         unsigned long flags;
 473
 474         spin_lock_irqsave(&chip->msg_lock, flags);
 475
 476         lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
 477         ret = lx_message_send_atomic(chip, &chip->rmh);
 478
 479         *rdsp_version = chip->rmh.stat[1];
 480         spin_unlock_irqrestore(&chip->msg_lock, flags);
 481         return ret;
 482 }
 483
 484 int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq)
 485 {
 486         u16 ret = 0;
 487         unsigned long flags;
 488         u32 freq_raw = 0;
 489         u32 freq = 0;
 490         u32 frequency = 0;
 491
 492         spin_lock_irqsave(&chip->msg_lock, flags);
 493
 494         lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
 495         ret = lx_message_send_atomic(chip, &chip->rmh);
 496
 497         if (ret == 0) {
 498                 freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET;
 499                 freq = freq_raw & XES_FREQ_COUNT8_MASK;
 500
 501                 if ((freq < XES_FREQ_COUNT8_48_MAX) ||
 502                     (freq > XES_FREQ_COUNT8_44_MIN))
 503                         frequency = 0; /* unknown */
 504                 else if (freq >= XES_FREQ_COUNT8_44_MAX)
 505                         frequency = 44100;
 506                 else
 507                         frequency = 48000;
 508         }
 509
 510         spin_unlock_irqrestore(&chip->msg_lock, flags);
 511
 512         *rfreq = frequency * chip->freq_ratio;
 513
 514         return ret;
 515 }
 516
 517 int lx_dsp_get_mac(struct lx6464es *chip, u8 *mac_address)
 518 {
 519         u32 macmsb, maclsb;
 520
 521         macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF;
 522         maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF;
 523
 524         /* todo: endianess handling */
 525         mac_address[5] = ((u8 *)(&maclsb))[0];
 526         mac_address[4] = ((u8 *)(&maclsb))[1];
 527         mac_address[3] = ((u8 *)(&maclsb))[2];
 528         mac_address[2] = ((u8 *)(&macmsb))[0];
 529         mac_address[1] = ((u8 *)(&macmsb))[1];
 530         mac_address[0] = ((u8 *)(&macmsb))[2];
 531
 532         return 0;
 533 }
 534
 535
 536 int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran)
 537 {
 538         unsigned long flags;
 539         int ret;
 540
 541         spin_lock_irqsave(&chip->msg_lock, flags);
 542
 543         lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY);
 544         chip->rmh.cmd[0] |= gran;
 545
 546         ret = lx_message_send_atomic(chip, &chip->rmh);
 547         spin_unlock_irqrestore(&chip->msg_lock, flags);
 548         return ret;
 549 }
 550
 551 int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data)
 552 {
 553         unsigned long flags;
 554         int ret;
 555
 556         spin_lock_irqsave(&chip->msg_lock, flags);
 557
 558         lx_message_init(&chip->rmh, CMD_04_GET_EVENT);
 559         chip->rmh.stat_len = 9; /* we don't necessarily need the full length */
 560
 561         ret = lx_message_send_atomic(chip, &chip->rmh);
 562
 563         if (!ret)
 564                 memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32));
 565
 566         spin_unlock_irqrestore(&chip->msg_lock, flags);
 567         return ret;
 568 }
 569
 570 #define CSES_TIMEOUT        100     /* microseconds */
 571 #define CSES_CE             0x0001
 572 #define CSES_BROADCAST      0x0002
 573 #define CSES_UPDATE_LDSV    0x0004
 574
 575 int lx_dsp_es_check_pipeline(struct lx6464es *chip)
 576 {
 577         int i;
 578
 579         for (i = 0; i != CSES_TIMEOUT; ++i) {
 580                 /*
 581                  * le bit CSES_UPDATE_LDSV est Ã  1 dÃ©s que le macprog
 582                  * est pret. il re-passe Ã  0 lorsque le premier read a
 583                  * Ã©tÃ© fait. pour l'instant on retire le test car ce bit
 584                  * passe a 1 environ 200 Ã  400 ms aprÃ©s que le registre
 585                  * confES Ã  Ã©tÃ© Ã©crit (kick du xilinx ES).
 586                  *
 587                  * On ne teste que le bit CE.
 588                  * */
 589
 590                 u32 cses = lx_dsp_reg_read(chip, eReg_CSES);
 591
 592                 if ((cses & CSES_CE) == 0)
 593                         return 0;
 594
 595                 udelay(1);
 596         }
 597
 598         return -ETIMEDOUT;
 599 }
 600
 601
 602 #define PIPE_INFO_TO_CMD(capture, pipe)                                 \
 603         ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET)
 604
 605
 606
 607 /* low-level pipe handling */
 608 int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture,
 609                      int channels)
 610 {
 611         int err;
 612         unsigned long flags;
 613
 614         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 615
 616         spin_lock_irqsave(&chip->msg_lock, flags);
 617         lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE);
 618
 619         chip->rmh.cmd[0] |= pipe_cmd;
 620         chip->rmh.cmd[0] |= channels;
 621
 622         err = lx_message_send_atomic(chip, &chip->rmh);
 623         spin_unlock_irqrestore(&chip->msg_lock, flags);
 624
 625         if (err != 0)
 626                 snd_printk(KERN_ERR "lx6464es: could not allocate pipe\n");
 627
 628         return err;
 629 }
 630
 631 int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture)
 632 {
 633         int err;
 634         unsigned long flags;
 635
 636         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 637
 638         spin_lock_irqsave(&chip->msg_lock, flags);
 639         lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE);
 640
 641         chip->rmh.cmd[0] |= pipe_cmd;
 642
 643         err = lx_message_send_atomic(chip, &chip->rmh);
 644         spin_unlock_irqrestore(&chip->msg_lock, flags);
 645
 646         return err;
 647 }
 648
 649 int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture,
 650                   u32 *r_needed, u32 *r_freed, u32 *size_array)
 651 {
 652         int err;
 653         unsigned long flags;
 654
 655         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 656
 657 #ifdef CONFIG_SND_DEBUG
 658         if (size_array)
 659                 memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER);
 660 #endif
 661
 662         *r_needed = 0;
 663         *r_freed = 0;
 664
 665         spin_lock_irqsave(&chip->msg_lock, flags);
 666         lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS);
 667
 668         chip->rmh.cmd[0] |= pipe_cmd;
 669
 670         err = lx_message_send_atomic(chip, &chip->rmh);
 671
 672         if (!err) {
 673                 int i;
 674                 for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
 675                         u32 stat = chip->rmh.stat[i];
 676                         if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) {
 677                                 /* finished */
 678                                 *r_freed += 1;
 679                                 if (size_array)
 680                                         size_array[i] = stat & MASK_DATA_SIZE;
 681                         } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET))
 682                                    == 0)
 683                                 /* free */
 684                                 *r_needed += 1;
 685                 }
 686
 687 #if 0
 688                 snd_printdd(LXP "CMD_08_ASK_BUFFERS: needed %d, freed %d\n",
 689                             *r_needed, *r_freed);
 690                 for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
 691                         for (i = 0; i != chip->rmh.stat_len; ++i)
 692                                 snd_printdd("  stat[%d]: %x, %x\n", i,
 693                                             chip->rmh.stat[i],
 694                                             chip->rmh.stat[i] & MASK_DATA_SIZE);
 695                 }
 696 #endif
 697         }
 698
 699         spin_unlock_irqrestore(&chip->msg_lock, flags);
 700         return err;
 701 }
 702
 703
 704 int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture)
 705 {
 706         int err;
 707         unsigned long flags;
 708
 709         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 710
 711         spin_lock_irqsave(&chip->msg_lock, flags);
 712         lx_message_init(&chip->rmh, CMD_09_STOP_PIPE);
 713
 714         chip->rmh.cmd[0] |= pipe_cmd;
 715
 716         err = lx_message_send_atomic(chip, &chip->rmh);
 717
 718         spin_unlock_irqrestore(&chip->msg_lock, flags);
 719         return err;
 720 }
 721
 722 static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture)
 723 {
 724         int err;
 725         unsigned long flags;
 726
 727         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 728
 729         spin_lock_irqsave(&chip->msg_lock, flags);
 730         lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE);
 731
 732         chip->rmh.cmd[0] |= pipe_cmd;
 733
 734         err = lx_message_send_atomic(chip, &chip->rmh);
 735
 736         spin_unlock_irqrestore(&chip->msg_lock, flags);
 737         return err;
 738 }
 739
 740
 741 int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture)
 742 {
 743         int err;
 744
 745         err = lx_pipe_wait_for_idle(chip, pipe, is_capture);
 746         if (err < 0)
 747                 return err;
 748
 749         err = lx_pipe_toggle_state(chip, pipe, is_capture);
 750
 751         return err;
 752 }
 753
 754 int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture)
 755 {
 756         int err = 0;
 757
 758         err = lx_pipe_wait_for_start(chip, pipe, is_capture);
 759         if (err < 0)
 760                 return err;
 761
 762         err = lx_pipe_toggle_state(chip, pipe, is_capture);
 763
 764         return err;
 765 }
 766
 767
 768 int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture,
 769                          u64 *rsample_count)
 770 {
 771         int err;
 772         unsigned long flags;
 773
 774         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 775
 776         spin_lock_irqsave(&chip->msg_lock, flags);
 777         lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
 778
 779         chip->rmh.cmd[0] |= pipe_cmd;
 780         chip->rmh.stat_len = 2; /* need all words here! */
 781
 782         err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */
 783
 784         if (err != 0)
 785                 snd_printk(KERN_ERR
 786                            "lx6464es: could not query pipe's sample count\n");
 787         else {
 788                 *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
 789                                   << 24)     /* hi part */
 790                         + chip->rmh.stat[1]; /* lo part */
 791         }
 792
 793         spin_unlock_irqrestore(&chip->msg_lock, flags);
 794         return err;
 795 }
 796
 797 int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate)
 798 {
 799         int err;
 800         unsigned long flags;
 801
 802         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 803
 804         spin_lock_irqsave(&chip->msg_lock, flags);
 805         lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
 806
 807         chip->rmh.cmd[0] |= pipe_cmd;
 808
 809         err = lx_message_send_atomic(chip, &chip->rmh);
 810
 811         if (err != 0)
 812                 snd_printk(KERN_ERR "lx6464es: could not query pipe's state\n");
 813         else
 814                 *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F;
 815
 816         spin_unlock_irqrestore(&chip->msg_lock, flags);
 817         return err;
 818 }
 819
 820 static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe,
 821                                   int is_capture, u16 state)
 822 {
 823         int i;
 824
 825         /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms:
 826          * timeout 50 ms */
 827         for (i = 0; i != 50; ++i) {
 828                 u16 current_state;
 829                 int err = lx_pipe_state(chip, pipe, is_capture, &current_state);
 830
 831                 if (err < 0)
 832                         return err;
 833
 834                 if (current_state == state)
 835                         return 0;
 836
 837                 mdelay(1);
 838         }
 839
 840         return -ETIMEDOUT;
 841 }
 842
 843 int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture)
 844 {
 845         return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN);
 846 }
 847
 848 int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture)
 849 {
 850         return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE);
 851 }
 852
 853 /* low-level stream handling */
 854 int lx_stream_set_state(struct lx6464es *chip, u32 pipe,
 855                                int is_capture, enum stream_state_t state)
 856 {
 857         int err;
 858         unsigned long flags;
 859
 860         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 861
 862         spin_lock_irqsave(&chip->msg_lock, flags);
 863         lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE);
 864
 865         chip->rmh.cmd[0] |= pipe_cmd;
 866         chip->rmh.cmd[0] |= state;
 867
 868         err = lx_message_send_atomic(chip, &chip->rmh);
 869         spin_unlock_irqrestore(&chip->msg_lock, flags);
 870
 871         return err;
 872 }
 873
 874 int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime,
 875                          u32 pipe, int is_capture)
 876 {
 877         int err;
 878         unsigned long flags;
 879
 880         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 881
 882         u32 channels = runtime->channels;
 883
 884         if (runtime->channels != channels)
 885                 snd_printk(KERN_ERR LXP "channel count mismatch: %d vs %d",
 886                            runtime->channels, channels);
 887
 888         spin_lock_irqsave(&chip->msg_lock, flags);
 889         lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM);
 890
 891         chip->rmh.cmd[0] |= pipe_cmd;
 892
 893         if (runtime->sample_bits == 16)
 894                 /* 16 bit format */
 895                 chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET);
 896
 897         if (snd_pcm_format_little_endian(runtime->format))
 898                 /* little endian/intel format */
 899                 chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET);
 900
 901         chip->rmh.cmd[0] |= channels-1;
 902
 903         err = lx_message_send_atomic(chip, &chip->rmh);
 904         spin_unlock_irqrestore(&chip->msg_lock, flags);
 905
 906         return err;
 907 }
 908
 909 int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture,
 910                     int *rstate)
 911 {
 912         int err;
 913         unsigned long flags;
 914
 915         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 916
 917         spin_lock_irqsave(&chip->msg_lock, flags);
 918         lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
 919
 920         chip->rmh.cmd[0] |= pipe_cmd;
 921
 922         err = lx_message_send_atomic(chip, &chip->rmh);
 923
 924         *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE;
 925
 926         spin_unlock_irqrestore(&chip->msg_lock, flags);
 927         return err;
 928 }
 929
 930 int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture,
 931                               u64 *r_bytepos)
 932 {
 933         int err;
 934         unsigned long flags;
 935
 936         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 937
 938         spin_lock_irqsave(&chip->msg_lock, flags);
 939         lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
 940
 941         chip->rmh.cmd[0] |= pipe_cmd;
 942
 943         err = lx_message_send_atomic(chip, &chip->rmh);
 944
 945         *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
 946                       << 32)         /* hi part */
 947                 + chip->rmh.stat[1]; /* lo part */
 948
 949         spin_unlock_irqrestore(&chip->msg_lock, flags);
 950         return err;
 951 }
 952
 953 /* low-level buffer handling */
 954 int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture,
 955                    u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi,
 956                    u32 *r_buffer_index)
 957 {
 958         int err;
 959         unsigned long flags;
 960
 961         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 962
 963         spin_lock_irqsave(&chip->msg_lock, flags);
 964         lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER);
 965
 966         chip->rmh.cmd[0] |= pipe_cmd;
 967         chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */
 968
 969         /* todo: pause request, circular buffer */
 970
 971         chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE;
 972         chip->rmh.cmd[2] = buf_address_lo;
 973
 974         if (buf_address_hi) {
 975                 chip->rmh.cmd_len = 4;
 976                 chip->rmh.cmd[3] = buf_address_hi;
 977                 chip->rmh.cmd[0] |= BF_64BITS_ADR;
 978         }
 979
 980         err = lx_message_send_atomic(chip, &chip->rmh);
 981
 982         if (err == 0) {
 983                 *r_buffer_index = chip->rmh.stat[0];
 984                 goto done;
 985         }
 986
 987         if (err == EB_RBUFFERS_TABLE_OVERFLOW)
 988                 snd_printk(LXP "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n");
 989
 990         if (err == EB_INVALID_STREAM)
 991                 snd_printk(LXP "lx_buffer_give EB_INVALID_STREAM\n");
 992
 993         if (err == EB_CMD_REFUSED)
 994                 snd_printk(LXP "lx_buffer_give EB_CMD_REFUSED\n");
 995
 996  done:
 997         spin_unlock_irqrestore(&chip->msg_lock, flags);
 998         return err;
 999 }
1000
1001 int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture,
1002                    u32 *r_buffer_size)
1003 {
1004         int err;
1005         unsigned long flags;
1006
1007         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
1008
1009         spin_lock_irqsave(&chip->msg_lock, flags);
1010         lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
1011
1012         chip->rmh.cmd[0] |= pipe_cmd;
1013         chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the
1014                                              * microblaze will seek for it */
1015
1016         err = lx_message_send_atomic(chip, &chip->rmh);
1017
1018         if (err == 0)
1019                 *r_buffer_size = chip->rmh.stat[0]  & MASK_DATA_SIZE;
1020
1021         spin_unlock_irqrestore(&chip->msg_lock, flags);
1022         return err;
1023 }
1024
1025 int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture,
1026                      u32 buffer_index)
1027 {
1028         int err;
1029         unsigned long flags;
1030
1031         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
1032
1033         spin_lock_irqsave(&chip->msg_lock, flags);
1034         lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
1035
1036         chip->rmh.cmd[0] |= pipe_cmd;
1037         chip->rmh.cmd[0] |= buffer_index;
1038
1039         err = lx_message_send_atomic(chip, &chip->rmh);
1040
1041         spin_unlock_irqrestore(&chip->msg_lock, flags);
1042         return err;
1043 }
1044
1045
1046 /* low-level gain/peak handling
1047  *
1048  * \todo: can we unmute capture/playback channels independently?
1049  *
1050  * */
1051 int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute)
1052 {
1053         int err;
1054         unsigned long flags;
1055
1056         /* bit set to 1: channel muted */
1057         u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU;
1058
1059         spin_lock_irqsave(&chip->msg_lock, flags);
1060         lx_message_init(&chip->rmh, CMD_0D_SET_MUTE);
1061
1062         chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0);
1063
1064         chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32);        /* hi part */
1065         chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */
1066
1067         snd_printk("mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1],
1068                    chip->rmh.cmd[2]);
1069
1070         err = lx_message_send_atomic(chip, &chip->rmh);
1071
1072         spin_unlock_irqrestore(&chip->msg_lock, flags);
1073         return err;
1074 }
1075
1076 static u32 peak_map[] = {
1077         0x00000109, /* -90.308dB */
1078         0x0000083B, /* -72.247dB */
1079         0x000020C4, /* -60.205dB */
1080         0x00008273, /* -48.030dB */
1081         0x00020756, /* -36.005dB */
1082         0x00040C37, /* -30.001dB */
1083         0x00081385, /* -24.002dB */
1084         0x00101D3F, /* -18.000dB */
1085         0x0016C310, /* -15.000dB */
1086         0x002026F2, /* -12.001dB */
1087         0x002D6A86, /* -9.000dB */
1088         0x004026E6, /* -6.004dB */
1089         0x005A9DF6, /* -3.000dB */
1090         0x0065AC8B, /* -2.000dB */
1091         0x00721481, /* -1.000dB */
1092         0x007FFFFF, /* FS */
1093 };
1094
1095 int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels,
1096                    u32 *r_levels)
1097 {
1098         int err = 0;
1099         unsigned long flags;
1100         int i;
1101         spin_lock_irqsave(&chip->msg_lock, flags);
1102
1103         for (i = 0; i < channels; i += 4) {
1104                 u32 s0, s1, s2, s3;
1105
1106                 lx_message_init(&chip->rmh, CMD_12_GET_PEAK);
1107                 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i);
1108
1109                 err = lx_message_send_atomic(chip, &chip->rmh);
1110
1111                 if (err == 0) {
1112                         s0 = peak_map[chip->rmh.stat[0] & 0x0F];
1113                         s1 = peak_map[(chip->rmh.stat[0] >>  4) & 0xf];
1114                         s2 = peak_map[(chip->rmh.stat[0] >>  8) & 0xf];
1115                         s3 = peak_map[(chip->rmh.stat[0] >>  12) & 0xf];
1116                 } else
1117                         s0 = s1 = s2 = s3 = 0;
1118
1119                 r_levels[0] = s0;
1120                 r_levels[1] = s1;
1121                 r_levels[2] = s2;
1122                 r_levels[3] = s3;
1123
1124                 r_levels += 4;
1125         }
1126
1127         spin_unlock_irqrestore(&chip->msg_lock, flags);
1128         return err;
1129 }
1130
1131 /* interrupt handling */
1132 #define PCX_IRQ_NONE 0
1133 #define IRQCS_ACTIVE_PCIDB  0x00002000L         /* Bit nÃ\83Â¸ 13 */
1134 #define IRQCS_ENABLE_PCIIRQ 0x00000100L         /* Bit nÃ\83Â¸ 08 */
1135 #define IRQCS_ENABLE_PCIDB  0x00000200L         /* Bit nÃ\83Â¸ 09 */
1136
1137 static u32 lx_interrupt_test_ack(struct lx6464es *chip)
1138 {
1139         u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS);
1140
1141         /* Test if PCI Doorbell interrupt is active */
1142         if (irqcs & IRQCS_ACTIVE_PCIDB) {
1143                 u32 temp;
1144                 irqcs = PCX_IRQ_NONE;
1145
1146                 while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) {
1147                         /* RAZ interrupt */
1148                         irqcs |= temp;
1149                         lx_plx_reg_write(chip, ePLX_L2PCIDB, temp);
1150                 }
1151
1152                 return irqcs;
1153         }
1154         return PCX_IRQ_NONE;
1155 }
1156
1157 static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc,
1158                             int *r_async_pending, int *r_async_escmd)
1159 {
1160         u32 irq_async;
1161         u32 irqsrc = lx_interrupt_test_ack(chip);
1162
1163         if (irqsrc == PCX_IRQ_NONE)
1164                 return 0;
1165
1166         *r_irqsrc = irqsrc;
1167
1168         irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response
1169                                                      * (set by xilinx) + EOB */
1170
1171         if (irq_async & MASK_SYS_STATUS_ESA) {
1172                 irq_async &= ~MASK_SYS_STATUS_ESA;
1173                 *r_async_escmd = 1;
1174         }
1175
1176         if (irqsrc & MASK_SYS_STATUS_CMD_DONE)
1177                 /* xilinx command notification */
1178                 atomic_set(&chip->send_message_locked, 0);
1179
1180         if (irq_async) {
1181                 /* snd_printd("interrupt: async event pending\n"); */
1182                 *r_async_pending = 1;
1183         }
1184
1185         return 1;
1186 }
1187
1188 static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc,
1189                                             int *r_freq_changed,
1190                                             u64 *r_notified_in_pipe_mask,
1191                                             u64 *r_notified_out_pipe_mask)
1192 {
1193         int err;
1194         u32 stat[9];            /* answer from CMD_04_GET_EVENT */
1195
1196         /* On peut optimiser pour ne pas lire les evenements vides
1197          * les mots de rÃ\83Â©ponse sont dans l'ordre suivant :
1198          * Stat[0]      mot de status gÃ\83Â©nÃ\83Â©ral
1199          * Stat[1]      fin de buffer OUT pF
1200          * Stat[2]      fin de buffer OUT pf
1201          * Stat[3]      fin de buffer IN pF
1202          * Stat[4]      fin de buffer IN pf
1203          * Stat[5]      underrun poid fort
1204          * Stat[6]      underrun poid faible
1205          * Stat[7]      overrun poid fort
1206          * Stat[8]      overrun poid faible
1207          * */
1208
1209         u64 orun_mask;
1210         u64 urun_mask;
1211 #if 0
1212         int has_underrun   = (irqsrc & MASK_SYS_STATUS_URUN) ? 1 : 0;
1213         int has_overrun    = (irqsrc & MASK_SYS_STATUS_ORUN) ? 1 : 0;
1214 #endif
1215         int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0;
1216         int eb_pending_in  = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0;
1217
1218         *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0;
1219
1220         err = lx_dsp_read_async_events(chip, stat);
1221         if (err < 0)
1222                 return err;
1223
1224         if (eb_pending_in) {
1225                 *r_notified_in_pipe_mask = ((u64)stat[3] << 32)
1226                         + stat[4];
1227                 snd_printdd(LXP "interrupt: EOBI pending %llx\n",
1228                             *r_notified_in_pipe_mask);
1229         }
1230         if (eb_pending_out) {
1231                 *r_notified_out_pipe_mask = ((u64)stat[1] << 32)
1232                         + stat[2];
1233                 snd_printdd(LXP "interrupt: EOBO pending %llx\n",
1234                             *r_notified_out_pipe_mask);
1235         }
1236
1237         orun_mask = ((u64)stat[7] << 32) + stat[8];
1238         urun_mask = ((u64)stat[5] << 32) + stat[6];
1239
1240         /* todo: handle xrun notification */
1241
1242         return err;
1243 }
1244
1245 static int lx_interrupt_request_new_buffer(struct lx6464es *chip,
1246                                            struct lx_stream *lx_stream)
1247 {
1248         struct snd_pcm_substream *substream = lx_stream->stream;
1249         int is_capture = lx_stream->is_capture;
1250         int err;
1251         unsigned long flags;
1252
1253         const u32 channels = substream->runtime->channels;
1254         const u32 bytes_per_frame = channels * 3;
1255         const u32 period_size = substream->runtime->period_size;
1256         const u32 period_bytes = period_size * bytes_per_frame;
1257         const u32 pos = lx_stream->frame_pos;
1258         const u32 next_pos = ((pos+1) == substream->runtime->periods) ?
1259                 0 : pos + 1;
1260
1261         dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes;
1262         u32 buf_hi = 0;
1263         u32 buf_lo = 0;
1264         u32 buffer_index = 0;
1265
1266         u32 needed, freed;
1267         u32 size_array[MAX_STREAM_BUFFER];
1268
1269         snd_printdd("->lx_interrupt_request_new_buffer\n");
1270
1271         spin_lock_irqsave(&chip->lock, flags);
1272
1273         err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array);
1274         snd_printdd(LXP "interrupt: needed %d, freed %d\n", needed, freed);
1275
1276         unpack_pointer(buf, &buf_lo, &buf_hi);
1277         err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi,
1278                              &buffer_index);
1279         snd_printdd(LXP "interrupt: gave buffer index %x on %p (%d bytes)\n",
1280                     buffer_index, (void *)buf, period_bytes);
1281
1282         lx_stream->frame_pos = next_pos;
1283         spin_unlock_irqrestore(&chip->lock, flags);
1284
1285         return err;
1286 }
1287
1288 void lx_tasklet_playback(unsigned long data)
1289 {
1290         struct lx6464es *chip = (struct lx6464es *)data;
1291         struct lx_stream *lx_stream = &chip->playback_stream;
1292         int err;
1293
1294         snd_printdd("->lx_tasklet_playback\n");
1295
1296         err = lx_interrupt_request_new_buffer(chip, lx_stream);
1297         if (err < 0)
1298                 snd_printk(KERN_ERR LXP
1299                            "cannot request new buffer for playback\n");
1300
1301         snd_pcm_period_elapsed(lx_stream->stream);
1302 }
1303
1304 void lx_tasklet_capture(unsigned long data)
1305 {
1306         struct lx6464es *chip = (struct lx6464es *)data;
1307         struct lx_stream *lx_stream = &chip->capture_stream;
1308         int err;
1309
1310         snd_printdd("->lx_tasklet_capture\n");
1311         err = lx_interrupt_request_new_buffer(chip, lx_stream);
1312         if (err < 0)
1313                 snd_printk(KERN_ERR LXP
1314                            "cannot request new buffer for capture\n");
1315
1316         snd_pcm_period_elapsed(lx_stream->stream);
1317 }
1318
1319
1320
1321 static int lx_interrupt_handle_audio_transfer(struct lx6464es *chip,
1322                                               u64 notified_in_pipe_mask,
1323                                               u64 notified_out_pipe_mask)
1324 {
1325         int err = 0;
1326
1327         if (notified_in_pipe_mask) {
1328                 snd_printdd(LXP "requesting audio transfer for capture\n");
1329                 tasklet_hi_schedule(&chip->tasklet_capture);
1330         }
1331
1332         if (notified_out_pipe_mask) {
1333                 snd_printdd(LXP "requesting audio transfer for playback\n");
1334                 tasklet_hi_schedule(&chip->tasklet_playback);
1335         }
1336
1337         return err;
1338 }
1339
1340
1341 irqreturn_t lx_interrupt(int irq, void *dev_id)
1342 {
1343         struct lx6464es *chip = dev_id;
1344         int async_pending, async_escmd;
1345         u32 irqsrc;
1346
1347         spin_lock(&chip->lock);
1348
1349         snd_printdd("**************************************************\n");
1350
1351         if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) {
1352                 spin_unlock(&chip->lock);
1353                 snd_printdd("IRQ_NONE\n");
1354                 return IRQ_NONE; /* this device did not cause the interrupt */
1355         }
1356
1357         if (irqsrc & MASK_SYS_STATUS_CMD_DONE)
1358                 goto exit;
1359
1360 #if 0
1361         if (irqsrc & MASK_SYS_STATUS_EOBI)
1362                 snd_printdd(LXP "interrupt: EOBI\n");
1363
1364         if (irqsrc & MASK_SYS_STATUS_EOBO)
1365                 snd_printdd(LXP "interrupt: EOBO\n");
1366
1367         if (irqsrc & MASK_SYS_STATUS_URUN)
1368                 snd_printdd(LXP "interrupt: URUN\n");
1369
1370         if (irqsrc & MASK_SYS_STATUS_ORUN)
1371                 snd_printdd(LXP "interrupt: ORUN\n");
1372 #endif
1373
1374         if (async_pending) {
1375                 u64 notified_in_pipe_mask = 0;
1376                 u64 notified_out_pipe_mask = 0;
1377                 int freq_changed;
1378                 int err;
1379
1380                 /* handle async events */
1381                 err = lx_interrupt_handle_async_events(chip, irqsrc,
1382                                                        &freq_changed,
1383                                                        &notified_in_pipe_mask,
1384                                                        &notified_out_pipe_mask);
1385                 if (err)
1386                         snd_printk(KERN_ERR LXP
1387                                    "error handling async events\n");
1388
1389                 err = lx_interrupt_handle_audio_transfer(chip,
1390                                                          notified_in_pipe_mask,
1391                                                          notified_out_pipe_mask
1392                         );
1393                 if (err)
1394                         snd_printk(KERN_ERR LXP
1395                                    "error during audio transfer\n");
1396         }
1397
1398         if (async_escmd) {
1399 #if 0
1400                 /* backdoor for ethersound commands
1401                  *
1402                  * for now, we do not need this
1403                  *
1404                  * */
1405
1406                 snd_printdd("lx6464es: interrupt requests escmd handling\n");
1407 #endif
1408         }
1409
1410 exit:
1411         spin_unlock(&chip->lock);
1412         return IRQ_HANDLED;     /* this device caused the interrupt */
1413 }
1414
1415
1416 static void lx_irq_set(struct lx6464es *chip, int enable)
1417 {
1418         u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS);
1419
1420         /* enable/disable interrupts
1421          *
1422          * Set the Doorbell and PCI interrupt enable bits
1423          *
1424          * */
1425         if (enable)
1426                 reg |=  (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1427         else
1428                 reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1429         lx_plx_reg_write(chip, ePLX_IRQCS, reg);
1430 }
1431
1432 void lx_irq_enable(struct lx6464es *chip)
1433 {
1434         snd_printdd("->lx_irq_enable\n");
1435         lx_irq_set(chip, 1);
1436 }
1437
1438 void lx_irq_disable(struct lx6464es *chip)
1439 {
1440         snd_printdd("->lx_irq_disable\n");
1441         lx_irq_set(chip, 0);
1442 }