1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
13 * Wu Fengguang <wfg@linux.intel.com>
16 * Wu Fengguang <wfg@linux.intel.com>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/asoundef.h>
27 #include <sound/tlv.h>
28 #include <sound/hdaudio.h>
29 #include <sound/hda_i915.h>
30 #include <sound/hda_chmap.h>
31 #include <sound/hda_codec.h>
32 #include "hda_local.h"
35 static bool static_hdmi_pcm;
36 module_param(static_hdmi_pcm, bool, 0644);
37 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
39 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
40 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
41 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
42 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
43 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
44 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
45 ((codec)->core.vendor_id == 0x80862800))
46 #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
47 #define is_icelake(codec) ((codec)->core.vendor_id == 0x8086280f)
48 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
49 || is_skylake(codec) || is_broxton(codec) \
50 || is_kabylake(codec) || is_geminilake(codec) \
51 || is_cannonlake(codec) || is_icelake(codec))
52 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
53 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
54 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
56 struct hdmi_spec_per_cvt {
59 unsigned int channels_min;
60 unsigned int channels_max;
66 /* max. connections to a widget */
67 #define HDA_MAX_CONNECTIONS 32
69 struct hdmi_spec_per_pin {
72 /* pin idx, different device entries on the same pin use the same idx */
75 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
79 struct hda_codec *codec;
80 struct hdmi_eld sink_eld;
82 struct delayed_work work;
83 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
84 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
86 bool setup; /* the stream has been set up by prepare callback */
87 int channels; /* current number of channels */
89 bool chmap_set; /* channel-map override by ALSA API? */
90 unsigned char chmap[8]; /* ALSA API channel-map */
91 #ifdef CONFIG_SND_PROC_FS
92 struct snd_info_entry *proc_entry;
96 /* operations used by generic code that can be overridden by patches */
98 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
99 unsigned char *buf, int *eld_size);
101 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
102 int ca, int active_channels, int conn_type);
104 /* enable/disable HBR (HD passthrough) */
105 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
107 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
108 hda_nid_t pin_nid, u32 stream_tag, int format);
110 void (*pin_cvt_fixup)(struct hda_codec *codec,
111 struct hdmi_spec_per_pin *per_pin,
117 struct snd_jack *jack;
118 struct snd_kcontrol *eld_ctl;
123 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
124 hda_nid_t cvt_nids[4]; /* only for haswell fix */
127 * num_pins is the number of virtual pins
128 * for example, there are 3 pins, and each pin
129 * has 4 device entries, then the num_pins is 12
133 * num_nids is the number of real pins
134 * In the above example, num_nids is 3
138 * dev_num is the number of device entries
140 * In the above example, dev_num is 4
143 struct snd_array pins; /* struct hdmi_spec_per_pin */
144 struct hdmi_pcm pcm_rec[16];
145 struct mutex pcm_lock;
146 /* pcm_bitmap means which pcms have been assigned to pins*/
147 unsigned long pcm_bitmap;
148 int pcm_used; /* counter of pcm_rec[] */
149 /* bitmap shows whether the pcm is opened in user space
150 * bit 0 means the first playback PCM (PCM3);
151 * bit 1 means the second playback PCM, and so on.
153 unsigned long pcm_in_use;
155 struct hdmi_eld temp_eld;
161 * Non-generic VIA/NVIDIA specific
163 struct hda_multi_out multiout;
164 struct hda_pcm_stream pcm_playback;
166 /* i915/powerwell (Haswell+/Valleyview+) specific */
167 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
168 struct drm_audio_component_audio_ops drm_audio_ops;
170 struct hdac_chmap chmap;
171 hda_nid_t vendor_nid;
176 #ifdef CONFIG_SND_HDA_COMPONENT
177 static inline bool codec_has_acomp(struct hda_codec *codec)
179 struct hdmi_spec *spec = codec->spec;
180 return spec->use_acomp_notifier;
183 #define codec_has_acomp(codec) false
186 struct hdmi_audio_infoframe {
193 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
197 u8 LFEPBL01_LSV36_DM_INH7;
200 struct dp_audio_infoframe {
203 u8 ver; /* 0x11 << 2 */
205 u8 CC02_CT47; /* match with HDMI infoframe from this on */
209 u8 LFEPBL01_LSV36_DM_INH7;
212 union audio_infoframe {
213 struct hdmi_audio_infoframe hdmi;
214 struct dp_audio_infoframe dp;
222 #define get_pin(spec, idx) \
223 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
224 #define get_cvt(spec, idx) \
225 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
226 /* obtain hdmi_pcm object assigned to idx */
227 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
228 /* obtain hda_pcm object assigned to idx */
229 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
231 static int pin_id_to_pin_index(struct hda_codec *codec,
232 hda_nid_t pin_nid, int dev_id)
234 struct hdmi_spec *spec = codec->spec;
236 struct hdmi_spec_per_pin *per_pin;
239 * (dev_id == -1) means it is NON-MST pin
240 * return the first virtual pin on this port
245 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
246 per_pin = get_pin(spec, pin_idx);
247 if ((per_pin->pin_nid == pin_nid) &&
248 (per_pin->dev_id == dev_id))
252 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
256 static int hinfo_to_pcm_index(struct hda_codec *codec,
257 struct hda_pcm_stream *hinfo)
259 struct hdmi_spec *spec = codec->spec;
262 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
263 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
266 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
270 static int hinfo_to_pin_index(struct hda_codec *codec,
271 struct hda_pcm_stream *hinfo)
273 struct hdmi_spec *spec = codec->spec;
274 struct hdmi_spec_per_pin *per_pin;
277 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
278 per_pin = get_pin(spec, pin_idx);
280 per_pin->pcm->pcm->stream == hinfo)
284 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
288 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
292 struct hdmi_spec_per_pin *per_pin;
294 for (i = 0; i < spec->num_pins; i++) {
295 per_pin = get_pin(spec, i);
296 if (per_pin->pcm_idx == pcm_idx)
302 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
304 struct hdmi_spec *spec = codec->spec;
307 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
308 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
311 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
315 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
316 struct snd_ctl_elem_info *uinfo)
318 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
319 struct hdmi_spec *spec = codec->spec;
320 struct hdmi_spec_per_pin *per_pin;
321 struct hdmi_eld *eld;
324 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
326 pcm_idx = kcontrol->private_value;
327 mutex_lock(&spec->pcm_lock);
328 per_pin = pcm_idx_to_pin(spec, pcm_idx);
330 /* no pin is bound to the pcm */
334 eld = &per_pin->sink_eld;
335 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
338 mutex_unlock(&spec->pcm_lock);
342 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
343 struct snd_ctl_elem_value *ucontrol)
345 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
346 struct hdmi_spec *spec = codec->spec;
347 struct hdmi_spec_per_pin *per_pin;
348 struct hdmi_eld *eld;
352 pcm_idx = kcontrol->private_value;
353 mutex_lock(&spec->pcm_lock);
354 per_pin = pcm_idx_to_pin(spec, pcm_idx);
356 /* no pin is bound to the pcm */
357 memset(ucontrol->value.bytes.data, 0,
358 ARRAY_SIZE(ucontrol->value.bytes.data));
362 eld = &per_pin->sink_eld;
363 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
364 eld->eld_size > ELD_MAX_SIZE) {
370 memset(ucontrol->value.bytes.data, 0,
371 ARRAY_SIZE(ucontrol->value.bytes.data));
373 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
377 mutex_unlock(&spec->pcm_lock);
381 static const struct snd_kcontrol_new eld_bytes_ctl = {
382 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
383 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
385 .info = hdmi_eld_ctl_info,
386 .get = hdmi_eld_ctl_get,
389 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
392 struct snd_kcontrol *kctl;
393 struct hdmi_spec *spec = codec->spec;
396 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
399 kctl->private_value = pcm_idx;
400 kctl->id.device = device;
402 /* no pin nid is associated with the kctl now
403 * tbd: associate pin nid to eld ctl later
405 err = snd_hda_ctl_add(codec, 0, kctl);
409 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
414 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
415 int *packet_index, int *byte_index)
419 val = snd_hda_codec_read(codec, pin_nid, 0,
420 AC_VERB_GET_HDMI_DIP_INDEX, 0);
422 *packet_index = val >> 5;
423 *byte_index = val & 0x1f;
427 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
428 int packet_index, int byte_index)
432 val = (packet_index << 5) | (byte_index & 0x1f);
434 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
437 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
440 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
443 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
445 struct hdmi_spec *spec = codec->spec;
449 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
450 snd_hda_codec_write(codec, pin_nid, 0,
451 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
453 if (spec->dyn_pin_out)
454 /* Disable pin out until stream is active */
457 /* Enable pin out: some machines with GM965 gets broken output
458 * when the pin is disabled or changed while using with HDMI
462 snd_hda_codec_write(codec, pin_nid, 0,
463 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
470 #ifdef CONFIG_SND_PROC_FS
471 static void print_eld_info(struct snd_info_entry *entry,
472 struct snd_info_buffer *buffer)
474 struct hdmi_spec_per_pin *per_pin = entry->private_data;
476 mutex_lock(&per_pin->lock);
477 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
478 mutex_unlock(&per_pin->lock);
481 static void write_eld_info(struct snd_info_entry *entry,
482 struct snd_info_buffer *buffer)
484 struct hdmi_spec_per_pin *per_pin = entry->private_data;
486 mutex_lock(&per_pin->lock);
487 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
488 mutex_unlock(&per_pin->lock);
491 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
494 struct hda_codec *codec = per_pin->codec;
495 struct snd_info_entry *entry;
498 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
499 err = snd_card_proc_new(codec->card, name, &entry);
503 snd_info_set_text_ops(entry, per_pin, print_eld_info);
504 entry->c.text.write = write_eld_info;
506 per_pin->proc_entry = entry;
511 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
513 if (!per_pin->codec->bus->shutdown) {
514 snd_info_free_entry(per_pin->proc_entry);
515 per_pin->proc_entry = NULL;
519 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
524 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
530 * Audio InfoFrame routines
534 * Enable Audio InfoFrame Transmission
536 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
539 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
540 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
545 * Disable Audio InfoFrame Transmission
547 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
550 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
551 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
555 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
557 #ifdef CONFIG_SND_DEBUG_VERBOSE
561 size = snd_hdmi_get_eld_size(codec, pin_nid);
562 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
564 for (i = 0; i < 8; i++) {
565 size = snd_hda_codec_read(codec, pin_nid, 0,
566 AC_VERB_GET_HDMI_DIP_SIZE, i);
567 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
572 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
578 for (i = 0; i < 8; i++) {
579 size = snd_hda_codec_read(codec, pin_nid, 0,
580 AC_VERB_GET_HDMI_DIP_SIZE, i);
584 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
585 for (j = 1; j < 1000; j++) {
586 hdmi_write_dip_byte(codec, pin_nid, 0x0);
587 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
589 codec_dbg(codec, "dip index %d: %d != %d\n",
591 if (bi == 0) /* byte index wrapped around */
595 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
601 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
603 u8 *bytes = (u8 *)hdmi_ai;
607 hdmi_ai->checksum = 0;
609 for (i = 0; i < sizeof(*hdmi_ai); i++)
612 hdmi_ai->checksum = -sum;
615 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
621 hdmi_debug_dip_size(codec, pin_nid);
622 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
624 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
625 for (i = 0; i < size; i++)
626 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
629 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
635 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
639 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
640 for (i = 0; i < size; i++) {
641 val = snd_hda_codec_read(codec, pin_nid, 0,
642 AC_VERB_GET_HDMI_DIP_DATA, 0);
650 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
652 int ca, int active_channels,
655 union audio_infoframe ai;
657 memset(&ai, 0, sizeof(ai));
658 if (conn_type == 0) { /* HDMI */
659 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
661 hdmi_ai->type = 0x84;
664 hdmi_ai->CC02_CT47 = active_channels - 1;
666 hdmi_checksum_audio_infoframe(hdmi_ai);
667 } else if (conn_type == 1) { /* DisplayPort */
668 struct dp_audio_infoframe *dp_ai = &ai.dp;
672 dp_ai->ver = 0x11 << 2;
673 dp_ai->CC02_CT47 = active_channels - 1;
676 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
682 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
683 * sizeof(*dp_ai) to avoid partial match/update problems when
684 * the user switches between HDMI/DP monitors.
686 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
689 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
691 active_channels, ca);
692 hdmi_stop_infoframe_trans(codec, pin_nid);
693 hdmi_fill_audio_infoframe(codec, pin_nid,
694 ai.bytes, sizeof(ai));
695 hdmi_start_infoframe_trans(codec, pin_nid);
699 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
700 struct hdmi_spec_per_pin *per_pin,
703 struct hdmi_spec *spec = codec->spec;
704 struct hdac_chmap *chmap = &spec->chmap;
705 hda_nid_t pin_nid = per_pin->pin_nid;
706 int channels = per_pin->channels;
708 struct hdmi_eld *eld;
714 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
715 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
716 snd_hda_codec_write(codec, pin_nid, 0,
717 AC_VERB_SET_AMP_GAIN_MUTE,
720 eld = &per_pin->sink_eld;
722 ca = snd_hdac_channel_allocation(&codec->core,
723 eld->info.spk_alloc, channels,
724 per_pin->chmap_set, non_pcm, per_pin->chmap);
726 active_channels = snd_hdac_get_active_channels(ca);
728 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
732 * always configure channel mapping, it may have been changed by the
733 * user in the meantime
735 snd_hdac_setup_channel_mapping(&spec->chmap,
736 pin_nid, non_pcm, ca, channels,
737 per_pin->chmap, per_pin->chmap_set);
739 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
740 eld->info.conn_type);
742 per_pin->non_pcm = non_pcm;
749 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
751 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
754 struct hdmi_spec *spec = codec->spec;
755 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
759 mutex_lock(&spec->pcm_lock);
760 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
761 snd_hda_jack_report_sync(codec);
762 mutex_unlock(&spec->pcm_lock);
765 static void jack_callback(struct hda_codec *codec,
766 struct hda_jack_callback *jack)
768 /* hda_jack don't support DP MST */
769 check_presence_and_report(codec, jack->nid, 0);
772 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
774 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
775 struct hda_jack_tbl *jack;
776 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
779 * assume DP MST uses dyn_pcm_assign and acomp and
781 * if DP MST supports unsol event, below code need
784 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
787 jack->jack_dirty = 1;
790 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
791 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
792 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
794 /* hda_jack don't support DP MST */
795 check_presence_and_report(codec, jack->nid, 0);
798 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
800 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
801 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
802 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
803 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
806 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
821 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
823 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
824 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
826 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
827 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
832 hdmi_intrinsic_event(codec, res);
834 hdmi_non_intrinsic_event(codec, res);
837 static void haswell_verify_D0(struct hda_codec *codec,
838 hda_nid_t cvt_nid, hda_nid_t nid)
842 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
843 * thus pins could only choose converter 0 for use. Make sure the
844 * converters are in correct power state */
845 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
846 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
848 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
849 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
852 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
853 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
854 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
862 /* HBR should be Non-PCM, 8 channels */
863 #define is_hbr_format(format) \
864 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
866 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
869 int pinctl, new_pinctl;
871 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
872 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
873 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
876 return hbr ? -EINVAL : 0;
878 new_pinctl = pinctl & ~AC_PINCTL_EPT;
880 new_pinctl |= AC_PINCTL_EPT_HBR;
882 new_pinctl |= AC_PINCTL_EPT_NATIVE;
885 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
887 pinctl == new_pinctl ? "" : "new-",
890 if (pinctl != new_pinctl)
891 snd_hda_codec_write(codec, pin_nid, 0,
892 AC_VERB_SET_PIN_WIDGET_CONTROL,
900 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
901 hda_nid_t pin_nid, u32 stream_tag, int format)
903 struct hdmi_spec *spec = codec->spec;
907 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
910 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
914 if (is_haswell_plus(codec)) {
917 * on recent platforms IEC Coding Type is required for HBR
918 * support, read current Digital Converter settings and set
919 * ICT bitfield if needed.
921 param = snd_hda_codec_read(codec, cvt_nid, 0,
922 AC_VERB_GET_DIGI_CONVERT_1, 0);
924 param = (param >> 16) & ~(AC_DIG3_ICT);
926 /* on recent platforms ICT mode is required for HBR support */
927 if (is_hbr_format(format))
930 snd_hda_codec_write(codec, cvt_nid, 0,
931 AC_VERB_SET_DIGI_CONVERT_3, param);
934 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
938 /* Try to find an available converter
939 * If pin_idx is less then zero, just try to find an available converter.
940 * Otherwise, try to find an available converter and get the cvt mux index
943 static int hdmi_choose_cvt(struct hda_codec *codec,
944 int pin_idx, int *cvt_id)
946 struct hdmi_spec *spec = codec->spec;
947 struct hdmi_spec_per_pin *per_pin;
948 struct hdmi_spec_per_cvt *per_cvt = NULL;
949 int cvt_idx, mux_idx = 0;
951 /* pin_idx < 0 means no pin will be bound to the converter */
955 per_pin = get_pin(spec, pin_idx);
957 /* Dynamically assign converter to stream */
958 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
959 per_cvt = get_cvt(spec, cvt_idx);
961 /* Must not already be assigned */
962 if (per_cvt->assigned)
966 /* Must be in pin's mux's list of converters */
967 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
968 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
970 /* Not in mux list */
971 if (mux_idx == per_pin->num_mux_nids)
976 /* No free converters */
977 if (cvt_idx == spec->num_cvts)
981 per_pin->mux_idx = mux_idx;
989 /* Assure the pin select the right convetor */
990 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
991 struct hdmi_spec_per_pin *per_pin)
993 hda_nid_t pin_nid = per_pin->pin_nid;
996 mux_idx = per_pin->mux_idx;
997 curr = snd_hda_codec_read(codec, pin_nid, 0,
998 AC_VERB_GET_CONNECT_SEL, 0);
1000 snd_hda_codec_write_cache(codec, pin_nid, 0,
1001 AC_VERB_SET_CONNECT_SEL,
1005 /* get the mux index for the converter of the pins
1006 * converter's mux index is the same for all pins on Intel platform
1008 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1013 for (i = 0; i < spec->num_cvts; i++)
1014 if (spec->cvt_nids[i] == cvt_nid)
1019 /* Intel HDMI workaround to fix audio routing issue:
1020 * For some Intel display codecs, pins share the same connection list.
1021 * So a conveter can be selected by multiple pins and playback on any of these
1022 * pins will generate sound on the external display, because audio flows from
1023 * the same converter to the display pipeline. Also muting one pin may make
1024 * other pins have no sound output.
1025 * So this function assures that an assigned converter for a pin is not selected
1026 * by any other pins.
1028 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1030 int dev_id, int mux_idx)
1032 struct hdmi_spec *spec = codec->spec;
1035 struct hdmi_spec_per_cvt *per_cvt;
1036 struct hdmi_spec_per_pin *per_pin;
1039 /* configure the pins connections */
1040 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1044 per_pin = get_pin(spec, pin_idx);
1046 * pin not connected to monitor
1047 * no need to operate on it
1052 if ((per_pin->pin_nid == pin_nid) &&
1053 (per_pin->dev_id == dev_id))
1057 * if per_pin->dev_id >= dev_num,
1058 * snd_hda_get_dev_select() will fail,
1059 * and the following operation is unpredictable.
1060 * So skip this situation.
1062 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1063 if (per_pin->dev_id >= dev_num)
1066 nid = per_pin->pin_nid;
1069 * Calling this function should not impact
1070 * on the device entry selection
1071 * So let's save the dev id for each pin,
1072 * and restore it when return
1074 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1075 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1076 curr = snd_hda_codec_read(codec, nid, 0,
1077 AC_VERB_GET_CONNECT_SEL, 0);
1078 if (curr != mux_idx) {
1079 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1084 /* choose an unassigned converter. The conveters in the
1085 * connection list are in the same order as in the codec.
1087 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1088 per_cvt = get_cvt(spec, cvt_idx);
1089 if (!per_cvt->assigned) {
1091 "choose cvt %d for pin nid %d\n",
1093 snd_hda_codec_write_cache(codec, nid, 0,
1094 AC_VERB_SET_CONNECT_SEL,
1099 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1103 /* A wrapper of intel_not_share_asigned_cvt() */
1104 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1105 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1108 struct hdmi_spec *spec = codec->spec;
1110 /* On Intel platform, the mapping of converter nid to
1111 * mux index of the pins are always the same.
1112 * The pin nid may be 0, this means all pins will not
1113 * share the converter.
1115 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1117 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1120 /* skeleton caller of pin_cvt_fixup ops */
1121 static void pin_cvt_fixup(struct hda_codec *codec,
1122 struct hdmi_spec_per_pin *per_pin,
1125 struct hdmi_spec *spec = codec->spec;
1127 if (spec->ops.pin_cvt_fixup)
1128 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1131 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1132 * in dyn_pcm_assign mode.
1134 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1135 struct hda_codec *codec,
1136 struct snd_pcm_substream *substream)
1138 struct hdmi_spec *spec = codec->spec;
1139 struct snd_pcm_runtime *runtime = substream->runtime;
1140 int cvt_idx, pcm_idx;
1141 struct hdmi_spec_per_cvt *per_cvt = NULL;
1144 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1148 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1152 per_cvt = get_cvt(spec, cvt_idx);
1153 per_cvt->assigned = 1;
1154 hinfo->nid = per_cvt->cvt_nid;
1156 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1158 set_bit(pcm_idx, &spec->pcm_in_use);
1159 /* todo: setup spdif ctls assign */
1161 /* Initially set the converter's capabilities */
1162 hinfo->channels_min = per_cvt->channels_min;
1163 hinfo->channels_max = per_cvt->channels_max;
1164 hinfo->rates = per_cvt->rates;
1165 hinfo->formats = per_cvt->formats;
1166 hinfo->maxbps = per_cvt->maxbps;
1168 /* Store the updated parameters */
1169 runtime->hw.channels_min = hinfo->channels_min;
1170 runtime->hw.channels_max = hinfo->channels_max;
1171 runtime->hw.formats = hinfo->formats;
1172 runtime->hw.rates = hinfo->rates;
1174 snd_pcm_hw_constraint_step(substream->runtime, 0,
1175 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1182 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1183 struct hda_codec *codec,
1184 struct snd_pcm_substream *substream)
1186 struct hdmi_spec *spec = codec->spec;
1187 struct snd_pcm_runtime *runtime = substream->runtime;
1188 int pin_idx, cvt_idx, pcm_idx;
1189 struct hdmi_spec_per_pin *per_pin;
1190 struct hdmi_eld *eld;
1191 struct hdmi_spec_per_cvt *per_cvt = NULL;
1194 /* Validate hinfo */
1195 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1199 mutex_lock(&spec->pcm_lock);
1200 pin_idx = hinfo_to_pin_index(codec, hinfo);
1201 if (!spec->dyn_pcm_assign) {
1202 if (snd_BUG_ON(pin_idx < 0)) {
1207 /* no pin is assigned to the PCM
1208 * PA need pcm open successfully when probe
1211 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1216 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1220 per_cvt = get_cvt(spec, cvt_idx);
1221 /* Claim converter */
1222 per_cvt->assigned = 1;
1224 set_bit(pcm_idx, &spec->pcm_in_use);
1225 per_pin = get_pin(spec, pin_idx);
1226 per_pin->cvt_nid = per_cvt->cvt_nid;
1227 hinfo->nid = per_cvt->cvt_nid;
1229 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1230 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1231 AC_VERB_SET_CONNECT_SEL,
1234 /* configure unused pins to choose other converters */
1235 pin_cvt_fixup(codec, per_pin, 0);
1237 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1239 /* Initially set the converter's capabilities */
1240 hinfo->channels_min = per_cvt->channels_min;
1241 hinfo->channels_max = per_cvt->channels_max;
1242 hinfo->rates = per_cvt->rates;
1243 hinfo->formats = per_cvt->formats;
1244 hinfo->maxbps = per_cvt->maxbps;
1246 eld = &per_pin->sink_eld;
1247 /* Restrict capabilities by ELD if this isn't disabled */
1248 if (!static_hdmi_pcm && eld->eld_valid) {
1249 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1250 if (hinfo->channels_min > hinfo->channels_max ||
1251 !hinfo->rates || !hinfo->formats) {
1252 per_cvt->assigned = 0;
1254 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1260 /* Store the updated parameters */
1261 runtime->hw.channels_min = hinfo->channels_min;
1262 runtime->hw.channels_max = hinfo->channels_max;
1263 runtime->hw.formats = hinfo->formats;
1264 runtime->hw.rates = hinfo->rates;
1266 snd_pcm_hw_constraint_step(substream->runtime, 0,
1267 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1269 mutex_unlock(&spec->pcm_lock);
1274 * HDA/HDMI auto parsing
1276 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1278 struct hdmi_spec *spec = codec->spec;
1279 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1280 hda_nid_t pin_nid = per_pin->pin_nid;
1282 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1284 "HDMI: pin %d wcaps %#x does not support connection list\n",
1285 pin_nid, get_wcaps(codec, pin_nid));
1289 /* all the device entries on the same pin have the same conn list */
1290 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1292 HDA_MAX_CONNECTIONS);
1297 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1298 struct hdmi_spec_per_pin *per_pin)
1302 /* try the prefer PCM */
1303 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1304 return per_pin->pin_nid_idx;
1306 /* have a second try; check the "reserved area" over num_pins */
1307 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1308 if (!test_bit(i, &spec->pcm_bitmap))
1312 /* the last try; check the empty slots in pins */
1313 for (i = 0; i < spec->num_nids; i++) {
1314 if (!test_bit(i, &spec->pcm_bitmap))
1320 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1321 struct hdmi_spec_per_pin *per_pin)
1325 /* pcm already be attached to the pin */
1328 idx = hdmi_find_pcm_slot(spec, per_pin);
1331 per_pin->pcm_idx = idx;
1332 per_pin->pcm = get_hdmi_pcm(spec, idx);
1333 set_bit(idx, &spec->pcm_bitmap);
1336 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1337 struct hdmi_spec_per_pin *per_pin)
1341 /* pcm already be detached from the pin */
1344 idx = per_pin->pcm_idx;
1345 per_pin->pcm_idx = -1;
1346 per_pin->pcm = NULL;
1347 if (idx >= 0 && idx < spec->pcm_used)
1348 clear_bit(idx, &spec->pcm_bitmap);
1351 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1352 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1356 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1357 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1362 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1364 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1365 struct hdmi_spec_per_pin *per_pin)
1367 struct hda_codec *codec = per_pin->codec;
1368 struct hda_pcm *pcm;
1369 struct hda_pcm_stream *hinfo;
1370 struct snd_pcm_substream *substream;
1374 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1375 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1380 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1383 /* hdmi audio only uses playback and one substream */
1384 hinfo = pcm->stream;
1385 substream = pcm->pcm->streams[0].substream;
1387 per_pin->cvt_nid = hinfo->nid;
1389 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1390 if (mux_idx < per_pin->num_mux_nids) {
1391 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1393 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1394 AC_VERB_SET_CONNECT_SEL,
1397 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1399 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1400 if (substream->runtime)
1401 per_pin->channels = substream->runtime->channels;
1402 per_pin->setup = true;
1403 per_pin->mux_idx = mux_idx;
1405 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1408 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1409 struct hdmi_spec_per_pin *per_pin)
1411 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1412 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1414 per_pin->chmap_set = false;
1415 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1417 per_pin->setup = false;
1418 per_pin->channels = 0;
1421 /* update per_pin ELD from the given new ELD;
1422 * setup info frame and notification accordingly
1424 static void update_eld(struct hda_codec *codec,
1425 struct hdmi_spec_per_pin *per_pin,
1426 struct hdmi_eld *eld)
1428 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1429 struct hdmi_spec *spec = codec->spec;
1430 bool old_eld_valid = pin_eld->eld_valid;
1434 /* for monitor disconnection, save pcm_idx firstly */
1435 pcm_idx = per_pin->pcm_idx;
1436 if (spec->dyn_pcm_assign) {
1437 if (eld->eld_valid) {
1438 hdmi_attach_hda_pcm(spec, per_pin);
1439 hdmi_pcm_setup_pin(spec, per_pin);
1441 hdmi_pcm_reset_pin(spec, per_pin);
1442 hdmi_detach_hda_pcm(spec, per_pin);
1445 /* if pcm_idx == -1, it means this is in monitor connection event
1446 * we can get the correct pcm_idx now.
1449 pcm_idx = per_pin->pcm_idx;
1452 snd_hdmi_show_eld(codec, &eld->info);
1454 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1455 if (eld->eld_valid && pin_eld->eld_valid)
1456 if (pin_eld->eld_size != eld->eld_size ||
1457 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1458 eld->eld_size) != 0)
1461 pin_eld->monitor_present = eld->monitor_present;
1462 pin_eld->eld_valid = eld->eld_valid;
1463 pin_eld->eld_size = eld->eld_size;
1465 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1466 pin_eld->info = eld->info;
1469 * Re-setup pin and infoframe. This is needed e.g. when
1470 * - sink is first plugged-in
1471 * - transcoder can change during stream playback on Haswell
1472 * and this can make HW reset converter selection on a pin.
1474 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1475 pin_cvt_fixup(codec, per_pin, 0);
1476 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1479 if (eld_changed && pcm_idx >= 0)
1480 snd_ctl_notify(codec->card,
1481 SNDRV_CTL_EVENT_MASK_VALUE |
1482 SNDRV_CTL_EVENT_MASK_INFO,
1483 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1486 /* update ELD and jack state via HD-audio verbs */
1487 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1490 struct hda_jack_tbl *jack;
1491 struct hda_codec *codec = per_pin->codec;
1492 struct hdmi_spec *spec = codec->spec;
1493 struct hdmi_eld *eld = &spec->temp_eld;
1494 hda_nid_t pin_nid = per_pin->pin_nid;
1496 * Always execute a GetPinSense verb here, even when called from
1497 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1498 * response's PD bit is not the real PD value, but indicates that
1499 * the real PD value changed. An older version of the HD-audio
1500 * specification worked this way. Hence, we just ignore the data in
1501 * the unsolicited response to avoid custom WARs.
1505 bool do_repoll = false;
1507 present = snd_hda_pin_sense(codec, pin_nid);
1509 mutex_lock(&per_pin->lock);
1510 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1511 if (eld->monitor_present)
1512 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1514 eld->eld_valid = false;
1517 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1518 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1520 if (eld->eld_valid) {
1521 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1522 &eld->eld_size) < 0)
1523 eld->eld_valid = false;
1525 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1527 eld->eld_valid = false;
1529 if (!eld->eld_valid && repoll)
1534 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1536 update_eld(codec, per_pin, eld);
1538 ret = !repoll || !eld->monitor_present || eld->eld_valid;
1540 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1542 jack->block_report = !ret;
1543 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ?
1544 AC_PINSENSE_PRESENCE : 0;
1546 mutex_unlock(&per_pin->lock);
1550 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1551 struct hdmi_spec_per_pin *per_pin)
1553 struct hdmi_spec *spec = codec->spec;
1554 struct snd_jack *jack = NULL;
1555 struct hda_jack_tbl *jack_tbl;
1557 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1558 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1559 * NULL even after snd_hda_jack_tbl_clear() is called to
1560 * free snd_jack. This may cause access invalid memory
1561 * when calling snd_jack_report
1563 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1564 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1565 else if (!spec->dyn_pcm_assign) {
1567 * jack tbl doesn't support DP MST
1568 * DP MST will use dyn_pcm_assign,
1569 * so DP MST will never come here
1571 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1573 jack = jack_tbl->jack;
1578 /* update ELD and jack state via audio component */
1579 static void sync_eld_via_acomp(struct hda_codec *codec,
1580 struct hdmi_spec_per_pin *per_pin)
1582 struct hdmi_spec *spec = codec->spec;
1583 struct hdmi_eld *eld = &spec->temp_eld;
1584 struct snd_jack *jack = NULL;
1587 mutex_lock(&per_pin->lock);
1588 eld->monitor_present = false;
1589 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1590 per_pin->dev_id, &eld->monitor_present,
1591 eld->eld_buffer, ELD_MAX_SIZE);
1593 size = min(size, ELD_MAX_SIZE);
1594 if (snd_hdmi_parse_eld(codec, &eld->info,
1595 eld->eld_buffer, size) < 0)
1600 eld->eld_valid = true;
1601 eld->eld_size = size;
1603 eld->eld_valid = false;
1607 /* pcm_idx >=0 before update_eld() means it is in monitor
1608 * disconnected event. Jack must be fetched before update_eld()
1610 jack = pin_idx_to_jack(codec, per_pin);
1611 update_eld(codec, per_pin, eld);
1613 jack = pin_idx_to_jack(codec, per_pin);
1616 snd_jack_report(jack,
1617 eld->monitor_present ? SND_JACK_AVOUT : 0);
1619 mutex_unlock(&per_pin->lock);
1622 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1624 struct hda_codec *codec = per_pin->codec;
1627 /* no temporary power up/down needed for component notifier */
1628 if (!codec_has_acomp(codec)) {
1629 ret = snd_hda_power_up_pm(codec);
1630 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) {
1631 snd_hda_power_down_pm(codec);
1636 if (codec_has_acomp(codec)) {
1637 sync_eld_via_acomp(codec, per_pin);
1638 ret = false; /* don't call snd_hda_jack_report_sync() */
1640 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1643 if (!codec_has_acomp(codec))
1644 snd_hda_power_down_pm(codec);
1649 static void hdmi_repoll_eld(struct work_struct *work)
1651 struct hdmi_spec_per_pin *per_pin =
1652 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1653 struct hda_codec *codec = per_pin->codec;
1654 struct hdmi_spec *spec = codec->spec;
1655 struct hda_jack_tbl *jack;
1657 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1659 jack->jack_dirty = 1;
1661 if (per_pin->repoll_count++ > 6)
1662 per_pin->repoll_count = 0;
1664 mutex_lock(&spec->pcm_lock);
1665 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1666 snd_hda_jack_report_sync(per_pin->codec);
1667 mutex_unlock(&spec->pcm_lock);
1670 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1673 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1675 struct hdmi_spec *spec = codec->spec;
1676 unsigned int caps, config;
1678 struct hdmi_spec_per_pin *per_pin;
1682 caps = snd_hda_query_pin_caps(codec, pin_nid);
1683 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1687 * For DP MST audio, Configuration Default is the same for
1688 * all device entries on the same pin
1690 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1691 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1695 * To simplify the implementation, malloc all
1696 * the virtual pins in the initialization statically
1698 if (is_haswell_plus(codec)) {
1700 * On Intel platforms, device entries number is
1701 * changed dynamically. If there is a DP MST
1702 * hub connected, the device entries number is 3.
1703 * Otherwise, it is 1.
1704 * Here we manually set dev_num to 3, so that
1705 * we can initialize all the device entries when
1706 * bootup statically.
1710 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1711 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1713 * spec->dev_num is the maxinum number of device entries
1714 * among all the pins
1716 spec->dev_num = (spec->dev_num > dev_num) ?
1717 spec->dev_num : dev_num;
1720 * If the platform doesn't support DP MST,
1721 * manually set dev_num to 1. This means
1722 * the pin has only one device entry.
1728 for (i = 0; i < dev_num; i++) {
1729 pin_idx = spec->num_pins;
1730 per_pin = snd_array_new(&spec->pins);
1735 if (spec->dyn_pcm_assign) {
1736 per_pin->pcm = NULL;
1737 per_pin->pcm_idx = -1;
1739 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1740 per_pin->pcm_idx = pin_idx;
1742 per_pin->pin_nid = pin_nid;
1743 per_pin->pin_nid_idx = spec->num_nids;
1744 per_pin->dev_id = i;
1745 per_pin->non_pcm = false;
1746 snd_hda_set_dev_select(codec, pin_nid, i);
1747 if (is_haswell_plus(codec))
1748 intel_haswell_fixup_connect_list(codec, pin_nid);
1749 err = hdmi_read_pin_conn(codec, pin_idx);
1759 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1761 struct hdmi_spec *spec = codec->spec;
1762 struct hdmi_spec_per_cvt *per_cvt;
1766 chans = get_wcaps(codec, cvt_nid);
1767 chans = get_wcaps_channels(chans);
1769 per_cvt = snd_array_new(&spec->cvts);
1773 per_cvt->cvt_nid = cvt_nid;
1774 per_cvt->channels_min = 2;
1776 per_cvt->channels_max = chans;
1777 if (chans > spec->chmap.channels_max)
1778 spec->chmap.channels_max = chans;
1781 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1788 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1789 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1795 static int hdmi_parse_codec(struct hda_codec *codec)
1800 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1801 if (!nid || nodes < 0) {
1802 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1806 for (i = 0; i < nodes; i++, nid++) {
1810 caps = get_wcaps(codec, nid);
1811 type = get_wcaps_type(caps);
1813 if (!(caps & AC_WCAP_DIGITAL))
1817 case AC_WID_AUD_OUT:
1818 hdmi_add_cvt(codec, nid);
1821 hdmi_add_pin(codec, nid);
1831 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1833 struct hda_spdif_out *spdif;
1836 mutex_lock(&codec->spdif_mutex);
1837 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1838 /* Add sanity check to pass klockwork check.
1839 * This should never happen.
1841 if (WARN_ON(spdif == NULL))
1843 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1844 mutex_unlock(&codec->spdif_mutex);
1852 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1853 struct hda_codec *codec,
1854 unsigned int stream_tag,
1855 unsigned int format,
1856 struct snd_pcm_substream *substream)
1858 hda_nid_t cvt_nid = hinfo->nid;
1859 struct hdmi_spec *spec = codec->spec;
1861 struct hdmi_spec_per_pin *per_pin;
1863 struct snd_pcm_runtime *runtime = substream->runtime;
1868 mutex_lock(&spec->pcm_lock);
1869 pin_idx = hinfo_to_pin_index(codec, hinfo);
1870 if (spec->dyn_pcm_assign && pin_idx < 0) {
1871 /* when dyn_pcm_assign and pcm is not bound to a pin
1872 * skip pin setup and return 0 to make audio playback
1875 pin_cvt_fixup(codec, NULL, cvt_nid);
1876 snd_hda_codec_setup_stream(codec, cvt_nid,
1877 stream_tag, 0, format);
1881 if (snd_BUG_ON(pin_idx < 0)) {
1885 per_pin = get_pin(spec, pin_idx);
1886 pin_nid = per_pin->pin_nid;
1888 /* Verify pin:cvt selections to avoid silent audio after S3.
1889 * After S3, the audio driver restores pin:cvt selections
1890 * but this can happen before gfx is ready and such selection
1891 * is overlooked by HW. Thus multiple pins can share a same
1892 * default convertor and mute control will affect each other,
1893 * which can cause a resumed audio playback become silent
1896 pin_cvt_fixup(codec, per_pin, 0);
1898 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1899 /* Todo: add DP1.2 MST audio support later */
1900 if (codec_has_acomp(codec))
1901 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
1904 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1905 mutex_lock(&per_pin->lock);
1906 per_pin->channels = substream->runtime->channels;
1907 per_pin->setup = true;
1909 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
1910 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
1912 snd_hda_codec_write(codec, cvt_nid, 0,
1913 AC_VERB_SET_STRIPE_CONTROL,
1917 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1918 mutex_unlock(&per_pin->lock);
1919 if (spec->dyn_pin_out) {
1920 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1921 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1922 snd_hda_codec_write(codec, pin_nid, 0,
1923 AC_VERB_SET_PIN_WIDGET_CONTROL,
1927 /* snd_hda_set_dev_select() has been called before */
1928 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1929 stream_tag, format);
1931 mutex_unlock(&spec->pcm_lock);
1935 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1936 struct hda_codec *codec,
1937 struct snd_pcm_substream *substream)
1939 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1943 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1944 struct hda_codec *codec,
1945 struct snd_pcm_substream *substream)
1947 struct hdmi_spec *spec = codec->spec;
1948 int cvt_idx, pin_idx, pcm_idx;
1949 struct hdmi_spec_per_cvt *per_cvt;
1950 struct hdmi_spec_per_pin *per_pin;
1955 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1956 if (snd_BUG_ON(pcm_idx < 0))
1958 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1959 if (snd_BUG_ON(cvt_idx < 0))
1961 per_cvt = get_cvt(spec, cvt_idx);
1963 snd_BUG_ON(!per_cvt->assigned);
1964 per_cvt->assigned = 0;
1967 mutex_lock(&spec->pcm_lock);
1968 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1969 clear_bit(pcm_idx, &spec->pcm_in_use);
1970 pin_idx = hinfo_to_pin_index(codec, hinfo);
1971 if (spec->dyn_pcm_assign && pin_idx < 0)
1974 if (snd_BUG_ON(pin_idx < 0)) {
1978 per_pin = get_pin(spec, pin_idx);
1980 if (spec->dyn_pin_out) {
1981 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1982 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1983 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1984 AC_VERB_SET_PIN_WIDGET_CONTROL,
1988 mutex_lock(&per_pin->lock);
1989 per_pin->chmap_set = false;
1990 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1992 per_pin->setup = false;
1993 per_pin->channels = 0;
1994 mutex_unlock(&per_pin->lock);
1996 mutex_unlock(&spec->pcm_lock);
2002 static const struct hda_pcm_ops generic_ops = {
2003 .open = hdmi_pcm_open,
2004 .close = hdmi_pcm_close,
2005 .prepare = generic_hdmi_playback_pcm_prepare,
2006 .cleanup = generic_hdmi_playback_pcm_cleanup,
2009 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2011 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2012 struct hdmi_spec *spec = codec->spec;
2013 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2018 return per_pin->sink_eld.info.spk_alloc;
2021 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2022 unsigned char *chmap)
2024 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2025 struct hdmi_spec *spec = codec->spec;
2026 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2028 /* chmap is already set to 0 in caller */
2032 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2035 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2036 unsigned char *chmap, int prepared)
2038 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2039 struct hdmi_spec *spec = codec->spec;
2040 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2044 mutex_lock(&per_pin->lock);
2045 per_pin->chmap_set = true;
2046 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2048 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2049 mutex_unlock(&per_pin->lock);
2052 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2054 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2055 struct hdmi_spec *spec = codec->spec;
2056 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2058 return per_pin ? true:false;
2061 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2063 struct hdmi_spec *spec = codec->spec;
2067 * for non-mst mode, pcm number is the same as before
2068 * for DP MST mode, pcm number is (nid number + dev_num - 1)
2069 * dev_num is the device entry number in a pin
2072 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
2073 struct hda_pcm *info;
2074 struct hda_pcm_stream *pstr;
2076 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2080 spec->pcm_rec[idx].pcm = info;
2082 info->pcm_type = HDA_PCM_TYPE_HDMI;
2083 info->own_chmap = true;
2085 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2086 pstr->substreams = 1;
2087 pstr->ops = generic_ops;
2088 /* pcm number is less than 16 */
2089 if (spec->pcm_used >= 16)
2091 /* other pstr fields are set in open */
2097 static void free_hdmi_jack_priv(struct snd_jack *jack)
2099 struct hdmi_pcm *pcm = jack->private_data;
2104 static int add_hdmi_jack_kctl(struct hda_codec *codec,
2105 struct hdmi_spec *spec,
2109 struct snd_jack *jack;
2112 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2117 spec->pcm_rec[pcm_idx].jack = jack;
2118 jack->private_data = &spec->pcm_rec[pcm_idx];
2119 jack->private_free = free_hdmi_jack_priv;
2123 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2125 char hdmi_str[32] = "HDMI/DP";
2126 struct hdmi_spec *spec = codec->spec;
2127 struct hdmi_spec_per_pin *per_pin;
2128 struct hda_jack_tbl *jack;
2129 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2134 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2136 if (spec->dyn_pcm_assign)
2137 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2139 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2140 /* if !dyn_pcm_assign, it must be non-MST mode.
2141 * This means pcms and pins are statically mapped.
2142 * And pcm_idx is pin_idx.
2144 per_pin = get_pin(spec, pcm_idx);
2145 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2147 strncat(hdmi_str, " Phantom",
2148 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2149 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2150 phantom_jack, 0, NULL);
2153 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2156 /* assign jack->jack to pcm_rec[].jack to
2157 * align with dyn_pcm_assign mode
2159 spec->pcm_rec[pcm_idx].jack = jack->jack;
2163 static int generic_hdmi_build_controls(struct hda_codec *codec)
2165 struct hdmi_spec *spec = codec->spec;
2167 int pin_idx, pcm_idx;
2169 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2170 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2171 /* no PCM: mark this for skipping permanently */
2172 set_bit(pcm_idx, &spec->pcm_bitmap);
2176 err = generic_hdmi_build_jack(codec, pcm_idx);
2180 /* create the spdif for each pcm
2181 * pin will be bound when monitor is connected
2183 if (spec->dyn_pcm_assign)
2184 err = snd_hda_create_dig_out_ctls(codec,
2185 0, spec->cvt_nids[0],
2188 struct hdmi_spec_per_pin *per_pin =
2189 get_pin(spec, pcm_idx);
2190 err = snd_hda_create_dig_out_ctls(codec,
2192 per_pin->mux_nids[0],
2197 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2199 dev = get_pcm_rec(spec, pcm_idx)->device;
2200 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2201 /* add control for ELD Bytes */
2202 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2208 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2209 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2211 hdmi_present_sense(per_pin, 0);
2214 /* add channel maps */
2215 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2216 struct hda_pcm *pcm;
2218 pcm = get_pcm_rec(spec, pcm_idx);
2219 if (!pcm || !pcm->pcm)
2221 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2229 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2231 struct hdmi_spec *spec = codec->spec;
2234 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2235 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2237 per_pin->codec = codec;
2238 mutex_init(&per_pin->lock);
2239 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2240 eld_proc_new(per_pin, pin_idx);
2245 static int generic_hdmi_init(struct hda_codec *codec)
2247 struct hdmi_spec *spec = codec->spec;
2250 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2251 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2252 hda_nid_t pin_nid = per_pin->pin_nid;
2253 int dev_id = per_pin->dev_id;
2255 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2256 hdmi_init_pin(codec, pin_nid);
2257 if (!codec_has_acomp(codec))
2258 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2259 codec->jackpoll_interval > 0 ?
2260 jack_callback : NULL);
2265 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2267 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2268 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2271 static void hdmi_array_free(struct hdmi_spec *spec)
2273 snd_array_free(&spec->pins);
2274 snd_array_free(&spec->cvts);
2277 static void generic_spec_free(struct hda_codec *codec)
2279 struct hdmi_spec *spec = codec->spec;
2282 hdmi_array_free(spec);
2286 codec->dp_mst = false;
2289 static void generic_hdmi_free(struct hda_codec *codec)
2291 struct hdmi_spec *spec = codec->spec;
2292 int pin_idx, pcm_idx;
2294 if (codec_has_acomp(codec))
2295 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2297 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2298 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2299 cancel_delayed_work_sync(&per_pin->work);
2300 eld_proc_free(per_pin);
2303 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2304 if (spec->pcm_rec[pcm_idx].jack == NULL)
2306 if (spec->dyn_pcm_assign)
2307 snd_device_free(codec->card,
2308 spec->pcm_rec[pcm_idx].jack);
2310 spec->pcm_rec[pcm_idx].jack = NULL;
2313 generic_spec_free(codec);
2317 static int generic_hdmi_resume(struct hda_codec *codec)
2319 struct hdmi_spec *spec = codec->spec;
2322 codec->patch_ops.init(codec);
2323 regcache_sync(codec->core.regmap);
2325 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2326 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2327 hdmi_present_sense(per_pin, 1);
2333 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2334 .init = generic_hdmi_init,
2335 .free = generic_hdmi_free,
2336 .build_pcms = generic_hdmi_build_pcms,
2337 .build_controls = generic_hdmi_build_controls,
2338 .unsol_event = hdmi_unsol_event,
2340 .resume = generic_hdmi_resume,
2344 static const struct hdmi_ops generic_standard_hdmi_ops = {
2345 .pin_get_eld = snd_hdmi_get_eld,
2346 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2347 .pin_hbr_setup = hdmi_pin_hbr_setup,
2348 .setup_stream = hdmi_setup_stream,
2351 /* allocate codec->spec and assign/initialize generic parser ops */
2352 static int alloc_generic_hdmi(struct hda_codec *codec)
2354 struct hdmi_spec *spec;
2356 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2360 spec->ops = generic_standard_hdmi_ops;
2361 spec->dev_num = 1; /* initialize to 1 */
2362 mutex_init(&spec->pcm_lock);
2363 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2365 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2366 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2367 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2368 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2371 hdmi_array_init(spec, 4);
2373 codec->patch_ops = generic_hdmi_patch_ops;
2378 /* generic HDMI parser */
2379 static int patch_generic_hdmi(struct hda_codec *codec)
2383 err = alloc_generic_hdmi(codec);
2387 err = hdmi_parse_codec(codec);
2389 generic_spec_free(codec);
2393 generic_hdmi_init_per_pins(codec);
2398 * Intel codec parsers and helpers
2401 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2404 struct hdmi_spec *spec = codec->spec;
2408 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2409 if (nconns == spec->num_cvts &&
2410 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2413 /* override pins connection list */
2414 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2415 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2418 #define INTEL_GET_VENDOR_VERB 0xf81
2419 #define INTEL_GET_VENDOR_VERB 0xf81
2420 #define INTEL_SET_VENDOR_VERB 0x781
2421 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2422 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2424 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2427 unsigned int vendor_param;
2428 struct hdmi_spec *spec = codec->spec;
2430 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2431 INTEL_GET_VENDOR_VERB, 0);
2432 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2435 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2436 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2437 INTEL_SET_VENDOR_VERB, vendor_param);
2438 if (vendor_param == -1)
2442 snd_hda_codec_update_widgets(codec);
2445 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2447 unsigned int vendor_param;
2448 struct hdmi_spec *spec = codec->spec;
2450 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2451 INTEL_GET_VENDOR_VERB, 0);
2452 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2455 /* enable DP1.2 mode */
2456 vendor_param |= INTEL_EN_DP12;
2457 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2458 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2459 INTEL_SET_VENDOR_VERB, vendor_param);
2462 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2463 * Otherwise you may get severe h/w communication errors.
2465 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2466 unsigned int power_state)
2468 if (power_state == AC_PWRST_D0) {
2469 intel_haswell_enable_all_pins(codec, false);
2470 intel_haswell_fixup_enable_dp12(codec);
2473 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2474 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2477 /* There is a fixed mapping between audio pin node and display port.
2478 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2479 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2480 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2481 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2484 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2485 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2486 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2488 static int intel_base_nid(struct hda_codec *codec)
2490 switch (codec->core.vendor_id) {
2491 case 0x80860054: /* ILK */
2492 case 0x80862804: /* ILK */
2493 case 0x80862882: /* VLV */
2500 static int intel_pin2port(void *audio_ptr, int pin_nid)
2502 struct hda_codec *codec = audio_ptr;
2503 struct hdmi_spec *spec = codec->spec;
2506 if (!spec->port_num) {
2507 base_nid = intel_base_nid(codec);
2508 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2510 return pin_nid - base_nid + 1; /* intel port is 1-based */
2514 * looking for the pin number in the mapping table and return
2515 * the index which indicate the port number
2517 for (i = 0; i < spec->port_num; i++) {
2518 if (pin_nid == spec->port_map[i])
2522 /* return -1 if pin number exceeds our expectation */
2523 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid);
2527 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2529 struct hda_codec *codec = audio_ptr;
2533 /* we assume only from port-B to port-D */
2534 if (port < 1 || port > 3)
2537 pin_nid = port + intel_base_nid(codec) - 1; /* intel port is 1-based */
2539 /* skip notification during system suspend (but not in runtime PM);
2540 * the state will be updated at resume
2542 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2544 /* ditto during suspend/resume process itself */
2545 if (snd_hdac_is_in_pm(&codec->core))
2548 snd_hdac_i915_set_bclk(&codec->bus->core);
2549 check_presence_and_report(codec, pin_nid, dev_id);
2552 /* register i915 component pin_eld_notify callback */
2553 static void register_i915_notifier(struct hda_codec *codec)
2555 struct hdmi_spec *spec = codec->spec;
2557 spec->use_acomp_notifier = true;
2558 spec->drm_audio_ops.audio_ptr = codec;
2559 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2560 * will call pin_eld_notify with using audio_ptr pointer
2561 * We need make sure audio_ptr is really setup
2564 spec->drm_audio_ops.pin2port = intel_pin2port;
2565 spec->drm_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2566 snd_hdac_acomp_register_notifier(&codec->bus->core,
2567 &spec->drm_audio_ops);
2570 /* setup_stream ops override for HSW+ */
2571 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2572 hda_nid_t pin_nid, u32 stream_tag, int format)
2574 haswell_verify_D0(codec, cvt_nid, pin_nid);
2575 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2578 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2579 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2580 struct hdmi_spec_per_pin *per_pin,
2584 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2586 intel_verify_pin_cvt_connect(codec, per_pin);
2587 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2588 per_pin->dev_id, per_pin->mux_idx);
2590 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2594 /* precondition and allocation for Intel codecs */
2595 static int alloc_intel_hdmi(struct hda_codec *codec)
2597 /* requires i915 binding */
2598 if (!codec->bus->core.audio_component) {
2599 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2600 /* set probe_id here to prevent generic fallback binding */
2601 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
2605 return alloc_generic_hdmi(codec);
2608 /* parse and post-process for Intel codecs */
2609 static int parse_intel_hdmi(struct hda_codec *codec)
2613 err = hdmi_parse_codec(codec);
2615 generic_spec_free(codec);
2619 generic_hdmi_init_per_pins(codec);
2620 register_i915_notifier(codec);
2624 /* Intel Haswell and onwards; audio component with eld notifier */
2625 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
2626 const int *port_map, int port_num)
2628 struct hdmi_spec *spec;
2631 err = alloc_intel_hdmi(codec);
2635 codec->dp_mst = true;
2636 spec->dyn_pcm_assign = true;
2637 spec->vendor_nid = vendor_nid;
2638 spec->port_map = port_map;
2639 spec->port_num = port_num;
2641 intel_haswell_enable_all_pins(codec, true);
2642 intel_haswell_fixup_enable_dp12(codec);
2644 codec->display_power_control = 1;
2646 codec->patch_ops.set_power_state = haswell_set_power_state;
2647 codec->depop_delay = 0;
2648 codec->auto_runtime_pm = 1;
2650 spec->ops.setup_stream = i915_hsw_setup_stream;
2651 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2653 return parse_intel_hdmi(codec);
2656 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2658 return intel_hsw_common_init(codec, 0x08, NULL, 0);
2661 static int patch_i915_glk_hdmi(struct hda_codec *codec)
2663 return intel_hsw_common_init(codec, 0x0b, NULL, 0);
2666 static int patch_i915_icl_hdmi(struct hda_codec *codec)
2669 * pin to port mapping table where the value indicate the pin number and
2670 * the index indicate the port number with 1 base.
2672 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb};
2674 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2677 /* Intel Baytrail and Braswell; with eld notifier */
2678 static int patch_i915_byt_hdmi(struct hda_codec *codec)
2680 struct hdmi_spec *spec;
2683 err = alloc_intel_hdmi(codec);
2688 /* For Valleyview/Cherryview, only the display codec is in the display
2689 * power well and can use link_power ops to request/release the power.
2691 codec->display_power_control = 1;
2693 codec->depop_delay = 0;
2694 codec->auto_runtime_pm = 1;
2696 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2698 return parse_intel_hdmi(codec);
2701 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2702 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2706 err = alloc_intel_hdmi(codec);
2709 return parse_intel_hdmi(codec);
2713 * Shared non-generic implementations
2716 static int simple_playback_build_pcms(struct hda_codec *codec)
2718 struct hdmi_spec *spec = codec->spec;
2719 struct hda_pcm *info;
2721 struct hda_pcm_stream *pstr;
2722 struct hdmi_spec_per_cvt *per_cvt;
2724 per_cvt = get_cvt(spec, 0);
2725 chans = get_wcaps(codec, per_cvt->cvt_nid);
2726 chans = get_wcaps_channels(chans);
2728 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2731 spec->pcm_rec[0].pcm = info;
2732 info->pcm_type = HDA_PCM_TYPE_HDMI;
2733 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2734 *pstr = spec->pcm_playback;
2735 pstr->nid = per_cvt->cvt_nid;
2736 if (pstr->channels_max <= 2 && chans && chans <= 16)
2737 pstr->channels_max = chans;
2742 /* unsolicited event for jack sensing */
2743 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2746 snd_hda_jack_set_dirty_all(codec);
2747 snd_hda_jack_report_sync(codec);
2750 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2751 * as long as spec->pins[] is set correctly
2753 #define simple_hdmi_build_jack generic_hdmi_build_jack
2755 static int simple_playback_build_controls(struct hda_codec *codec)
2757 struct hdmi_spec *spec = codec->spec;
2758 struct hdmi_spec_per_cvt *per_cvt;
2761 per_cvt = get_cvt(spec, 0);
2762 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2767 return simple_hdmi_build_jack(codec, 0);
2770 static int simple_playback_init(struct hda_codec *codec)
2772 struct hdmi_spec *spec = codec->spec;
2773 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2774 hda_nid_t pin = per_pin->pin_nid;
2776 snd_hda_codec_write(codec, pin, 0,
2777 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2778 /* some codecs require to unmute the pin */
2779 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2780 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2782 snd_hda_jack_detect_enable(codec, pin);
2786 static void simple_playback_free(struct hda_codec *codec)
2788 struct hdmi_spec *spec = codec->spec;
2790 hdmi_array_free(spec);
2795 * Nvidia specific implementations
2798 #define Nv_VERB_SET_Channel_Allocation 0xF79
2799 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2800 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2801 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2803 #define nvhdmi_master_con_nid_7x 0x04
2804 #define nvhdmi_master_pin_nid_7x 0x05
2806 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2807 /*front, rear, clfe, rear_surr */
2811 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2812 /* set audio protect on */
2813 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2814 /* enable digital output on pin widget */
2815 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2819 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2820 /* set audio protect on */
2821 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2822 /* enable digital output on pin widget */
2823 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2824 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2825 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2826 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2827 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2831 #ifdef LIMITED_RATE_FMT_SUPPORT
2832 /* support only the safe format and rate */
2833 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2834 #define SUPPORTED_MAXBPS 16
2835 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2837 /* support all rates and formats */
2838 #define SUPPORTED_RATES \
2839 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2840 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2841 SNDRV_PCM_RATE_192000)
2842 #define SUPPORTED_MAXBPS 24
2843 #define SUPPORTED_FORMATS \
2844 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2847 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2849 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2853 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2855 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2859 static const unsigned int channels_2_6_8[] = {
2863 static const unsigned int channels_2_8[] = {
2867 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2868 .count = ARRAY_SIZE(channels_2_6_8),
2869 .list = channels_2_6_8,
2873 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2874 .count = ARRAY_SIZE(channels_2_8),
2875 .list = channels_2_8,
2879 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2880 struct hda_codec *codec,
2881 struct snd_pcm_substream *substream)
2883 struct hdmi_spec *spec = codec->spec;
2884 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2886 switch (codec->preset->vendor_id) {
2891 hw_constraints_channels = &hw_constraints_2_8_channels;
2894 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2900 if (hw_constraints_channels != NULL) {
2901 snd_pcm_hw_constraint_list(substream->runtime, 0,
2902 SNDRV_PCM_HW_PARAM_CHANNELS,
2903 hw_constraints_channels);
2905 snd_pcm_hw_constraint_step(substream->runtime, 0,
2906 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2909 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2912 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2913 struct hda_codec *codec,
2914 struct snd_pcm_substream *substream)
2916 struct hdmi_spec *spec = codec->spec;
2917 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2920 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2921 struct hda_codec *codec,
2922 unsigned int stream_tag,
2923 unsigned int format,
2924 struct snd_pcm_substream *substream)
2926 struct hdmi_spec *spec = codec->spec;
2927 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2928 stream_tag, format, substream);
2931 static const struct hda_pcm_stream simple_pcm_playback = {
2936 .open = simple_playback_pcm_open,
2937 .close = simple_playback_pcm_close,
2938 .prepare = simple_playback_pcm_prepare
2942 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2943 .build_controls = simple_playback_build_controls,
2944 .build_pcms = simple_playback_build_pcms,
2945 .init = simple_playback_init,
2946 .free = simple_playback_free,
2947 .unsol_event = simple_hdmi_unsol_event,
2950 static int patch_simple_hdmi(struct hda_codec *codec,
2951 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2953 struct hdmi_spec *spec;
2954 struct hdmi_spec_per_cvt *per_cvt;
2955 struct hdmi_spec_per_pin *per_pin;
2957 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2962 hdmi_array_init(spec, 1);
2964 spec->multiout.num_dacs = 0; /* no analog */
2965 spec->multiout.max_channels = 2;
2966 spec->multiout.dig_out_nid = cvt_nid;
2969 per_pin = snd_array_new(&spec->pins);
2970 per_cvt = snd_array_new(&spec->cvts);
2971 if (!per_pin || !per_cvt) {
2972 simple_playback_free(codec);
2975 per_cvt->cvt_nid = cvt_nid;
2976 per_pin->pin_nid = pin_nid;
2977 spec->pcm_playback = simple_pcm_playback;
2979 codec->patch_ops = simple_hdmi_patch_ops;
2984 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2987 unsigned int chanmask;
2988 int chan = channels ? (channels - 1) : 1;
3007 /* Set the audio infoframe channel allocation and checksum fields. The
3008 * channel count is computed implicitly by the hardware. */
3009 snd_hda_codec_write(codec, 0x1, 0,
3010 Nv_VERB_SET_Channel_Allocation, chanmask);
3012 snd_hda_codec_write(codec, 0x1, 0,
3013 Nv_VERB_SET_Info_Frame_Checksum,
3014 (0x71 - chan - chanmask));
3017 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3018 struct hda_codec *codec,
3019 struct snd_pcm_substream *substream)
3021 struct hdmi_spec *spec = codec->spec;
3024 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3025 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3026 for (i = 0; i < 4; i++) {
3027 /* set the stream id */
3028 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3029 AC_VERB_SET_CHANNEL_STREAMID, 0);
3030 /* set the stream format */
3031 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3032 AC_VERB_SET_STREAM_FORMAT, 0);
3035 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3036 * streams are disabled. */
3037 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3039 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3042 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3043 struct hda_codec *codec,
3044 unsigned int stream_tag,
3045 unsigned int format,
3046 struct snd_pcm_substream *substream)
3049 unsigned int dataDCC2, channel_id;
3051 struct hdmi_spec *spec = codec->spec;
3052 struct hda_spdif_out *spdif;
3053 struct hdmi_spec_per_cvt *per_cvt;
3055 mutex_lock(&codec->spdif_mutex);
3056 per_cvt = get_cvt(spec, 0);
3057 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3059 chs = substream->runtime->channels;
3063 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3064 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3065 snd_hda_codec_write(codec,
3066 nvhdmi_master_con_nid_7x,
3068 AC_VERB_SET_DIGI_CONVERT_1,
3069 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3071 /* set the stream id */
3072 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3073 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3075 /* set the stream format */
3076 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3077 AC_VERB_SET_STREAM_FORMAT, format);
3079 /* turn on again (if needed) */
3080 /* enable and set the channel status audio/data flag */
3081 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3082 snd_hda_codec_write(codec,
3083 nvhdmi_master_con_nid_7x,
3085 AC_VERB_SET_DIGI_CONVERT_1,
3086 spdif->ctls & 0xff);
3087 snd_hda_codec_write(codec,
3088 nvhdmi_master_con_nid_7x,
3090 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3093 for (i = 0; i < 4; i++) {
3099 /* turn off SPDIF once;
3100 *otherwise the IEC958 bits won't be updated
3102 if (codec->spdif_status_reset &&
3103 (spdif->ctls & AC_DIG1_ENABLE))
3104 snd_hda_codec_write(codec,
3105 nvhdmi_con_nids_7x[i],
3107 AC_VERB_SET_DIGI_CONVERT_1,
3108 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3109 /* set the stream id */
3110 snd_hda_codec_write(codec,
3111 nvhdmi_con_nids_7x[i],
3113 AC_VERB_SET_CHANNEL_STREAMID,
3114 (stream_tag << 4) | channel_id);
3115 /* set the stream format */
3116 snd_hda_codec_write(codec,
3117 nvhdmi_con_nids_7x[i],
3119 AC_VERB_SET_STREAM_FORMAT,
3121 /* turn on again (if needed) */
3122 /* enable and set the channel status audio/data flag */
3123 if (codec->spdif_status_reset &&
3124 (spdif->ctls & AC_DIG1_ENABLE)) {
3125 snd_hda_codec_write(codec,
3126 nvhdmi_con_nids_7x[i],
3128 AC_VERB_SET_DIGI_CONVERT_1,
3129 spdif->ctls & 0xff);
3130 snd_hda_codec_write(codec,
3131 nvhdmi_con_nids_7x[i],
3133 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3137 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3139 mutex_unlock(&codec->spdif_mutex);
3143 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3147 .nid = nvhdmi_master_con_nid_7x,
3148 .rates = SUPPORTED_RATES,
3149 .maxbps = SUPPORTED_MAXBPS,
3150 .formats = SUPPORTED_FORMATS,
3152 .open = simple_playback_pcm_open,
3153 .close = nvhdmi_8ch_7x_pcm_close,
3154 .prepare = nvhdmi_8ch_7x_pcm_prepare
3158 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3160 struct hdmi_spec *spec;
3161 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3162 nvhdmi_master_pin_nid_7x);
3166 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3167 /* override the PCM rates, etc, as the codec doesn't give full list */
3169 spec->pcm_playback.rates = SUPPORTED_RATES;
3170 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3171 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3175 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3177 struct hdmi_spec *spec = codec->spec;
3178 int err = simple_playback_build_pcms(codec);
3180 struct hda_pcm *info = get_pcm_rec(spec, 0);
3181 info->own_chmap = true;
3186 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3188 struct hdmi_spec *spec = codec->spec;
3189 struct hda_pcm *info;
3190 struct snd_pcm_chmap *chmap;
3193 err = simple_playback_build_controls(codec);
3197 /* add channel maps */
3198 info = get_pcm_rec(spec, 0);
3199 err = snd_pcm_add_chmap_ctls(info->pcm,
3200 SNDRV_PCM_STREAM_PLAYBACK,
3201 snd_pcm_alt_chmaps, 8, 0, &chmap);
3204 switch (codec->preset->vendor_id) {
3209 chmap->channel_mask = (1U << 2) | (1U << 8);
3212 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3217 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3219 struct hdmi_spec *spec;
3220 int err = patch_nvhdmi_2ch(codec);
3224 spec->multiout.max_channels = 8;
3225 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3226 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3227 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3228 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3230 /* Initialize the audio infoframe channel mask and checksum to something
3232 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3238 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3242 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3243 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3245 if (cap->ca_index == 0x00 && channels == 2)
3246 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3248 /* If the speaker allocation matches the channel count, it is OK. */
3249 if (cap->channels != channels)
3252 /* all channels are remappable freely */
3253 return SNDRV_CTL_TLVT_CHMAP_VAR;
3256 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3257 int ca, int chs, unsigned char *map)
3259 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3265 static int patch_nvhdmi(struct hda_codec *codec)
3267 struct hdmi_spec *spec;
3270 err = patch_generic_hdmi(codec);
3275 spec->dyn_pin_out = true;
3277 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3278 nvhdmi_chmap_cea_alloc_validate_get_type;
3279 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3285 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3286 * accessed using vendor-defined verbs. These registers can be used for
3287 * interoperability between the HDA and HDMI drivers.
3290 /* Audio Function Group node */
3291 #define NVIDIA_AFG_NID 0x01
3294 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3295 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3296 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3297 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3298 * additional bit (at position 30) to signal the validity of the format.
3300 * | 31 | 30 | 29 16 | 15 0 |
3301 * +---------+-------+--------+--------+
3302 * | TRIGGER | VALID | UNUSED | FORMAT |
3303 * +-----------------------------------|
3305 * Note that for the trigger bit to take effect it needs to change value
3306 * (i.e. it needs to be toggled).
3308 #define NVIDIA_GET_SCRATCH0 0xfa6
3309 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3310 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3311 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3312 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3313 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3314 #define NVIDIA_SCRATCH_VALID (1 << 6)
3316 #define NVIDIA_GET_SCRATCH1 0xfab
3317 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3318 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3319 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3320 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3323 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3324 * the format is invalidated so that the HDMI codec can be disabled.
3326 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3330 /* bits [31:30] contain the trigger and valid bits */
3331 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3332 NVIDIA_GET_SCRATCH0, 0);
3333 value = (value >> 24) & 0xff;
3335 /* bits [15:0] are used to store the HDA format */
3336 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3337 NVIDIA_SET_SCRATCH0_BYTE0,
3338 (format >> 0) & 0xff);
3339 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3340 NVIDIA_SET_SCRATCH0_BYTE1,
3341 (format >> 8) & 0xff);
3343 /* bits [16:24] are unused */
3344 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3345 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3348 * Bit 30 signals that the data is valid and hence that HDMI audio can
3352 value &= ~NVIDIA_SCRATCH_VALID;
3354 value |= NVIDIA_SCRATCH_VALID;
3357 * Whenever the trigger bit is toggled, an interrupt is raised in the
3358 * HDMI codec. The HDMI driver will use that as trigger to update its
3361 value ^= NVIDIA_SCRATCH_TRIGGER;
3363 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3364 NVIDIA_SET_SCRATCH0_BYTE3, value);
3367 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3368 struct hda_codec *codec,
3369 unsigned int stream_tag,
3370 unsigned int format,
3371 struct snd_pcm_substream *substream)
3375 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3380 /* notify the HDMI codec of the format change */
3381 tegra_hdmi_set_format(codec, format);
3386 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3387 struct hda_codec *codec,
3388 struct snd_pcm_substream *substream)
3390 /* invalidate the format in the HDMI codec */
3391 tegra_hdmi_set_format(codec, 0);
3393 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3396 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3398 struct hdmi_spec *spec = codec->spec;
3401 for (i = 0; i < spec->num_pins; i++) {
3402 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3404 if (pcm->pcm_type == type)
3411 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3413 struct hda_pcm_stream *stream;
3414 struct hda_pcm *pcm;
3417 err = generic_hdmi_build_pcms(codec);
3421 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3426 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3427 * codec about format changes.
3429 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3430 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3431 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3436 static int patch_tegra_hdmi(struct hda_codec *codec)
3440 err = patch_generic_hdmi(codec);
3444 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3450 * ATI/AMD-specific implementations
3453 #define is_amdhdmi_rev3_or_later(codec) \
3454 ((codec)->core.vendor_id == 0x1002aa01 && \
3455 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3456 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3458 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3459 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3460 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3461 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3462 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3463 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3464 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3465 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3466 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3467 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3468 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3469 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3470 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3471 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3472 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3473 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3474 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3475 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3476 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3477 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3478 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3479 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3480 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3481 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3482 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3484 /* AMD specific HDA cvt verbs */
3485 #define ATI_VERB_SET_RAMP_RATE 0x770
3486 #define ATI_VERB_GET_RAMP_RATE 0xf70
3488 #define ATI_OUT_ENABLE 0x1
3490 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3491 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3493 #define ATI_HBR_CAPABLE 0x01
3494 #define ATI_HBR_ENABLE 0x10
3496 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3497 unsigned char *buf, int *eld_size)
3499 /* call hda_eld.c ATI/AMD-specific function */
3500 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3501 is_amdhdmi_rev3_or_later(codec));
3504 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3505 int active_channels, int conn_type)
3507 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3510 static int atihdmi_paired_swap_fc_lfe(int pos)
3513 * ATI/AMD have automatic FC/LFE swap built-in
3514 * when in pairwise mapping mode.
3518 /* see channel_allocations[].speakers[] */
3527 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3528 int ca, int chs, unsigned char *map)
3530 struct hdac_cea_channel_speaker_allocation *cap;
3533 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3535 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3536 for (i = 0; i < chs; ++i) {
3537 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3539 bool companion_ok = false;
3544 for (j = 0 + i % 2; j < 8; j += 2) {
3545 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3546 if (cap->speakers[chan_idx] == mask) {
3547 /* channel is in a supported position */
3550 if (i % 2 == 0 && i + 1 < chs) {
3551 /* even channel, check the odd companion */
3552 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3553 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3554 int comp_mask_act = cap->speakers[comp_chan_idx];
3556 if (comp_mask_req == comp_mask_act)
3557 companion_ok = true;
3569 i++; /* companion channel already checked */
3575 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3576 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3578 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3580 int ati_channel_setup = 0;
3585 if (!has_amd_full_remap_support(codec)) {
3586 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3588 /* In case this is an odd slot but without stream channel, do not
3589 * disable the slot since the corresponding even slot could have a
3590 * channel. In case neither have a channel, the slot pair will be
3591 * disabled when this function is called for the even slot. */
3592 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3595 hdmi_slot -= hdmi_slot % 2;
3597 if (stream_channel != 0xf)
3598 stream_channel -= stream_channel % 2;
3601 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3603 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3605 if (stream_channel != 0xf)
3606 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3608 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3611 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3612 hda_nid_t pin_nid, int asp_slot)
3614 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3615 bool was_odd = false;
3616 int ati_asp_slot = asp_slot;
3618 int ati_channel_setup;
3623 if (!has_amd_full_remap_support(codec)) {
3624 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3625 if (ati_asp_slot % 2 != 0) {
3631 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3633 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3635 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3638 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3641 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3642 struct hdac_chmap *chmap,
3643 struct hdac_cea_channel_speaker_allocation *cap,
3649 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3650 * we need to take that into account (a single channel may take 2
3651 * channel slots if we need to carry a silent channel next to it).
3652 * On Rev3+ AMD codecs this function is not used.
3656 /* We only produce even-numbered channel count TLVs */
3657 if ((channels % 2) != 0)
3660 for (c = 0; c < 7; c += 2) {
3661 if (cap->speakers[c] || cap->speakers[c+1])
3665 if (chanpairs * 2 != channels)
3668 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3671 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3672 struct hdac_cea_channel_speaker_allocation *cap,
3673 unsigned int *chmap, int channels)
3675 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3679 for (c = 7; c >= 0; c--) {
3680 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3681 int spk = cap->speakers[chan];
3683 /* add N/A channel if the companion channel is occupied */
3684 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3685 chmap[count++] = SNDRV_CHMAP_NA;
3690 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3693 WARN_ON(count != channels);
3696 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3699 int hbr_ctl, hbr_ctl_new;
3701 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3702 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3704 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3706 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3709 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3711 hbr_ctl == hbr_ctl_new ? "" : "new-",
3714 if (hbr_ctl != hbr_ctl_new)
3715 snd_hda_codec_write(codec, pin_nid, 0,
3716 ATI_VERB_SET_HBR_CONTROL,
3725 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3726 hda_nid_t pin_nid, u32 stream_tag, int format)
3729 if (is_amdhdmi_rev3_or_later(codec)) {
3730 int ramp_rate = 180; /* default as per AMD spec */
3731 /* disable ramp-up/down for non-pcm as per AMD spec */
3732 if (format & AC_FMT_TYPE_NON_PCM)
3735 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3738 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3742 static int atihdmi_init(struct hda_codec *codec)
3744 struct hdmi_spec *spec = codec->spec;
3747 err = generic_hdmi_init(codec);
3752 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3753 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3755 /* make sure downmix information in infoframe is zero */
3756 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3758 /* enable channel-wise remap mode if supported */
3759 if (has_amd_full_remap_support(codec))
3760 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3761 ATI_VERB_SET_MULTICHANNEL_MODE,
3762 ATI_MULTICHANNEL_MODE_SINGLE);
3768 static int patch_atihdmi(struct hda_codec *codec)
3770 struct hdmi_spec *spec;
3771 struct hdmi_spec_per_cvt *per_cvt;
3774 err = patch_generic_hdmi(codec);
3779 codec->patch_ops.init = atihdmi_init;
3783 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3784 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3785 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3786 spec->ops.setup_stream = atihdmi_setup_stream;
3788 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3789 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3791 if (!has_amd_full_remap_support(codec)) {
3792 /* override to ATI/AMD-specific versions with pairwise mapping */
3793 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3794 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3795 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3796 atihdmi_paired_cea_alloc_to_tlv_chmap;
3797 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3800 /* ATI/AMD converters do not advertise all of their capabilities */
3801 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3802 per_cvt = get_cvt(spec, cvt_idx);
3803 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3804 per_cvt->rates |= SUPPORTED_RATES;
3805 per_cvt->formats |= SUPPORTED_FORMATS;
3806 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3809 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3811 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
3812 * the link-down as is. Tell the core to allow it.
3814 codec->link_down_at_suspend = 1;
3819 /* VIA HDMI Implementation */
3820 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3821 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3823 static int patch_via_hdmi(struct hda_codec *codec)
3825 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3831 static const struct hda_device_id snd_hda_id_hdmi[] = {
3832 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3833 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3834 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3835 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3836 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3837 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3838 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3839 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
3840 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3841 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3842 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
3843 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3844 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3845 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3846 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
3847 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
3848 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3849 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3850 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3851 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3852 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3853 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3854 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3855 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3856 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3857 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3858 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3859 /* 17 is known to be absent */
3860 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3861 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3862 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3863 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3864 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3865 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3866 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3867 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3868 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3869 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
3870 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
3871 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
3872 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
3873 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3874 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3875 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3876 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3877 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3878 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
3879 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
3880 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3881 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
3882 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3883 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
3884 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
3885 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3886 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3887 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3888 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3889 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
3890 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
3891 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
3892 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
3893 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
3894 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3895 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
3896 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
3897 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
3898 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3899 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
3900 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
3901 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
3902 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
3903 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
3904 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
3905 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
3906 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
3907 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
3908 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
3909 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
3910 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3911 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
3912 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3913 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3914 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3915 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3916 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3917 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
3918 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3919 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3920 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3921 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3922 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3923 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
3924 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
3925 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
3926 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
3927 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
3928 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
3929 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
3930 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
3931 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
3932 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3933 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3934 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
3935 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3936 /* special ID for generic HDMI */
3937 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3940 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3942 MODULE_LICENSE("GPL");
3943 MODULE_DESCRIPTION("HDMI HD-audio codec");
3944 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3945 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3946 MODULE_ALIAS("snd-hda-codec-atihdmi");
3948 static struct hda_codec_driver hdmi_driver = {
3949 .id = snd_hda_id_hdmi,
3952 module_hda_codec_driver(hdmi_driver);