3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
12 * Wu Fengguang <wfg@linux.intel.com>
15 * Wu Fengguang <wfg@linux.intel.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include <sound/hdaudio.h>
41 #include <sound/hda_i915.h>
42 #include <sound/hda_chmap.h>
43 #include "hda_codec.h"
44 #include "hda_local.h"
47 static bool static_hdmi_pcm;
48 module_param(static_hdmi_pcm, bool, 0644);
49 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
51 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
52 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
53 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
54 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
55 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
56 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
57 ((codec)->core.vendor_id == 0x80862800))
58 #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
59 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
60 || is_skylake(codec) || is_broxton(codec) \
61 || is_kabylake(codec)) || is_geminilake(codec) \
62 || is_cannonlake(codec)
63 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
64 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
65 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
67 struct hdmi_spec_per_cvt {
70 unsigned int channels_min;
71 unsigned int channels_max;
77 /* max. connections to a widget */
78 #define HDA_MAX_CONNECTIONS 32
80 struct hdmi_spec_per_pin {
83 /* pin idx, different device entries on the same pin use the same idx */
86 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
90 struct hda_codec *codec;
91 struct hdmi_eld sink_eld;
93 struct delayed_work work;
94 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
95 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
97 bool setup; /* the stream has been set up by prepare callback */
98 int channels; /* current number of channels */
100 bool chmap_set; /* channel-map override by ALSA API? */
101 unsigned char chmap[8]; /* ALSA API channel-map */
102 #ifdef CONFIG_SND_PROC_FS
103 struct snd_info_entry *proc_entry;
107 /* operations used by generic code that can be overridden by patches */
109 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
110 unsigned char *buf, int *eld_size);
112 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
113 int ca, int active_channels, int conn_type);
115 /* enable/disable HBR (HD passthrough) */
116 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
118 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
119 hda_nid_t pin_nid, u32 stream_tag, int format);
121 void (*pin_cvt_fixup)(struct hda_codec *codec,
122 struct hdmi_spec_per_pin *per_pin,
128 struct snd_jack *jack;
129 struct snd_kcontrol *eld_ctl;
134 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
135 hda_nid_t cvt_nids[4]; /* only for haswell fix */
138 * num_pins is the number of virtual pins
139 * for example, there are 3 pins, and each pin
140 * has 4 device entries, then the num_pins is 12
144 * num_nids is the number of real pins
145 * In the above example, num_nids is 3
149 * dev_num is the number of device entries
151 * In the above example, dev_num is 4
154 struct snd_array pins; /* struct hdmi_spec_per_pin */
155 struct hdmi_pcm pcm_rec[16];
156 struct mutex pcm_lock;
157 /* pcm_bitmap means which pcms have been assigned to pins*/
158 unsigned long pcm_bitmap;
159 int pcm_used; /* counter of pcm_rec[] */
160 /* bitmap shows whether the pcm is opened in user space
161 * bit 0 means the first playback PCM (PCM3);
162 * bit 1 means the second playback PCM, and so on.
164 unsigned long pcm_in_use;
166 struct hdmi_eld temp_eld;
172 * Non-generic VIA/NVIDIA specific
174 struct hda_multi_out multiout;
175 struct hda_pcm_stream pcm_playback;
177 /* i915/powerwell (Haswell+/Valleyview+) specific */
178 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
179 struct i915_audio_component_audio_ops i915_audio_ops;
181 struct hdac_chmap chmap;
182 hda_nid_t vendor_nid;
185 #ifdef CONFIG_SND_HDA_I915
186 static inline bool codec_has_acomp(struct hda_codec *codec)
188 struct hdmi_spec *spec = codec->spec;
189 return spec->use_acomp_notifier;
192 #define codec_has_acomp(codec) false
195 struct hdmi_audio_infoframe {
202 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
206 u8 LFEPBL01_LSV36_DM_INH7;
209 struct dp_audio_infoframe {
212 u8 ver; /* 0x11 << 2 */
214 u8 CC02_CT47; /* match with HDMI infoframe from this on */
218 u8 LFEPBL01_LSV36_DM_INH7;
221 union audio_infoframe {
222 struct hdmi_audio_infoframe hdmi;
223 struct dp_audio_infoframe dp;
231 #define get_pin(spec, idx) \
232 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
233 #define get_cvt(spec, idx) \
234 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
235 /* obtain hdmi_pcm object assigned to idx */
236 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
237 /* obtain hda_pcm object assigned to idx */
238 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
240 static int pin_id_to_pin_index(struct hda_codec *codec,
241 hda_nid_t pin_nid, int dev_id)
243 struct hdmi_spec *spec = codec->spec;
245 struct hdmi_spec_per_pin *per_pin;
248 * (dev_id == -1) means it is NON-MST pin
249 * return the first virtual pin on this port
254 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
255 per_pin = get_pin(spec, pin_idx);
256 if ((per_pin->pin_nid == pin_nid) &&
257 (per_pin->dev_id == dev_id))
261 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
265 static int hinfo_to_pcm_index(struct hda_codec *codec,
266 struct hda_pcm_stream *hinfo)
268 struct hdmi_spec *spec = codec->spec;
271 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
272 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
275 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
279 static int hinfo_to_pin_index(struct hda_codec *codec,
280 struct hda_pcm_stream *hinfo)
282 struct hdmi_spec *spec = codec->spec;
283 struct hdmi_spec_per_pin *per_pin;
286 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
287 per_pin = get_pin(spec, pin_idx);
289 per_pin->pcm->pcm->stream == hinfo)
293 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
297 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
301 struct hdmi_spec_per_pin *per_pin;
303 for (i = 0; i < spec->num_pins; i++) {
304 per_pin = get_pin(spec, i);
305 if (per_pin->pcm_idx == pcm_idx)
311 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
313 struct hdmi_spec *spec = codec->spec;
316 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
317 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
320 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
324 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
325 struct snd_ctl_elem_info *uinfo)
327 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
328 struct hdmi_spec *spec = codec->spec;
329 struct hdmi_spec_per_pin *per_pin;
330 struct hdmi_eld *eld;
333 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
335 pcm_idx = kcontrol->private_value;
336 mutex_lock(&spec->pcm_lock);
337 per_pin = pcm_idx_to_pin(spec, pcm_idx);
339 /* no pin is bound to the pcm */
341 mutex_unlock(&spec->pcm_lock);
344 eld = &per_pin->sink_eld;
345 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
346 mutex_unlock(&spec->pcm_lock);
351 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
352 struct snd_ctl_elem_value *ucontrol)
354 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
355 struct hdmi_spec *spec = codec->spec;
356 struct hdmi_spec_per_pin *per_pin;
357 struct hdmi_eld *eld;
360 pcm_idx = kcontrol->private_value;
361 mutex_lock(&spec->pcm_lock);
362 per_pin = pcm_idx_to_pin(spec, pcm_idx);
364 /* no pin is bound to the pcm */
365 memset(ucontrol->value.bytes.data, 0,
366 ARRAY_SIZE(ucontrol->value.bytes.data));
367 mutex_unlock(&spec->pcm_lock);
370 eld = &per_pin->sink_eld;
372 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
373 eld->eld_size > ELD_MAX_SIZE) {
374 mutex_unlock(&spec->pcm_lock);
379 memset(ucontrol->value.bytes.data, 0,
380 ARRAY_SIZE(ucontrol->value.bytes.data));
382 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
384 mutex_unlock(&spec->pcm_lock);
389 static const struct snd_kcontrol_new eld_bytes_ctl = {
390 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
391 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
393 .info = hdmi_eld_ctl_info,
394 .get = hdmi_eld_ctl_get,
397 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
400 struct snd_kcontrol *kctl;
401 struct hdmi_spec *spec = codec->spec;
404 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
407 kctl->private_value = pcm_idx;
408 kctl->id.device = device;
410 /* no pin nid is associated with the kctl now
411 * tbd: associate pin nid to eld ctl later
413 err = snd_hda_ctl_add(codec, 0, kctl);
417 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
422 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
423 int *packet_index, int *byte_index)
427 val = snd_hda_codec_read(codec, pin_nid, 0,
428 AC_VERB_GET_HDMI_DIP_INDEX, 0);
430 *packet_index = val >> 5;
431 *byte_index = val & 0x1f;
435 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
436 int packet_index, int byte_index)
440 val = (packet_index << 5) | (byte_index & 0x1f);
442 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
445 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
448 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
451 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
453 struct hdmi_spec *spec = codec->spec;
457 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
458 snd_hda_codec_write(codec, pin_nid, 0,
459 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
461 if (spec->dyn_pin_out)
462 /* Disable pin out until stream is active */
465 /* Enable pin out: some machines with GM965 gets broken output
466 * when the pin is disabled or changed while using with HDMI
470 snd_hda_codec_write(codec, pin_nid, 0,
471 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
478 #ifdef CONFIG_SND_PROC_FS
479 static void print_eld_info(struct snd_info_entry *entry,
480 struct snd_info_buffer *buffer)
482 struct hdmi_spec_per_pin *per_pin = entry->private_data;
484 mutex_lock(&per_pin->lock);
485 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
486 mutex_unlock(&per_pin->lock);
489 static void write_eld_info(struct snd_info_entry *entry,
490 struct snd_info_buffer *buffer)
492 struct hdmi_spec_per_pin *per_pin = entry->private_data;
494 mutex_lock(&per_pin->lock);
495 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
496 mutex_unlock(&per_pin->lock);
499 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
502 struct hda_codec *codec = per_pin->codec;
503 struct snd_info_entry *entry;
506 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
507 err = snd_card_proc_new(codec->card, name, &entry);
511 snd_info_set_text_ops(entry, per_pin, print_eld_info);
512 entry->c.text.write = write_eld_info;
513 entry->mode |= S_IWUSR;
514 per_pin->proc_entry = entry;
519 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
521 if (!per_pin->codec->bus->shutdown) {
522 snd_info_free_entry(per_pin->proc_entry);
523 per_pin->proc_entry = NULL;
527 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
532 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
538 * Audio InfoFrame routines
542 * Enable Audio InfoFrame Transmission
544 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
547 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
548 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
553 * Disable Audio InfoFrame Transmission
555 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
558 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
559 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
563 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
565 #ifdef CONFIG_SND_DEBUG_VERBOSE
569 size = snd_hdmi_get_eld_size(codec, pin_nid);
570 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
572 for (i = 0; i < 8; i++) {
573 size = snd_hda_codec_read(codec, pin_nid, 0,
574 AC_VERB_GET_HDMI_DIP_SIZE, i);
575 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
580 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
586 for (i = 0; i < 8; i++) {
587 size = snd_hda_codec_read(codec, pin_nid, 0,
588 AC_VERB_GET_HDMI_DIP_SIZE, i);
592 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
593 for (j = 1; j < 1000; j++) {
594 hdmi_write_dip_byte(codec, pin_nid, 0x0);
595 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
597 codec_dbg(codec, "dip index %d: %d != %d\n",
599 if (bi == 0) /* byte index wrapped around */
603 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
609 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
611 u8 *bytes = (u8 *)hdmi_ai;
615 hdmi_ai->checksum = 0;
617 for (i = 0; i < sizeof(*hdmi_ai); i++)
620 hdmi_ai->checksum = -sum;
623 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
629 hdmi_debug_dip_size(codec, pin_nid);
630 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
632 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
633 for (i = 0; i < size; i++)
634 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
637 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
643 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
647 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
648 for (i = 0; i < size; i++) {
649 val = snd_hda_codec_read(codec, pin_nid, 0,
650 AC_VERB_GET_HDMI_DIP_DATA, 0);
658 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
660 int ca, int active_channels,
663 union audio_infoframe ai;
665 memset(&ai, 0, sizeof(ai));
666 if (conn_type == 0) { /* HDMI */
667 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
669 hdmi_ai->type = 0x84;
672 hdmi_ai->CC02_CT47 = active_channels - 1;
674 hdmi_checksum_audio_infoframe(hdmi_ai);
675 } else if (conn_type == 1) { /* DisplayPort */
676 struct dp_audio_infoframe *dp_ai = &ai.dp;
680 dp_ai->ver = 0x11 << 2;
681 dp_ai->CC02_CT47 = active_channels - 1;
684 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
690 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
691 * sizeof(*dp_ai) to avoid partial match/update problems when
692 * the user switches between HDMI/DP monitors.
694 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
697 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
699 active_channels, ca);
700 hdmi_stop_infoframe_trans(codec, pin_nid);
701 hdmi_fill_audio_infoframe(codec, pin_nid,
702 ai.bytes, sizeof(ai));
703 hdmi_start_infoframe_trans(codec, pin_nid);
707 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
708 struct hdmi_spec_per_pin *per_pin,
711 struct hdmi_spec *spec = codec->spec;
712 struct hdac_chmap *chmap = &spec->chmap;
713 hda_nid_t pin_nid = per_pin->pin_nid;
714 int channels = per_pin->channels;
716 struct hdmi_eld *eld;
722 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
723 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
724 snd_hda_codec_write(codec, pin_nid, 0,
725 AC_VERB_SET_AMP_GAIN_MUTE,
728 eld = &per_pin->sink_eld;
730 ca = snd_hdac_channel_allocation(&codec->core,
731 eld->info.spk_alloc, channels,
732 per_pin->chmap_set, non_pcm, per_pin->chmap);
734 active_channels = snd_hdac_get_active_channels(ca);
736 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
740 * always configure channel mapping, it may have been changed by the
741 * user in the meantime
743 snd_hdac_setup_channel_mapping(&spec->chmap,
744 pin_nid, non_pcm, ca, channels,
745 per_pin->chmap, per_pin->chmap_set);
747 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
748 eld->info.conn_type);
750 per_pin->non_pcm = non_pcm;
757 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
759 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
762 struct hdmi_spec *spec = codec->spec;
763 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
767 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
768 snd_hda_jack_report_sync(codec);
771 static void jack_callback(struct hda_codec *codec,
772 struct hda_jack_callback *jack)
774 /* hda_jack don't support DP MST */
775 check_presence_and_report(codec, jack->nid, 0);
778 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
780 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
781 struct hda_jack_tbl *jack;
782 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
785 * assume DP MST uses dyn_pcm_assign and acomp and
787 * if DP MST supports unsol event, below code need
790 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
793 jack->jack_dirty = 1;
796 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
797 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
798 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
800 /* hda_jack don't support DP MST */
801 check_presence_and_report(codec, jack->nid, 0);
804 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
806 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
807 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
808 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
809 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
812 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
827 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
829 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
830 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
832 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
833 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
838 hdmi_intrinsic_event(codec, res);
840 hdmi_non_intrinsic_event(codec, res);
843 static void haswell_verify_D0(struct hda_codec *codec,
844 hda_nid_t cvt_nid, hda_nid_t nid)
848 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
849 * thus pins could only choose converter 0 for use. Make sure the
850 * converters are in correct power state */
851 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
852 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
854 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
855 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
858 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
859 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
860 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
868 /* HBR should be Non-PCM, 8 channels */
869 #define is_hbr_format(format) \
870 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
872 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
875 int pinctl, new_pinctl;
877 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
878 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
879 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
882 return hbr ? -EINVAL : 0;
884 new_pinctl = pinctl & ~AC_PINCTL_EPT;
886 new_pinctl |= AC_PINCTL_EPT_HBR;
888 new_pinctl |= AC_PINCTL_EPT_NATIVE;
891 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
893 pinctl == new_pinctl ? "" : "new-",
896 if (pinctl != new_pinctl)
897 snd_hda_codec_write(codec, pin_nid, 0,
898 AC_VERB_SET_PIN_WIDGET_CONTROL,
906 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
907 hda_nid_t pin_nid, u32 stream_tag, int format)
909 struct hdmi_spec *spec = codec->spec;
913 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
916 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
920 if (is_haswell_plus(codec)) {
923 * on recent platforms IEC Coding Type is required for HBR
924 * support, read current Digital Converter settings and set
925 * ICT bitfield if needed.
927 param = snd_hda_codec_read(codec, cvt_nid, 0,
928 AC_VERB_GET_DIGI_CONVERT_1, 0);
930 param = (param >> 16) & ~(AC_DIG3_ICT);
932 /* on recent platforms ICT mode is required for HBR support */
933 if (is_hbr_format(format))
936 snd_hda_codec_write(codec, cvt_nid, 0,
937 AC_VERB_SET_DIGI_CONVERT_3, param);
940 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
944 /* Try to find an available converter
945 * If pin_idx is less then zero, just try to find an available converter.
946 * Otherwise, try to find an available converter and get the cvt mux index
949 static int hdmi_choose_cvt(struct hda_codec *codec,
950 int pin_idx, int *cvt_id)
952 struct hdmi_spec *spec = codec->spec;
953 struct hdmi_spec_per_pin *per_pin;
954 struct hdmi_spec_per_cvt *per_cvt = NULL;
955 int cvt_idx, mux_idx = 0;
957 /* pin_idx < 0 means no pin will be bound to the converter */
961 per_pin = get_pin(spec, pin_idx);
963 /* Dynamically assign converter to stream */
964 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
965 per_cvt = get_cvt(spec, cvt_idx);
967 /* Must not already be assigned */
968 if (per_cvt->assigned)
972 /* Must be in pin's mux's list of converters */
973 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
974 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
976 /* Not in mux list */
977 if (mux_idx == per_pin->num_mux_nids)
982 /* No free converters */
983 if (cvt_idx == spec->num_cvts)
987 per_pin->mux_idx = mux_idx;
995 /* Assure the pin select the right convetor */
996 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
997 struct hdmi_spec_per_pin *per_pin)
999 hda_nid_t pin_nid = per_pin->pin_nid;
1002 mux_idx = per_pin->mux_idx;
1003 curr = snd_hda_codec_read(codec, pin_nid, 0,
1004 AC_VERB_GET_CONNECT_SEL, 0);
1005 if (curr != mux_idx)
1006 snd_hda_codec_write_cache(codec, pin_nid, 0,
1007 AC_VERB_SET_CONNECT_SEL,
1011 /* get the mux index for the converter of the pins
1012 * converter's mux index is the same for all pins on Intel platform
1014 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1019 for (i = 0; i < spec->num_cvts; i++)
1020 if (spec->cvt_nids[i] == cvt_nid)
1025 /* Intel HDMI workaround to fix audio routing issue:
1026 * For some Intel display codecs, pins share the same connection list.
1027 * So a conveter can be selected by multiple pins and playback on any of these
1028 * pins will generate sound on the external display, because audio flows from
1029 * the same converter to the display pipeline. Also muting one pin may make
1030 * other pins have no sound output.
1031 * So this function assures that an assigned converter for a pin is not selected
1032 * by any other pins.
1034 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1036 int dev_id, int mux_idx)
1038 struct hdmi_spec *spec = codec->spec;
1041 struct hdmi_spec_per_cvt *per_cvt;
1042 struct hdmi_spec_per_pin *per_pin;
1045 /* configure the pins connections */
1046 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1050 per_pin = get_pin(spec, pin_idx);
1052 * pin not connected to monitor
1053 * no need to operate on it
1058 if ((per_pin->pin_nid == pin_nid) &&
1059 (per_pin->dev_id == dev_id))
1063 * if per_pin->dev_id >= dev_num,
1064 * snd_hda_get_dev_select() will fail,
1065 * and the following operation is unpredictable.
1066 * So skip this situation.
1068 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1069 if (per_pin->dev_id >= dev_num)
1072 nid = per_pin->pin_nid;
1075 * Calling this function should not impact
1076 * on the device entry selection
1077 * So let's save the dev id for each pin,
1078 * and restore it when return
1080 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1081 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1082 curr = snd_hda_codec_read(codec, nid, 0,
1083 AC_VERB_GET_CONNECT_SEL, 0);
1084 if (curr != mux_idx) {
1085 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1090 /* choose an unassigned converter. The conveters in the
1091 * connection list are in the same order as in the codec.
1093 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1094 per_cvt = get_cvt(spec, cvt_idx);
1095 if (!per_cvt->assigned) {
1097 "choose cvt %d for pin nid %d\n",
1099 snd_hda_codec_write_cache(codec, nid, 0,
1100 AC_VERB_SET_CONNECT_SEL,
1105 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1109 /* A wrapper of intel_not_share_asigned_cvt() */
1110 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1111 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1114 struct hdmi_spec *spec = codec->spec;
1116 /* On Intel platform, the mapping of converter nid to
1117 * mux index of the pins are always the same.
1118 * The pin nid may be 0, this means all pins will not
1119 * share the converter.
1121 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1123 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1126 /* skeleton caller of pin_cvt_fixup ops */
1127 static void pin_cvt_fixup(struct hda_codec *codec,
1128 struct hdmi_spec_per_pin *per_pin,
1131 struct hdmi_spec *spec = codec->spec;
1133 if (spec->ops.pin_cvt_fixup)
1134 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1137 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1138 * in dyn_pcm_assign mode.
1140 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1141 struct hda_codec *codec,
1142 struct snd_pcm_substream *substream)
1144 struct hdmi_spec *spec = codec->spec;
1145 struct snd_pcm_runtime *runtime = substream->runtime;
1146 int cvt_idx, pcm_idx;
1147 struct hdmi_spec_per_cvt *per_cvt = NULL;
1150 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1154 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1158 per_cvt = get_cvt(spec, cvt_idx);
1159 per_cvt->assigned = 1;
1160 hinfo->nid = per_cvt->cvt_nid;
1162 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1164 set_bit(pcm_idx, &spec->pcm_in_use);
1165 /* todo: setup spdif ctls assign */
1167 /* Initially set the converter's capabilities */
1168 hinfo->channels_min = per_cvt->channels_min;
1169 hinfo->channels_max = per_cvt->channels_max;
1170 hinfo->rates = per_cvt->rates;
1171 hinfo->formats = per_cvt->formats;
1172 hinfo->maxbps = per_cvt->maxbps;
1174 /* Store the updated parameters */
1175 runtime->hw.channels_min = hinfo->channels_min;
1176 runtime->hw.channels_max = hinfo->channels_max;
1177 runtime->hw.formats = hinfo->formats;
1178 runtime->hw.rates = hinfo->rates;
1180 snd_pcm_hw_constraint_step(substream->runtime, 0,
1181 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1188 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1189 struct hda_codec *codec,
1190 struct snd_pcm_substream *substream)
1192 struct hdmi_spec *spec = codec->spec;
1193 struct snd_pcm_runtime *runtime = substream->runtime;
1194 int pin_idx, cvt_idx, pcm_idx;
1195 struct hdmi_spec_per_pin *per_pin;
1196 struct hdmi_eld *eld;
1197 struct hdmi_spec_per_cvt *per_cvt = NULL;
1200 /* Validate hinfo */
1201 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1205 mutex_lock(&spec->pcm_lock);
1206 pin_idx = hinfo_to_pin_index(codec, hinfo);
1207 if (!spec->dyn_pcm_assign) {
1208 if (snd_BUG_ON(pin_idx < 0)) {
1209 mutex_unlock(&spec->pcm_lock);
1213 /* no pin is assigned to the PCM
1214 * PA need pcm open successfully when probe
1217 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1218 mutex_unlock(&spec->pcm_lock);
1223 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1225 mutex_unlock(&spec->pcm_lock);
1229 per_cvt = get_cvt(spec, cvt_idx);
1230 /* Claim converter */
1231 per_cvt->assigned = 1;
1233 set_bit(pcm_idx, &spec->pcm_in_use);
1234 per_pin = get_pin(spec, pin_idx);
1235 per_pin->cvt_nid = per_cvt->cvt_nid;
1236 hinfo->nid = per_cvt->cvt_nid;
1238 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1239 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1240 AC_VERB_SET_CONNECT_SEL,
1243 /* configure unused pins to choose other converters */
1244 pin_cvt_fixup(codec, per_pin, 0);
1246 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1248 /* Initially set the converter's capabilities */
1249 hinfo->channels_min = per_cvt->channels_min;
1250 hinfo->channels_max = per_cvt->channels_max;
1251 hinfo->rates = per_cvt->rates;
1252 hinfo->formats = per_cvt->formats;
1253 hinfo->maxbps = per_cvt->maxbps;
1255 eld = &per_pin->sink_eld;
1256 /* Restrict capabilities by ELD if this isn't disabled */
1257 if (!static_hdmi_pcm && eld->eld_valid) {
1258 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1259 if (hinfo->channels_min > hinfo->channels_max ||
1260 !hinfo->rates || !hinfo->formats) {
1261 per_cvt->assigned = 0;
1263 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1264 mutex_unlock(&spec->pcm_lock);
1269 mutex_unlock(&spec->pcm_lock);
1270 /* Store the updated parameters */
1271 runtime->hw.channels_min = hinfo->channels_min;
1272 runtime->hw.channels_max = hinfo->channels_max;
1273 runtime->hw.formats = hinfo->formats;
1274 runtime->hw.rates = hinfo->rates;
1276 snd_pcm_hw_constraint_step(substream->runtime, 0,
1277 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1282 * HDA/HDMI auto parsing
1284 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1286 struct hdmi_spec *spec = codec->spec;
1287 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1288 hda_nid_t pin_nid = per_pin->pin_nid;
1290 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1292 "HDMI: pin %d wcaps %#x does not support connection list\n",
1293 pin_nid, get_wcaps(codec, pin_nid));
1297 /* all the device entries on the same pin have the same conn list */
1298 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1300 HDA_MAX_CONNECTIONS);
1305 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1306 struct hdmi_spec_per_pin *per_pin)
1310 /* try the prefer PCM */
1311 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1312 return per_pin->pin_nid_idx;
1314 /* have a second try; check the "reserved area" over num_pins */
1315 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1316 if (!test_bit(i, &spec->pcm_bitmap))
1320 /* the last try; check the empty slots in pins */
1321 for (i = 0; i < spec->num_nids; i++) {
1322 if (!test_bit(i, &spec->pcm_bitmap))
1328 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1329 struct hdmi_spec_per_pin *per_pin)
1333 /* pcm already be attached to the pin */
1336 idx = hdmi_find_pcm_slot(spec, per_pin);
1339 per_pin->pcm_idx = idx;
1340 per_pin->pcm = get_hdmi_pcm(spec, idx);
1341 set_bit(idx, &spec->pcm_bitmap);
1344 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1345 struct hdmi_spec_per_pin *per_pin)
1349 /* pcm already be detached from the pin */
1352 idx = per_pin->pcm_idx;
1353 per_pin->pcm_idx = -1;
1354 per_pin->pcm = NULL;
1355 if (idx >= 0 && idx < spec->pcm_used)
1356 clear_bit(idx, &spec->pcm_bitmap);
1359 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1360 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1364 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1365 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1370 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1372 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1373 struct hdmi_spec_per_pin *per_pin)
1375 struct hda_codec *codec = per_pin->codec;
1376 struct hda_pcm *pcm;
1377 struct hda_pcm_stream *hinfo;
1378 struct snd_pcm_substream *substream;
1382 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1383 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1386 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1389 /* hdmi audio only uses playback and one substream */
1390 hinfo = pcm->stream;
1391 substream = pcm->pcm->streams[0].substream;
1393 per_pin->cvt_nid = hinfo->nid;
1395 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1396 if (mux_idx < per_pin->num_mux_nids) {
1397 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1399 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1400 AC_VERB_SET_CONNECT_SEL,
1403 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1405 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1406 if (substream->runtime)
1407 per_pin->channels = substream->runtime->channels;
1408 per_pin->setup = true;
1409 per_pin->mux_idx = mux_idx;
1411 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1414 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1415 struct hdmi_spec_per_pin *per_pin)
1417 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1418 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1420 per_pin->chmap_set = false;
1421 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1423 per_pin->setup = false;
1424 per_pin->channels = 0;
1427 /* update per_pin ELD from the given new ELD;
1428 * setup info frame and notification accordingly
1430 static void update_eld(struct hda_codec *codec,
1431 struct hdmi_spec_per_pin *per_pin,
1432 struct hdmi_eld *eld)
1434 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1435 struct hdmi_spec *spec = codec->spec;
1436 bool old_eld_valid = pin_eld->eld_valid;
1440 /* for monitor disconnection, save pcm_idx firstly */
1441 pcm_idx = per_pin->pcm_idx;
1442 if (spec->dyn_pcm_assign) {
1443 if (eld->eld_valid) {
1444 hdmi_attach_hda_pcm(spec, per_pin);
1445 hdmi_pcm_setup_pin(spec, per_pin);
1447 hdmi_pcm_reset_pin(spec, per_pin);
1448 hdmi_detach_hda_pcm(spec, per_pin);
1451 /* if pcm_idx == -1, it means this is in monitor connection event
1452 * we can get the correct pcm_idx now.
1455 pcm_idx = per_pin->pcm_idx;
1458 snd_hdmi_show_eld(codec, &eld->info);
1460 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1461 if (eld->eld_valid && pin_eld->eld_valid)
1462 if (pin_eld->eld_size != eld->eld_size ||
1463 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1464 eld->eld_size) != 0)
1467 pin_eld->monitor_present = eld->monitor_present;
1468 pin_eld->eld_valid = eld->eld_valid;
1469 pin_eld->eld_size = eld->eld_size;
1471 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1472 pin_eld->info = eld->info;
1475 * Re-setup pin and infoframe. This is needed e.g. when
1476 * - sink is first plugged-in
1477 * - transcoder can change during stream playback on Haswell
1478 * and this can make HW reset converter selection on a pin.
1480 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1481 pin_cvt_fixup(codec, per_pin, 0);
1482 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1485 if (eld_changed && pcm_idx >= 0)
1486 snd_ctl_notify(codec->card,
1487 SNDRV_CTL_EVENT_MASK_VALUE |
1488 SNDRV_CTL_EVENT_MASK_INFO,
1489 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1492 /* update ELD and jack state via HD-audio verbs */
1493 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1496 struct hda_jack_tbl *jack;
1497 struct hda_codec *codec = per_pin->codec;
1498 struct hdmi_spec *spec = codec->spec;
1499 struct hdmi_eld *eld = &spec->temp_eld;
1500 hda_nid_t pin_nid = per_pin->pin_nid;
1502 * Always execute a GetPinSense verb here, even when called from
1503 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1504 * response's PD bit is not the real PD value, but indicates that
1505 * the real PD value changed. An older version of the HD-audio
1506 * specification worked this way. Hence, we just ignore the data in
1507 * the unsolicited response to avoid custom WARs.
1511 bool do_repoll = false;
1513 present = snd_hda_pin_sense(codec, pin_nid);
1515 mutex_lock(&per_pin->lock);
1516 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1517 if (eld->monitor_present)
1518 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1520 eld->eld_valid = false;
1523 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1524 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1526 if (eld->eld_valid) {
1527 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1528 &eld->eld_size) < 0)
1529 eld->eld_valid = false;
1531 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1533 eld->eld_valid = false;
1535 if (!eld->eld_valid && repoll)
1540 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1542 update_eld(codec, per_pin, eld);
1544 ret = !repoll || !eld->monitor_present || eld->eld_valid;
1546 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1548 jack->block_report = !ret;
1550 mutex_unlock(&per_pin->lock);
1554 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1555 struct hdmi_spec_per_pin *per_pin)
1557 struct hdmi_spec *spec = codec->spec;
1558 struct snd_jack *jack = NULL;
1559 struct hda_jack_tbl *jack_tbl;
1561 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1562 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1563 * NULL even after snd_hda_jack_tbl_clear() is called to
1564 * free snd_jack. This may cause access invalid memory
1565 * when calling snd_jack_report
1567 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1568 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1569 else if (!spec->dyn_pcm_assign) {
1571 * jack tbl doesn't support DP MST
1572 * DP MST will use dyn_pcm_assign,
1573 * so DP MST will never come here
1575 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1577 jack = jack_tbl->jack;
1582 /* update ELD and jack state via audio component */
1583 static void sync_eld_via_acomp(struct hda_codec *codec,
1584 struct hdmi_spec_per_pin *per_pin)
1586 struct hdmi_spec *spec = codec->spec;
1587 struct hdmi_eld *eld = &spec->temp_eld;
1588 struct snd_jack *jack = NULL;
1591 mutex_lock(&per_pin->lock);
1592 eld->monitor_present = false;
1593 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1594 per_pin->dev_id, &eld->monitor_present,
1595 eld->eld_buffer, ELD_MAX_SIZE);
1597 size = min(size, ELD_MAX_SIZE);
1598 if (snd_hdmi_parse_eld(codec, &eld->info,
1599 eld->eld_buffer, size) < 0)
1604 eld->eld_valid = true;
1605 eld->eld_size = size;
1607 eld->eld_valid = false;
1611 /* pcm_idx >=0 before update_eld() means it is in monitor
1612 * disconnected event. Jack must be fetched before update_eld()
1614 jack = pin_idx_to_jack(codec, per_pin);
1615 update_eld(codec, per_pin, eld);
1617 jack = pin_idx_to_jack(codec, per_pin);
1620 snd_jack_report(jack,
1621 eld->monitor_present ? SND_JACK_AVOUT : 0);
1623 mutex_unlock(&per_pin->lock);
1626 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1628 struct hda_codec *codec = per_pin->codec;
1629 struct hdmi_spec *spec = codec->spec;
1632 /* no temporary power up/down needed for component notifier */
1633 if (!codec_has_acomp(codec))
1634 snd_hda_power_up_pm(codec);
1636 mutex_lock(&spec->pcm_lock);
1637 if (codec_has_acomp(codec)) {
1638 sync_eld_via_acomp(codec, per_pin);
1639 ret = false; /* don't call snd_hda_jack_report_sync() */
1641 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1643 mutex_unlock(&spec->pcm_lock);
1645 if (!codec_has_acomp(codec))
1646 snd_hda_power_down_pm(codec);
1651 static void hdmi_repoll_eld(struct work_struct *work)
1653 struct hdmi_spec_per_pin *per_pin =
1654 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1656 if (per_pin->repoll_count++ > 6)
1657 per_pin->repoll_count = 0;
1659 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1660 snd_hda_jack_report_sync(per_pin->codec);
1663 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1666 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1668 struct hdmi_spec *spec = codec->spec;
1669 unsigned int caps, config;
1671 struct hdmi_spec_per_pin *per_pin;
1675 caps = snd_hda_query_pin_caps(codec, pin_nid);
1676 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1680 * For DP MST audio, Configuration Default is the same for
1681 * all device entries on the same pin
1683 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1684 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1688 * To simplify the implementation, malloc all
1689 * the virtual pins in the initialization statically
1691 if (is_haswell_plus(codec)) {
1693 * On Intel platforms, device entries number is
1694 * changed dynamically. If there is a DP MST
1695 * hub connected, the device entries number is 3.
1696 * Otherwise, it is 1.
1697 * Here we manually set dev_num to 3, so that
1698 * we can initialize all the device entries when
1699 * bootup statically.
1703 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1704 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1706 * spec->dev_num is the maxinum number of device entries
1707 * among all the pins
1709 spec->dev_num = (spec->dev_num > dev_num) ?
1710 spec->dev_num : dev_num;
1713 * If the platform doesn't support DP MST,
1714 * manually set dev_num to 1. This means
1715 * the pin has only one device entry.
1721 for (i = 0; i < dev_num; i++) {
1722 pin_idx = spec->num_pins;
1723 per_pin = snd_array_new(&spec->pins);
1728 if (spec->dyn_pcm_assign) {
1729 per_pin->pcm = NULL;
1730 per_pin->pcm_idx = -1;
1732 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1733 per_pin->pcm_idx = pin_idx;
1735 per_pin->pin_nid = pin_nid;
1736 per_pin->pin_nid_idx = spec->num_nids;
1737 per_pin->dev_id = i;
1738 per_pin->non_pcm = false;
1739 snd_hda_set_dev_select(codec, pin_nid, i);
1740 if (is_haswell_plus(codec))
1741 intel_haswell_fixup_connect_list(codec, pin_nid);
1742 err = hdmi_read_pin_conn(codec, pin_idx);
1752 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1754 struct hdmi_spec *spec = codec->spec;
1755 struct hdmi_spec_per_cvt *per_cvt;
1759 chans = get_wcaps(codec, cvt_nid);
1760 chans = get_wcaps_channels(chans);
1762 per_cvt = snd_array_new(&spec->cvts);
1766 per_cvt->cvt_nid = cvt_nid;
1767 per_cvt->channels_min = 2;
1769 per_cvt->channels_max = chans;
1770 if (chans > spec->chmap.channels_max)
1771 spec->chmap.channels_max = chans;
1774 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1781 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1782 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1788 static int hdmi_parse_codec(struct hda_codec *codec)
1793 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1794 if (!nid || nodes < 0) {
1795 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1799 for (i = 0; i < nodes; i++, nid++) {
1803 caps = get_wcaps(codec, nid);
1804 type = get_wcaps_type(caps);
1806 if (!(caps & AC_WCAP_DIGITAL))
1810 case AC_WID_AUD_OUT:
1811 hdmi_add_cvt(codec, nid);
1814 hdmi_add_pin(codec, nid);
1824 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1826 struct hda_spdif_out *spdif;
1829 mutex_lock(&codec->spdif_mutex);
1830 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1831 /* Add sanity check to pass klockwork check.
1832 * This should never happen.
1834 if (WARN_ON(spdif == NULL))
1836 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1837 mutex_unlock(&codec->spdif_mutex);
1845 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1846 struct hda_codec *codec,
1847 unsigned int stream_tag,
1848 unsigned int format,
1849 struct snd_pcm_substream *substream)
1851 hda_nid_t cvt_nid = hinfo->nid;
1852 struct hdmi_spec *spec = codec->spec;
1854 struct hdmi_spec_per_pin *per_pin;
1856 struct snd_pcm_runtime *runtime = substream->runtime;
1861 mutex_lock(&spec->pcm_lock);
1862 pin_idx = hinfo_to_pin_index(codec, hinfo);
1863 if (spec->dyn_pcm_assign && pin_idx < 0) {
1864 /* when dyn_pcm_assign and pcm is not bound to a pin
1865 * skip pin setup and return 0 to make audio playback
1868 pin_cvt_fixup(codec, NULL, cvt_nid);
1869 snd_hda_codec_setup_stream(codec, cvt_nid,
1870 stream_tag, 0, format);
1871 mutex_unlock(&spec->pcm_lock);
1875 if (snd_BUG_ON(pin_idx < 0)) {
1876 mutex_unlock(&spec->pcm_lock);
1879 per_pin = get_pin(spec, pin_idx);
1880 pin_nid = per_pin->pin_nid;
1882 /* Verify pin:cvt selections to avoid silent audio after S3.
1883 * After S3, the audio driver restores pin:cvt selections
1884 * but this can happen before gfx is ready and such selection
1885 * is overlooked by HW. Thus multiple pins can share a same
1886 * default convertor and mute control will affect each other,
1887 * which can cause a resumed audio playback become silent
1890 pin_cvt_fixup(codec, per_pin, 0);
1892 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1893 /* Todo: add DP1.2 MST audio support later */
1894 if (codec_has_acomp(codec))
1895 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
1898 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1899 mutex_lock(&per_pin->lock);
1900 per_pin->channels = substream->runtime->channels;
1901 per_pin->setup = true;
1903 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1904 mutex_unlock(&per_pin->lock);
1905 if (spec->dyn_pin_out) {
1906 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1907 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1908 snd_hda_codec_write(codec, pin_nid, 0,
1909 AC_VERB_SET_PIN_WIDGET_CONTROL,
1913 /* snd_hda_set_dev_select() has been called before */
1914 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1915 stream_tag, format);
1916 mutex_unlock(&spec->pcm_lock);
1920 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1921 struct hda_codec *codec,
1922 struct snd_pcm_substream *substream)
1924 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1928 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1929 struct hda_codec *codec,
1930 struct snd_pcm_substream *substream)
1932 struct hdmi_spec *spec = codec->spec;
1933 int cvt_idx, pin_idx, pcm_idx;
1934 struct hdmi_spec_per_cvt *per_cvt;
1935 struct hdmi_spec_per_pin *per_pin;
1939 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1940 if (snd_BUG_ON(pcm_idx < 0))
1942 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1943 if (snd_BUG_ON(cvt_idx < 0))
1945 per_cvt = get_cvt(spec, cvt_idx);
1947 snd_BUG_ON(!per_cvt->assigned);
1948 per_cvt->assigned = 0;
1951 mutex_lock(&spec->pcm_lock);
1952 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1953 clear_bit(pcm_idx, &spec->pcm_in_use);
1954 pin_idx = hinfo_to_pin_index(codec, hinfo);
1955 if (spec->dyn_pcm_assign && pin_idx < 0) {
1956 mutex_unlock(&spec->pcm_lock);
1960 if (snd_BUG_ON(pin_idx < 0)) {
1961 mutex_unlock(&spec->pcm_lock);
1964 per_pin = get_pin(spec, pin_idx);
1966 if (spec->dyn_pin_out) {
1967 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1968 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1969 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1970 AC_VERB_SET_PIN_WIDGET_CONTROL,
1974 mutex_lock(&per_pin->lock);
1975 per_pin->chmap_set = false;
1976 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1978 per_pin->setup = false;
1979 per_pin->channels = 0;
1980 mutex_unlock(&per_pin->lock);
1981 mutex_unlock(&spec->pcm_lock);
1987 static const struct hda_pcm_ops generic_ops = {
1988 .open = hdmi_pcm_open,
1989 .close = hdmi_pcm_close,
1990 .prepare = generic_hdmi_playback_pcm_prepare,
1991 .cleanup = generic_hdmi_playback_pcm_cleanup,
1994 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
1996 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1997 struct hdmi_spec *spec = codec->spec;
1998 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2003 return per_pin->sink_eld.info.spk_alloc;
2006 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2007 unsigned char *chmap)
2009 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2010 struct hdmi_spec *spec = codec->spec;
2011 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2013 /* chmap is already set to 0 in caller */
2017 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2020 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2021 unsigned char *chmap, int prepared)
2023 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2024 struct hdmi_spec *spec = codec->spec;
2025 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2029 mutex_lock(&per_pin->lock);
2030 per_pin->chmap_set = true;
2031 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2033 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2034 mutex_unlock(&per_pin->lock);
2037 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2039 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2040 struct hdmi_spec *spec = codec->spec;
2041 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2043 return per_pin ? true:false;
2046 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2048 struct hdmi_spec *spec = codec->spec;
2052 * for non-mst mode, pcm number is the same as before
2053 * for DP MST mode, pcm number is (nid number + dev_num - 1)
2054 * dev_num is the device entry number in a pin
2057 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
2058 struct hda_pcm *info;
2059 struct hda_pcm_stream *pstr;
2061 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2065 spec->pcm_rec[idx].pcm = info;
2067 info->pcm_type = HDA_PCM_TYPE_HDMI;
2068 info->own_chmap = true;
2070 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2071 pstr->substreams = 1;
2072 pstr->ops = generic_ops;
2073 /* pcm number is less than 16 */
2074 if (spec->pcm_used >= 16)
2076 /* other pstr fields are set in open */
2082 static void free_hdmi_jack_priv(struct snd_jack *jack)
2084 struct hdmi_pcm *pcm = jack->private_data;
2089 static int add_hdmi_jack_kctl(struct hda_codec *codec,
2090 struct hdmi_spec *spec,
2094 struct snd_jack *jack;
2097 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2102 spec->pcm_rec[pcm_idx].jack = jack;
2103 jack->private_data = &spec->pcm_rec[pcm_idx];
2104 jack->private_free = free_hdmi_jack_priv;
2108 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2110 char hdmi_str[32] = "HDMI/DP";
2111 struct hdmi_spec *spec = codec->spec;
2112 struct hdmi_spec_per_pin *per_pin;
2113 struct hda_jack_tbl *jack;
2114 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2119 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2121 if (spec->dyn_pcm_assign)
2122 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2124 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2125 /* if !dyn_pcm_assign, it must be non-MST mode.
2126 * This means pcms and pins are statically mapped.
2127 * And pcm_idx is pin_idx.
2129 per_pin = get_pin(spec, pcm_idx);
2130 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2132 strncat(hdmi_str, " Phantom",
2133 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2134 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2138 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2141 /* assign jack->jack to pcm_rec[].jack to
2142 * align with dyn_pcm_assign mode
2144 spec->pcm_rec[pcm_idx].jack = jack->jack;
2148 static int generic_hdmi_build_controls(struct hda_codec *codec)
2150 struct hdmi_spec *spec = codec->spec;
2152 int pin_idx, pcm_idx;
2155 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2156 err = generic_hdmi_build_jack(codec, pcm_idx);
2160 /* create the spdif for each pcm
2161 * pin will be bound when monitor is connected
2163 if (spec->dyn_pcm_assign)
2164 err = snd_hda_create_dig_out_ctls(codec,
2165 0, spec->cvt_nids[0],
2168 struct hdmi_spec_per_pin *per_pin =
2169 get_pin(spec, pcm_idx);
2170 err = snd_hda_create_dig_out_ctls(codec,
2172 per_pin->mux_nids[0],
2177 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2179 dev = get_pcm_rec(spec, pcm_idx)->device;
2180 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2181 /* add control for ELD Bytes */
2182 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2188 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2189 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2191 hdmi_present_sense(per_pin, 0);
2194 /* add channel maps */
2195 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2196 struct hda_pcm *pcm;
2198 pcm = get_pcm_rec(spec, pcm_idx);
2199 if (!pcm || !pcm->pcm)
2201 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2209 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2211 struct hdmi_spec *spec = codec->spec;
2214 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2215 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2217 per_pin->codec = codec;
2218 mutex_init(&per_pin->lock);
2219 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2220 eld_proc_new(per_pin, pin_idx);
2225 static int generic_hdmi_init(struct hda_codec *codec)
2227 struct hdmi_spec *spec = codec->spec;
2230 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2231 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2232 hda_nid_t pin_nid = per_pin->pin_nid;
2233 int dev_id = per_pin->dev_id;
2235 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2236 hdmi_init_pin(codec, pin_nid);
2237 if (!codec_has_acomp(codec))
2238 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2239 codec->jackpoll_interval > 0 ?
2240 jack_callback : NULL);
2245 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2247 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2248 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2251 static void hdmi_array_free(struct hdmi_spec *spec)
2253 snd_array_free(&spec->pins);
2254 snd_array_free(&spec->cvts);
2257 static void generic_spec_free(struct hda_codec *codec)
2259 struct hdmi_spec *spec = codec->spec;
2262 hdmi_array_free(spec);
2266 codec->dp_mst = false;
2269 static void generic_hdmi_free(struct hda_codec *codec)
2271 struct hdmi_spec *spec = codec->spec;
2272 int pin_idx, pcm_idx;
2274 if (codec_has_acomp(codec))
2275 snd_hdac_i915_register_notifier(NULL);
2277 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2278 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2279 cancel_delayed_work_sync(&per_pin->work);
2280 eld_proc_free(per_pin);
2283 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2284 if (spec->pcm_rec[pcm_idx].jack == NULL)
2286 if (spec->dyn_pcm_assign)
2287 snd_device_free(codec->card,
2288 spec->pcm_rec[pcm_idx].jack);
2290 spec->pcm_rec[pcm_idx].jack = NULL;
2293 generic_spec_free(codec);
2297 static int generic_hdmi_resume(struct hda_codec *codec)
2299 struct hdmi_spec *spec = codec->spec;
2302 codec->patch_ops.init(codec);
2303 regcache_sync(codec->core.regmap);
2305 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2306 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2307 hdmi_present_sense(per_pin, 1);
2313 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2314 .init = generic_hdmi_init,
2315 .free = generic_hdmi_free,
2316 .build_pcms = generic_hdmi_build_pcms,
2317 .build_controls = generic_hdmi_build_controls,
2318 .unsol_event = hdmi_unsol_event,
2320 .resume = generic_hdmi_resume,
2324 static const struct hdmi_ops generic_standard_hdmi_ops = {
2325 .pin_get_eld = snd_hdmi_get_eld,
2326 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2327 .pin_hbr_setup = hdmi_pin_hbr_setup,
2328 .setup_stream = hdmi_setup_stream,
2331 /* allocate codec->spec and assign/initialize generic parser ops */
2332 static int alloc_generic_hdmi(struct hda_codec *codec)
2334 struct hdmi_spec *spec;
2336 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2340 spec->ops = generic_standard_hdmi_ops;
2341 spec->dev_num = 1; /* initialize to 1 */
2342 mutex_init(&spec->pcm_lock);
2343 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2345 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2346 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2347 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2348 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2351 hdmi_array_init(spec, 4);
2353 codec->patch_ops = generic_hdmi_patch_ops;
2358 /* generic HDMI parser */
2359 static int patch_generic_hdmi(struct hda_codec *codec)
2363 err = alloc_generic_hdmi(codec);
2367 err = hdmi_parse_codec(codec);
2369 generic_spec_free(codec);
2373 generic_hdmi_init_per_pins(codec);
2378 * Intel codec parsers and helpers
2381 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2384 struct hdmi_spec *spec = codec->spec;
2388 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2389 if (nconns == spec->num_cvts &&
2390 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2393 /* override pins connection list */
2394 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2395 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2398 #define INTEL_VENDOR_NID 0x08
2399 #define INTEL_GLK_VENDOR_NID 0x0B
2400 #define INTEL_GET_VENDOR_VERB 0xf81
2401 #define INTEL_SET_VENDOR_VERB 0x781
2402 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2403 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2405 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2408 unsigned int vendor_param;
2409 struct hdmi_spec *spec = codec->spec;
2411 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2412 INTEL_GET_VENDOR_VERB, 0);
2413 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2416 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2417 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2418 INTEL_SET_VENDOR_VERB, vendor_param);
2419 if (vendor_param == -1)
2423 snd_hda_codec_update_widgets(codec);
2426 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2428 unsigned int vendor_param;
2429 struct hdmi_spec *spec = codec->spec;
2431 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2432 INTEL_GET_VENDOR_VERB, 0);
2433 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2436 /* enable DP1.2 mode */
2437 vendor_param |= INTEL_EN_DP12;
2438 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2439 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2440 INTEL_SET_VENDOR_VERB, vendor_param);
2443 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2444 * Otherwise you may get severe h/w communication errors.
2446 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2447 unsigned int power_state)
2449 if (power_state == AC_PWRST_D0) {
2450 intel_haswell_enable_all_pins(codec, false);
2451 intel_haswell_fixup_enable_dp12(codec);
2454 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2455 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2458 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2460 struct hda_codec *codec = audio_ptr;
2464 /* we assume only from port-B to port-D */
2465 if (port < 1 || port > 3)
2468 switch (codec->core.vendor_id) {
2469 case 0x80860054: /* ILK */
2470 case 0x80862804: /* ILK */
2471 case 0x80862882: /* VLV */
2472 pin_nid = port + 0x03;
2475 pin_nid = port + 0x04;
2479 /* skip notification during system suspend (but not in runtime PM);
2480 * the state will be updated at resume
2482 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2484 /* ditto during suspend/resume process itself */
2485 if (atomic_read(&(codec)->core.in_pm))
2488 snd_hdac_i915_set_bclk(&codec->bus->core);
2489 check_presence_and_report(codec, pin_nid, dev_id);
2492 /* register i915 component pin_eld_notify callback */
2493 static void register_i915_notifier(struct hda_codec *codec)
2495 struct hdmi_spec *spec = codec->spec;
2497 spec->use_acomp_notifier = true;
2498 spec->i915_audio_ops.audio_ptr = codec;
2499 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2500 * will call pin_eld_notify with using audio_ptr pointer
2501 * We need make sure audio_ptr is really setup
2504 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2505 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2508 /* setup_stream ops override for HSW+ */
2509 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2510 hda_nid_t pin_nid, u32 stream_tag, int format)
2512 haswell_verify_D0(codec, cvt_nid, pin_nid);
2513 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2516 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2517 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2518 struct hdmi_spec_per_pin *per_pin,
2522 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2524 intel_verify_pin_cvt_connect(codec, per_pin);
2525 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2526 per_pin->dev_id, per_pin->mux_idx);
2528 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2532 /* precondition and allocation for Intel codecs */
2533 static int alloc_intel_hdmi(struct hda_codec *codec)
2535 /* requires i915 binding */
2536 if (!codec->bus->core.audio_component) {
2537 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2541 return alloc_generic_hdmi(codec);
2544 /* parse and post-process for Intel codecs */
2545 static int parse_intel_hdmi(struct hda_codec *codec)
2549 err = hdmi_parse_codec(codec);
2551 generic_spec_free(codec);
2555 generic_hdmi_init_per_pins(codec);
2556 register_i915_notifier(codec);
2560 /* Intel Haswell and onwards; audio component with eld notifier */
2561 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid)
2563 struct hdmi_spec *spec;
2566 err = alloc_intel_hdmi(codec);
2570 codec->dp_mst = true;
2571 spec->dyn_pcm_assign = true;
2572 spec->vendor_nid = vendor_nid;
2574 intel_haswell_enable_all_pins(codec, true);
2575 intel_haswell_fixup_enable_dp12(codec);
2577 /* For Haswell/Broadwell, the controller is also in the power well and
2578 * can cover the codec power request, and so need not set this flag.
2580 if (!is_haswell(codec) && !is_broadwell(codec))
2581 codec->core.link_power_control = 1;
2583 codec->patch_ops.set_power_state = haswell_set_power_state;
2584 codec->depop_delay = 0;
2585 codec->auto_runtime_pm = 1;
2587 spec->ops.setup_stream = i915_hsw_setup_stream;
2588 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2590 return parse_intel_hdmi(codec);
2593 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2595 return intel_hsw_common_init(codec, INTEL_VENDOR_NID);
2598 static int patch_i915_glk_hdmi(struct hda_codec *codec)
2600 return intel_hsw_common_init(codec, INTEL_GLK_VENDOR_NID);
2603 /* Intel Baytrail and Braswell; with eld notifier */
2604 static int patch_i915_byt_hdmi(struct hda_codec *codec)
2606 struct hdmi_spec *spec;
2609 err = alloc_intel_hdmi(codec);
2614 /* For Valleyview/Cherryview, only the display codec is in the display
2615 * power well and can use link_power ops to request/release the power.
2617 codec->core.link_power_control = 1;
2619 codec->depop_delay = 0;
2620 codec->auto_runtime_pm = 1;
2622 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2624 return parse_intel_hdmi(codec);
2627 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2628 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2632 err = alloc_intel_hdmi(codec);
2635 return parse_intel_hdmi(codec);
2639 * Shared non-generic implementations
2642 static int simple_playback_build_pcms(struct hda_codec *codec)
2644 struct hdmi_spec *spec = codec->spec;
2645 struct hda_pcm *info;
2647 struct hda_pcm_stream *pstr;
2648 struct hdmi_spec_per_cvt *per_cvt;
2650 per_cvt = get_cvt(spec, 0);
2651 chans = get_wcaps(codec, per_cvt->cvt_nid);
2652 chans = get_wcaps_channels(chans);
2654 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2657 spec->pcm_rec[0].pcm = info;
2658 info->pcm_type = HDA_PCM_TYPE_HDMI;
2659 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2660 *pstr = spec->pcm_playback;
2661 pstr->nid = per_cvt->cvt_nid;
2662 if (pstr->channels_max <= 2 && chans && chans <= 16)
2663 pstr->channels_max = chans;
2668 /* unsolicited event for jack sensing */
2669 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2672 snd_hda_jack_set_dirty_all(codec);
2673 snd_hda_jack_report_sync(codec);
2676 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2677 * as long as spec->pins[] is set correctly
2679 #define simple_hdmi_build_jack generic_hdmi_build_jack
2681 static int simple_playback_build_controls(struct hda_codec *codec)
2683 struct hdmi_spec *spec = codec->spec;
2684 struct hdmi_spec_per_cvt *per_cvt;
2687 per_cvt = get_cvt(spec, 0);
2688 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2693 return simple_hdmi_build_jack(codec, 0);
2696 static int simple_playback_init(struct hda_codec *codec)
2698 struct hdmi_spec *spec = codec->spec;
2699 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2700 hda_nid_t pin = per_pin->pin_nid;
2702 snd_hda_codec_write(codec, pin, 0,
2703 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2704 /* some codecs require to unmute the pin */
2705 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2706 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2708 snd_hda_jack_detect_enable(codec, pin);
2712 static void simple_playback_free(struct hda_codec *codec)
2714 struct hdmi_spec *spec = codec->spec;
2716 hdmi_array_free(spec);
2721 * Nvidia specific implementations
2724 #define Nv_VERB_SET_Channel_Allocation 0xF79
2725 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2726 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2727 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2729 #define nvhdmi_master_con_nid_7x 0x04
2730 #define nvhdmi_master_pin_nid_7x 0x05
2732 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2733 /*front, rear, clfe, rear_surr */
2737 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2738 /* set audio protect on */
2739 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2740 /* enable digital output on pin widget */
2741 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2745 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2746 /* set audio protect on */
2747 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2748 /* enable digital output on pin widget */
2749 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2750 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2751 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2752 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2753 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2757 #ifdef LIMITED_RATE_FMT_SUPPORT
2758 /* support only the safe format and rate */
2759 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2760 #define SUPPORTED_MAXBPS 16
2761 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2763 /* support all rates and formats */
2764 #define SUPPORTED_RATES \
2765 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2766 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2767 SNDRV_PCM_RATE_192000)
2768 #define SUPPORTED_MAXBPS 24
2769 #define SUPPORTED_FORMATS \
2770 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2773 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2775 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2779 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2781 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2785 static const unsigned int channels_2_6_8[] = {
2789 static const unsigned int channels_2_8[] = {
2793 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2794 .count = ARRAY_SIZE(channels_2_6_8),
2795 .list = channels_2_6_8,
2799 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2800 .count = ARRAY_SIZE(channels_2_8),
2801 .list = channels_2_8,
2805 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2806 struct hda_codec *codec,
2807 struct snd_pcm_substream *substream)
2809 struct hdmi_spec *spec = codec->spec;
2810 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2812 switch (codec->preset->vendor_id) {
2817 hw_constraints_channels = &hw_constraints_2_8_channels;
2820 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2826 if (hw_constraints_channels != NULL) {
2827 snd_pcm_hw_constraint_list(substream->runtime, 0,
2828 SNDRV_PCM_HW_PARAM_CHANNELS,
2829 hw_constraints_channels);
2831 snd_pcm_hw_constraint_step(substream->runtime, 0,
2832 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2835 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2838 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2839 struct hda_codec *codec,
2840 struct snd_pcm_substream *substream)
2842 struct hdmi_spec *spec = codec->spec;
2843 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2846 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2847 struct hda_codec *codec,
2848 unsigned int stream_tag,
2849 unsigned int format,
2850 struct snd_pcm_substream *substream)
2852 struct hdmi_spec *spec = codec->spec;
2853 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2854 stream_tag, format, substream);
2857 static const struct hda_pcm_stream simple_pcm_playback = {
2862 .open = simple_playback_pcm_open,
2863 .close = simple_playback_pcm_close,
2864 .prepare = simple_playback_pcm_prepare
2868 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2869 .build_controls = simple_playback_build_controls,
2870 .build_pcms = simple_playback_build_pcms,
2871 .init = simple_playback_init,
2872 .free = simple_playback_free,
2873 .unsol_event = simple_hdmi_unsol_event,
2876 static int patch_simple_hdmi(struct hda_codec *codec,
2877 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2879 struct hdmi_spec *spec;
2880 struct hdmi_spec_per_cvt *per_cvt;
2881 struct hdmi_spec_per_pin *per_pin;
2883 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2888 hdmi_array_init(spec, 1);
2890 spec->multiout.num_dacs = 0; /* no analog */
2891 spec->multiout.max_channels = 2;
2892 spec->multiout.dig_out_nid = cvt_nid;
2895 per_pin = snd_array_new(&spec->pins);
2896 per_cvt = snd_array_new(&spec->cvts);
2897 if (!per_pin || !per_cvt) {
2898 simple_playback_free(codec);
2901 per_cvt->cvt_nid = cvt_nid;
2902 per_pin->pin_nid = pin_nid;
2903 spec->pcm_playback = simple_pcm_playback;
2905 codec->patch_ops = simple_hdmi_patch_ops;
2910 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2913 unsigned int chanmask;
2914 int chan = channels ? (channels - 1) : 1;
2933 /* Set the audio infoframe channel allocation and checksum fields. The
2934 * channel count is computed implicitly by the hardware. */
2935 snd_hda_codec_write(codec, 0x1, 0,
2936 Nv_VERB_SET_Channel_Allocation, chanmask);
2938 snd_hda_codec_write(codec, 0x1, 0,
2939 Nv_VERB_SET_Info_Frame_Checksum,
2940 (0x71 - chan - chanmask));
2943 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2944 struct hda_codec *codec,
2945 struct snd_pcm_substream *substream)
2947 struct hdmi_spec *spec = codec->spec;
2950 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2951 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2952 for (i = 0; i < 4; i++) {
2953 /* set the stream id */
2954 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2955 AC_VERB_SET_CHANNEL_STREAMID, 0);
2956 /* set the stream format */
2957 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2958 AC_VERB_SET_STREAM_FORMAT, 0);
2961 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2962 * streams are disabled. */
2963 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2965 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2968 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2969 struct hda_codec *codec,
2970 unsigned int stream_tag,
2971 unsigned int format,
2972 struct snd_pcm_substream *substream)
2975 unsigned int dataDCC2, channel_id;
2977 struct hdmi_spec *spec = codec->spec;
2978 struct hda_spdif_out *spdif;
2979 struct hdmi_spec_per_cvt *per_cvt;
2981 mutex_lock(&codec->spdif_mutex);
2982 per_cvt = get_cvt(spec, 0);
2983 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2985 chs = substream->runtime->channels;
2989 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2990 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2991 snd_hda_codec_write(codec,
2992 nvhdmi_master_con_nid_7x,
2994 AC_VERB_SET_DIGI_CONVERT_1,
2995 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2997 /* set the stream id */
2998 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2999 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3001 /* set the stream format */
3002 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3003 AC_VERB_SET_STREAM_FORMAT, format);
3005 /* turn on again (if needed) */
3006 /* enable and set the channel status audio/data flag */
3007 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3008 snd_hda_codec_write(codec,
3009 nvhdmi_master_con_nid_7x,
3011 AC_VERB_SET_DIGI_CONVERT_1,
3012 spdif->ctls & 0xff);
3013 snd_hda_codec_write(codec,
3014 nvhdmi_master_con_nid_7x,
3016 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3019 for (i = 0; i < 4; i++) {
3025 /* turn off SPDIF once;
3026 *otherwise the IEC958 bits won't be updated
3028 if (codec->spdif_status_reset &&
3029 (spdif->ctls & AC_DIG1_ENABLE))
3030 snd_hda_codec_write(codec,
3031 nvhdmi_con_nids_7x[i],
3033 AC_VERB_SET_DIGI_CONVERT_1,
3034 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3035 /* set the stream id */
3036 snd_hda_codec_write(codec,
3037 nvhdmi_con_nids_7x[i],
3039 AC_VERB_SET_CHANNEL_STREAMID,
3040 (stream_tag << 4) | channel_id);
3041 /* set the stream format */
3042 snd_hda_codec_write(codec,
3043 nvhdmi_con_nids_7x[i],
3045 AC_VERB_SET_STREAM_FORMAT,
3047 /* turn on again (if needed) */
3048 /* enable and set the channel status audio/data flag */
3049 if (codec->spdif_status_reset &&
3050 (spdif->ctls & AC_DIG1_ENABLE)) {
3051 snd_hda_codec_write(codec,
3052 nvhdmi_con_nids_7x[i],
3054 AC_VERB_SET_DIGI_CONVERT_1,
3055 spdif->ctls & 0xff);
3056 snd_hda_codec_write(codec,
3057 nvhdmi_con_nids_7x[i],
3059 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3063 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3065 mutex_unlock(&codec->spdif_mutex);
3069 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3073 .nid = nvhdmi_master_con_nid_7x,
3074 .rates = SUPPORTED_RATES,
3075 .maxbps = SUPPORTED_MAXBPS,
3076 .formats = SUPPORTED_FORMATS,
3078 .open = simple_playback_pcm_open,
3079 .close = nvhdmi_8ch_7x_pcm_close,
3080 .prepare = nvhdmi_8ch_7x_pcm_prepare
3084 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3086 struct hdmi_spec *spec;
3087 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3088 nvhdmi_master_pin_nid_7x);
3092 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3093 /* override the PCM rates, etc, as the codec doesn't give full list */
3095 spec->pcm_playback.rates = SUPPORTED_RATES;
3096 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3097 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3101 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3103 struct hdmi_spec *spec = codec->spec;
3104 int err = simple_playback_build_pcms(codec);
3106 struct hda_pcm *info = get_pcm_rec(spec, 0);
3107 info->own_chmap = true;
3112 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3114 struct hdmi_spec *spec = codec->spec;
3115 struct hda_pcm *info;
3116 struct snd_pcm_chmap *chmap;
3119 err = simple_playback_build_controls(codec);
3123 /* add channel maps */
3124 info = get_pcm_rec(spec, 0);
3125 err = snd_pcm_add_chmap_ctls(info->pcm,
3126 SNDRV_PCM_STREAM_PLAYBACK,
3127 snd_pcm_alt_chmaps, 8, 0, &chmap);
3130 switch (codec->preset->vendor_id) {
3135 chmap->channel_mask = (1U << 2) | (1U << 8);
3138 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3143 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3145 struct hdmi_spec *spec;
3146 int err = patch_nvhdmi_2ch(codec);
3150 spec->multiout.max_channels = 8;
3151 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3152 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3153 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3154 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3156 /* Initialize the audio infoframe channel mask and checksum to something
3158 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3164 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3168 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3169 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3171 if (cap->ca_index == 0x00 && channels == 2)
3172 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3174 /* If the speaker allocation matches the channel count, it is OK. */
3175 if (cap->channels != channels)
3178 /* all channels are remappable freely */
3179 return SNDRV_CTL_TLVT_CHMAP_VAR;
3182 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3183 int ca, int chs, unsigned char *map)
3185 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3191 static int patch_nvhdmi(struct hda_codec *codec)
3193 struct hdmi_spec *spec;
3196 err = patch_generic_hdmi(codec);
3201 spec->dyn_pin_out = true;
3203 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3204 nvhdmi_chmap_cea_alloc_validate_get_type;
3205 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3211 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3212 * accessed using vendor-defined verbs. These registers can be used for
3213 * interoperability between the HDA and HDMI drivers.
3216 /* Audio Function Group node */
3217 #define NVIDIA_AFG_NID 0x01
3220 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3221 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3222 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3223 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3224 * additional bit (at position 30) to signal the validity of the format.
3226 * | 31 | 30 | 29 16 | 15 0 |
3227 * +---------+-------+--------+--------+
3228 * | TRIGGER | VALID | UNUSED | FORMAT |
3229 * +-----------------------------------|
3231 * Note that for the trigger bit to take effect it needs to change value
3232 * (i.e. it needs to be toggled).
3234 #define NVIDIA_GET_SCRATCH0 0xfa6
3235 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3236 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3237 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3238 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3239 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3240 #define NVIDIA_SCRATCH_VALID (1 << 6)
3242 #define NVIDIA_GET_SCRATCH1 0xfab
3243 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3244 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3245 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3246 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3249 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3250 * the format is invalidated so that the HDMI codec can be disabled.
3252 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3256 /* bits [31:30] contain the trigger and valid bits */
3257 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3258 NVIDIA_GET_SCRATCH0, 0);
3259 value = (value >> 24) & 0xff;
3261 /* bits [15:0] are used to store the HDA format */
3262 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3263 NVIDIA_SET_SCRATCH0_BYTE0,
3264 (format >> 0) & 0xff);
3265 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3266 NVIDIA_SET_SCRATCH0_BYTE1,
3267 (format >> 8) & 0xff);
3269 /* bits [16:24] are unused */
3270 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3271 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3274 * Bit 30 signals that the data is valid and hence that HDMI audio can
3278 value &= ~NVIDIA_SCRATCH_VALID;
3280 value |= NVIDIA_SCRATCH_VALID;
3283 * Whenever the trigger bit is toggled, an interrupt is raised in the
3284 * HDMI codec. The HDMI driver will use that as trigger to update its
3287 value ^= NVIDIA_SCRATCH_TRIGGER;
3289 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3290 NVIDIA_SET_SCRATCH0_BYTE3, value);
3293 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3294 struct hda_codec *codec,
3295 unsigned int stream_tag,
3296 unsigned int format,
3297 struct snd_pcm_substream *substream)
3301 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3306 /* notify the HDMI codec of the format change */
3307 tegra_hdmi_set_format(codec, format);
3312 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3313 struct hda_codec *codec,
3314 struct snd_pcm_substream *substream)
3316 /* invalidate the format in the HDMI codec */
3317 tegra_hdmi_set_format(codec, 0);
3319 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3322 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3324 struct hdmi_spec *spec = codec->spec;
3327 for (i = 0; i < spec->num_pins; i++) {
3328 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3330 if (pcm->pcm_type == type)
3337 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3339 struct hda_pcm_stream *stream;
3340 struct hda_pcm *pcm;
3343 err = generic_hdmi_build_pcms(codec);
3347 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3352 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3353 * codec about format changes.
3355 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3356 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3357 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3362 static int patch_tegra_hdmi(struct hda_codec *codec)
3366 err = patch_generic_hdmi(codec);
3370 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3376 * ATI/AMD-specific implementations
3379 #define is_amdhdmi_rev3_or_later(codec) \
3380 ((codec)->core.vendor_id == 0x1002aa01 && \
3381 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3382 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3384 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3385 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3386 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3387 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3388 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3389 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3390 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3391 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3392 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3393 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3394 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3395 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3396 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3397 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3398 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3399 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3400 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3401 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3402 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3403 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3404 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3405 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3406 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3407 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3408 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3410 /* AMD specific HDA cvt verbs */
3411 #define ATI_VERB_SET_RAMP_RATE 0x770
3412 #define ATI_VERB_GET_RAMP_RATE 0xf70
3414 #define ATI_OUT_ENABLE 0x1
3416 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3417 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3419 #define ATI_HBR_CAPABLE 0x01
3420 #define ATI_HBR_ENABLE 0x10
3422 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3423 unsigned char *buf, int *eld_size)
3425 /* call hda_eld.c ATI/AMD-specific function */
3426 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3427 is_amdhdmi_rev3_or_later(codec));
3430 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3431 int active_channels, int conn_type)
3433 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3436 static int atihdmi_paired_swap_fc_lfe(int pos)
3439 * ATI/AMD have automatic FC/LFE swap built-in
3440 * when in pairwise mapping mode.
3444 /* see channel_allocations[].speakers[] */
3453 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3454 int ca, int chs, unsigned char *map)
3456 struct hdac_cea_channel_speaker_allocation *cap;
3459 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3461 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3462 for (i = 0; i < chs; ++i) {
3463 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3465 bool companion_ok = false;
3470 for (j = 0 + i % 2; j < 8; j += 2) {
3471 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3472 if (cap->speakers[chan_idx] == mask) {
3473 /* channel is in a supported position */
3476 if (i % 2 == 0 && i + 1 < chs) {
3477 /* even channel, check the odd companion */
3478 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3479 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3480 int comp_mask_act = cap->speakers[comp_chan_idx];
3482 if (comp_mask_req == comp_mask_act)
3483 companion_ok = true;
3495 i++; /* companion channel already checked */
3501 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3502 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3504 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3506 int ati_channel_setup = 0;
3511 if (!has_amd_full_remap_support(codec)) {
3512 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3514 /* In case this is an odd slot but without stream channel, do not
3515 * disable the slot since the corresponding even slot could have a
3516 * channel. In case neither have a channel, the slot pair will be
3517 * disabled when this function is called for the even slot. */
3518 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3521 hdmi_slot -= hdmi_slot % 2;
3523 if (stream_channel != 0xf)
3524 stream_channel -= stream_channel % 2;
3527 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3529 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3531 if (stream_channel != 0xf)
3532 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3534 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3537 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3538 hda_nid_t pin_nid, int asp_slot)
3540 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3541 bool was_odd = false;
3542 int ati_asp_slot = asp_slot;
3544 int ati_channel_setup;
3549 if (!has_amd_full_remap_support(codec)) {
3550 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3551 if (ati_asp_slot % 2 != 0) {
3557 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3559 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3561 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3564 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3567 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3568 struct hdac_chmap *chmap,
3569 struct hdac_cea_channel_speaker_allocation *cap,
3575 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3576 * we need to take that into account (a single channel may take 2
3577 * channel slots if we need to carry a silent channel next to it).
3578 * On Rev3+ AMD codecs this function is not used.
3582 /* We only produce even-numbered channel count TLVs */
3583 if ((channels % 2) != 0)
3586 for (c = 0; c < 7; c += 2) {
3587 if (cap->speakers[c] || cap->speakers[c+1])
3591 if (chanpairs * 2 != channels)
3594 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3597 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3598 struct hdac_cea_channel_speaker_allocation *cap,
3599 unsigned int *chmap, int channels)
3601 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3605 for (c = 7; c >= 0; c--) {
3606 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3607 int spk = cap->speakers[chan];
3609 /* add N/A channel if the companion channel is occupied */
3610 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3611 chmap[count++] = SNDRV_CHMAP_NA;
3616 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3619 WARN_ON(count != channels);
3622 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3625 int hbr_ctl, hbr_ctl_new;
3627 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3628 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3630 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3632 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3635 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3637 hbr_ctl == hbr_ctl_new ? "" : "new-",
3640 if (hbr_ctl != hbr_ctl_new)
3641 snd_hda_codec_write(codec, pin_nid, 0,
3642 ATI_VERB_SET_HBR_CONTROL,
3651 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3652 hda_nid_t pin_nid, u32 stream_tag, int format)
3655 if (is_amdhdmi_rev3_or_later(codec)) {
3656 int ramp_rate = 180; /* default as per AMD spec */
3657 /* disable ramp-up/down for non-pcm as per AMD spec */
3658 if (format & AC_FMT_TYPE_NON_PCM)
3661 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3664 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3668 static int atihdmi_init(struct hda_codec *codec)
3670 struct hdmi_spec *spec = codec->spec;
3673 err = generic_hdmi_init(codec);
3678 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3679 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3681 /* make sure downmix information in infoframe is zero */
3682 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3684 /* enable channel-wise remap mode if supported */
3685 if (has_amd_full_remap_support(codec))
3686 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3687 ATI_VERB_SET_MULTICHANNEL_MODE,
3688 ATI_MULTICHANNEL_MODE_SINGLE);
3694 static int patch_atihdmi(struct hda_codec *codec)
3696 struct hdmi_spec *spec;
3697 struct hdmi_spec_per_cvt *per_cvt;
3700 err = patch_generic_hdmi(codec);
3705 codec->patch_ops.init = atihdmi_init;
3709 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3710 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3711 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3712 spec->ops.setup_stream = atihdmi_setup_stream;
3714 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3715 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3717 if (!has_amd_full_remap_support(codec)) {
3718 /* override to ATI/AMD-specific versions with pairwise mapping */
3719 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3720 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3721 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3722 atihdmi_paired_cea_alloc_to_tlv_chmap;
3723 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3726 /* ATI/AMD converters do not advertise all of their capabilities */
3727 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3728 per_cvt = get_cvt(spec, cvt_idx);
3729 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3730 per_cvt->rates |= SUPPORTED_RATES;
3731 per_cvt->formats |= SUPPORTED_FORMATS;
3732 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3735 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3740 /* VIA HDMI Implementation */
3741 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3742 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3744 static int patch_via_hdmi(struct hda_codec *codec)
3746 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3752 static const struct hda_device_id snd_hda_id_hdmi[] = {
3753 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3754 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3755 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3756 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3757 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3758 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3759 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3760 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
3761 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3762 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3763 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
3764 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3765 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3766 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3767 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
3768 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
3769 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3770 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3771 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3772 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3773 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3774 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3775 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3776 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3777 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3778 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3779 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3780 /* 17 is known to be absent */
3781 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3782 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3783 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3784 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3785 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3786 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3787 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3788 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3789 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3790 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3791 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3792 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3793 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3794 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3795 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
3796 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
3797 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3798 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
3799 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3800 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
3801 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
3802 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3803 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3804 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3805 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3806 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
3807 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
3808 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
3809 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
3810 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
3811 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3812 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
3813 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
3814 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
3815 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3816 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
3817 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
3818 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
3819 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
3820 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
3821 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
3822 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
3823 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
3824 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
3825 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
3826 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
3827 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3828 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
3829 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3830 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3831 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3832 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3833 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3834 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3835 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3836 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3837 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3838 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3839 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
3840 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
3841 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
3842 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
3843 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
3844 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
3845 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
3846 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
3847 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
3848 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3849 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3850 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
3851 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3852 /* special ID for generic HDMI */
3853 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3856 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3858 MODULE_LICENSE("GPL");
3859 MODULE_DESCRIPTION("HDMI HD-audio codec");
3860 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3861 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3862 MODULE_ALIAS("snd-hda-codec-atihdmi");
3864 static struct hda_codec_driver hdmi_driver = {
3865 .id = snd_hda_id_hdmi,
3868 module_hda_codec_driver(hdmi_driver);