3 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/clocksource.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mutex.h>
31 #include <linux/of_device.h>
32 #include <linux/reboot.h>
33 #include <linux/slab.h>
34 #include <linux/time.h>
36 #include <sound/core.h>
37 #include <sound/initval.h>
39 #include "hda_codec.h"
40 #include "hda_controller.h"
43 /* Defines for Nvidia Tegra HDA support */
44 #define HDA_BAR0 0x8000
46 #define HDA_CFG_CMD 0x1004
47 #define HDA_CFG_BAR0 0x1010
49 #define HDA_ENABLE_IO_SPACE (1 << 0)
50 #define HDA_ENABLE_MEM_SPACE (1 << 1)
51 #define HDA_ENABLE_BUS_MASTER (1 << 2)
52 #define HDA_ENABLE_SERR (1 << 8)
53 #define HDA_DISABLE_INTR (1 << 10)
54 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
55 #define HDA_BAR0_FINAL_PROGRAM (1 << 14)
58 #define HDA_IPFS_CONFIG 0x180
59 #define HDA_IPFS_EN_FPCI 0x1
61 #define HDA_IPFS_FPCI_BAR0 0x80
62 #define HDA_FPCI_BAR0_START 0x40
64 #define HDA_IPFS_INTR_MASK 0x188
65 #define HDA_IPFS_EN_INTR (1 << 16)
67 /* max number of SDs */
68 #define NUM_CAPTURE_SD 1
69 #define NUM_PLAYBACK_SD 1
75 struct clk *hda2codec_2x_clk;
76 struct clk *hda2hdmi_clk;
81 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
82 module_param(power_save, bint, 0644);
83 MODULE_PARM_DESC(power_save,
84 "Automatic power-saving timeout (in seconds, 0 = disable).");
86 static int power_save = 0;
90 * DMA page allocation ops.
92 static int dma_alloc_pages(struct azx *chip, int type, size_t size,
93 struct snd_dma_buffer *buf)
95 return snd_dma_alloc_pages(type, chip->card->dev, size, buf);
98 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
100 snd_dma_free_pages(buf);
103 static int substream_alloc_pages(struct azx *chip,
104 struct snd_pcm_substream *substream,
107 struct azx_dev *azx_dev = get_azx_dev(substream);
109 azx_dev->bufsize = 0;
110 azx_dev->period_bytes = 0;
111 azx_dev->format_val = 0;
112 return snd_pcm_lib_malloc_pages(substream, size);
115 static int substream_free_pages(struct azx *chip,
116 struct snd_pcm_substream *substream)
118 return snd_pcm_lib_free_pages(substream);
122 * Register access ops. Tegra HDA register access is DWORD only.
124 static void hda_tegra_writel(u32 value, u32 *addr)
129 static u32 hda_tegra_readl(u32 *addr)
134 static void hda_tegra_writew(u16 value, u16 *addr)
136 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
137 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
140 v = readl(dword_addr);
141 v &= ~(0xffff << shift);
143 writel(v, dword_addr);
146 static u16 hda_tegra_readw(u16 *addr)
148 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
149 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
152 v = readl(dword_addr);
153 return (v >> shift) & 0xffff;
156 static void hda_tegra_writeb(u8 value, u8 *addr)
158 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
159 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
162 v = readl(dword_addr);
163 v &= ~(0xff << shift);
165 writel(v, dword_addr);
168 static u8 hda_tegra_readb(u8 *addr)
170 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
171 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
174 v = readl(dword_addr);
175 return (v >> shift) & 0xff;
178 static const struct hda_controller_ops hda_tegra_ops = {
179 .reg_writel = hda_tegra_writel,
180 .reg_readl = hda_tegra_readl,
181 .reg_writew = hda_tegra_writew,
182 .reg_readw = hda_tegra_readw,
183 .reg_writeb = hda_tegra_writeb,
184 .reg_readb = hda_tegra_readb,
185 .dma_alloc_pages = dma_alloc_pages,
186 .dma_free_pages = dma_free_pages,
187 .substream_alloc_pages = substream_alloc_pages,
188 .substream_free_pages = substream_free_pages,
191 static void hda_tegra_init(struct hda_tegra *hda)
195 /* Enable PCI access */
196 v = readl(hda->regs + HDA_IPFS_CONFIG);
197 v |= HDA_IPFS_EN_FPCI;
198 writel(v, hda->regs + HDA_IPFS_CONFIG);
200 /* Enable MEM/IO space and bus master */
201 v = readl(hda->regs + HDA_CFG_CMD);
202 v &= ~HDA_DISABLE_INTR;
203 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
204 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
205 writel(v, hda->regs + HDA_CFG_CMD);
207 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
208 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
209 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
211 v = readl(hda->regs + HDA_IPFS_INTR_MASK);
212 v |= HDA_IPFS_EN_INTR;
213 writel(v, hda->regs + HDA_IPFS_INTR_MASK);
216 static int hda_tegra_enable_clocks(struct hda_tegra *data)
220 rc = clk_prepare_enable(data->hda_clk);
223 rc = clk_prepare_enable(data->hda2codec_2x_clk);
226 rc = clk_prepare_enable(data->hda2hdmi_clk);
228 goto disable_codec_2x;
233 clk_disable_unprepare(data->hda2codec_2x_clk);
235 clk_disable_unprepare(data->hda_clk);
239 static void hda_tegra_disable_clocks(struct hda_tegra *data)
241 clk_disable_unprepare(data->hda2hdmi_clk);
242 clk_disable_unprepare(data->hda2codec_2x_clk);
243 clk_disable_unprepare(data->hda_clk);
246 #ifdef CONFIG_PM_SLEEP
250 static int hda_tegra_suspend(struct device *dev)
252 struct snd_card *card = dev_get_drvdata(dev);
253 struct azx *chip = card->private_data;
255 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
257 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
258 list_for_each_entry(p, &chip->pcm_list, list)
259 snd_pcm_suspend_all(p->pcm);
260 if (chip->initialized)
261 snd_hda_suspend(chip->bus);
264 azx_enter_link_reset(chip);
265 hda_tegra_disable_clocks(hda);
270 static int hda_tegra_resume(struct device *dev)
272 struct snd_card *card = dev_get_drvdata(dev);
273 struct azx *chip = card->private_data;
274 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
277 hda_tegra_enable_clocks(hda);
279 /* Read STATESTS before controller reset */
280 status = azx_readw(chip, STATESTS);
284 azx_init_chip(chip, 1);
286 snd_hda_resume(chip->bus);
287 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
291 #endif /* CONFIG_PM_SLEEP */
293 static const struct dev_pm_ops hda_tegra_pm = {
294 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
298 * reboot notifier for hang-up problem at power-down
300 static int hda_tegra_halt(struct notifier_block *nb, unsigned long event,
303 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
304 snd_hda_bus_reboot_notify(chip->bus);
309 static void hda_tegra_notifier_register(struct azx *chip)
311 chip->reboot_notifier.notifier_call = hda_tegra_halt;
312 register_reboot_notifier(&chip->reboot_notifier);
315 static void hda_tegra_notifier_unregister(struct azx *chip)
317 if (chip->reboot_notifier.notifier_call)
318 unregister_reboot_notifier(&chip->reboot_notifier);
324 static int hda_tegra_dev_free(struct snd_device *device)
327 struct azx *chip = device->device_data;
329 hda_tegra_notifier_unregister(chip);
331 if (chip->initialized) {
332 for (i = 0; i < chip->num_streams; i++)
333 azx_stream_stop(chip, &chip->azx_dev[i]);
337 azx_free_stream_pages(chip);
342 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
344 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
345 struct device *dev = hda->dev;
346 struct resource *res;
349 hda->hda_clk = devm_clk_get(dev, "hda");
350 if (IS_ERR(hda->hda_clk))
351 return PTR_ERR(hda->hda_clk);
352 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
353 if (IS_ERR(hda->hda2codec_2x_clk))
354 return PTR_ERR(hda->hda2codec_2x_clk);
355 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
356 if (IS_ERR(hda->hda2hdmi_clk))
357 return PTR_ERR(hda->hda2hdmi_clk);
359 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
360 hda->regs = devm_ioremap_resource(dev, res);
361 if (IS_ERR(chip->remap_addr))
362 return PTR_ERR(chip->remap_addr);
364 chip->remap_addr = hda->regs + HDA_BAR0;
365 chip->addr = res->start + HDA_BAR0;
367 err = hda_tegra_enable_clocks(hda);
377 * The codecs were powered up in snd_hda_codec_new().
378 * Now all initialization done, so turn them down if possible
380 static void power_down_all_codecs(struct azx *chip)
382 struct hda_codec *codec;
383 list_for_each_entry(codec, &chip->bus->codec_list, list)
384 snd_hda_power_down(codec);
387 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
389 struct snd_card *card = chip->card;
392 int irq_id = platform_get_irq(pdev, 0);
394 err = hda_tegra_init_chip(chip, pdev);
398 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
399 IRQF_SHARED, KBUILD_MODNAME, chip);
401 dev_err(chip->card->dev,
402 "unable to request IRQ %d, disabling device\n",
408 synchronize_irq(chip->irq);
410 gcap = azx_readw(chip, GCAP);
411 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
413 /* read number of streams from GCAP register instead of using
416 chip->capture_streams = (gcap >> 8) & 0x0f;
417 chip->playback_streams = (gcap >> 12) & 0x0f;
418 if (!chip->playback_streams && !chip->capture_streams) {
419 /* gcap didn't give any info, switching to old method */
420 chip->playback_streams = NUM_PLAYBACK_SD;
421 chip->capture_streams = NUM_CAPTURE_SD;
423 chip->capture_index_offset = 0;
424 chip->playback_index_offset = chip->capture_streams;
425 chip->num_streams = chip->playback_streams + chip->capture_streams;
426 chip->azx_dev = devm_kcalloc(card->dev, chip->num_streams,
427 sizeof(*chip->azx_dev), GFP_KERNEL);
431 err = azx_alloc_stream_pages(chip);
435 /* initialize streams */
436 azx_init_stream(chip);
438 /* initialize chip */
439 azx_init_chip(chip, 1);
441 /* codec detection */
442 if (!chip->codec_mask) {
443 dev_err(card->dev, "no codecs found!\n");
447 strcpy(card->driver, "tegra-hda");
448 strcpy(card->shortname, "tegra-hda");
449 snprintf(card->longname, sizeof(card->longname),
450 "%s at 0x%lx irq %i",
451 card->shortname, chip->addr, chip->irq);
459 static int hda_tegra_create(struct snd_card *card,
460 unsigned int driver_caps,
461 const struct hda_controller_ops *hda_ops,
462 struct hda_tegra *hda)
464 static struct snd_device_ops ops = {
465 .dev_free = hda_tegra_dev_free,
472 spin_lock_init(&chip->reg_lock);
473 mutex_init(&chip->open_mutex);
477 chip->driver_caps = driver_caps;
478 chip->driver_type = driver_caps & 0xff;
480 INIT_LIST_HEAD(&chip->pcm_list);
481 INIT_LIST_HEAD(&chip->list);
483 chip->position_fix[0] = POS_FIX_AUTO;
484 chip->position_fix[1] = POS_FIX_AUTO;
485 chip->codec_probe_mask = -1;
487 chip->single_cmd = false;
490 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
492 dev_err(card->dev, "Error creating device\n");
499 static const struct of_device_id hda_tegra_match[] = {
500 { .compatible = "nvidia,tegra30-hda" },
503 MODULE_DEVICE_TABLE(of, hda_tegra_match);
505 static int hda_tegra_probe(struct platform_device *pdev)
507 struct snd_card *card;
509 struct hda_tegra *hda;
511 const unsigned int driver_flags = AZX_DCAPS_RIRB_DELAY;
513 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
516 hda->dev = &pdev->dev;
519 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
520 THIS_MODULE, 0, &card);
522 dev_err(&pdev->dev, "Error creating card!\n");
526 err = hda_tegra_create(card, driver_flags, &hda_tegra_ops, hda);
529 card->private_data = chip;
531 dev_set_drvdata(&pdev->dev, card);
533 err = hda_tegra_first_init(chip, pdev);
537 /* create codec instances */
538 err = azx_codec_create(chip, NULL, 0, &power_save);
542 err = azx_codec_configure(chip);
546 /* create PCM streams */
547 err = snd_hda_build_pcms(chip->bus);
551 /* create mixer controls */
552 err = azx_mixer_create(chip);
556 err = snd_card_register(chip->card);
561 power_down_all_codecs(chip);
562 hda_tegra_notifier_register(chip);
571 static int hda_tegra_remove(struct platform_device *pdev)
573 return snd_card_free(dev_get_drvdata(&pdev->dev));
576 static struct platform_driver tegra_platform_hda = {
580 .of_match_table = hda_tegra_match,
582 .probe = hda_tegra_probe,
583 .remove = hda_tegra_remove,
585 module_platform_driver(tegra_platform_hda);
587 MODULE_DESCRIPTION("Tegra HDA bus driver");
588 MODULE_LICENSE("GPL v2");