1 // SPDX-License-Identifier: GPL-2.0-only
4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
8 #include <linux/clocksource.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/mutex.h>
19 #include <linux/of_device.h>
20 #include <linux/slab.h>
21 #include <linux/time.h>
22 #include <linux/string.h>
23 #include <linux/pm_runtime.h>
25 #include <sound/core.h>
26 #include <sound/initval.h>
28 #include <sound/hda_codec.h>
29 #include "hda_controller.h"
31 /* Defines for Nvidia Tegra HDA support */
32 #define HDA_BAR0 0x8000
34 #define HDA_CFG_CMD 0x1004
35 #define HDA_CFG_BAR0 0x1010
37 #define HDA_ENABLE_IO_SPACE (1 << 0)
38 #define HDA_ENABLE_MEM_SPACE (1 << 1)
39 #define HDA_ENABLE_BUS_MASTER (1 << 2)
40 #define HDA_ENABLE_SERR (1 << 8)
41 #define HDA_DISABLE_INTR (1 << 10)
42 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
43 #define HDA_BAR0_FINAL_PROGRAM (1 << 14)
46 #define HDA_IPFS_CONFIG 0x180
47 #define HDA_IPFS_EN_FPCI 0x1
49 #define HDA_IPFS_FPCI_BAR0 0x80
50 #define HDA_FPCI_BAR0_START 0x40
52 #define HDA_IPFS_INTR_MASK 0x188
53 #define HDA_IPFS_EN_INTR (1 << 16)
55 /* max number of SDs */
56 #define NUM_CAPTURE_SD 1
57 #define NUM_PLAYBACK_SD 1
63 struct clk *hda2codec_2x_clk;
64 struct clk *hda2hdmi_clk;
66 struct work_struct probe_work;
70 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
71 module_param(power_save, bint, 0644);
72 MODULE_PARM_DESC(power_save,
73 "Automatic power-saving timeout (in seconds, 0 = disable).");
78 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
80 static void hda_tegra_init(struct hda_tegra *hda)
84 /* Enable PCI access */
85 v = readl(hda->regs + HDA_IPFS_CONFIG);
86 v |= HDA_IPFS_EN_FPCI;
87 writel(v, hda->regs + HDA_IPFS_CONFIG);
89 /* Enable MEM/IO space and bus master */
90 v = readl(hda->regs + HDA_CFG_CMD);
91 v &= ~HDA_DISABLE_INTR;
92 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
93 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
94 writel(v, hda->regs + HDA_CFG_CMD);
96 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
97 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
98 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
100 v = readl(hda->regs + HDA_IPFS_INTR_MASK);
101 v |= HDA_IPFS_EN_INTR;
102 writel(v, hda->regs + HDA_IPFS_INTR_MASK);
105 static int hda_tegra_enable_clocks(struct hda_tegra *data)
109 rc = clk_prepare_enable(data->hda_clk);
112 rc = clk_prepare_enable(data->hda2codec_2x_clk);
115 rc = clk_prepare_enable(data->hda2hdmi_clk);
117 goto disable_codec_2x;
122 clk_disable_unprepare(data->hda2codec_2x_clk);
124 clk_disable_unprepare(data->hda_clk);
128 static void hda_tegra_disable_clocks(struct hda_tegra *data)
130 clk_disable_unprepare(data->hda2hdmi_clk);
131 clk_disable_unprepare(data->hda2codec_2x_clk);
132 clk_disable_unprepare(data->hda_clk);
138 static int __maybe_unused hda_tegra_suspend(struct device *dev)
140 struct snd_card *card = dev_get_drvdata(dev);
143 rc = pm_runtime_force_suspend(dev);
146 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
151 static int __maybe_unused hda_tegra_resume(struct device *dev)
153 struct snd_card *card = dev_get_drvdata(dev);
156 rc = pm_runtime_force_resume(dev);
159 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
164 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
166 struct snd_card *card = dev_get_drvdata(dev);
167 struct azx *chip = card->private_data;
168 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
169 struct hdac_bus *bus = azx_bus(chip);
171 if (chip && chip->running) {
173 synchronize_irq(bus->irq);
174 azx_enter_link_reset(chip);
176 hda_tegra_disable_clocks(hda);
181 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
183 struct snd_card *card = dev_get_drvdata(dev);
184 struct azx *chip = card->private_data;
185 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
188 rc = hda_tegra_enable_clocks(hda);
191 if (chip && chip->running) {
193 azx_init_chip(chip, 1);
199 static const struct dev_pm_ops hda_tegra_pm = {
200 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
201 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
202 hda_tegra_runtime_resume,
206 static int hda_tegra_dev_disconnect(struct snd_device *device)
208 struct azx *chip = device->device_data;
210 chip->bus.shutdown = 1;
217 static int hda_tegra_dev_free(struct snd_device *device)
219 struct azx *chip = device->device_data;
220 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
222 cancel_work_sync(&hda->probe_work);
223 if (azx_bus(chip)->chip_init) {
224 azx_stop_all_streams(chip);
228 azx_free_stream_pages(chip);
229 azx_free_streams(chip);
230 snd_hdac_bus_exit(azx_bus(chip));
235 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
237 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
238 struct hdac_bus *bus = azx_bus(chip);
239 struct device *dev = hda->dev;
240 struct resource *res;
242 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
243 hda->regs = devm_ioremap_resource(dev, res);
244 if (IS_ERR(hda->regs))
245 return PTR_ERR(hda->regs);
247 bus->remap_addr = hda->regs + HDA_BAR0;
248 bus->addr = res->start + HDA_BAR0;
255 static int hda_tegra_init_clk(struct hda_tegra *hda)
257 struct device *dev = hda->dev;
259 hda->hda_clk = devm_clk_get(dev, "hda");
260 if (IS_ERR(hda->hda_clk)) {
261 dev_err(dev, "failed to get hda clock\n");
262 return PTR_ERR(hda->hda_clk);
264 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
265 if (IS_ERR(hda->hda2codec_2x_clk)) {
266 dev_err(dev, "failed to get hda2codec_2x clock\n");
267 return PTR_ERR(hda->hda2codec_2x_clk);
269 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
270 if (IS_ERR(hda->hda2hdmi_clk)) {
271 dev_err(dev, "failed to get hda2hdmi clock\n");
272 return PTR_ERR(hda->hda2hdmi_clk);
278 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
280 struct hdac_bus *bus = azx_bus(chip);
281 struct snd_card *card = chip->card;
284 int irq_id = platform_get_irq(pdev, 0);
285 const char *sname, *drv_name = "tegra-hda";
286 struct device_node *np = pdev->dev.of_node;
288 err = hda_tegra_init_chip(chip, pdev);
292 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
293 IRQF_SHARED, KBUILD_MODNAME, chip);
295 dev_err(chip->card->dev,
296 "unable to request IRQ %d, disabling device\n",
302 synchronize_irq(bus->irq);
304 gcap = azx_readw(chip, GCAP);
305 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
307 /* read number of streams from GCAP register instead of using
310 chip->capture_streams = (gcap >> 8) & 0x0f;
311 chip->playback_streams = (gcap >> 12) & 0x0f;
312 if (!chip->playback_streams && !chip->capture_streams) {
313 /* gcap didn't give any info, switching to old method */
314 chip->playback_streams = NUM_PLAYBACK_SD;
315 chip->capture_streams = NUM_CAPTURE_SD;
317 chip->capture_index_offset = 0;
318 chip->playback_index_offset = chip->capture_streams;
319 chip->num_streams = chip->playback_streams + chip->capture_streams;
321 /* initialize streams */
322 err = azx_init_streams(chip);
324 dev_err(card->dev, "failed to initialize streams: %d\n", err);
328 err = azx_alloc_stream_pages(chip);
330 dev_err(card->dev, "failed to allocate stream pages: %d\n",
335 /* initialize chip */
336 azx_init_chip(chip, 1);
338 /* codec detection */
339 if (!bus->codec_mask) {
340 dev_err(card->dev, "no codecs found!\n");
345 strncpy(card->driver, drv_name, sizeof(card->driver));
346 /* shortname for card */
347 sname = of_get_property(np, "nvidia,model", NULL);
350 if (strlen(sname) > sizeof(card->shortname))
351 dev_info(card->dev, "truncating shortname for card\n");
352 strncpy(card->shortname, sname, sizeof(card->shortname));
354 /* longname for card */
355 snprintf(card->longname, sizeof(card->longname),
356 "%s at 0x%lx irq %i",
357 card->shortname, bus->addr, bus->irq);
366 static void hda_tegra_probe_work(struct work_struct *work);
368 static int hda_tegra_create(struct snd_card *card,
369 unsigned int driver_caps,
370 struct hda_tegra *hda)
372 static struct snd_device_ops ops = {
373 .dev_disconnect = hda_tegra_dev_disconnect,
374 .dev_free = hda_tegra_dev_free,
381 mutex_init(&chip->open_mutex);
383 chip->ops = &hda_tegra_ops;
384 chip->driver_caps = driver_caps;
385 chip->driver_type = driver_caps & 0xff;
387 INIT_LIST_HEAD(&chip->pcm_list);
389 chip->codec_probe_mask = -1;
391 chip->single_cmd = false;
394 INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
396 err = azx_bus_init(chip, NULL);
400 chip->bus.needs_damn_long_delay = 1;
402 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
404 dev_err(card->dev, "Error creating device\n");
411 static const struct of_device_id hda_tegra_match[] = {
412 { .compatible = "nvidia,tegra30-hda" },
415 MODULE_DEVICE_TABLE(of, hda_tegra_match);
417 static int hda_tegra_probe(struct platform_device *pdev)
419 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
420 AZX_DCAPS_PM_RUNTIME;
421 struct snd_card *card;
423 struct hda_tegra *hda;
426 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
429 hda->dev = &pdev->dev;
432 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
433 THIS_MODULE, 0, &card);
435 dev_err(&pdev->dev, "Error creating card!\n");
439 err = hda_tegra_init_clk(hda);
443 err = hda_tegra_create(card, driver_flags, hda);
446 card->private_data = chip;
448 dev_set_drvdata(&pdev->dev, card);
450 pm_runtime_enable(hda->dev);
451 if (!azx_has_pm_runtime(chip))
452 pm_runtime_forbid(hda->dev);
454 schedule_work(&hda->probe_work);
463 static void hda_tegra_probe_work(struct work_struct *work)
465 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
466 struct azx *chip = &hda->chip;
467 struct platform_device *pdev = to_platform_device(hda->dev);
470 pm_runtime_get_sync(hda->dev);
471 err = hda_tegra_first_init(chip, pdev);
475 /* create codec instances */
476 err = azx_probe_codecs(chip, 8);
480 err = azx_codec_configure(chip);
484 err = snd_card_register(chip->card);
489 snd_hda_set_power_save(&chip->bus, power_save * 1000);
492 pm_runtime_put(hda->dev);
493 return; /* no error return from async probe */
496 static int hda_tegra_remove(struct platform_device *pdev)
500 ret = snd_card_free(dev_get_drvdata(&pdev->dev));
501 pm_runtime_disable(&pdev->dev);
506 static void hda_tegra_shutdown(struct platform_device *pdev)
508 struct snd_card *card = dev_get_drvdata(&pdev->dev);
513 chip = card->private_data;
514 if (chip && chip->running)
518 static struct platform_driver tegra_platform_hda = {
522 .of_match_table = hda_tegra_match,
524 .probe = hda_tegra_probe,
525 .remove = hda_tegra_remove,
526 .shutdown = hda_tegra_shutdown,
528 module_platform_driver(tegra_platform_hda);
530 MODULE_DESCRIPTION("Tegra HDA bus driver");
531 MODULE_LICENSE("GPL v2");