2 * Common defines for the alsa driver code base for HD Audio.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #ifndef __SOUND_HDA_PRIV_H
16 #define __SOUND_HDA_PRIV_H
18 #include <linux/clocksource.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
25 #define ICH6_REG_GCAP 0x00
26 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
27 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
28 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
29 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
30 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
31 #define ICH6_REG_VMIN 0x02
32 #define ICH6_REG_VMAJ 0x03
33 #define ICH6_REG_OUTPAY 0x04
34 #define ICH6_REG_INPAY 0x06
35 #define ICH6_REG_GCTL 0x08
36 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
37 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
38 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
39 #define ICH6_REG_WAKEEN 0x0c
40 #define ICH6_REG_STATESTS 0x0e
41 #define ICH6_REG_GSTS 0x10
42 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
43 #define ICH6_REG_INTCTL 0x20
44 #define ICH6_REG_INTSTS 0x24
45 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
46 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
47 #define ICH6_REG_SSYNC 0x38
48 #define ICH6_REG_CORBLBASE 0x40
49 #define ICH6_REG_CORBUBASE 0x44
50 #define ICH6_REG_CORBWP 0x48
51 #define ICH6_REG_CORBRP 0x4a
52 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
53 #define ICH6_REG_CORBCTL 0x4c
54 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
55 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
56 #define ICH6_REG_CORBSTS 0x4d
57 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
58 #define ICH6_REG_CORBSIZE 0x4e
60 #define ICH6_REG_RIRBLBASE 0x50
61 #define ICH6_REG_RIRBUBASE 0x54
62 #define ICH6_REG_RIRBWP 0x58
63 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
64 #define ICH6_REG_RINTCNT 0x5a
65 #define ICH6_REG_RIRBCTL 0x5c
66 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
67 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
68 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
69 #define ICH6_REG_RIRBSTS 0x5d
70 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
71 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
72 #define ICH6_REG_RIRBSIZE 0x5e
74 #define ICH6_REG_IC 0x60
75 #define ICH6_REG_IR 0x64
76 #define ICH6_REG_IRS 0x68
77 #define ICH6_IRS_VALID (1<<1)
78 #define ICH6_IRS_BUSY (1<<0)
80 #define ICH6_REG_DPLBASE 0x70
81 #define ICH6_REG_DPUBASE 0x74
82 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
84 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
85 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
87 /* stream register offsets from stream base */
88 #define ICH6_REG_SD_CTL 0x00
89 #define ICH6_REG_SD_STS 0x03
90 #define ICH6_REG_SD_LPIB 0x04
91 #define ICH6_REG_SD_CBL 0x08
92 #define ICH6_REG_SD_LVI 0x0c
93 #define ICH6_REG_SD_FIFOW 0x0e
94 #define ICH6_REG_SD_FIFOSIZE 0x10
95 #define ICH6_REG_SD_FORMAT 0x12
96 #define ICH6_REG_SD_BDLPL 0x18
97 #define ICH6_REG_SD_BDLPU 0x1c
100 #define ICH6_PCIREG_TCSEL 0x44
106 /* max number of SDs */
107 /* ICH, ATI and VIA have 4 playback and 4 capture */
108 #define ICH6_NUM_CAPTURE 4
109 #define ICH6_NUM_PLAYBACK 4
111 /* ULI has 6 playback and 5 capture */
112 #define ULI_NUM_CAPTURE 5
113 #define ULI_NUM_PLAYBACK 6
115 /* ATI HDMI may have up to 8 playbacks and 0 capture */
116 #define ATIHDMI_NUM_CAPTURE 0
117 #define ATIHDMI_NUM_PLAYBACK 8
119 /* TERA has 4 playback and 3 capture */
120 #define TERA_NUM_CAPTURE 3
121 #define TERA_NUM_PLAYBACK 4
123 /* this number is statically defined for simplicity */
124 #define MAX_AZX_DEV 16
126 /* max number of fragments - we may use more if allocating more pages for BDL */
127 #define BDL_SIZE 4096
128 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
129 #define AZX_MAX_FRAG 32
130 /* max buffer size - no h/w limit, you can increase as you like */
131 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
133 /* RIRB int mask: overrun[2], response[0] */
134 #define RIRB_INT_RESPONSE 0x01
135 #define RIRB_INT_OVERRUN 0x04
136 #define RIRB_INT_MASK 0x05
138 /* STATESTS int mask: S3,SD2,SD1,SD0 */
139 #define AZX_MAX_CODECS 8
140 #define AZX_DEFAULT_CODECS 4
141 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
144 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
145 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
146 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
147 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
148 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
149 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
150 #define SD_CTL_STREAM_TAG_SHIFT 20
152 /* SD_CTL and SD_STS */
153 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
154 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
155 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
156 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
160 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
162 /* INTCTL and INTSTS */
163 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
164 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
165 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
167 /* below are so far hardcoded - should read registers in future */
168 #define ICH6_MAX_CORB_ENTRIES 256
169 #define ICH6_MAX_RIRB_ENTRIES 256
171 /* driver quirks (capabilities) */
172 /* bits 0-7 are used for indicating driver type */
173 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
174 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
175 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
176 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
177 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
178 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
179 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
180 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
181 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
182 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
183 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
184 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
185 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
186 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
187 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
188 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
189 #define AZX_DCAPS_REVERSE_ASSIGN (1 << 24) /* Assign devices in reverse order */
190 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
191 #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
192 #define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */
193 #define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */
195 /* position fix mode */
204 /* Defines for ATI HD Audio support in SB450 south bridge */
205 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
206 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
208 /* Defines for Nvidia HDA support */
209 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
210 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
211 #define NVIDIA_HDA_ISTRM_COH 0x4d
212 #define NVIDIA_HDA_OSTRM_COH 0x4c
213 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
215 /* Defines for Intel SCH HDA snoop control */
216 #define INTEL_SCH_HDA_DEVC 0x78
217 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
219 /* Define IN stream 0 FIFO size offset in VIA controller */
220 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
221 /* Define VIA HD Audio Device ID*/
222 #define VIA_HDAC_DEVICE_ID 0x3288
224 /* HD Audio class code */
225 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
228 struct snd_dma_buffer bdl; /* BDL buffer */
229 u32 *posbuf; /* position buffer pointer */
231 unsigned int bufsize; /* size of the play buffer in bytes */
232 unsigned int period_bytes; /* size of the period in bytes */
233 unsigned int frags; /* number for period in the play buffer */
234 unsigned int fifo_size; /* FIFO size */
235 unsigned long start_wallclk; /* start + minimum wallclk */
236 unsigned long period_wallclk; /* wallclk for period */
238 void __iomem *sd_addr; /* stream descriptor pointer */
240 u32 sd_int_sta_mask; /* stream int status mask */
243 struct snd_pcm_substream *substream; /* assigned substream,
246 unsigned int format_val; /* format value to be set in the
247 * controller and the codec
249 unsigned char stream_tag; /* assigned stream */
250 unsigned char index; /* stream index */
251 int assigned_key; /* last device# key assigned to */
253 unsigned int opened:1;
254 unsigned int running:1;
255 unsigned int irq_pending:1;
256 unsigned int prepared:1;
257 unsigned int locked:1;
260 * A flag to ensure DMA position is 0
261 * when link position is not greater than FIFO size
263 unsigned int insufficient:1;
264 unsigned int wc_marked:1;
265 unsigned int no_period_wakeup:1;
267 struct timecounter azx_tc;
268 struct cyclecounter azx_cc;
270 int delay_negative_threshold;
272 #ifdef CONFIG_SND_HDA_DSP_LOADER
273 /* Allows dsp load to have sole access to the playback stream. */
274 struct mutex dsp_mutex;
280 u32 *buf; /* CORB/RIRB buffer
281 * Each CORB entry is 4byte, RIRB is 8byte
283 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
285 unsigned short rp, wp; /* read/write pointers */
286 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
287 u32 res[AZX_MAX_CODECS]; /* last read value */
292 /* Functions to read/write to hda registers. */
293 struct hda_controller_ops {
294 /* Register Access */
295 void (*reg_writel)(u32 value, u32 __iomem *addr);
296 u32 (*reg_readl)(u32 __iomem *addr);
297 void (*reg_writew)(u16 value, u16 __iomem *addr);
298 u16 (*reg_readw)(u16 __iomem *addr);
299 void (*reg_writeb)(u8 value, u8 __iomem *addr);
300 u8 (*reg_readb)(u8 __iomem *addr);
301 /* Disable msi if supported, PCI only */
302 int (*disable_msi_reset_irq)(struct azx *);
304 int (*dma_alloc_pages)(struct azx *chip,
307 struct snd_dma_buffer *buf);
308 void (*dma_free_pages)(struct azx *chip, struct snd_dma_buffer *buf);
309 int (*substream_alloc_pages)(struct azx *chip,
310 struct snd_pcm_substream *substream,
312 int (*substream_free_pages)(struct azx *chip,
313 struct snd_pcm_substream *substream);
314 void (*pcm_mmap_prepare)(struct snd_pcm_substream *substream,
315 struct vm_area_struct *area);
316 /* Check if current position is acceptable */
317 int (*position_check)(struct azx *chip, struct azx_dev *azx_dev);
323 struct hda_codec *codec;
324 struct hda_pcm_stream *hinfo[2];
325 struct list_head list;
329 struct snd_card *card;
333 /* chip type specific */
335 unsigned int driver_caps;
336 int playback_streams;
337 int playback_index_offset;
339 int capture_index_offset;
341 const int *jackpoll_ms; /* per-card jack poll interval */
343 /* Register interaction. */
344 const struct hda_controller_ops *ops;
348 void __iomem *remap_addr;
353 struct mutex open_mutex; /* Prevents concurrent open/close operations */
354 struct completion probe_wait;
356 /* streams (x num_streams) */
357 struct azx_dev *azx_dev;
360 struct list_head pcm_list; /* azx_pcm list */
363 unsigned short codec_mask;
364 int codec_probe_mask; /* copied from probe_mask option */
366 unsigned int beep_mode;
372 /* CORB/RIRB and position buffers */
373 struct snd_dma_buffer rb;
374 struct snd_dma_buffer posbuf;
376 #ifdef CONFIG_SND_HDA_PATCH_LOADER
377 const struct firmware *fw;
381 int position_fix[2]; /* for both playback/capture streams */
382 const int *bdl_pos_adj;
384 unsigned int running:1;
385 unsigned int initialized:1;
386 unsigned int single_cmd:1;
387 unsigned int polling_mode:1;
389 unsigned int irq_pending_warned:1;
390 unsigned int probing:1; /* codec probing phase */
391 unsigned int snoop:1;
392 unsigned int align_buffer_size:1;
393 unsigned int region_requested:1;
395 /* VGA-switcheroo setup */
396 unsigned int use_vga_switcheroo:1;
397 unsigned int vga_switcheroo_registered:1;
398 unsigned int init_failed:1; /* delayed init failed */
399 unsigned int disabled:1; /* disabled by VGA-switcher */
402 unsigned int last_cmd[AZX_MAX_CODECS];
404 /* for pending irqs */
405 struct work_struct irq_pending_work;
407 struct work_struct probe_work;
409 /* reboot notifier (for mysterious hangup problem at power-down) */
410 struct notifier_block reboot_notifier;
412 /* card list (for power_save trigger) */
413 struct list_head list;
415 #ifdef CONFIG_SND_HDA_DSP_LOADER
416 struct azx_dev saved_azx_dev;
419 /* secondary power domain for hdmi audio under vga device */
420 struct dev_pm_domain hdmi_pm_domain;
423 #ifdef CONFIG_SND_VERBOSE_PRINTK
424 #define SFX /* nop */
426 #define SFX "hda-intel "
430 #define azx_snoop(chip) ((chip)->snoop)
432 #define azx_snoop(chip) true
436 * macros for easy use
439 #define azx_writel(chip, reg, value) \
440 ((chip)->ops->reg_writel(value, (chip)->remap_addr + ICH6_REG_##reg))
441 #define azx_readl(chip, reg) \
442 ((chip)->ops->reg_readl((chip)->remap_addr + ICH6_REG_##reg))
443 #define azx_writew(chip, reg, value) \
444 ((chip)->ops->reg_writew(value, (chip)->remap_addr + ICH6_REG_##reg))
445 #define azx_readw(chip, reg) \
446 ((chip)->ops->reg_readw((chip)->remap_addr + ICH6_REG_##reg))
447 #define azx_writeb(chip, reg, value) \
448 ((chip)->ops->reg_writeb(value, (chip)->remap_addr + ICH6_REG_##reg))
449 #define azx_readb(chip, reg) \
450 ((chip)->ops->reg_readb((chip)->remap_addr + ICH6_REG_##reg))
452 #define azx_sd_writel(chip, dev, reg, value) \
453 ((chip)->ops->reg_writel(value, (dev)->sd_addr + ICH6_REG_##reg))
454 #define azx_sd_readl(chip, dev, reg) \
455 ((chip)->ops->reg_readl((dev)->sd_addr + ICH6_REG_##reg))
456 #define azx_sd_writew(chip, dev, reg, value) \
457 ((chip)->ops->reg_writew(value, (dev)->sd_addr + ICH6_REG_##reg))
458 #define azx_sd_readw(chip, dev, reg) \
459 ((chip)->ops->reg_readw((dev)->sd_addr + ICH6_REG_##reg))
460 #define azx_sd_writeb(chip, dev, reg, value) \
461 ((chip)->ops->reg_writeb(value, (dev)->sd_addr + ICH6_REG_##reg))
462 #define azx_sd_readb(chip, dev, reg) \
463 ((chip)->ops->reg_readb((dev)->sd_addr + ICH6_REG_##reg))
465 #endif /* __SOUND_HDA_PRIV_H */