sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/set_memory.h>
  57 #include <asm/cpufeature.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <sound/hdaudio.h>
  62 #include <sound/hda_i915.h>
  63 #include <linux/vgaarb.h>
  64 #include <linux/vga_switcheroo.h>
  65 #include <linux/firmware.h>
  66 #include <sound/hda_codec.h>
  67 #include "hda_controller.h"
  68 #include "hda_intel.h"
  69
  70 #define CREATE_TRACE_POINTS
  71 #include "hda_intel_trace.h"
  72
  73 /* position fix mode */
  74 enum {
  75         POS_FIX_AUTO,
  76         POS_FIX_LPIB,
  77         POS_FIX_POSBUF,
  78         POS_FIX_VIACOMBO,
  79         POS_FIX_COMBO,
  80         POS_FIX_SKL,
  81 };
  82
  83 /* Defines for ATI HD Audio support in SB450 south bridge */
  84 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  85 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  86
  87 /* Defines for Nvidia HDA support */
  88 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  89 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  90 #define NVIDIA_HDA_ISTRM_COH          0x4d
  91 #define NVIDIA_HDA_OSTRM_COH          0x4c
  92 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  93
  94 /* Defines for Intel SCH HDA snoop control */
  95 #define INTEL_HDA_CGCTL  0x48
  96 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  97 #define INTEL_SCH_HDA_DEVC      0x78
  98 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  99
 100 /* Define IN stream 0 FIFO size offset in VIA controller */
 101 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 102 /* Define VIA HD Audio Device ID*/
 103 #define VIA_HDAC_DEVICE_ID              0x3288
 104
 105 /* max number of SDs */
 106 /* ICH, ATI and VIA have 4 playback and 4 capture */
 107 #define ICH6_NUM_CAPTURE        4
 108 #define ICH6_NUM_PLAYBACK       4
 109
 110 /* ULI has 6 playback and 5 capture */
 111 #define ULI_NUM_CAPTURE         5
 112 #define ULI_NUM_PLAYBACK        6
 113
 114 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 115 #define ATIHDMI_NUM_CAPTURE     0
 116 #define ATIHDMI_NUM_PLAYBACK    8
 117
 118 /* TERA has 4 playback and 3 capture */
 119 #define TERA_NUM_CAPTURE        3
 120 #define TERA_NUM_PLAYBACK       4
 121
 122
 123 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 124 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 125 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 126 static char *model[SNDRV_CARDS];
 127 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 128 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 129 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 130 static int probe_only[SNDRV_CARDS];
 131 static int jackpoll_ms[SNDRV_CARDS];
 132 static int single_cmd = -1;
 133 static int enable_msi = -1;
 134 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 135 static char *patch[SNDRV_CARDS];
 136 #endif
 137 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 138 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 139                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 140 #endif
 141
 142 module_param_array(index, int, NULL, 0444);
 143 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 144 module_param_array(id, charp, NULL, 0444);
 145 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 146 module_param_array(enable, bool, NULL, 0444);
 147 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 148 module_param_array(model, charp, NULL, 0444);
 149 MODULE_PARM_DESC(model, "Use the given board model.");
 150 module_param_array(position_fix, int, NULL, 0444);
 151 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 152                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
 153 module_param_array(bdl_pos_adj, int, NULL, 0644);
 154 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 155 module_param_array(probe_mask, int, NULL, 0444);
 156 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 157 module_param_array(probe_only, int, NULL, 0444);
 158 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 159 module_param_array(jackpoll_ms, int, NULL, 0444);
 160 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 161 module_param(single_cmd, bint, 0444);
 162 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 163                  "(for debugging only).");
 164 module_param(enable_msi, bint, 0444);
 165 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 166 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 167 module_param_array(patch, charp, NULL, 0444);
 168 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 169 #endif
 170 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 171 module_param_array(beep_mode, bool, NULL, 0444);
 172 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 173                             "(0=off, 1=on) (default=1).");
 174 #endif
 175
 176 #ifdef CONFIG_PM
 177 static int param_set_xint(const char *val, const struct kernel_param *kp);
 178 static const struct kernel_param_ops param_ops_xint = {
 179         .set = param_set_xint,
 180         .get = param_get_int,
 181 };
 182 #define param_check_xint param_check_int
 183
 184 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 185 module_param(power_save, xint, 0644);
 186 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 187                  "(in second, 0 = disable).");
 188
 189 static bool pm_blacklist = true;
 190 module_param(pm_blacklist, bool, 0644);
 191 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 192
 193 /* reset the HD-audio controller in power save mode.
 194  * this may give more power-saving, but will take longer time to
 195  * wake up.
 196  */
 197 static bool power_save_controller = 1;
 198 module_param(power_save_controller, bool, 0644);
 199 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 200 #else
 201 #define power_save      0
 202 #endif /* CONFIG_PM */
 203
 204 static int align_buffer_size = -1;
 205 module_param(align_buffer_size, bint, 0644);
 206 MODULE_PARM_DESC(align_buffer_size,
 207                 "Force buffer and period sizes to be multiple of 128 bytes.");
 208
 209 #ifdef CONFIG_X86
 210 static int hda_snoop = -1;
 211 module_param_named(snoop, hda_snoop, bint, 0444);
 212 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 213 #else
 214 #define hda_snoop               true
 215 #endif
 216
 217
 218 MODULE_LICENSE("GPL");
 219 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 220                          "{Intel, ICH6M},"
 221                          "{Intel, ICH7},"
 222                          "{Intel, ESB2},"
 223                          "{Intel, ICH8},"
 224                          "{Intel, ICH9},"
 225                          "{Intel, ICH10},"
 226                          "{Intel, PCH},"
 227                          "{Intel, CPT},"
 228                          "{Intel, PPT},"
 229                          "{Intel, LPT},"
 230                          "{Intel, LPT_LP},"
 231                          "{Intel, WPT_LP},"
 232                          "{Intel, SPT},"
 233                          "{Intel, SPT_LP},"
 234                          "{Intel, HPT},"
 235                          "{Intel, PBG},"
 236                          "{Intel, SCH},"
 237                          "{ATI, SB450},"
 238                          "{ATI, SB600},"
 239                          "{ATI, RS600},"
 240                          "{ATI, RS690},"
 241                          "{ATI, RS780},"
 242                          "{ATI, R600},"
 243                          "{ATI, RV630},"
 244                          "{ATI, RV610},"
 245                          "{ATI, RV670},"
 246                          "{ATI, RV635},"
 247                          "{ATI, RV620},"
 248                          "{ATI, RV770},"
 249                          "{VIA, VT8251},"
 250                          "{VIA, VT8237A},"
 251                          "{SiS, SIS966},"
 252                          "{ULI, M5461}}");
 253 MODULE_DESCRIPTION("Intel HDA driver");
 254
 255 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 256 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 257 #define SUPPORT_VGA_SWITCHEROO
 258 #endif
 259 #endif
 260
 261
 262 /*
 263  */
 264
 265 /* driver types */
 266 enum {
 267         AZX_DRIVER_ICH,
 268         AZX_DRIVER_PCH,
 269         AZX_DRIVER_SCH,
 270         AZX_DRIVER_SKL,
 271         AZX_DRIVER_HDMI,
 272         AZX_DRIVER_ATI,
 273         AZX_DRIVER_ATIHDMI,
 274         AZX_DRIVER_ATIHDMI_NS,
 275         AZX_DRIVER_VIA,
 276         AZX_DRIVER_SIS,
 277         AZX_DRIVER_ULI,
 278         AZX_DRIVER_NVIDIA,
 279         AZX_DRIVER_TERA,
 280         AZX_DRIVER_CTX,
 281         AZX_DRIVER_CTHDA,
 282         AZX_DRIVER_CMEDIA,
 283         AZX_DRIVER_GENERIC,
 284         AZX_NUM_DRIVERS, /* keep this as last entry */
 285 };
 286
 287 #define azx_get_snoop_type(chip) \
 288         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 289 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 290
 291 /* quirks for old Intel chipsets */
 292 #define AZX_DCAPS_INTEL_ICH \
 293         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 294
 295 /* quirks for Intel PCH */
 296 #define AZX_DCAPS_INTEL_PCH_BASE \
 297         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 298          AZX_DCAPS_SNOOP_TYPE(SCH))
 299
 300 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 301 #define AZX_DCAPS_INTEL_PCH_NOPM \
 302         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 303
 304 /* PCH for HSW/BDW; with runtime PM */
 305 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 306 #define AZX_DCAPS_INTEL_PCH \
 307         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 308
 309 /* HSW HDMI */
 310 #define AZX_DCAPS_INTEL_HASWELL \
 311         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 312          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 313          AZX_DCAPS_SNOOP_TYPE(SCH))
 314
 315 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 316 #define AZX_DCAPS_INTEL_BROADWELL \
 317         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 318          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 319          AZX_DCAPS_SNOOP_TYPE(SCH))
 320
 321 #define AZX_DCAPS_INTEL_BAYTRAIL \
 322         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 323
 324 #define AZX_DCAPS_INTEL_BRASWELL \
 325         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 326          AZX_DCAPS_I915_COMPONENT)
 327
 328 #define AZX_DCAPS_INTEL_SKYLAKE \
 329         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 330          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 331
 332 #define AZX_DCAPS_INTEL_BROXTON \
 333         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 334          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 335
 336 /* quirks for ATI SB / AMD Hudson */
 337 #define AZX_DCAPS_PRESET_ATI_SB \
 338         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 339          AZX_DCAPS_SNOOP_TYPE(ATI))
 340
 341 /* quirks for ATI/AMD HDMI */
 342 #define AZX_DCAPS_PRESET_ATI_HDMI \
 343         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 344          AZX_DCAPS_NO_MSI64)
 345
 346 /* quirks for ATI HDMI with snoop off */
 347 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 348         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 349
 350 /* quirks for Nvidia */
 351 #define AZX_DCAPS_PRESET_NVIDIA \
 352         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 353          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 354
 355 #define AZX_DCAPS_PRESET_CTHDA \
 356         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 357          AZX_DCAPS_NO_64BIT |\
 358          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 359
 360 /*
 361  * vga_switcheroo support
 362  */
 363 #ifdef SUPPORT_VGA_SWITCHEROO
 364 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 365 #define needs_eld_notify_link(chip)     ((chip)->need_eld_notify_link)
 366 #else
 367 #define use_vga_switcheroo(chip)        0
 368 #define needs_eld_notify_link(chip)     false
 369 #endif
 370
 371 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 372                                         ((pci)->device == 0x0c0c) || \
 373                                         ((pci)->device == 0x0d0c) || \
 374                                         ((pci)->device == 0x160c))
 375
 376 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 377 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 378 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 379
 380 static char *driver_short_names[] = {
 381         [AZX_DRIVER_ICH] = "HDA Intel",
 382         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 383         [AZX_DRIVER_SCH] = "HDA Intel MID",
 384         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 385         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 386         [AZX_DRIVER_ATI] = "HDA ATI SB",
 387         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 388         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 389         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 390         [AZX_DRIVER_SIS] = "HDA SIS966",
 391         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 392         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 393         [AZX_DRIVER_TERA] = "HDA Teradici",
 394         [AZX_DRIVER_CTX] = "HDA Creative",
 395         [AZX_DRIVER_CTHDA] = "HDA Creative",
 396         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 397         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 398 };
 399
 400 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 401 static void set_default_power_save(struct azx *chip);
 402
 403 /*
 404  * initialize the PCI registers
 405  */
 406 /* update bits in a PCI register byte */
 407 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 408                             unsigned char mask, unsigned char val)
 409 {
 410         unsigned char data;
 411
 412         pci_read_config_byte(pci, reg, &data);
 413         data &= ~mask;
 414         data |= (val & mask);
 415         pci_write_config_byte(pci, reg, data);
 416 }
 417
 418 static void azx_init_pci(struct azx *chip)
 419 {
 420         int snoop_type = azx_get_snoop_type(chip);
 421
 422         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 423          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 424          * Ensuring these bits are 0 clears playback static on some HD Audio
 425          * codecs.
 426          * The PCI register TCSEL is defined in the Intel manuals.
 427          */
 428         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 429                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 430                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 431         }
 432
 433         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 434          * we need to enable snoop.
 435          */
 436         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 437                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 438                         azx_snoop(chip));
 439                 update_pci_byte(chip->pci,
 440                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 441                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 442         }
 443
 444         /* For NVIDIA HDA, enable snoop */
 445         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 446                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 447                         azx_snoop(chip));
 448                 update_pci_byte(chip->pci,
 449                                 NVIDIA_HDA_TRANSREG_ADDR,
 450                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 451                 update_pci_byte(chip->pci,
 452                                 NVIDIA_HDA_ISTRM_COH,
 453                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 454                 update_pci_byte(chip->pci,
 455                                 NVIDIA_HDA_OSTRM_COH,
 456                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 457         }
 458
 459         /* Enable SCH/PCH snoop if needed */
 460         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 461                 unsigned short snoop;
 462                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 463                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 464                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 465                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 466                         if (!azx_snoop(chip))
 467                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 468                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 469                         pci_read_config_word(chip->pci,
 470                                 INTEL_SCH_HDA_DEVC, &snoop);
 471                 }
 472                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 473                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 474                         "Disabled" : "Enabled");
 475         }
 476 }
 477
 478 /*
 479  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 480  * and makes an audio stream sensitive to system latencies when
 481  * 24/32 bits are playing.
 482  * Adjusting threshold of DMA fifo to force the DMA request
 483  * sooner to improve latency tolerance at the expense of power.
 484  */
 485 static void bxt_reduce_dma_latency(struct azx *chip)
 486 {
 487         u32 val;
 488
 489         val = azx_readl(chip, VS_EM4L);
 490         val &= (0x3 << 20);
 491         azx_writel(chip, VS_EM4L, val);
 492 }
 493
 494 /*
 495  * ML_LCAP bits:
 496  *  bit 0: 6 MHz Supported
 497  *  bit 1: 12 MHz Supported
 498  *  bit 2: 24 MHz Supported
 499  *  bit 3: 48 MHz Supported
 500  *  bit 4: 96 MHz Supported
 501  *  bit 5: 192 MHz Supported
 502  */
 503 static int intel_get_lctl_scf(struct azx *chip)
 504 {
 505         struct hdac_bus *bus = azx_bus(chip);
 506         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 507         u32 val, t;
 508         int i;
 509
 510         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 511
 512         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 513                 t = preferred_bits[i];
 514                 if (val & (1 << t))
 515                         return t;
 516         }
 517
 518         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 519         return 0;
 520 }
 521
 522 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 523 {
 524         struct hdac_bus *bus = azx_bus(chip);
 525         u32 val;
 526         int timeout;
 527
 528         /*
 529          * the codecs are sharing the first link setting by default
 530          * If other links are enabled for stream, they need similar fix
 531          */
 532         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 533         val &= ~AZX_MLCTL_SPA;
 534         val |= state << AZX_MLCTL_SPA_SHIFT;
 535         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 536         /* wait for CPA */
 537         timeout = 50;
 538         while (timeout) {
 539                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 540                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 541                         return 0;
 542                 timeout--;
 543                 udelay(10);
 544         }
 545
 546         return -1;
 547 }
 548
 549 static void intel_init_lctl(struct azx *chip)
 550 {
 551         struct hdac_bus *bus = azx_bus(chip);
 552         u32 val;
 553         int ret;
 554
 555         /* 0. check lctl register value is correct or not */
 556         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 557         /* if SCF is already set, let's use it */
 558         if ((val & ML_LCTL_SCF_MASK) != 0)
 559                 return;
 560
 561         /*
 562          * Before operating on SPA, CPA must match SPA.
 563          * Any deviation may result in undefined behavior.
 564          */
 565         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 566                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 567                 return;
 568
 569         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 570         ret = intel_ml_lctl_set_power(chip, 0);
 571         udelay(100);
 572         if (ret)
 573                 goto set_spa;
 574
 575         /* 2. update SCF to select a properly audio clock*/
 576         val &= ~ML_LCTL_SCF_MASK;
 577         val |= intel_get_lctl_scf(chip);
 578         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 579
 580 set_spa:
 581         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 582         intel_ml_lctl_set_power(chip, 1);
 583         udelay(100);
 584 }
 585
 586 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 587 {
 588         struct hdac_bus *bus = azx_bus(chip);
 589         struct pci_dev *pci = chip->pci;
 590         u32 val;
 591
 592         snd_hdac_set_codec_wakeup(bus, true);
 593         if (chip->driver_type == AZX_DRIVER_SKL) {
 594                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 595                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 596                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 597         }
 598         azx_init_chip(chip, full_reset);
 599         if (chip->driver_type == AZX_DRIVER_SKL) {
 600                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 601                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 602                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 603         }
 604
 605         snd_hdac_set_codec_wakeup(bus, false);
 606
 607         /* reduce dma latency to avoid noise */
 608         if (IS_BXT(pci))
 609                 bxt_reduce_dma_latency(chip);
 610
 611         if (bus->mlcap != NULL)
 612                 intel_init_lctl(chip);
 613 }
 614
 615 /* calculate runtime delay from LPIB */
 616 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 617                                    unsigned int pos)
 618 {
 619         struct snd_pcm_substream *substream = azx_dev->core.substream;
 620         int stream = substream->stream;
 621         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 622         int delay;
 623
 624         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 625                 delay = pos - lpib_pos;
 626         else
 627                 delay = lpib_pos - pos;
 628         if (delay < 0) {
 629                 if (delay >= azx_dev->core.delay_negative_threshold)
 630                         delay = 0;
 631                 else
 632                         delay += azx_dev->core.bufsize;
 633         }
 634
 635         if (delay >= azx_dev->core.period_bytes) {
 636                 dev_info(chip->card->dev,
 637                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 638                          delay, azx_dev->core.period_bytes);
 639                 delay = 0;
 640                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 641                 chip->get_delay[stream] = NULL;
 642         }
 643
 644         return bytes_to_frames(substream->runtime, delay);
 645 }
 646
 647 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 648
 649 /* called from IRQ */
 650 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 651 {
 652         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 653         int ok;
 654
 655         ok = azx_position_ok(chip, azx_dev);
 656         if (ok == 1) {
 657                 azx_dev->irq_pending = 0;
 658                 return ok;
 659         } else if (ok == 0) {
 660                 /* bogus IRQ, process it later */
 661                 azx_dev->irq_pending = 1;
 662                 schedule_work(&hda->irq_pending_work);
 663         }
 664         return 0;
 665 }
 666
 667 #define display_power(chip, enable) \
 668         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 669
 670 /*
 671  * Check whether the current DMA position is acceptable for updating
 672  * periods.  Returns non-zero if it's OK.
 673  *
 674  * Many HD-audio controllers appear pretty inaccurate about
 675  * the update-IRQ timing.  The IRQ is issued before actually the
 676  * data is processed.  So, we need to process it afterwords in a
 677  * workqueue.
 678  */
 679 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 680 {
 681         struct snd_pcm_substream *substream = azx_dev->core.substream;
 682         int stream = substream->stream;
 683         u32 wallclk;
 684         unsigned int pos;
 685
 686         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 687         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 688                 return -1;      /* bogus (too early) interrupt */
 689
 690         if (chip->get_position[stream])
 691                 pos = chip->get_position[stream](chip, azx_dev);
 692         else { /* use the position buffer as default */
 693                 pos = azx_get_pos_posbuf(chip, azx_dev);
 694                 if (!pos || pos == (u32)-1) {
 695                         dev_info(chip->card->dev,
 696                                  "Invalid position buffer, using LPIB read method instead.\n");
 697                         chip->get_position[stream] = azx_get_pos_lpib;
 698                         if (chip->get_position[0] == azx_get_pos_lpib &&
 699                             chip->get_position[1] == azx_get_pos_lpib)
 700                                 azx_bus(chip)->use_posbuf = false;
 701                         pos = azx_get_pos_lpib(chip, azx_dev);
 702                         chip->get_delay[stream] = NULL;
 703                 } else {
 704                         chip->get_position[stream] = azx_get_pos_posbuf;
 705                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 706                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 707                 }
 708         }
 709
 710         if (pos >= azx_dev->core.bufsize)
 711                 pos = 0;
 712
 713         if (WARN_ONCE(!azx_dev->core.period_bytes,
 714                       "hda-intel: zero azx_dev->period_bytes"))
 715                 return -1; /* this shouldn't happen! */
 716         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 717             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 718                 /* NG - it's below the first next period boundary */
 719                 return chip->bdl_pos_adj ? 0 : -1;
 720         azx_dev->core.start_wallclk += wallclk;
 721         return 1; /* OK, it's fine */
 722 }
 723
 724 /*
 725  * The work for pending PCM period updates.
 726  */
 727 static void azx_irq_pending_work(struct work_struct *work)
 728 {
 729         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 730         struct azx *chip = &hda->chip;
 731         struct hdac_bus *bus = azx_bus(chip);
 732         struct hdac_stream *s;
 733         int pending, ok;
 734
 735         if (!hda->irq_pending_warned) {
 736                 dev_info(chip->card->dev,
 737                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 738                          chip->card->number);
 739                 hda->irq_pending_warned = 1;
 740         }
 741
 742         for (;;) {
 743                 pending = 0;
 744                 spin_lock_irq(&bus->reg_lock);
 745                 list_for_each_entry(s, &bus->stream_list, list) {
 746                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 747                         if (!azx_dev->irq_pending ||
 748                             !s->substream ||
 749                             !s->running)
 750                                 continue;
 751                         ok = azx_position_ok(chip, azx_dev);
 752                         if (ok > 0) {
 753                                 azx_dev->irq_pending = 0;
 754                                 spin_unlock(&bus->reg_lock);
 755                                 snd_pcm_period_elapsed(s->substream);
 756                                 spin_lock(&bus->reg_lock);
 757                         } else if (ok < 0) {
 758                                 pending = 0;    /* too early */
 759                         } else
 760                                 pending++;
 761                 }
 762                 spin_unlock_irq(&bus->reg_lock);
 763                 if (!pending)
 764                         return;
 765                 msleep(1);
 766         }
 767 }
 768
 769 /* clear irq_pending flags and assure no on-going workq */
 770 static void azx_clear_irq_pending(struct azx *chip)
 771 {
 772         struct hdac_bus *bus = azx_bus(chip);
 773         struct hdac_stream *s;
 774
 775         spin_lock_irq(&bus->reg_lock);
 776         list_for_each_entry(s, &bus->stream_list, list) {
 777                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 778                 azx_dev->irq_pending = 0;
 779         }
 780         spin_unlock_irq(&bus->reg_lock);
 781 }
 782
 783 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 784 {
 785         struct hdac_bus *bus = azx_bus(chip);
 786
 787         if (request_irq(chip->pci->irq, azx_interrupt,
 788                         chip->msi ? 0 : IRQF_SHARED,
 789                         chip->card->irq_descr, chip)) {
 790                 dev_err(chip->card->dev,
 791                         "unable to grab IRQ %d, disabling device\n",
 792                         chip->pci->irq);
 793                 if (do_disconnect)
 794                         snd_card_disconnect(chip->card);
 795                 return -1;
 796         }
 797         bus->irq = chip->pci->irq;
 798         pci_intx(chip->pci, !chip->msi);
 799         return 0;
 800 }
 801
 802 /* get the current DMA position with correction on VIA chips */
 803 static unsigned int azx_via_get_position(struct azx *chip,
 804                                          struct azx_dev *azx_dev)
 805 {
 806         unsigned int link_pos, mini_pos, bound_pos;
 807         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 808         unsigned int fifo_size;
 809
 810         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 811         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 812                 /* Playback, no problem using link position */
 813                 return link_pos;
 814         }
 815
 816         /* Capture */
 817         /* For new chipset,
 818          * use mod to get the DMA position just like old chipset
 819          */
 820         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 821         mod_dma_pos %= azx_dev->core.period_bytes;
 822
 823         /* azx_dev->fifo_size can't get FIFO size of in stream.
 824          * Get from base address + offset.
 825          */
 826         fifo_size = readw(azx_bus(chip)->remap_addr +
 827                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 828
 829         if (azx_dev->insufficient) {
 830                 /* Link position never gather than FIFO size */
 831                 if (link_pos <= fifo_size)
 832                         return 0;
 833
 834                 azx_dev->insufficient = 0;
 835         }
 836
 837         if (link_pos <= fifo_size)
 838                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 839         else
 840                 mini_pos = link_pos - fifo_size;
 841
 842         /* Find nearest previous boudary */
 843         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 844         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 845         if (mod_link_pos >= fifo_size)
 846                 bound_pos = link_pos - mod_link_pos;
 847         else if (mod_dma_pos >= mod_mini_pos)
 848                 bound_pos = mini_pos - mod_mini_pos;
 849         else {
 850                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 851                 if (bound_pos >= azx_dev->core.bufsize)
 852                         bound_pos = 0;
 853         }
 854
 855         /* Calculate real DMA position we want */
 856         return bound_pos + mod_dma_pos;
 857 }
 858
 859 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 860                                          struct azx_dev *azx_dev)
 861 {
 862         return _snd_hdac_chip_readl(azx_bus(chip),
 863                                     AZX_REG_VS_SDXDPIB_XBASE +
 864                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 865                                      azx_dev->core.index));
 866 }
 867
 868 /* get the current DMA position with correction on SKL+ chips */
 869 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 870 {
 871         /* DPIB register gives a more accurate position for playback */
 872         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 873                 return azx_skl_get_dpib_pos(chip, azx_dev);
 874
 875         /* For capture, we need to read posbuf, but it requires a delay
 876          * for the possible boundary overlap; the read of DPIB fetches the
 877          * actual posbuf
 878          */
 879         udelay(20);
 880         azx_skl_get_dpib_pos(chip, azx_dev);
 881         return azx_get_pos_posbuf(chip, azx_dev);
 882 }
 883
 884 #ifdef CONFIG_PM
 885 static DEFINE_MUTEX(card_list_lock);
 886 static LIST_HEAD(card_list);
 887
 888 static void azx_add_card_list(struct azx *chip)
 889 {
 890         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 891         mutex_lock(&card_list_lock);
 892         list_add(&hda->list, &card_list);
 893         mutex_unlock(&card_list_lock);
 894 }
 895
 896 static void azx_del_card_list(struct azx *chip)
 897 {
 898         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 899         mutex_lock(&card_list_lock);
 900         list_del_init(&hda->list);
 901         mutex_unlock(&card_list_lock);
 902 }
 903
 904 /* trigger power-save check at writing parameter */
 905 static int param_set_xint(const char *val, const struct kernel_param *kp)
 906 {
 907         struct hda_intel *hda;
 908         struct azx *chip;
 909         int prev = power_save;
 910         int ret = param_set_int(val, kp);
 911
 912         if (ret || prev == power_save)
 913                 return ret;
 914
 915         mutex_lock(&card_list_lock);
 916         list_for_each_entry(hda, &card_list, list) {
 917                 chip = &hda->chip;
 918                 if (!hda->probe_continued || chip->disabled)
 919                         continue;
 920                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 921         }
 922         mutex_unlock(&card_list_lock);
 923         return 0;
 924 }
 925
 926 /*
 927  * power management
 928  */
 929 static bool azx_is_pm_ready(struct snd_card *card)
 930 {
 931         struct azx *chip;
 932         struct hda_intel *hda;
 933
 934         if (!card)
 935                 return false;
 936         chip = card->private_data;
 937         hda = container_of(chip, struct hda_intel, chip);
 938         if (chip->disabled || hda->init_failed || !chip->running)
 939                 return false;
 940         return true;
 941 }
 942
 943 static void __azx_runtime_suspend(struct azx *chip)
 944 {
 945         azx_stop_chip(chip);
 946         azx_enter_link_reset(chip);
 947         azx_clear_irq_pending(chip);
 948         display_power(chip, false);
 949 }
 950
 951 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 952 {
 953         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 954         struct hdac_bus *bus = azx_bus(chip);
 955         struct hda_codec *codec;
 956         int status;
 957
 958         display_power(chip, true);
 959         if (hda->need_i915_power)
 960                 snd_hdac_i915_set_bclk(bus);
 961
 962         /* Read STATESTS before controller reset */
 963         status = azx_readw(chip, STATESTS);
 964
 965         azx_init_pci(chip);
 966         hda_intel_init_chip(chip, true);
 967
 968         if (status && from_rt) {
 969                 list_for_each_codec(codec, &chip->bus)
 970                         if (status & (1 << codec->addr))
 971                                 schedule_delayed_work(&codec->jackpoll_work,
 972                                                       codec->jackpoll_interval);
 973         }
 974
 975         /* power down again for link-controlled chips */
 976         if (!hda->need_i915_power)
 977                 display_power(chip, false);
 978 }
 979
 980 #ifdef CONFIG_PM_SLEEP
 981 static int azx_suspend(struct device *dev)
 982 {
 983         struct snd_card *card = dev_get_drvdata(dev);
 984         struct azx *chip;
 985         struct hdac_bus *bus;
 986
 987         if (!azx_is_pm_ready(card))
 988                 return 0;
 989
 990         chip = card->private_data;
 991         bus = azx_bus(chip);
 992         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 993         __azx_runtime_suspend(chip);
 994         if (bus->irq >= 0) {
 995                 free_irq(bus->irq, chip);
 996                 bus->irq = -1;
 997         }
 998
 999         if (chip->msi)
1000                 pci_disable_msi(chip->pci);
1001
1002         trace_azx_suspend(chip);
1003         return 0;
1004 }
1005
1006 static int azx_resume(struct device *dev)
1007 {
1008         struct snd_card *card = dev_get_drvdata(dev);
1009         struct azx *chip;
1010
1011         if (!azx_is_pm_ready(card))
1012                 return 0;
1013
1014         chip = card->private_data;
1015         if (chip->msi)
1016                 if (pci_enable_msi(chip->pci) < 0)
1017                         chip->msi = 0;
1018         if (azx_acquire_irq(chip, 1) < 0)
1019                 return -EIO;
1020         __azx_runtime_resume(chip, false);
1021         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1022
1023         trace_azx_resume(chip);
1024         return 0;
1025 }
1026
1027 /* put codec down to D3 at hibernation for Intel SKL+;
1028  * otherwise BIOS may still access the codec and screw up the driver
1029  */
1030 static int azx_freeze_noirq(struct device *dev)
1031 {
1032         struct snd_card *card = dev_get_drvdata(dev);
1033         struct azx *chip = card->private_data;
1034         struct pci_dev *pci = to_pci_dev(dev);
1035
1036         if (chip->driver_type == AZX_DRIVER_SKL)
1037                 pci_set_power_state(pci, PCI_D3hot);
1038
1039         return 0;
1040 }
1041
1042 static int azx_thaw_noirq(struct device *dev)
1043 {
1044         struct snd_card *card = dev_get_drvdata(dev);
1045         struct azx *chip = card->private_data;
1046         struct pci_dev *pci = to_pci_dev(dev);
1047
1048         if (chip->driver_type == AZX_DRIVER_SKL)
1049                 pci_set_power_state(pci, PCI_D0);
1050
1051         return 0;
1052 }
1053 #endif /* CONFIG_PM_SLEEP */
1054
1055 static int azx_runtime_suspend(struct device *dev)
1056 {
1057         struct snd_card *card = dev_get_drvdata(dev);
1058         struct azx *chip;
1059
1060         if (!azx_is_pm_ready(card))
1061                 return 0;
1062         chip = card->private_data;
1063         if (!azx_has_pm_runtime(chip))
1064                 return 0;
1065
1066         /* enable controller wake up event */
1067         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1068                   STATESTS_INT_MASK);
1069
1070         __azx_runtime_suspend(chip);
1071         trace_azx_runtime_suspend(chip);
1072         return 0;
1073 }
1074
1075 static int azx_runtime_resume(struct device *dev)
1076 {
1077         struct snd_card *card = dev_get_drvdata(dev);
1078         struct azx *chip;
1079
1080         if (!azx_is_pm_ready(card))
1081                 return 0;
1082         chip = card->private_data;
1083         if (!azx_has_pm_runtime(chip))
1084                 return 0;
1085         __azx_runtime_resume(chip, true);
1086
1087         /* disable controller Wake Up event*/
1088         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1089                         ~STATESTS_INT_MASK);
1090
1091         trace_azx_runtime_resume(chip);
1092         return 0;
1093 }
1094
1095 static int azx_runtime_idle(struct device *dev)
1096 {
1097         struct snd_card *card = dev_get_drvdata(dev);
1098         struct azx *chip;
1099         struct hda_intel *hda;
1100
1101         if (!card)
1102                 return 0;
1103
1104         chip = card->private_data;
1105         hda = container_of(chip, struct hda_intel, chip);
1106         if (chip->disabled || hda->init_failed)
1107                 return 0;
1108
1109         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1110             azx_bus(chip)->codec_powered || !chip->running)
1111                 return -EBUSY;
1112
1113         /* ELD notification gets broken when HD-audio bus is off */
1114         if (needs_eld_notify_link(hda))
1115                 return -EBUSY;
1116
1117         return 0;
1118 }
1119
1120 static const struct dev_pm_ops azx_pm = {
1121         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1122 #ifdef CONFIG_PM_SLEEP
1123         .freeze_noirq = azx_freeze_noirq,
1124         .thaw_noirq = azx_thaw_noirq,
1125 #endif
1126         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1127 };
1128
1129 #define AZX_PM_OPS      &azx_pm
1130 #else
1131 #define azx_add_card_list(chip) /* NOP */
1132 #define azx_del_card_list(chip) /* NOP */
1133 #define AZX_PM_OPS      NULL
1134 #endif /* CONFIG_PM */
1135
1136
1137 static int azx_probe_continue(struct azx *chip);
1138
1139 #ifdef SUPPORT_VGA_SWITCHEROO
1140 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1141
1142 static void azx_vs_set_state(struct pci_dev *pci,
1143                              enum vga_switcheroo_state state)
1144 {
1145         struct snd_card *card = pci_get_drvdata(pci);
1146         struct azx *chip = card->private_data;
1147         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1148         struct hda_codec *codec;
1149         bool disabled;
1150
1151         wait_for_completion(&hda->probe_wait);
1152         if (hda->init_failed)
1153                 return;
1154
1155         disabled = (state == VGA_SWITCHEROO_OFF);
1156         if (chip->disabled == disabled)
1157                 return;
1158
1159         if (!hda->probe_continued) {
1160                 chip->disabled = disabled;
1161                 if (!disabled) {
1162                         dev_info(chip->card->dev,
1163                                  "Start delayed initialization\n");
1164                         if (azx_probe_continue(chip) < 0) {
1165                                 dev_err(chip->card->dev, "initialization error\n");
1166                                 hda->init_failed = true;
1167                         }
1168                 }
1169         } else {
1170                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1171                          disabled ? "Disabling" : "Enabling");
1172                 if (disabled) {
1173                         list_for_each_codec(codec, &chip->bus) {
1174                                 pm_runtime_suspend(hda_codec_dev(codec));
1175                                 pm_runtime_disable(hda_codec_dev(codec));
1176                         }
1177                         pm_runtime_suspend(card->dev);
1178                         pm_runtime_disable(card->dev);
1179                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1180                          * however we have no ACPI handle, so pci/acpi can't put us there,
1181                          * put ourselves there */
1182                         pci->current_state = PCI_D3cold;
1183                         chip->disabled = true;
1184                         if (snd_hda_lock_devices(&chip->bus))
1185                                 dev_warn(chip->card->dev,
1186                                          "Cannot lock devices!\n");
1187                 } else {
1188                         snd_hda_unlock_devices(&chip->bus);
1189                         chip->disabled = false;
1190                         pm_runtime_enable(card->dev);
1191                         list_for_each_codec(codec, &chip->bus) {
1192                                 pm_runtime_enable(hda_codec_dev(codec));
1193                                 pm_runtime_resume(hda_codec_dev(codec));
1194                         }
1195                 }
1196         }
1197 }
1198
1199 static bool azx_vs_can_switch(struct pci_dev *pci)
1200 {
1201         struct snd_card *card = pci_get_drvdata(pci);
1202         struct azx *chip = card->private_data;
1203         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1204
1205         wait_for_completion(&hda->probe_wait);
1206         if (hda->init_failed)
1207                 return false;
1208         if (chip->disabled || !hda->probe_continued)
1209                 return true;
1210         if (snd_hda_lock_devices(&chip->bus))
1211                 return false;
1212         snd_hda_unlock_devices(&chip->bus);
1213         return true;
1214 }
1215
1216 /*
1217  * The discrete GPU cannot power down unless the HDA controller runtime
1218  * suspends, so activate runtime PM on codecs even if power_save == 0.
1219  */
1220 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1221 {
1222         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1223         struct hda_codec *codec;
1224
1225         if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1226                 list_for_each_codec(codec, &chip->bus)
1227                         codec->auto_runtime_pm = 1;
1228                 /* reset the power save setup */
1229                 if (chip->running)
1230                         set_default_power_save(chip);
1231         }
1232 }
1233
1234 static void azx_vs_gpu_bound(struct pci_dev *pci,
1235                              enum vga_switcheroo_client_id client_id)
1236 {
1237         struct snd_card *card = pci_get_drvdata(pci);
1238         struct azx *chip = card->private_data;
1239         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1240
1241         if (client_id == VGA_SWITCHEROO_DIS)
1242                 hda->need_eld_notify_link = 0;
1243         setup_vga_switcheroo_runtime_pm(chip);
1244 }
1245
1246 static void init_vga_switcheroo(struct azx *chip)
1247 {
1248         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1249         struct pci_dev *p = get_bound_vga(chip->pci);
1250         if (p) {
1251                 dev_info(chip->card->dev,
1252                          "Handle vga_switcheroo audio client\n");
1253                 hda->use_vga_switcheroo = 1;
1254                 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
1255                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1256                 pci_dev_put(p);
1257         }
1258 }
1259
1260 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1261         .set_gpu_state = azx_vs_set_state,
1262         .can_switch = azx_vs_can_switch,
1263         .gpu_bound = azx_vs_gpu_bound,
1264 };
1265
1266 static int register_vga_switcheroo(struct azx *chip)
1267 {
1268         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1269         struct pci_dev *p;
1270         int err;
1271
1272         if (!hda->use_vga_switcheroo)
1273                 return 0;
1274
1275         p = get_bound_vga(chip->pci);
1276         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1277         pci_dev_put(p);
1278
1279         if (err < 0)
1280                 return err;
1281         hda->vga_switcheroo_registered = 1;
1282
1283         return 0;
1284 }
1285 #else
1286 #define init_vga_switcheroo(chip)               /* NOP */
1287 #define register_vga_switcheroo(chip)           0
1288 #define check_hdmi_disabled(pci)        false
1289 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1290 #endif /* SUPPORT_VGA_SWITCHER */
1291
1292 /*
1293  * destructor
1294  */
1295 static int azx_free(struct azx *chip)
1296 {
1297         struct pci_dev *pci = chip->pci;
1298         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1299         struct hdac_bus *bus = azx_bus(chip);
1300
1301         if (azx_has_pm_runtime(chip) && chip->running)
1302                 pm_runtime_get_noresume(&pci->dev);
1303         chip->running = 0;
1304
1305         azx_del_card_list(chip);
1306
1307         hda->init_failed = 1; /* to be sure */
1308         complete_all(&hda->probe_wait);
1309
1310         if (use_vga_switcheroo(hda)) {
1311                 if (chip->disabled && hda->probe_continued)
1312                         snd_hda_unlock_devices(&chip->bus);
1313                 if (hda->vga_switcheroo_registered)
1314                         vga_switcheroo_unregister_client(chip->pci);
1315         }
1316
1317         if (bus->chip_init) {
1318                 azx_clear_irq_pending(chip);
1319                 azx_stop_all_streams(chip);
1320                 azx_stop_chip(chip);
1321         }
1322
1323         if (bus->irq >= 0)
1324                 free_irq(bus->irq, (void*)chip);
1325         if (chip->msi)
1326                 pci_disable_msi(chip->pci);
1327         iounmap(bus->remap_addr);
1328
1329         azx_free_stream_pages(chip);
1330         azx_free_streams(chip);
1331         snd_hdac_bus_exit(bus);
1332
1333         if (chip->region_requested)
1334                 pci_release_regions(chip->pci);
1335
1336         pci_disable_device(chip->pci);
1337 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1338         release_firmware(chip->fw);
1339 #endif
1340         display_power(chip, false);
1341
1342         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1343                 snd_hdac_i915_exit(bus);
1344         kfree(hda);
1345
1346         return 0;
1347 }
1348
1349 static int azx_dev_disconnect(struct snd_device *device)
1350 {
1351         struct azx *chip = device->device_data;
1352
1353         chip->bus.shutdown = 1;
1354         return 0;
1355 }
1356
1357 static int azx_dev_free(struct snd_device *device)
1358 {
1359         return azx_free(device->device_data);
1360 }
1361
1362 #ifdef SUPPORT_VGA_SWITCHEROO
1363 /*
1364  * Check of disabled HDMI controller by vga_switcheroo
1365  */
1366 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1367 {
1368         struct pci_dev *p;
1369
1370         /* check only discrete GPU */
1371         switch (pci->vendor) {
1372         case PCI_VENDOR_ID_ATI:
1373         case PCI_VENDOR_ID_AMD:
1374         case PCI_VENDOR_ID_NVIDIA:
1375                 if (pci->devfn == 1) {
1376                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1377                                                         pci->bus->number, 0);
1378                         if (p) {
1379                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1380                                         return p;
1381                                 pci_dev_put(p);
1382                         }
1383                 }
1384                 break;
1385         }
1386         return NULL;
1387 }
1388
1389 static bool check_hdmi_disabled(struct pci_dev *pci)
1390 {
1391         bool vga_inactive = false;
1392         struct pci_dev *p = get_bound_vga(pci);
1393
1394         if (p) {
1395                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1396                         vga_inactive = true;
1397                 pci_dev_put(p);
1398         }
1399         return vga_inactive;
1400 }
1401 #endif /* SUPPORT_VGA_SWITCHEROO */
1402
1403 /*
1404  * white/black-listing for position_fix
1405  */
1406 static struct snd_pci_quirk position_fix_list[] = {
1407         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1408         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1409         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1410         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1411         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1412         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1413         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1414         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1415         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1416         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1417         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1418         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1419         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1420         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1421         {}
1422 };
1423
1424 static int check_position_fix(struct azx *chip, int fix)
1425 {
1426         const struct snd_pci_quirk *q;
1427
1428         switch (fix) {
1429         case POS_FIX_AUTO:
1430         case POS_FIX_LPIB:
1431         case POS_FIX_POSBUF:
1432         case POS_FIX_VIACOMBO:
1433         case POS_FIX_COMBO:
1434         case POS_FIX_SKL:
1435                 return fix;
1436         }
1437
1438         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1439         if (q) {
1440                 dev_info(chip->card->dev,
1441                          "position_fix set to %d for device %04x:%04x\n",
1442                          q->value, q->subvendor, q->subdevice);
1443                 return q->value;
1444         }
1445
1446         /* Check VIA/ATI HD Audio Controller exist */
1447         if (chip->driver_type == AZX_DRIVER_VIA) {
1448                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1449                 return POS_FIX_VIACOMBO;
1450         }
1451         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1452                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1453                 return POS_FIX_LPIB;
1454         }
1455         if (chip->driver_type == AZX_DRIVER_SKL) {
1456                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1457                 return POS_FIX_SKL;
1458         }
1459         return POS_FIX_AUTO;
1460 }
1461
1462 static void assign_position_fix(struct azx *chip, int fix)
1463 {
1464         static azx_get_pos_callback_t callbacks[] = {
1465                 [POS_FIX_AUTO] = NULL,
1466                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1467                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1468                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1469                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1470                 [POS_FIX_SKL] = azx_get_pos_skl,
1471         };
1472
1473         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1474
1475         /* combo mode uses LPIB only for playback */
1476         if (fix == POS_FIX_COMBO)
1477                 chip->get_position[1] = NULL;
1478
1479         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1480             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1481                 chip->get_delay[0] = chip->get_delay[1] =
1482                         azx_get_delay_from_lpib;
1483         }
1484
1485 }
1486
1487 /*
1488  * black-lists for probe_mask
1489  */
1490 static struct snd_pci_quirk probe_mask_list[] = {
1491         /* Thinkpad often breaks the controller communication when accessing
1492          * to the non-working (or non-existing) modem codec slot.
1493          */
1494         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1495         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1496         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1497         /* broken BIOS */
1498         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1499         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1500         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1501         /* forced codec slots */
1502         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1503         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1504         /* WinFast VP200 H (Teradici) user reported broken communication */
1505         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1506         {}
1507 };
1508
1509 #define AZX_FORCE_CODEC_MASK    0x100
1510
1511 static void check_probe_mask(struct azx *chip, int dev)
1512 {
1513         const struct snd_pci_quirk *q;
1514
1515         chip->codec_probe_mask = probe_mask[dev];
1516         if (chip->codec_probe_mask == -1) {
1517                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1518                 if (q) {
1519                         dev_info(chip->card->dev,
1520                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1521                                  q->value, q->subvendor, q->subdevice);
1522                         chip->codec_probe_mask = q->value;
1523                 }
1524         }
1525
1526         /* check forced option */
1527         if (chip->codec_probe_mask != -1 &&
1528             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1529                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1530                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1531                          (int)azx_bus(chip)->codec_mask);
1532         }
1533 }
1534
1535 /*
1536  * white/black-list for enable_msi
1537  */
1538 static struct snd_pci_quirk msi_black_list[] = {
1539         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1540         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1541         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1542         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1543         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1544         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1545         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1546         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1547         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1548         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1549         {}
1550 };
1551
1552 static void check_msi(struct azx *chip)
1553 {
1554         const struct snd_pci_quirk *q;
1555
1556         if (enable_msi >= 0) {
1557                 chip->msi = !!enable_msi;
1558                 return;
1559         }
1560         chip->msi = 1;  /* enable MSI as default */
1561         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1562         if (q) {
1563                 dev_info(chip->card->dev,
1564                          "msi for device %04x:%04x set to %d\n",
1565                          q->subvendor, q->subdevice, q->value);
1566                 chip->msi = q->value;
1567                 return;
1568         }
1569
1570         /* NVidia chipsets seem to cause troubles with MSI */
1571         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1572                 dev_info(chip->card->dev, "Disabling MSI\n");
1573                 chip->msi = 0;
1574         }
1575 }
1576
1577 /* check the snoop mode availability */
1578 static void azx_check_snoop_available(struct azx *chip)
1579 {
1580         int snoop = hda_snoop;
1581
1582         if (snoop >= 0) {
1583                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1584                          snoop ? "snoop" : "non-snoop");
1585                 chip->snoop = snoop;
1586                 chip->uc_buffer = !snoop;
1587                 return;
1588         }
1589
1590         snoop = true;
1591         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1592             chip->driver_type == AZX_DRIVER_VIA) {
1593                 /* force to non-snoop mode for a new VIA controller
1594                  * when BIOS is set
1595                  */
1596                 u8 val;
1597                 pci_read_config_byte(chip->pci, 0x42, &val);
1598                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1599                                       chip->pci->revision == 0x20))
1600                         snoop = false;
1601         }
1602
1603         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1604                 snoop = false;
1605
1606         chip->snoop = snoop;
1607         if (!snoop) {
1608                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1609                 /* C-Media requires non-cached pages only for CORB/RIRB */
1610                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1611                         chip->uc_buffer = true;
1612         }
1613 }
1614
1615 static void azx_probe_work(struct work_struct *work)
1616 {
1617         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1618         azx_probe_continue(&hda->chip);
1619 }
1620
1621 static int default_bdl_pos_adj(struct azx *chip)
1622 {
1623         /* some exceptions: Atoms seem problematic with value 1 */
1624         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1625                 switch (chip->pci->device) {
1626                 case 0x0f04: /* Baytrail */
1627                 case 0x2284: /* Braswell */
1628                         return 32;
1629                 }
1630         }
1631
1632         switch (chip->driver_type) {
1633         case AZX_DRIVER_ICH:
1634         case AZX_DRIVER_PCH:
1635                 return 1;
1636         default:
1637                 return 32;
1638         }
1639 }
1640
1641 /*
1642  * constructor
1643  */
1644 static const struct hdac_io_ops pci_hda_io_ops;
1645 static const struct hda_controller_ops pci_hda_ops;
1646
1647 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1648                       int dev, unsigned int driver_caps,
1649                       struct azx **rchip)
1650 {
1651         static struct snd_device_ops ops = {
1652                 .dev_disconnect = azx_dev_disconnect,
1653                 .dev_free = azx_dev_free,
1654         };
1655         struct hda_intel *hda;
1656         struct azx *chip;
1657         int err;
1658
1659         *rchip = NULL;
1660
1661         err = pci_enable_device(pci);
1662         if (err < 0)
1663                 return err;
1664
1665         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1666         if (!hda) {
1667                 pci_disable_device(pci);
1668                 return -ENOMEM;
1669         }
1670
1671         chip = &hda->chip;
1672         mutex_init(&chip->open_mutex);
1673         chip->card = card;
1674         chip->pci = pci;
1675         chip->ops = &pci_hda_ops;
1676         chip->driver_caps = driver_caps;
1677         chip->driver_type = driver_caps & 0xff;
1678         check_msi(chip);
1679         chip->dev_index = dev;
1680         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1681                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1682         INIT_LIST_HEAD(&chip->pcm_list);
1683         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1684         INIT_LIST_HEAD(&hda->list);
1685         init_vga_switcheroo(chip);
1686         init_completion(&hda->probe_wait);
1687
1688         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1689
1690         check_probe_mask(chip, dev);
1691
1692         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1693                 chip->fallback_to_single_cmd = 1;
1694         else /* explicitly set to single_cmd or not */
1695                 chip->single_cmd = single_cmd;
1696
1697         azx_check_snoop_available(chip);
1698
1699         if (bdl_pos_adj[dev] < 0)
1700                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1701         else
1702                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1703
1704         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1705         if (err < 0) {
1706                 kfree(hda);
1707                 pci_disable_device(pci);
1708                 return err;
1709         }
1710
1711         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1712         if (IS_CFL(pci) || IS_CNL(pci))
1713                 azx_bus(chip)->polling_mode = 1;
1714
1715         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1716                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1717                 chip->bus.needs_damn_long_delay = 1;
1718         }
1719
1720         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1721         if (err < 0) {
1722                 dev_err(card->dev, "Error creating device [card]!\n");
1723                 azx_free(chip);
1724                 return err;
1725         }
1726
1727         /* continue probing in work context as may trigger request module */
1728         INIT_WORK(&hda->probe_work, azx_probe_work);
1729
1730         *rchip = chip;
1731
1732         return 0;
1733 }
1734
1735 static int azx_first_init(struct azx *chip)
1736 {
1737         int dev = chip->dev_index;
1738         struct pci_dev *pci = chip->pci;
1739         struct snd_card *card = chip->card;
1740         struct hdac_bus *bus = azx_bus(chip);
1741         int err;
1742         unsigned short gcap;
1743         unsigned int dma_bits = 64;
1744
1745 #if BITS_PER_LONG != 64
1746         /* Fix up base address on ULI M5461 */
1747         if (chip->driver_type == AZX_DRIVER_ULI) {
1748                 u16 tmp3;
1749                 pci_read_config_word(pci, 0x40, &tmp3);
1750                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1751                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1752         }
1753 #endif
1754
1755         err = pci_request_regions(pci, "ICH HD audio");
1756         if (err < 0)
1757                 return err;
1758         chip->region_requested = 1;
1759
1760         bus->addr = pci_resource_start(pci, 0);
1761         bus->remap_addr = pci_ioremap_bar(pci, 0);
1762         if (bus->remap_addr == NULL) {
1763                 dev_err(card->dev, "ioremap error\n");
1764                 return -ENXIO;
1765         }
1766
1767         if (chip->driver_type == AZX_DRIVER_SKL)
1768                 snd_hdac_bus_parse_capabilities(bus);
1769
1770         /*
1771          * Some Intel CPUs has always running timer (ART) feature and
1772          * controller may have Global time sync reporting capability, so
1773          * check both of these before declaring synchronized time reporting
1774          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1775          */
1776         chip->gts_present = false;
1777
1778 #ifdef CONFIG_X86
1779         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1780                 chip->gts_present = true;
1781 #endif
1782
1783         if (chip->msi) {
1784                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1785                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1786                         pci->no_64bit_msi = true;
1787                 }
1788                 if (pci_enable_msi(pci) < 0)
1789                         chip->msi = 0;
1790         }
1791
1792         pci_set_master(pci);
1793         synchronize_irq(bus->irq);
1794
1795         gcap = azx_readw(chip, GCAP);
1796         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1797
1798         /* AMD devices support 40 or 48bit DMA, take the safe one */
1799         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1800                 dma_bits = 40;
1801
1802         /* disable SB600 64bit support for safety */
1803         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1804                 struct pci_dev *p_smbus;
1805                 dma_bits = 40;
1806                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1807                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1808                                          NULL);
1809                 if (p_smbus) {
1810                         if (p_smbus->revision < 0x30)
1811                                 gcap &= ~AZX_GCAP_64OK;
1812                         pci_dev_put(p_smbus);
1813                 }
1814         }
1815
1816         /* NVidia hardware normally only supports up to 40 bits of DMA */
1817         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1818                 dma_bits = 40;
1819
1820         /* disable 64bit DMA address on some devices */
1821         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1822                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1823                 gcap &= ~AZX_GCAP_64OK;
1824         }
1825
1826         /* disable buffer size rounding to 128-byte multiples if supported */
1827         if (align_buffer_size >= 0)
1828                 chip->align_buffer_size = !!align_buffer_size;
1829         else {
1830                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1831                         chip->align_buffer_size = 0;
1832                 else
1833                         chip->align_buffer_size = 1;
1834         }
1835
1836         /* allow 64bit DMA address if supported by H/W */
1837         if (!(gcap & AZX_GCAP_64OK))
1838                 dma_bits = 32;
1839         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1840                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1841         } else {
1842                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1843                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1844         }
1845
1846         /* read number of streams from GCAP register instead of using
1847          * hardcoded value
1848          */
1849         chip->capture_streams = (gcap >> 8) & 0x0f;
1850         chip->playback_streams = (gcap >> 12) & 0x0f;
1851         if (!chip->playback_streams && !chip->capture_streams) {
1852                 /* gcap didn't give any info, switching to old method */
1853
1854                 switch (chip->driver_type) {
1855                 case AZX_DRIVER_ULI:
1856                         chip->playback_streams = ULI_NUM_PLAYBACK;
1857                         chip->capture_streams = ULI_NUM_CAPTURE;
1858                         break;
1859                 case AZX_DRIVER_ATIHDMI:
1860                 case AZX_DRIVER_ATIHDMI_NS:
1861                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1862                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1863                         break;
1864                 case AZX_DRIVER_GENERIC:
1865                 default:
1866                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1867                         chip->capture_streams = ICH6_NUM_CAPTURE;
1868                         break;
1869                 }
1870         }
1871         chip->capture_index_offset = 0;
1872         chip->playback_index_offset = chip->capture_streams;
1873         chip->num_streams = chip->playback_streams + chip->capture_streams;
1874
1875         /* sanity check for the SDxCTL.STRM field overflow */
1876         if (chip->num_streams > 15 &&
1877             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1878                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1879                          "forcing separate stream tags", chip->num_streams);
1880                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1881         }
1882
1883         /* initialize streams */
1884         err = azx_init_streams(chip);
1885         if (err < 0)
1886                 return err;
1887
1888         err = azx_alloc_stream_pages(chip);
1889         if (err < 0)
1890                 return err;
1891
1892         /* initialize chip */
1893         azx_init_pci(chip);
1894
1895         snd_hdac_i915_set_bclk(bus);
1896
1897         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1898
1899         /* codec detection */
1900         if (!azx_bus(chip)->codec_mask) {
1901                 dev_err(card->dev, "no codecs found!\n");
1902                 return -ENODEV;
1903         }
1904
1905         if (azx_acquire_irq(chip, 0) < 0)
1906                 return -EBUSY;
1907
1908         strcpy(card->driver, "HDA-Intel");
1909         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1910                 sizeof(card->shortname));
1911         snprintf(card->longname, sizeof(card->longname),
1912                  "%s at 0x%lx irq %i",
1913                  card->shortname, bus->addr, bus->irq);
1914
1915         return 0;
1916 }
1917
1918 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1919 /* callback from request_firmware_nowait() */
1920 static void azx_firmware_cb(const struct firmware *fw, void *context)
1921 {
1922         struct snd_card *card = context;
1923         struct azx *chip = card->private_data;
1924         struct pci_dev *pci = chip->pci;
1925
1926         if (!fw) {
1927                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1928                 goto error;
1929         }
1930
1931         chip->fw = fw;
1932         if (!chip->disabled) {
1933                 /* continue probing */
1934                 if (azx_probe_continue(chip))
1935                         goto error;
1936         }
1937         return; /* OK */
1938
1939  error:
1940         snd_card_free(card);
1941         pci_set_drvdata(pci, NULL);
1942 }
1943 #endif
1944
1945 /*
1946  * HDA controller ops.
1947  */
1948
1949 /* PCI register access. */
1950 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1951 {
1952         writel(value, addr);
1953 }
1954
1955 static u32 pci_azx_readl(u32 __iomem *addr)
1956 {
1957         return readl(addr);
1958 }
1959
1960 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1961 {
1962         writew(value, addr);
1963 }
1964
1965 static u16 pci_azx_readw(u16 __iomem *addr)
1966 {
1967         return readw(addr);
1968 }
1969
1970 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1971 {
1972         writeb(value, addr);
1973 }
1974
1975 static u8 pci_azx_readb(u8 __iomem *addr)
1976 {
1977         return readb(addr);
1978 }
1979
1980 static int disable_msi_reset_irq(struct azx *chip)
1981 {
1982         struct hdac_bus *bus = azx_bus(chip);
1983         int err;
1984
1985         free_irq(bus->irq, chip);
1986         bus->irq = -1;
1987         pci_disable_msi(chip->pci);
1988         chip->msi = 0;
1989         err = azx_acquire_irq(chip, 1);
1990         if (err < 0)
1991                 return err;
1992
1993         return 0;
1994 }
1995
1996 /* DMA page allocation helpers.  */
1997 static int dma_alloc_pages(struct hdac_bus *bus,
1998                            int type,
1999                            size_t size,
2000                            struct snd_dma_buffer *buf)
2001 {
2002         struct azx *chip = bus_to_azx(bus);
2003
2004         if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV)
2005                 type = SNDRV_DMA_TYPE_DEV_UC;
2006         return snd_dma_alloc_pages(type, bus->dev, size, buf);
2007 }
2008
2009 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2010 {
2011         snd_dma_free_pages(buf);
2012 }
2013
2014 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2015                              struct vm_area_struct *area)
2016 {
2017 #ifdef CONFIG_X86
2018         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2019         struct azx *chip = apcm->chip;
2020         if (chip->uc_buffer)
2021                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2022 #endif
2023 }
2024
2025 static const struct hdac_io_ops pci_hda_io_ops = {
2026         .reg_writel = pci_azx_writel,
2027         .reg_readl = pci_azx_readl,
2028         .reg_writew = pci_azx_writew,
2029         .reg_readw = pci_azx_readw,
2030         .reg_writeb = pci_azx_writeb,
2031         .reg_readb = pci_azx_readb,
2032         .dma_alloc_pages = dma_alloc_pages,
2033         .dma_free_pages = dma_free_pages,
2034 };
2035
2036 static const struct hda_controller_ops pci_hda_ops = {
2037         .disable_msi_reset_irq = disable_msi_reset_irq,
2038         .pcm_mmap_prepare = pcm_mmap_prepare,
2039         .position_check = azx_position_check,
2040 };
2041
2042 static int azx_probe(struct pci_dev *pci,
2043                      const struct pci_device_id *pci_id)
2044 {
2045         static int dev;
2046         struct snd_card *card;
2047         struct hda_intel *hda;
2048         struct azx *chip;
2049         bool schedule_probe;
2050         int err;
2051
2052         if (dev >= SNDRV_CARDS)
2053                 return -ENODEV;
2054         if (!enable[dev]) {
2055                 dev++;
2056                 return -ENOENT;
2057         }
2058
2059         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2060                            0, &card);
2061         if (err < 0) {
2062                 dev_err(&pci->dev, "Error creating card!\n");
2063                 return err;
2064         }
2065
2066         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2067         if (err < 0)
2068                 goto out_free;
2069         card->private_data = chip;
2070         hda = container_of(chip, struct hda_intel, chip);
2071
2072         pci_set_drvdata(pci, card);
2073
2074         err = register_vga_switcheroo(chip);
2075         if (err < 0) {
2076                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2077                 goto out_free;
2078         }
2079
2080         if (check_hdmi_disabled(pci)) {
2081                 dev_info(card->dev, "VGA controller is disabled\n");
2082                 dev_info(card->dev, "Delaying initialization\n");
2083                 chip->disabled = true;
2084         }
2085
2086         schedule_probe = !chip->disabled;
2087
2088 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2089         if (patch[dev] && *patch[dev]) {
2090                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2091                          patch[dev]);
2092                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2093                                               &pci->dev, GFP_KERNEL, card,
2094                                               azx_firmware_cb);
2095                 if (err < 0)
2096                         goto out_free;
2097                 schedule_probe = false; /* continued in azx_firmware_cb() */
2098         }
2099 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2100
2101 #ifndef CONFIG_SND_HDA_I915
2102         if (CONTROLLER_IN_GPU(pci))
2103                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2104 #endif
2105
2106         if (schedule_probe)
2107                 schedule_work(&hda->probe_work);
2108
2109         dev++;
2110         if (chip->disabled)
2111                 complete_all(&hda->probe_wait);
2112         return 0;
2113
2114 out_free:
2115         snd_card_free(card);
2116         return err;
2117 }
2118
2119 #ifdef CONFIG_PM
2120 /* On some boards setting power_save to a non 0 value leads to clicking /
2121  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2122  * figure out how to avoid these sounds, but that is not always feasible.
2123  * So we keep a list of devices where we disable powersaving as its known
2124  * to causes problems on these devices.
2125  */
2126 static struct snd_pci_quirk power_save_blacklist[] = {
2127         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2128         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2129         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2130         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2131         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2132         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2133         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2134         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2135         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2136         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2137         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2138         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2139         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2140         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2141         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2142         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2143         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2144         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2145         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2146         /* https://bugs.launchpad.net/bugs/1821663 */
2147         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2148         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2149         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2150         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2151         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2152         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2153         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2154         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2155         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2156         /* https://bugs.launchpad.net/bugs/1821663 */
2157         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2158         {}
2159 };
2160 #endif /* CONFIG_PM */
2161
2162 static void set_default_power_save(struct azx *chip)
2163 {
2164         int val = power_save;
2165
2166 #ifdef CONFIG_PM
2167         if (pm_blacklist) {
2168                 const struct snd_pci_quirk *q;
2169
2170                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2171                 if (q && val) {
2172                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2173                                  q->subvendor, q->subdevice);
2174                         val = 0;
2175                 }
2176         }
2177 #endif /* CONFIG_PM */
2178         snd_hda_set_power_save(&chip->bus, val * 1000);
2179 }
2180
2181 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2182 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2183         [AZX_DRIVER_NVIDIA] = 8,
2184         [AZX_DRIVER_TERA] = 1,
2185 };
2186
2187 static int azx_probe_continue(struct azx *chip)
2188 {
2189         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2190         struct hdac_bus *bus = azx_bus(chip);
2191         struct pci_dev *pci = chip->pci;
2192         int dev = chip->dev_index;
2193         int err;
2194
2195         to_hda_bus(bus)->bus_probing = 1;
2196         hda->probe_continued = 1;
2197
2198         /* bind with i915 if needed */
2199         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2200                 err = snd_hdac_i915_init(bus);
2201                 if (err < 0) {
2202                         /* if the controller is bound only with HDMI/DP
2203                          * (for HSW and BDW), we need to abort the probe;
2204                          * for other chips, still continue probing as other
2205                          * codecs can be on the same link.
2206                          */
2207                         if (CONTROLLER_IN_GPU(pci)) {
2208                                 dev_err(chip->card->dev,
2209                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2210                                 goto out_free;
2211                         } else {
2212                                 /* don't bother any longer */
2213                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2214                         }
2215                 }
2216
2217                 /* HSW/BDW controllers need this power */
2218                 if (CONTROLLER_IN_GPU(pci))
2219                         hda->need_i915_power = 1;
2220         }
2221
2222         /* Request display power well for the HDA controller or codec. For
2223          * Haswell/Broadwell, both the display HDA controller and codec need
2224          * this power. For other platforms, like Baytrail/Braswell, only the
2225          * display codec needs the power and it can be released after probe.
2226          */
2227         display_power(chip, true);
2228
2229         err = azx_first_init(chip);
2230         if (err < 0)
2231                 goto out_free;
2232
2233 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2234         chip->beep_mode = beep_mode[dev];
2235 #endif
2236
2237         /* create codec instances */
2238         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2239         if (err < 0)
2240                 goto out_free;
2241
2242 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2243         if (chip->fw) {
2244                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2245                                          chip->fw->data);
2246                 if (err < 0)
2247                         goto out_free;
2248 #ifndef CONFIG_PM
2249                 release_firmware(chip->fw); /* no longer needed */
2250                 chip->fw = NULL;
2251 #endif
2252         }
2253 #endif
2254         if ((probe_only[dev] & 1) == 0) {
2255                 err = azx_codec_configure(chip);
2256                 if (err < 0)
2257                         goto out_free;
2258         }
2259
2260         err = snd_card_register(chip->card);
2261         if (err < 0)
2262                 goto out_free;
2263
2264         setup_vga_switcheroo_runtime_pm(chip);
2265
2266         chip->running = 1;
2267         azx_add_card_list(chip);
2268
2269         set_default_power_save(chip);
2270
2271         if (azx_has_pm_runtime(chip))
2272                 pm_runtime_put_autosuspend(&pci->dev);
2273
2274 out_free:
2275         if (err < 0 || !hda->need_i915_power)
2276                 display_power(chip, false);
2277         if (err < 0)
2278                 hda->init_failed = 1;
2279         complete_all(&hda->probe_wait);
2280         to_hda_bus(bus)->bus_probing = 0;
2281         return err;
2282 }
2283
2284 static void azx_remove(struct pci_dev *pci)
2285 {
2286         struct snd_card *card = pci_get_drvdata(pci);
2287         struct azx *chip;
2288         struct hda_intel *hda;
2289
2290         if (card) {
2291                 /* cancel the pending probing work */
2292                 chip = card->private_data;
2293                 hda = container_of(chip, struct hda_intel, chip);
2294                 /* FIXME: below is an ugly workaround.
2295                  * Both device_release_driver() and driver_probe_device()
2296                  * take *both* the device's and its parent's lock before
2297                  * calling the remove() and probe() callbacks.  The codec
2298                  * probe takes the locks of both the codec itself and its
2299                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2300                  * the PCI controller is unbound, it takes its lock, too
2301                  * ==> ouch, a deadlock!
2302                  * As a workaround, we unlock temporarily here the controller
2303                  * device during cancel_work_sync() call.
2304                  */
2305                 device_unlock(&pci->dev);
2306                 cancel_work_sync(&hda->probe_work);
2307                 device_lock(&pci->dev);
2308
2309                 snd_card_free(card);
2310         }
2311 }
2312
2313 static void azx_shutdown(struct pci_dev *pci)
2314 {
2315         struct snd_card *card = pci_get_drvdata(pci);
2316         struct azx *chip;
2317
2318         if (!card)
2319                 return;
2320         chip = card->private_data;
2321         if (chip && chip->running)
2322                 azx_stop_chip(chip);
2323 }
2324
2325 /* PCI IDs */
2326 static const struct pci_device_id azx_ids[] = {
2327         /* CPT */
2328         { PCI_DEVICE(0x8086, 0x1c20),
2329           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2330         /* PBG */
2331         { PCI_DEVICE(0x8086, 0x1d20),
2332           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2333         /* Panther Point */
2334         { PCI_DEVICE(0x8086, 0x1e20),
2335           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2336         /* Lynx Point */
2337         { PCI_DEVICE(0x8086, 0x8c20),
2338           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2339         /* 9 Series */
2340         { PCI_DEVICE(0x8086, 0x8ca0),
2341           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2342         /* Wellsburg */
2343         { PCI_DEVICE(0x8086, 0x8d20),
2344           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2345         { PCI_DEVICE(0x8086, 0x8d21),
2346           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2347         /* Lewisburg */
2348         { PCI_DEVICE(0x8086, 0xa1f0),
2349           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2350         { PCI_DEVICE(0x8086, 0xa270),
2351           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2352         /* Lynx Point-LP */
2353         { PCI_DEVICE(0x8086, 0x9c20),
2354           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2355         /* Lynx Point-LP */
2356         { PCI_DEVICE(0x8086, 0x9c21),
2357           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2358         /* Wildcat Point-LP */
2359         { PCI_DEVICE(0x8086, 0x9ca0),
2360           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2361         /* Sunrise Point */
2362         { PCI_DEVICE(0x8086, 0xa170),
2363           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2364         /* Sunrise Point-LP */
2365         { PCI_DEVICE(0x8086, 0x9d70),
2366           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2367         /* Kabylake */
2368         { PCI_DEVICE(0x8086, 0xa171),
2369           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2370         /* Kabylake-LP */
2371         { PCI_DEVICE(0x8086, 0x9d71),
2372           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2373         /* Kabylake-H */
2374         { PCI_DEVICE(0x8086, 0xa2f0),
2375           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2376         /* Coffelake */
2377         { PCI_DEVICE(0x8086, 0xa348),
2378           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2379         /* Cannonlake */
2380         { PCI_DEVICE(0x8086, 0x9dc8),
2381           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2382         /* CometLake-LP */
2383         { PCI_DEVICE(0x8086, 0x02C8),
2384           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2385         /* CometLake-H */
2386         { PCI_DEVICE(0x8086, 0x06C8),
2387           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2388         /* Icelake */
2389         { PCI_DEVICE(0x8086, 0x34c8),
2390           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2391         /* Elkhart Lake */
2392         { PCI_DEVICE(0x8086, 0x4b55),
2393           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2394         /* Broxton-P(Apollolake) */
2395         { PCI_DEVICE(0x8086, 0x5a98),
2396           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2397         /* Broxton-T */
2398         { PCI_DEVICE(0x8086, 0x1a98),
2399           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2400         /* Gemini-Lake */
2401         { PCI_DEVICE(0x8086, 0x3198),
2402           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2403         /* Haswell */
2404         { PCI_DEVICE(0x8086, 0x0a0c),
2405           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2406         { PCI_DEVICE(0x8086, 0x0c0c),
2407           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2408         { PCI_DEVICE(0x8086, 0x0d0c),
2409           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2410         /* Broadwell */
2411         { PCI_DEVICE(0x8086, 0x160c),
2412           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2413         /* 5 Series/3400 */
2414         { PCI_DEVICE(0x8086, 0x3b56),
2415           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2416         /* Poulsbo */
2417         { PCI_DEVICE(0x8086, 0x811b),
2418           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2419         /* Oaktrail */
2420         { PCI_DEVICE(0x8086, 0x080a),
2421           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2422         /* BayTrail */
2423         { PCI_DEVICE(0x8086, 0x0f04),
2424           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2425         /* Braswell */
2426         { PCI_DEVICE(0x8086, 0x2284),
2427           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2428         /* ICH6 */
2429         { PCI_DEVICE(0x8086, 0x2668),
2430           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2431         /* ICH7 */
2432         { PCI_DEVICE(0x8086, 0x27d8),
2433           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2434         /* ESB2 */
2435         { PCI_DEVICE(0x8086, 0x269a),
2436           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2437         /* ICH8 */
2438         { PCI_DEVICE(0x8086, 0x284b),
2439           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2440         /* ICH9 */
2441         { PCI_DEVICE(0x8086, 0x293e),
2442           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2443         /* ICH9 */
2444         { PCI_DEVICE(0x8086, 0x293f),
2445           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2446         /* ICH10 */
2447         { PCI_DEVICE(0x8086, 0x3a3e),
2448           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2449         /* ICH10 */
2450         { PCI_DEVICE(0x8086, 0x3a6e),
2451           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2452         /* Generic Intel */
2453         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2454           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2455           .class_mask = 0xffffff,
2456           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2457         /* ATI SB 450/600/700/800/900 */
2458         { PCI_DEVICE(0x1002, 0x437b),
2459           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2460         { PCI_DEVICE(0x1002, 0x4383),
2461           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2462         /* AMD Hudson */
2463         { PCI_DEVICE(0x1022, 0x780d),
2464           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2465         /* AMD Stoney */
2466         { PCI_DEVICE(0x1022, 0x157a),
2467           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2468                          AZX_DCAPS_PM_RUNTIME },
2469         /* AMD Raven */
2470         { PCI_DEVICE(0x1022, 0x15e3),
2471           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2472                          AZX_DCAPS_PM_RUNTIME },
2473         /* ATI HDMI */
2474         { PCI_DEVICE(0x1002, 0x0002),
2475           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2476         { PCI_DEVICE(0x1002, 0x1308),
2477           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2478         { PCI_DEVICE(0x1002, 0x157a),
2479           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2480         { PCI_DEVICE(0x1002, 0x15b3),
2481           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2482         { PCI_DEVICE(0x1002, 0x793b),
2483           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2484         { PCI_DEVICE(0x1002, 0x7919),
2485           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2486         { PCI_DEVICE(0x1002, 0x960f),
2487           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2488         { PCI_DEVICE(0x1002, 0x970f),
2489           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2490         { PCI_DEVICE(0x1002, 0x9840),
2491           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2492         { PCI_DEVICE(0x1002, 0xaa00),
2493           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2494         { PCI_DEVICE(0x1002, 0xaa08),
2495           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2496         { PCI_DEVICE(0x1002, 0xaa10),
2497           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2498         { PCI_DEVICE(0x1002, 0xaa18),
2499           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2500         { PCI_DEVICE(0x1002, 0xaa20),
2501           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2502         { PCI_DEVICE(0x1002, 0xaa28),
2503           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2504         { PCI_DEVICE(0x1002, 0xaa30),
2505           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2506         { PCI_DEVICE(0x1002, 0xaa38),
2507           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2508         { PCI_DEVICE(0x1002, 0xaa40),
2509           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510         { PCI_DEVICE(0x1002, 0xaa48),
2511           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512         { PCI_DEVICE(0x1002, 0xaa50),
2513           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2514         { PCI_DEVICE(0x1002, 0xaa58),
2515           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2516         { PCI_DEVICE(0x1002, 0xaa60),
2517           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2518         { PCI_DEVICE(0x1002, 0xaa68),
2519           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2520         { PCI_DEVICE(0x1002, 0xaa80),
2521           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2522         { PCI_DEVICE(0x1002, 0xaa88),
2523           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2524         { PCI_DEVICE(0x1002, 0xaa90),
2525           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2526         { PCI_DEVICE(0x1002, 0xaa98),
2527           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2528         { PCI_DEVICE(0x1002, 0x9902),
2529           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2530         { PCI_DEVICE(0x1002, 0xaaa0),
2531           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2532         { PCI_DEVICE(0x1002, 0xaaa8),
2533           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2534         { PCI_DEVICE(0x1002, 0xaab0),
2535           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2536         { PCI_DEVICE(0x1002, 0xaac0),
2537           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2538         { PCI_DEVICE(0x1002, 0xaac8),
2539           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2540         { PCI_DEVICE(0x1002, 0xaad8),
2541           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2542         { PCI_DEVICE(0x1002, 0xaae8),
2543           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2544         { PCI_DEVICE(0x1002, 0xaae0),
2545           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2546         { PCI_DEVICE(0x1002, 0xaaf0),
2547           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2548         /* VIA VT8251/VT8237A */
2549         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2550         /* VIA GFX VT7122/VX900 */
2551         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2552         /* VIA GFX VT6122/VX11 */
2553         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2554         /* SIS966 */
2555         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2556         /* ULI M5461 */
2557         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2558         /* NVIDIA MCP */
2559         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2560           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2561           .class_mask = 0xffffff,
2562           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2563         /* Teradici */
2564         { PCI_DEVICE(0x6549, 0x1200),
2565           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2566         { PCI_DEVICE(0x6549, 0x2200),
2567           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2568         /* Creative X-Fi (CA0110-IBG) */
2569         /* CTHDA chips */
2570         { PCI_DEVICE(0x1102, 0x0010),
2571           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2572         { PCI_DEVICE(0x1102, 0x0012),
2573           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2574 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2575         /* the following entry conflicts with snd-ctxfi driver,
2576          * as ctxfi driver mutates from HD-audio to native mode with
2577          * a special command sequence.
2578          */
2579         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2580           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2581           .class_mask = 0xffffff,
2582           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2583           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2584 #else
2585         /* this entry seems still valid -- i.e. without emu20kx chip */
2586         { PCI_DEVICE(0x1102, 0x0009),
2587           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2588           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2589 #endif
2590         /* CM8888 */
2591         { PCI_DEVICE(0x13f6, 0x5011),
2592           .driver_data = AZX_DRIVER_CMEDIA |
2593           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2594         /* Vortex86MX */
2595         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2596         /* VMware HDAudio */
2597         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2598         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2599         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2600           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2601           .class_mask = 0xffffff,
2602           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2603         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2604           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2605           .class_mask = 0xffffff,
2606           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2607         { 0, }
2608 };
2609 MODULE_DEVICE_TABLE(pci, azx_ids);
2610
2611 /* pci_driver definition */
2612 static struct pci_driver azx_driver = {
2613         .name = KBUILD_MODNAME,
2614         .id_table = azx_ids,
2615         .probe = azx_probe,
2616         .remove = azx_remove,
2617         .shutdown = azx_shutdown,
2618         .driver = {
2619                 .pm = AZX_PM_OPS,
2620         },
2621 };
2622
2623 module_pci_driver(azx_driver);