3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi = -1;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch[SNDRV_CARDS];
67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
72 module_param_array(index, int, NULL, 0444);
73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
74 module_param_array(id, charp, NULL, 0444);
75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
76 module_param_array(enable, bool, NULL, 0444);
77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78 module_param_array(model, charp, NULL, 0444);
79 MODULE_PARM_DESC(model, "Use the given board model.");
80 module_param_array(position_fix, int, NULL, 0444);
81 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
82 "(0 = auto, 1 = none, 2 = POSBUF).");
83 module_param_array(bdl_pos_adj, int, NULL, 0644);
84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
85 module_param_array(probe_mask, int, NULL, 0444);
86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
87 module_param_array(probe_only, bool, NULL, 0444);
88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
89 module_param(single_cmd, bool, 0444);
90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
92 module_param(enable_msi, int, 0444);
93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
95 module_param_array(patch, charp, NULL, 0444);
96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
99 module_param_array(beep_mode, int, NULL, 0444);
100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
104 #ifdef CONFIG_SND_HDA_POWER_SAVE
105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106 module_param(power_save, int, 0644);
107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
110 /* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
114 static int power_save_controller = 1;
115 module_param(power_save_controller, bool, 0644);
116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
119 MODULE_LICENSE("GPL");
120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
146 MODULE_DESCRIPTION("Intel HDA driver");
148 #ifdef CONFIG_SND_VERBOSE_PRINTK
149 #define SFX /* nop */
151 #define SFX "hda-intel: "
157 #define ICH6_REG_GCAP 0x00
158 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
159 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
160 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
161 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
162 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
163 #define ICH6_REG_VMIN 0x02
164 #define ICH6_REG_VMAJ 0x03
165 #define ICH6_REG_OUTPAY 0x04
166 #define ICH6_REG_INPAY 0x06
167 #define ICH6_REG_GCTL 0x08
168 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
169 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
170 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
171 #define ICH6_REG_WAKEEN 0x0c
172 #define ICH6_REG_STATESTS 0x0e
173 #define ICH6_REG_GSTS 0x10
174 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
175 #define ICH6_REG_INTCTL 0x20
176 #define ICH6_REG_INTSTS 0x24
177 #define ICH6_REG_WALCLK 0x30
178 #define ICH6_REG_SYNC 0x34
179 #define ICH6_REG_CORBLBASE 0x40
180 #define ICH6_REG_CORBUBASE 0x44
181 #define ICH6_REG_CORBWP 0x48
182 #define ICH6_REG_CORBRP 0x4a
183 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
184 #define ICH6_REG_CORBCTL 0x4c
185 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
186 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
187 #define ICH6_REG_CORBSTS 0x4d
188 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
189 #define ICH6_REG_CORBSIZE 0x4e
191 #define ICH6_REG_RIRBLBASE 0x50
192 #define ICH6_REG_RIRBUBASE 0x54
193 #define ICH6_REG_RIRBWP 0x58
194 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
195 #define ICH6_REG_RINTCNT 0x5a
196 #define ICH6_REG_RIRBCTL 0x5c
197 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
198 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
199 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
200 #define ICH6_REG_RIRBSTS 0x5d
201 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
202 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
203 #define ICH6_REG_RIRBSIZE 0x5e
205 #define ICH6_REG_IC 0x60
206 #define ICH6_REG_IR 0x64
207 #define ICH6_REG_IRS 0x68
208 #define ICH6_IRS_VALID (1<<1)
209 #define ICH6_IRS_BUSY (1<<0)
211 #define ICH6_REG_DPLBASE 0x70
212 #define ICH6_REG_DPUBASE 0x74
213 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
215 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
216 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
218 /* stream register offsets from stream base */
219 #define ICH6_REG_SD_CTL 0x00
220 #define ICH6_REG_SD_STS 0x03
221 #define ICH6_REG_SD_LPIB 0x04
222 #define ICH6_REG_SD_CBL 0x08
223 #define ICH6_REG_SD_LVI 0x0c
224 #define ICH6_REG_SD_FIFOW 0x0e
225 #define ICH6_REG_SD_FIFOSIZE 0x10
226 #define ICH6_REG_SD_FORMAT 0x12
227 #define ICH6_REG_SD_BDLPL 0x18
228 #define ICH6_REG_SD_BDLPU 0x1c
231 #define ICH6_PCIREG_TCSEL 0x44
237 /* max number of SDs */
238 /* ICH, ATI and VIA have 4 playback and 4 capture */
239 #define ICH6_NUM_CAPTURE 4
240 #define ICH6_NUM_PLAYBACK 4
242 /* ULI has 6 playback and 5 capture */
243 #define ULI_NUM_CAPTURE 5
244 #define ULI_NUM_PLAYBACK 6
246 /* ATI HDMI has 1 playback and 0 capture */
247 #define ATIHDMI_NUM_CAPTURE 0
248 #define ATIHDMI_NUM_PLAYBACK 1
250 /* TERA has 4 playback and 3 capture */
251 #define TERA_NUM_CAPTURE 3
252 #define TERA_NUM_PLAYBACK 4
254 /* this number is statically defined for simplicity */
255 #define MAX_AZX_DEV 16
257 /* max number of fragments - we may use more if allocating more pages for BDL */
258 #define BDL_SIZE 4096
259 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
260 #define AZX_MAX_FRAG 32
261 /* max buffer size - no h/w limit, you can increase as you like */
262 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
264 /* RIRB int mask: overrun[2], response[0] */
265 #define RIRB_INT_RESPONSE 0x01
266 #define RIRB_INT_OVERRUN 0x04
267 #define RIRB_INT_MASK 0x05
269 /* STATESTS int mask: S3,SD2,SD1,SD0 */
270 #define AZX_MAX_CODECS 4
271 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
274 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
275 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
276 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
277 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
278 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
279 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
280 #define SD_CTL_STREAM_TAG_SHIFT 20
282 /* SD_CTL and SD_STS */
283 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
284 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
285 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
286 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
290 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
292 /* INTCTL and INTSTS */
293 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
294 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
295 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
297 /* below are so far hardcoded - should read registers in future */
298 #define ICH6_MAX_CORB_ENTRIES 256
299 #define ICH6_MAX_RIRB_ENTRIES 256
301 /* position fix mode */
308 /* Defines for ATI HD Audio support in SB450 south bridge */
309 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
310 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
312 /* Defines for Nvidia HDA support */
313 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
314 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
315 #define NVIDIA_HDA_ISTRM_COH 0x4d
316 #define NVIDIA_HDA_OSTRM_COH 0x4c
317 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
319 /* Defines for Intel SCH HDA snoop control */
320 #define INTEL_SCH_HDA_DEVC 0x78
321 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
323 /* Define IN stream 0 FIFO size offset in VIA controller */
324 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
325 /* Define VIA HD Audio Device ID*/
326 #define VIA_HDAC_DEVICE_ID 0x3288
328 /* HD Audio class code */
329 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
335 struct snd_dma_buffer bdl; /* BDL buffer */
336 u32 *posbuf; /* position buffer pointer */
338 unsigned int bufsize; /* size of the play buffer in bytes */
339 unsigned int period_bytes; /* size of the period in bytes */
340 unsigned int frags; /* number for period in the play buffer */
341 unsigned int fifo_size; /* FIFO size */
342 unsigned long start_jiffies; /* start + minimum jiffies */
343 unsigned long min_jiffies; /* minimum jiffies before position is valid */
345 void __iomem *sd_addr; /* stream descriptor pointer */
347 u32 sd_int_sta_mask; /* stream int status mask */
350 struct snd_pcm_substream *substream; /* assigned substream,
353 unsigned int format_val; /* format value to be set in the
354 * controller and the codec
356 unsigned char stream_tag; /* assigned stream */
357 unsigned char index; /* stream index */
358 int device; /* last device number assigned to */
360 unsigned int opened :1;
361 unsigned int running :1;
362 unsigned int irq_pending :1;
363 unsigned int start_flag: 1; /* stream full start flag */
366 * A flag to ensure DMA position is 0
367 * when link position is not greater than FIFO size
369 unsigned int insufficient :1;
374 u32 *buf; /* CORB/RIRB buffer
375 * Each CORB entry is 4byte, RIRB is 8byte
377 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
379 unsigned short rp, wp; /* read/write pointers */
380 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
381 u32 res[AZX_MAX_CODECS]; /* last read value */
385 struct snd_card *card;
389 /* chip type specific */
391 int playback_streams;
392 int playback_index_offset;
394 int capture_index_offset;
399 void __iomem *remap_addr;
404 struct mutex open_mutex;
406 /* streams (x num_streams) */
407 struct azx_dev *azx_dev;
410 struct snd_pcm *pcm[HDA_MAX_PCMS];
413 unsigned short codec_mask;
414 int codec_probe_mask; /* copied from probe_mask option */
416 unsigned int beep_mode;
422 /* CORB/RIRB and position buffers */
423 struct snd_dma_buffer rb;
424 struct snd_dma_buffer posbuf;
429 unsigned int running :1;
430 unsigned int initialized :1;
431 unsigned int single_cmd :1;
432 unsigned int polling_mode :1;
434 unsigned int irq_pending_warned :1;
435 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
436 unsigned int probing :1; /* codec probing phase */
439 unsigned int last_cmd[AZX_MAX_CODECS];
441 /* for pending irqs */
442 struct work_struct irq_pending_work;
444 /* reboot notifier (for mysterious hangup problem at power-down) */
445 struct notifier_block reboot_notifier;
461 AZX_NUM_DRIVERS, /* keep this as last entry */
464 static char *driver_short_names[] __devinitdata = {
465 [AZX_DRIVER_ICH] = "HDA Intel",
466 [AZX_DRIVER_PCH] = "HDA Intel PCH",
467 [AZX_DRIVER_SCH] = "HDA Intel MID",
468 [AZX_DRIVER_ATI] = "HDA ATI SB",
469 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
470 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
471 [AZX_DRIVER_SIS] = "HDA SIS966",
472 [AZX_DRIVER_ULI] = "HDA ULI M5461",
473 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
474 [AZX_DRIVER_TERA] = "HDA Teradici",
475 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
479 * macros for easy use
481 #define azx_writel(chip,reg,value) \
482 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
483 #define azx_readl(chip,reg) \
484 readl((chip)->remap_addr + ICH6_REG_##reg)
485 #define azx_writew(chip,reg,value) \
486 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
487 #define azx_readw(chip,reg) \
488 readw((chip)->remap_addr + ICH6_REG_##reg)
489 #define azx_writeb(chip,reg,value) \
490 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
491 #define azx_readb(chip,reg) \
492 readb((chip)->remap_addr + ICH6_REG_##reg)
494 #define azx_sd_writel(dev,reg,value) \
495 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
496 #define azx_sd_readl(dev,reg) \
497 readl((dev)->sd_addr + ICH6_REG_##reg)
498 #define azx_sd_writew(dev,reg,value) \
499 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
500 #define azx_sd_readw(dev,reg) \
501 readw((dev)->sd_addr + ICH6_REG_##reg)
502 #define azx_sd_writeb(dev,reg,value) \
503 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
504 #define azx_sd_readb(dev,reg) \
505 readb((dev)->sd_addr + ICH6_REG_##reg)
507 /* for pcm support */
508 #define get_azx_dev(substream) (substream->runtime->private_data)
510 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
511 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
513 * Interface for HD codec
517 * CORB / RIRB interface
519 static int azx_alloc_cmd_io(struct azx *chip)
523 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
524 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
525 snd_dma_pci_data(chip->pci),
526 PAGE_SIZE, &chip->rb);
528 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
534 static void azx_init_cmd_io(struct azx *chip)
536 spin_lock_irq(&chip->reg_lock);
538 chip->corb.addr = chip->rb.addr;
539 chip->corb.buf = (u32 *)chip->rb.area;
540 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
541 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
543 /* set the corb size to 256 entries (ULI requires explicitly) */
544 azx_writeb(chip, CORBSIZE, 0x02);
545 /* set the corb write pointer to 0 */
546 azx_writew(chip, CORBWP, 0);
547 /* reset the corb hw read pointer */
548 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
549 /* enable corb dma */
550 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
553 chip->rirb.addr = chip->rb.addr + 2048;
554 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
555 chip->rirb.wp = chip->rirb.rp = 0;
556 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
557 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
558 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
560 /* set the rirb size to 256 entries (ULI requires explicitly) */
561 azx_writeb(chip, RIRBSIZE, 0x02);
562 /* reset the rirb hw write pointer */
563 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
564 /* set N=1, get RIRB response interrupt for new entry */
565 azx_writew(chip, RINTCNT, 1);
566 /* enable rirb dma and response irq */
567 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
568 spin_unlock_irq(&chip->reg_lock);
571 static void azx_free_cmd_io(struct azx *chip)
573 spin_lock_irq(&chip->reg_lock);
574 /* disable ringbuffer DMAs */
575 azx_writeb(chip, RIRBCTL, 0);
576 azx_writeb(chip, CORBCTL, 0);
577 spin_unlock_irq(&chip->reg_lock);
580 static unsigned int azx_command_addr(u32 cmd)
582 unsigned int addr = cmd >> 28;
584 if (addr >= AZX_MAX_CODECS) {
592 static unsigned int azx_response_addr(u32 res)
594 unsigned int addr = res & 0xf;
596 if (addr >= AZX_MAX_CODECS) {
605 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
607 struct azx *chip = bus->private_data;
608 unsigned int addr = azx_command_addr(val);
611 spin_lock_irq(&chip->reg_lock);
613 /* add command to corb */
614 wp = azx_readb(chip, CORBWP);
616 wp %= ICH6_MAX_CORB_ENTRIES;
618 chip->rirb.cmds[addr]++;
619 chip->corb.buf[wp] = cpu_to_le32(val);
620 azx_writel(chip, CORBWP, wp);
622 spin_unlock_irq(&chip->reg_lock);
627 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
629 /* retrieve RIRB entry - called from interrupt handler */
630 static void azx_update_rirb(struct azx *chip)
636 wp = azx_readb(chip, RIRBWP);
637 if (wp == chip->rirb.wp)
641 while (chip->rirb.rp != wp) {
643 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
645 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
646 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
647 res = le32_to_cpu(chip->rirb.buf[rp]);
648 addr = azx_response_addr(res_ex);
649 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
650 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
651 else if (chip->rirb.cmds[addr]) {
652 chip->rirb.res[addr] = res;
654 chip->rirb.cmds[addr]--;
656 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
659 chip->last_cmd[addr]);
663 /* receive a response */
664 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
667 struct azx *chip = bus->private_data;
668 unsigned long timeout;
672 timeout = jiffies + msecs_to_jiffies(1000);
674 if (chip->polling_mode || do_poll) {
675 spin_lock_irq(&chip->reg_lock);
676 azx_update_rirb(chip);
677 spin_unlock_irq(&chip->reg_lock);
679 if (!chip->rirb.cmds[addr]) {
684 chip->poll_count = 0;
685 return chip->rirb.res[addr]; /* the last value */
687 if (time_after(jiffies, timeout))
689 if (bus->needs_damn_long_delay)
690 msleep(2); /* temporary workaround */
697 if (!chip->polling_mode && chip->poll_count < 2) {
698 snd_printdd(SFX "azx_get_response timeout, "
699 "polling the codec once: last cmd=0x%08x\n",
700 chip->last_cmd[addr]);
707 if (!chip->polling_mode) {
708 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
709 "switching to polling mode: last cmd=0x%08x\n",
710 chip->last_cmd[addr]);
711 chip->polling_mode = 1;
716 snd_printk(KERN_WARNING SFX "No response from codec, "
717 "disabling MSI: last cmd=0x%08x\n",
718 chip->last_cmd[addr]);
719 free_irq(chip->irq, chip);
721 pci_disable_msi(chip->pci);
723 if (azx_acquire_irq(chip, 1) < 0) {
731 /* If this critical timeout happens during the codec probing
732 * phase, this is likely an access to a non-existing codec
733 * slot. Better to return an error and reset the system.
738 /* a fatal communication error; need either to reset or to fallback
739 * to the single_cmd mode
742 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
743 bus->response_reset = 1;
744 return -1; /* give a chance to retry */
747 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
748 "switching to single_cmd mode: last cmd=0x%08x\n",
749 chip->last_cmd[addr]);
750 chip->single_cmd = 1;
751 bus->response_reset = 0;
752 /* release CORB/RIRB */
753 azx_free_cmd_io(chip);
754 /* disable unsolicited responses */
755 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
760 * Use the single immediate command instead of CORB/RIRB for simplicity
762 * Note: according to Intel, this is not preferred use. The command was
763 * intended for the BIOS only, and may get confused with unsolicited
764 * responses. So, we shouldn't use it for normal operation from the
766 * I left the codes, however, for debugging/testing purposes.
769 /* receive a response */
770 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
775 /* check IRV busy bit */
776 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
777 /* reuse rirb.res as the response return value */
778 chip->rirb.res[addr] = azx_readl(chip, IR);
783 if (printk_ratelimit())
784 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
785 azx_readw(chip, IRS));
786 chip->rirb.res[addr] = -1;
791 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
793 struct azx *chip = bus->private_data;
794 unsigned int addr = azx_command_addr(val);
799 /* check ICB busy bit */
800 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
801 /* Clear IRV valid bit */
802 azx_writew(chip, IRS, azx_readw(chip, IRS) |
804 azx_writel(chip, IC, val);
805 azx_writew(chip, IRS, azx_readw(chip, IRS) |
807 return azx_single_wait_for_response(chip, addr);
811 if (printk_ratelimit())
812 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
813 azx_readw(chip, IRS), val);
817 /* receive a response */
818 static unsigned int azx_single_get_response(struct hda_bus *bus,
821 struct azx *chip = bus->private_data;
822 return chip->rirb.res[addr];
826 * The below are the main callbacks from hda_codec.
828 * They are just the skeleton to call sub-callbacks according to the
829 * current setting of chip->single_cmd.
833 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
835 struct azx *chip = bus->private_data;
837 chip->last_cmd[azx_command_addr(val)] = val;
838 if (chip->single_cmd)
839 return azx_single_send_cmd(bus, val);
841 return azx_corb_send_cmd(bus, val);
845 static unsigned int azx_get_response(struct hda_bus *bus,
848 struct azx *chip = bus->private_data;
849 if (chip->single_cmd)
850 return azx_single_get_response(bus, addr);
852 return azx_rirb_get_response(bus, addr);
855 #ifdef CONFIG_SND_HDA_POWER_SAVE
856 static void azx_power_notify(struct hda_bus *bus);
859 /* reset codec link */
860 static int azx_reset(struct azx *chip)
865 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
867 /* reset controller */
868 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
871 while (azx_readb(chip, GCTL) && --count)
874 /* delay for >= 100us for codec PLL to settle per spec
875 * Rev 0.9 section 5.5.1
879 /* Bring controller out of reset */
880 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
883 while (!azx_readb(chip, GCTL) && --count)
886 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
889 /* check to see if controller is ready */
890 if (!azx_readb(chip, GCTL)) {
891 snd_printd(SFX "azx_reset: controller not ready!\n");
895 /* Accept unsolicited responses */
896 if (!chip->single_cmd)
897 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
901 if (!chip->codec_mask) {
902 chip->codec_mask = azx_readw(chip, STATESTS);
903 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
914 /* enable interrupts */
915 static void azx_int_enable(struct azx *chip)
917 /* enable controller CIE and GIE */
918 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
919 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
922 /* disable interrupts */
923 static void azx_int_disable(struct azx *chip)
927 /* disable interrupts in stream descriptor */
928 for (i = 0; i < chip->num_streams; i++) {
929 struct azx_dev *azx_dev = &chip->azx_dev[i];
930 azx_sd_writeb(azx_dev, SD_CTL,
931 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
934 /* disable SIE for all streams */
935 azx_writeb(chip, INTCTL, 0);
937 /* disable controller CIE and GIE */
938 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
939 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
942 /* clear interrupts */
943 static void azx_int_clear(struct azx *chip)
947 /* clear stream status */
948 for (i = 0; i < chip->num_streams; i++) {
949 struct azx_dev *azx_dev = &chip->azx_dev[i];
950 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
954 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
956 /* clear rirb status */
957 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
959 /* clear int status */
960 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
964 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
967 * Before stream start, initialize parameter
969 azx_dev->insufficient = 1;
972 azx_writel(chip, INTCTL,
973 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
974 /* set DMA start and interrupt mask */
975 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
976 SD_CTL_DMA_START | SD_INT_MASK);
980 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
982 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
983 ~(SD_CTL_DMA_START | SD_INT_MASK));
984 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
988 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
990 azx_stream_clear(chip, azx_dev);
992 azx_writel(chip, INTCTL,
993 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
998 * reset and start the controller registers
1000 static void azx_init_chip(struct azx *chip)
1002 if (chip->initialized)
1005 /* reset controller */
1008 /* initialize interrupts */
1009 azx_int_clear(chip);
1010 azx_int_enable(chip);
1012 /* initialize the codec command I/O */
1013 if (!chip->single_cmd)
1014 azx_init_cmd_io(chip);
1016 /* program the position buffer */
1017 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1018 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1020 chip->initialized = 1;
1024 * initialize the PCI registers
1026 /* update bits in a PCI register byte */
1027 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1028 unsigned char mask, unsigned char val)
1032 pci_read_config_byte(pci, reg, &data);
1034 data |= (val & mask);
1035 pci_write_config_byte(pci, reg, data);
1038 static void azx_init_pci(struct azx *chip)
1040 unsigned short snoop;
1042 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1043 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1044 * Ensuring these bits are 0 clears playback static on some HD Audio
1047 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1049 switch (chip->driver_type) {
1050 case AZX_DRIVER_ATI:
1051 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1052 update_pci_byte(chip->pci,
1053 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1054 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1056 case AZX_DRIVER_NVIDIA:
1057 /* For NVIDIA HDA, enable snoop */
1058 update_pci_byte(chip->pci,
1059 NVIDIA_HDA_TRANSREG_ADDR,
1060 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1061 update_pci_byte(chip->pci,
1062 NVIDIA_HDA_ISTRM_COH,
1063 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1064 update_pci_byte(chip->pci,
1065 NVIDIA_HDA_OSTRM_COH,
1066 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1068 case AZX_DRIVER_SCH:
1069 case AZX_DRIVER_PCH:
1070 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1071 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1072 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1073 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1074 pci_read_config_word(chip->pci,
1075 INTEL_SCH_HDA_DEVC, &snoop);
1076 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1077 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1086 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1091 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1093 struct azx *chip = dev_id;
1094 struct azx_dev *azx_dev;
1098 spin_lock(&chip->reg_lock);
1100 status = azx_readl(chip, INTSTS);
1102 spin_unlock(&chip->reg_lock);
1106 for (i = 0; i < chip->num_streams; i++) {
1107 azx_dev = &chip->azx_dev[i];
1108 if (status & azx_dev->sd_int_sta_mask) {
1109 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1110 if (!azx_dev->substream || !azx_dev->running)
1112 /* check whether this IRQ is really acceptable */
1113 ok = azx_position_ok(chip, azx_dev);
1115 azx_dev->irq_pending = 0;
1116 spin_unlock(&chip->reg_lock);
1117 snd_pcm_period_elapsed(azx_dev->substream);
1118 spin_lock(&chip->reg_lock);
1119 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1120 /* bogus IRQ, process it later */
1121 azx_dev->irq_pending = 1;
1122 queue_work(chip->bus->workq,
1123 &chip->irq_pending_work);
1128 /* clear rirb int */
1129 status = azx_readb(chip, RIRBSTS);
1130 if (status & RIRB_INT_MASK) {
1131 if (status & RIRB_INT_RESPONSE)
1132 azx_update_rirb(chip);
1133 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1137 /* clear state status int */
1138 if (azx_readb(chip, STATESTS) & 0x04)
1139 azx_writeb(chip, STATESTS, 0x04);
1141 spin_unlock(&chip->reg_lock);
1148 * set up a BDL entry
1150 static int setup_bdle(struct snd_pcm_substream *substream,
1151 struct azx_dev *azx_dev, u32 **bdlp,
1152 int ofs, int size, int with_ioc)
1160 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1163 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1164 /* program the address field of the BDL entry */
1165 bdl[0] = cpu_to_le32((u32)addr);
1166 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1167 /* program the size field of the BDL entry */
1168 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1169 bdl[2] = cpu_to_le32(chunk);
1170 /* program the IOC to enable interrupt
1171 * only when the whole fragment is processed
1174 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1184 * set up BDL entries
1186 static int azx_setup_periods(struct azx *chip,
1187 struct snd_pcm_substream *substream,
1188 struct azx_dev *azx_dev)
1191 int i, ofs, periods, period_bytes;
1194 /* reset BDL address */
1195 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1196 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1198 period_bytes = azx_dev->period_bytes;
1199 periods = azx_dev->bufsize / period_bytes;
1201 /* program the initial BDL entries */
1202 bdl = (u32 *)azx_dev->bdl.area;
1205 pos_adj = bdl_pos_adj[chip->dev_index];
1207 struct snd_pcm_runtime *runtime = substream->runtime;
1208 int pos_align = pos_adj;
1209 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1211 pos_adj = pos_align;
1213 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1215 pos_adj = frames_to_bytes(runtime, pos_adj);
1216 if (pos_adj >= period_bytes) {
1217 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1218 bdl_pos_adj[chip->dev_index]);
1221 ofs = setup_bdle(substream, azx_dev,
1222 &bdl, ofs, pos_adj, 1);
1228 for (i = 0; i < periods; i++) {
1229 if (i == periods - 1 && pos_adj)
1230 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1231 period_bytes - pos_adj, 0);
1233 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1241 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1242 azx_dev->bufsize, period_bytes);
1247 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1252 azx_stream_clear(chip, azx_dev);
1254 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1255 SD_CTL_STREAM_RESET);
1258 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1261 val &= ~SD_CTL_STREAM_RESET;
1262 azx_sd_writeb(azx_dev, SD_CTL, val);
1266 /* waiting for hardware to report that the stream is out of reset */
1267 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1271 /* reset first position - may not be synced with hw at this time */
1272 *azx_dev->posbuf = 0;
1276 * set up the SD for streaming
1278 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1280 /* make sure the run bit is zero for SD */
1281 azx_stream_clear(chip, azx_dev);
1282 /* program the stream_tag */
1283 azx_sd_writel(azx_dev, SD_CTL,
1284 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1285 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1287 /* program the length of samples in cyclic buffer */
1288 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1290 /* program the stream format */
1291 /* this value needs to be the same as the one programmed */
1292 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1294 /* program the stream LVI (last valid index) of the BDL */
1295 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1297 /* program the BDL address */
1298 /* lower BDL address */
1299 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1300 /* upper BDL address */
1301 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1303 /* enable the position buffer */
1304 if (chip->position_fix == POS_FIX_POSBUF ||
1305 chip->position_fix == POS_FIX_AUTO ||
1306 chip->via_dmapos_patch) {
1307 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1308 azx_writel(chip, DPLBASE,
1309 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1312 /* set the interrupt enable bits in the descriptor control register */
1313 azx_sd_writel(azx_dev, SD_CTL,
1314 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1320 * Probe the given codec address
1322 static int probe_codec(struct azx *chip, int addr)
1324 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1325 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1328 mutex_lock(&chip->bus->cmd_mutex);
1330 azx_send_cmd(chip->bus, cmd);
1331 res = azx_get_response(chip->bus, addr);
1333 mutex_unlock(&chip->bus->cmd_mutex);
1336 snd_printdd(SFX "codec #%d probed OK\n", addr);
1340 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1341 struct hda_pcm *cpcm);
1342 static void azx_stop_chip(struct azx *chip);
1344 static void azx_bus_reset(struct hda_bus *bus)
1346 struct azx *chip = bus->private_data;
1349 azx_stop_chip(chip);
1350 azx_init_chip(chip);
1352 if (chip->initialized) {
1355 for (i = 0; i < HDA_MAX_PCMS; i++)
1356 snd_pcm_suspend_all(chip->pcm[i]);
1357 snd_hda_suspend(chip->bus);
1358 snd_hda_resume(chip->bus);
1365 * Codec initialization
1368 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1369 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1370 [AZX_DRIVER_TERA] = 1,
1373 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1375 struct hda_bus_template bus_temp;
1379 memset(&bus_temp, 0, sizeof(bus_temp));
1380 bus_temp.private_data = chip;
1381 bus_temp.modelname = model;
1382 bus_temp.pci = chip->pci;
1383 bus_temp.ops.command = azx_send_cmd;
1384 bus_temp.ops.get_response = azx_get_response;
1385 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1386 bus_temp.ops.bus_reset = azx_bus_reset;
1387 #ifdef CONFIG_SND_HDA_POWER_SAVE
1388 bus_temp.power_save = &power_save;
1389 bus_temp.ops.pm_notify = azx_power_notify;
1392 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1396 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1397 chip->bus->needs_damn_long_delay = 1;
1400 max_slots = azx_max_codecs[chip->driver_type];
1402 max_slots = AZX_MAX_CODECS;
1404 /* First try to probe all given codec slots */
1405 for (c = 0; c < max_slots; c++) {
1406 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1407 if (probe_codec(chip, c) < 0) {
1408 /* Some BIOSen give you wrong codec addresses
1411 snd_printk(KERN_WARNING SFX
1412 "Codec #%d probe error; "
1413 "disabling it...\n", c);
1414 chip->codec_mask &= ~(1 << c);
1415 /* More badly, accessing to a non-existing
1416 * codec often screws up the controller chip,
1417 * and disturbs the further communications.
1418 * Thus if an error occurs during probing,
1419 * better to reset the controller chip to
1420 * get back to the sanity state.
1422 azx_stop_chip(chip);
1423 azx_init_chip(chip);
1428 /* Then create codec instances */
1429 for (c = 0; c < max_slots; c++) {
1430 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1431 struct hda_codec *codec;
1432 err = snd_hda_codec_new(chip->bus, c, &codec);
1435 codec->beep_mode = chip->beep_mode;
1440 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1446 /* configure each codec instance */
1447 static int __devinit azx_codec_configure(struct azx *chip)
1449 struct hda_codec *codec;
1450 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1451 snd_hda_codec_configure(codec);
1461 /* assign a stream for the PCM */
1462 static inline struct azx_dev *
1463 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1466 struct azx_dev *res = NULL;
1468 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1469 dev = chip->playback_index_offset;
1470 nums = chip->playback_streams;
1472 dev = chip->capture_index_offset;
1473 nums = chip->capture_streams;
1475 for (i = 0; i < nums; i++, dev++)
1476 if (!chip->azx_dev[dev].opened) {
1477 res = &chip->azx_dev[dev];
1478 if (res->device == substream->pcm->device)
1483 res->device = substream->pcm->device;
1488 /* release the assigned stream */
1489 static inline void azx_release_device(struct azx_dev *azx_dev)
1491 azx_dev->opened = 0;
1494 static struct snd_pcm_hardware azx_pcm_hw = {
1495 .info = (SNDRV_PCM_INFO_MMAP |
1496 SNDRV_PCM_INFO_INTERLEAVED |
1497 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1498 SNDRV_PCM_INFO_MMAP_VALID |
1499 /* No full-resume yet implemented */
1500 /* SNDRV_PCM_INFO_RESUME |*/
1501 SNDRV_PCM_INFO_PAUSE |
1502 SNDRV_PCM_INFO_SYNC_START),
1503 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1504 .rates = SNDRV_PCM_RATE_48000,
1509 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1510 .period_bytes_min = 128,
1511 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1513 .periods_max = AZX_MAX_FRAG,
1519 struct hda_codec *codec;
1520 struct hda_pcm_stream *hinfo[2];
1523 static int azx_pcm_open(struct snd_pcm_substream *substream)
1525 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1526 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1527 struct azx *chip = apcm->chip;
1528 struct azx_dev *azx_dev;
1529 struct snd_pcm_runtime *runtime = substream->runtime;
1530 unsigned long flags;
1533 mutex_lock(&chip->open_mutex);
1534 azx_dev = azx_assign_device(chip, substream);
1535 if (azx_dev == NULL) {
1536 mutex_unlock(&chip->open_mutex);
1539 runtime->hw = azx_pcm_hw;
1540 runtime->hw.channels_min = hinfo->channels_min;
1541 runtime->hw.channels_max = hinfo->channels_max;
1542 runtime->hw.formats = hinfo->formats;
1543 runtime->hw.rates = hinfo->rates;
1544 snd_pcm_limit_hw_rates(runtime);
1545 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1546 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1548 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1550 snd_hda_power_up(apcm->codec);
1551 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1553 azx_release_device(azx_dev);
1554 snd_hda_power_down(apcm->codec);
1555 mutex_unlock(&chip->open_mutex);
1558 snd_pcm_limit_hw_rates(runtime);
1560 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1561 snd_BUG_ON(!runtime->hw.channels_max) ||
1562 snd_BUG_ON(!runtime->hw.formats) ||
1563 snd_BUG_ON(!runtime->hw.rates)) {
1564 azx_release_device(azx_dev);
1565 hinfo->ops.close(hinfo, apcm->codec, substream);
1566 snd_hda_power_down(apcm->codec);
1567 mutex_unlock(&chip->open_mutex);
1570 spin_lock_irqsave(&chip->reg_lock, flags);
1571 azx_dev->substream = substream;
1572 azx_dev->running = 0;
1573 spin_unlock_irqrestore(&chip->reg_lock, flags);
1575 runtime->private_data = azx_dev;
1576 snd_pcm_set_sync(substream);
1577 mutex_unlock(&chip->open_mutex);
1581 static int azx_pcm_close(struct snd_pcm_substream *substream)
1583 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1584 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1585 struct azx *chip = apcm->chip;
1586 struct azx_dev *azx_dev = get_azx_dev(substream);
1587 unsigned long flags;
1589 mutex_lock(&chip->open_mutex);
1590 spin_lock_irqsave(&chip->reg_lock, flags);
1591 azx_dev->substream = NULL;
1592 azx_dev->running = 0;
1593 spin_unlock_irqrestore(&chip->reg_lock, flags);
1594 azx_release_device(azx_dev);
1595 hinfo->ops.close(hinfo, apcm->codec, substream);
1596 snd_hda_power_down(apcm->codec);
1597 mutex_unlock(&chip->open_mutex);
1601 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1602 struct snd_pcm_hw_params *hw_params)
1604 struct azx_dev *azx_dev = get_azx_dev(substream);
1606 azx_dev->bufsize = 0;
1607 azx_dev->period_bytes = 0;
1608 azx_dev->format_val = 0;
1609 return snd_pcm_lib_malloc_pages(substream,
1610 params_buffer_bytes(hw_params));
1613 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1615 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1616 struct azx_dev *azx_dev = get_azx_dev(substream);
1617 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1619 /* reset BDL address */
1620 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1621 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1622 azx_sd_writel(azx_dev, SD_CTL, 0);
1623 azx_dev->bufsize = 0;
1624 azx_dev->period_bytes = 0;
1625 azx_dev->format_val = 0;
1627 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1629 return snd_pcm_lib_free_pages(substream);
1632 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1634 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1635 struct azx *chip = apcm->chip;
1636 struct azx_dev *azx_dev = get_azx_dev(substream);
1637 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1638 struct snd_pcm_runtime *runtime = substream->runtime;
1639 unsigned int bufsize, period_bytes, format_val;
1642 azx_stream_reset(chip, azx_dev);
1643 format_val = snd_hda_calc_stream_format(runtime->rate,
1648 snd_printk(KERN_ERR SFX
1649 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1650 runtime->rate, runtime->channels, runtime->format);
1654 bufsize = snd_pcm_lib_buffer_bytes(substream);
1655 period_bytes = snd_pcm_lib_period_bytes(substream);
1657 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1658 bufsize, format_val);
1660 if (bufsize != azx_dev->bufsize ||
1661 period_bytes != azx_dev->period_bytes ||
1662 format_val != azx_dev->format_val) {
1663 azx_dev->bufsize = bufsize;
1664 azx_dev->period_bytes = period_bytes;
1665 azx_dev->format_val = format_val;
1666 err = azx_setup_periods(chip, substream, azx_dev);
1671 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1672 (runtime->rate * 2);
1673 azx_setup_controller(chip, azx_dev);
1674 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1675 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1677 azx_dev->fifo_size = 0;
1679 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1680 azx_dev->format_val, substream);
1683 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1685 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1686 struct azx *chip = apcm->chip;
1687 struct azx_dev *azx_dev;
1688 struct snd_pcm_substream *s;
1689 int rstart = 0, start, nsync = 0, sbits = 0;
1693 case SNDRV_PCM_TRIGGER_START:
1695 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1696 case SNDRV_PCM_TRIGGER_RESUME:
1699 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1700 case SNDRV_PCM_TRIGGER_SUSPEND:
1701 case SNDRV_PCM_TRIGGER_STOP:
1708 snd_pcm_group_for_each_entry(s, substream) {
1709 if (s->pcm->card != substream->pcm->card)
1711 azx_dev = get_azx_dev(s);
1712 sbits |= 1 << azx_dev->index;
1714 snd_pcm_trigger_done(s, substream);
1717 spin_lock(&chip->reg_lock);
1719 /* first, set SYNC bits of corresponding streams */
1720 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1722 snd_pcm_group_for_each_entry(s, substream) {
1723 if (s->pcm->card != substream->pcm->card)
1725 azx_dev = get_azx_dev(s);
1727 azx_dev->start_flag = 1;
1728 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1731 azx_stream_start(chip, azx_dev);
1733 azx_stream_stop(chip, azx_dev);
1734 azx_dev->running = start;
1736 spin_unlock(&chip->reg_lock);
1740 /* wait until all FIFOs get ready */
1741 for (timeout = 5000; timeout; timeout--) {
1743 snd_pcm_group_for_each_entry(s, substream) {
1744 if (s->pcm->card != substream->pcm->card)
1746 azx_dev = get_azx_dev(s);
1747 if (!(azx_sd_readb(azx_dev, SD_STS) &
1756 /* wait until all RUN bits are cleared */
1757 for (timeout = 5000; timeout; timeout--) {
1759 snd_pcm_group_for_each_entry(s, substream) {
1760 if (s->pcm->card != substream->pcm->card)
1762 azx_dev = get_azx_dev(s);
1763 if (azx_sd_readb(azx_dev, SD_CTL) &
1773 spin_lock(&chip->reg_lock);
1774 /* reset SYNC bits */
1775 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1776 spin_unlock(&chip->reg_lock);
1781 /* get the current DMA position with correction on VIA chips */
1782 static unsigned int azx_via_get_position(struct azx *chip,
1783 struct azx_dev *azx_dev)
1785 unsigned int link_pos, mini_pos, bound_pos;
1786 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1787 unsigned int fifo_size;
1789 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1790 if (azx_dev->index >= 4) {
1791 /* Playback, no problem using link position */
1797 * use mod to get the DMA position just like old chipset
1799 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1800 mod_dma_pos %= azx_dev->period_bytes;
1802 /* azx_dev->fifo_size can't get FIFO size of in stream.
1803 * Get from base address + offset.
1805 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1807 if (azx_dev->insufficient) {
1808 /* Link position never gather than FIFO size */
1809 if (link_pos <= fifo_size)
1812 azx_dev->insufficient = 0;
1815 if (link_pos <= fifo_size)
1816 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1818 mini_pos = link_pos - fifo_size;
1820 /* Find nearest previous boudary */
1821 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1822 mod_link_pos = link_pos % azx_dev->period_bytes;
1823 if (mod_link_pos >= fifo_size)
1824 bound_pos = link_pos - mod_link_pos;
1825 else if (mod_dma_pos >= mod_mini_pos)
1826 bound_pos = mini_pos - mod_mini_pos;
1828 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1829 if (bound_pos >= azx_dev->bufsize)
1833 /* Calculate real DMA position we want */
1834 return bound_pos + mod_dma_pos;
1837 static unsigned int azx_get_position(struct azx *chip,
1838 struct azx_dev *azx_dev)
1842 if (chip->via_dmapos_patch)
1843 pos = azx_via_get_position(chip, azx_dev);
1844 else if (chip->position_fix == POS_FIX_POSBUF ||
1845 chip->position_fix == POS_FIX_AUTO) {
1846 /* use the position buffer */
1847 pos = le32_to_cpu(*azx_dev->posbuf);
1850 pos = azx_sd_readl(azx_dev, SD_LPIB);
1852 if (pos >= azx_dev->bufsize)
1857 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1859 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1860 struct azx *chip = apcm->chip;
1861 struct azx_dev *azx_dev = get_azx_dev(substream);
1862 return bytes_to_frames(substream->runtime,
1863 azx_get_position(chip, azx_dev));
1867 * Check whether the current DMA position is acceptable for updating
1868 * periods. Returns non-zero if it's OK.
1870 * Many HD-audio controllers appear pretty inaccurate about
1871 * the update-IRQ timing. The IRQ is issued before actually the
1872 * data is processed. So, we need to process it afterwords in a
1875 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1879 if (azx_dev->start_flag &&
1880 time_before_eq(jiffies, azx_dev->start_jiffies))
1881 return -1; /* bogus (too early) interrupt */
1882 azx_dev->start_flag = 0;
1884 pos = azx_get_position(chip, azx_dev);
1885 if (chip->position_fix == POS_FIX_AUTO) {
1888 "hda-intel: Invalid position buffer, "
1889 "using LPIB read method instead.\n");
1890 chip->position_fix = POS_FIX_LPIB;
1891 pos = azx_get_position(chip, azx_dev);
1893 chip->position_fix = POS_FIX_POSBUF;
1896 if (!bdl_pos_adj[chip->dev_index])
1897 return 1; /* no delayed ack */
1898 if (WARN_ONCE(!azx_dev->period_bytes,
1899 "hda-intel: zero azx_dev->period_bytes"))
1900 return 0; /* this shouldn't happen! */
1901 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1902 return 0; /* NG - it's below the period boundary */
1903 return 1; /* OK, it's fine */
1907 * The work for pending PCM period updates.
1909 static void azx_irq_pending_work(struct work_struct *work)
1911 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1914 if (!chip->irq_pending_warned) {
1916 "hda-intel: IRQ timing workaround is activated "
1917 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1918 chip->card->number);
1919 chip->irq_pending_warned = 1;
1924 spin_lock_irq(&chip->reg_lock);
1925 for (i = 0; i < chip->num_streams; i++) {
1926 struct azx_dev *azx_dev = &chip->azx_dev[i];
1927 if (!azx_dev->irq_pending ||
1928 !azx_dev->substream ||
1931 if (azx_position_ok(chip, azx_dev)) {
1932 azx_dev->irq_pending = 0;
1933 spin_unlock(&chip->reg_lock);
1934 snd_pcm_period_elapsed(azx_dev->substream);
1935 spin_lock(&chip->reg_lock);
1939 spin_unlock_irq(&chip->reg_lock);
1946 /* clear irq_pending flags and assure no on-going workq */
1947 static void azx_clear_irq_pending(struct azx *chip)
1951 spin_lock_irq(&chip->reg_lock);
1952 for (i = 0; i < chip->num_streams; i++)
1953 chip->azx_dev[i].irq_pending = 0;
1954 spin_unlock_irq(&chip->reg_lock);
1957 static struct snd_pcm_ops azx_pcm_ops = {
1958 .open = azx_pcm_open,
1959 .close = azx_pcm_close,
1960 .ioctl = snd_pcm_lib_ioctl,
1961 .hw_params = azx_pcm_hw_params,
1962 .hw_free = azx_pcm_hw_free,
1963 .prepare = azx_pcm_prepare,
1964 .trigger = azx_pcm_trigger,
1965 .pointer = azx_pcm_pointer,
1966 .page = snd_pcm_sgbuf_ops_page,
1969 static void azx_pcm_free(struct snd_pcm *pcm)
1971 struct azx_pcm *apcm = pcm->private_data;
1973 apcm->chip->pcm[pcm->device] = NULL;
1979 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1980 struct hda_pcm *cpcm)
1982 struct azx *chip = bus->private_data;
1983 struct snd_pcm *pcm;
1984 struct azx_pcm *apcm;
1985 int pcm_dev = cpcm->device;
1988 if (pcm_dev >= HDA_MAX_PCMS) {
1989 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1993 if (chip->pcm[pcm_dev]) {
1994 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1997 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1998 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1999 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2003 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2004 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2008 apcm->codec = codec;
2009 pcm->private_data = apcm;
2010 pcm->private_free = azx_pcm_free;
2011 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2012 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2013 chip->pcm[pcm_dev] = pcm;
2015 for (s = 0; s < 2; s++) {
2016 apcm->hinfo[s] = &cpcm->stream[s];
2017 if (cpcm->stream[s].substreams)
2018 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2020 /* buffer pre-allocation */
2021 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2022 snd_dma_pci_data(chip->pci),
2023 1024 * 64, 32 * 1024 * 1024);
2028 * mixer creation - all stuff is implemented in hda module
2030 static int __devinit azx_mixer_create(struct azx *chip)
2032 return snd_hda_build_controls(chip->bus);
2037 * initialize SD streams
2039 static int __devinit azx_init_stream(struct azx *chip)
2043 /* initialize each stream (aka device)
2044 * assign the starting bdl address to each stream (device)
2047 for (i = 0; i < chip->num_streams; i++) {
2048 struct azx_dev *azx_dev = &chip->azx_dev[i];
2049 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2050 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2051 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2052 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2053 azx_dev->sd_int_sta_mask = 1 << i;
2054 /* stream tag: must be non-zero and unique */
2056 azx_dev->stream_tag = i + 1;
2062 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2064 if (request_irq(chip->pci->irq, azx_interrupt,
2065 chip->msi ? 0 : IRQF_SHARED,
2066 "hda_intel", chip)) {
2067 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2068 "disabling device\n", chip->pci->irq);
2070 snd_card_disconnect(chip->card);
2073 chip->irq = chip->pci->irq;
2074 pci_intx(chip->pci, !chip->msi);
2079 static void azx_stop_chip(struct azx *chip)
2081 if (!chip->initialized)
2084 /* disable interrupts */
2085 azx_int_disable(chip);
2086 azx_int_clear(chip);
2088 /* disable CORB/RIRB */
2089 azx_free_cmd_io(chip);
2091 /* disable position buffer */
2092 azx_writel(chip, DPLBASE, 0);
2093 azx_writel(chip, DPUBASE, 0);
2095 chip->initialized = 0;
2098 #ifdef CONFIG_SND_HDA_POWER_SAVE
2099 /* power-up/down the controller */
2100 static void azx_power_notify(struct hda_bus *bus)
2102 struct azx *chip = bus->private_data;
2103 struct hda_codec *c;
2106 list_for_each_entry(c, &bus->codec_list, list) {
2113 azx_init_chip(chip);
2114 else if (chip->running && power_save_controller &&
2115 !bus->power_keep_link_on)
2116 azx_stop_chip(chip);
2118 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2125 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2127 struct hda_codec *codec;
2129 list_for_each_entry(codec, &bus->codec_list, list) {
2130 if (snd_hda_codec_needs_resume(codec))
2136 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2138 struct snd_card *card = pci_get_drvdata(pci);
2139 struct azx *chip = card->private_data;
2142 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2143 azx_clear_irq_pending(chip);
2144 for (i = 0; i < HDA_MAX_PCMS; i++)
2145 snd_pcm_suspend_all(chip->pcm[i]);
2146 if (chip->initialized)
2147 snd_hda_suspend(chip->bus);
2148 azx_stop_chip(chip);
2149 if (chip->irq >= 0) {
2150 free_irq(chip->irq, chip);
2154 pci_disable_msi(chip->pci);
2155 pci_disable_device(pci);
2156 pci_save_state(pci);
2157 pci_set_power_state(pci, pci_choose_state(pci, state));
2161 static int azx_resume(struct pci_dev *pci)
2163 struct snd_card *card = pci_get_drvdata(pci);
2164 struct azx *chip = card->private_data;
2166 pci_set_power_state(pci, PCI_D0);
2167 pci_restore_state(pci);
2168 if (pci_enable_device(pci) < 0) {
2169 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2170 "disabling device\n");
2171 snd_card_disconnect(card);
2174 pci_set_master(pci);
2176 if (pci_enable_msi(pci) < 0)
2178 if (azx_acquire_irq(chip, 1) < 0)
2182 if (snd_hda_codecs_inuse(chip->bus))
2183 azx_init_chip(chip);
2185 snd_hda_resume(chip->bus);
2186 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2189 #endif /* CONFIG_PM */
2193 * reboot notifier for hang-up problem at power-down
2195 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2197 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2198 snd_hda_bus_reboot_notify(chip->bus);
2199 azx_stop_chip(chip);
2203 static void azx_notifier_register(struct azx *chip)
2205 chip->reboot_notifier.notifier_call = azx_halt;
2206 register_reboot_notifier(&chip->reboot_notifier);
2209 static void azx_notifier_unregister(struct azx *chip)
2211 if (chip->reboot_notifier.notifier_call)
2212 unregister_reboot_notifier(&chip->reboot_notifier);
2218 static int azx_free(struct azx *chip)
2222 azx_notifier_unregister(chip);
2224 if (chip->initialized) {
2225 azx_clear_irq_pending(chip);
2226 for (i = 0; i < chip->num_streams; i++)
2227 azx_stream_stop(chip, &chip->azx_dev[i]);
2228 azx_stop_chip(chip);
2232 free_irq(chip->irq, (void*)chip);
2234 pci_disable_msi(chip->pci);
2235 if (chip->remap_addr)
2236 iounmap(chip->remap_addr);
2238 if (chip->azx_dev) {
2239 for (i = 0; i < chip->num_streams; i++)
2240 if (chip->azx_dev[i].bdl.area)
2241 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2244 snd_dma_free_pages(&chip->rb);
2245 if (chip->posbuf.area)
2246 snd_dma_free_pages(&chip->posbuf);
2247 pci_release_regions(chip->pci);
2248 pci_disable_device(chip->pci);
2249 kfree(chip->azx_dev);
2255 static int azx_dev_free(struct snd_device *device)
2257 return azx_free(device->device_data);
2261 * white/black-listing for position_fix
2263 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2264 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2265 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2266 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2267 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2268 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2269 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2273 static int __devinit check_position_fix(struct azx *chip, int fix)
2275 const struct snd_pci_quirk *q;
2279 case POS_FIX_POSBUF:
2283 /* Check VIA/ATI HD Audio Controller exist */
2284 switch (chip->driver_type) {
2285 case AZX_DRIVER_VIA:
2286 case AZX_DRIVER_ATI:
2287 chip->via_dmapos_patch = 1;
2288 /* Use link position directly, avoid any transfer problem. */
2289 return POS_FIX_LPIB;
2291 chip->via_dmapos_patch = 0;
2293 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2296 "hda_intel: position_fix set to %d "
2297 "for device %04x:%04x\n",
2298 q->value, q->subvendor, q->subdevice);
2301 return POS_FIX_AUTO;
2305 * black-lists for probe_mask
2307 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2308 /* Thinkpad often breaks the controller communication when accessing
2309 * to the non-working (or non-existing) modem codec slot.
2311 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2312 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2313 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2315 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2316 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2317 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2318 /* forced codec slots */
2319 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2320 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2324 #define AZX_FORCE_CODEC_MASK 0x100
2326 static void __devinit check_probe_mask(struct azx *chip, int dev)
2328 const struct snd_pci_quirk *q;
2330 chip->codec_probe_mask = probe_mask[dev];
2331 if (chip->codec_probe_mask == -1) {
2332 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2335 "hda_intel: probe_mask set to 0x%x "
2336 "for device %04x:%04x\n",
2337 q->value, q->subvendor, q->subdevice);
2338 chip->codec_probe_mask = q->value;
2342 /* check forced option */
2343 if (chip->codec_probe_mask != -1 &&
2344 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2345 chip->codec_mask = chip->codec_probe_mask & 0xff;
2346 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2352 * white/black-list for enable_msi
2354 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2355 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2356 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2360 static void __devinit check_msi(struct azx *chip)
2362 const struct snd_pci_quirk *q;
2364 if (enable_msi >= 0) {
2365 chip->msi = !!enable_msi;
2368 chip->msi = 1; /* enable MSI as default */
2369 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2372 "hda_intel: msi for device %04x:%04x set to %d\n",
2373 q->subvendor, q->subdevice, q->value);
2374 chip->msi = q->value;
2382 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2383 int dev, int driver_type,
2388 unsigned short gcap;
2389 static struct snd_device_ops ops = {
2390 .dev_free = azx_dev_free,
2395 err = pci_enable_device(pci);
2399 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2401 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2402 pci_disable_device(pci);
2406 spin_lock_init(&chip->reg_lock);
2407 mutex_init(&chip->open_mutex);
2411 chip->driver_type = driver_type;
2413 chip->dev_index = dev;
2414 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2416 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2417 check_probe_mask(chip, dev);
2419 chip->single_cmd = single_cmd;
2421 if (bdl_pos_adj[dev] < 0) {
2422 switch (chip->driver_type) {
2423 case AZX_DRIVER_ICH:
2424 case AZX_DRIVER_PCH:
2425 bdl_pos_adj[dev] = 1;
2428 bdl_pos_adj[dev] = 32;
2433 #if BITS_PER_LONG != 64
2434 /* Fix up base address on ULI M5461 */
2435 if (chip->driver_type == AZX_DRIVER_ULI) {
2437 pci_read_config_word(pci, 0x40, &tmp3);
2438 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2439 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2443 err = pci_request_regions(pci, "ICH HD audio");
2446 pci_disable_device(pci);
2450 chip->addr = pci_resource_start(pci, 0);
2451 chip->remap_addr = pci_ioremap_bar(pci, 0);
2452 if (chip->remap_addr == NULL) {
2453 snd_printk(KERN_ERR SFX "ioremap error\n");
2459 if (pci_enable_msi(pci) < 0)
2462 if (azx_acquire_irq(chip, 0) < 0) {
2467 pci_set_master(pci);
2468 synchronize_irq(chip->irq);
2470 gcap = azx_readw(chip, GCAP);
2471 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2473 /* disable SB600 64bit support for safety */
2474 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2475 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2476 struct pci_dev *p_smbus;
2477 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2478 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2481 if (p_smbus->revision < 0x30)
2482 gcap &= ~ICH6_GCAP_64OK;
2483 pci_dev_put(p_smbus);
2487 /* disable 64bit DMA address for Teradici */
2488 /* it does not work with device 6549:1200 subsys e4a2:040b */
2489 if (chip->driver_type == AZX_DRIVER_TERA)
2490 gcap &= ~ICH6_GCAP_64OK;
2492 /* allow 64bit DMA address if supported by H/W */
2493 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2494 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2496 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2497 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2500 /* read number of streams from GCAP register instead of using
2503 chip->capture_streams = (gcap >> 8) & 0x0f;
2504 chip->playback_streams = (gcap >> 12) & 0x0f;
2505 if (!chip->playback_streams && !chip->capture_streams) {
2506 /* gcap didn't give any info, switching to old method */
2508 switch (chip->driver_type) {
2509 case AZX_DRIVER_ULI:
2510 chip->playback_streams = ULI_NUM_PLAYBACK;
2511 chip->capture_streams = ULI_NUM_CAPTURE;
2513 case AZX_DRIVER_ATIHDMI:
2514 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2515 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2517 case AZX_DRIVER_GENERIC:
2519 chip->playback_streams = ICH6_NUM_PLAYBACK;
2520 chip->capture_streams = ICH6_NUM_CAPTURE;
2524 chip->capture_index_offset = 0;
2525 chip->playback_index_offset = chip->capture_streams;
2526 chip->num_streams = chip->playback_streams + chip->capture_streams;
2527 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2529 if (!chip->azx_dev) {
2530 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2534 for (i = 0; i < chip->num_streams; i++) {
2535 /* allocate memory for the BDL for each stream */
2536 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2537 snd_dma_pci_data(chip->pci),
2538 BDL_SIZE, &chip->azx_dev[i].bdl);
2540 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2544 /* allocate memory for the position buffer */
2545 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2546 snd_dma_pci_data(chip->pci),
2547 chip->num_streams * 8, &chip->posbuf);
2549 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2552 /* allocate CORB/RIRB */
2553 err = azx_alloc_cmd_io(chip);
2557 /* initialize streams */
2558 azx_init_stream(chip);
2560 /* initialize chip */
2562 azx_init_chip(chip);
2564 /* codec detection */
2565 if (!chip->codec_mask) {
2566 snd_printk(KERN_ERR SFX "no codecs found!\n");
2571 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2573 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2577 strcpy(card->driver, "HDA-Intel");
2578 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2579 sizeof(card->shortname));
2580 snprintf(card->longname, sizeof(card->longname),
2581 "%s at 0x%lx irq %i",
2582 card->shortname, chip->addr, chip->irq);
2592 static void power_down_all_codecs(struct azx *chip)
2594 #ifdef CONFIG_SND_HDA_POWER_SAVE
2595 /* The codecs were powered up in snd_hda_codec_new().
2596 * Now all initialization done, so turn them down if possible
2598 struct hda_codec *codec;
2599 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2600 snd_hda_power_down(codec);
2605 static int __devinit azx_probe(struct pci_dev *pci,
2606 const struct pci_device_id *pci_id)
2609 struct snd_card *card;
2613 if (dev >= SNDRV_CARDS)
2620 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2622 snd_printk(KERN_ERR SFX "Error creating card!\n");
2626 /* set this here since it's referred in snd_hda_load_patch() */
2627 snd_card_set_dev(card, &pci->dev);
2629 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2632 card->private_data = chip;
2634 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2635 chip->beep_mode = beep_mode[dev];
2638 /* create codec instances */
2639 err = azx_codec_create(chip, model[dev]);
2642 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2644 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2646 err = snd_hda_load_patch(chip->bus, patch[dev]);
2651 if (!probe_only[dev]) {
2652 err = azx_codec_configure(chip);
2657 /* create PCM streams */
2658 err = snd_hda_build_pcms(chip->bus);
2662 /* create mixer controls */
2663 err = azx_mixer_create(chip);
2667 err = snd_card_register(card);
2671 pci_set_drvdata(pci, card);
2673 power_down_all_codecs(chip);
2674 azx_notifier_register(chip);
2679 snd_card_free(card);
2683 static void __devexit azx_remove(struct pci_dev *pci)
2685 snd_card_free(pci_get_drvdata(pci));
2686 pci_set_drvdata(pci, NULL);
2690 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2692 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2693 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2694 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2695 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2696 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2697 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2698 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2699 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2700 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2702 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2704 { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
2706 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2707 /* ATI SB 450/600 */
2708 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2709 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2711 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2712 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2713 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2714 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2715 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2716 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2717 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2718 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2719 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2720 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2721 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2722 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2723 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2724 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2725 /* VIA VT8251/VT8237A */
2726 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2728 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2730 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2732 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2733 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2734 .class_mask = 0xffffff,
2735 .driver_data = AZX_DRIVER_NVIDIA },
2737 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2738 /* Creative X-Fi (CA0110-IBG) */
2739 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2740 /* the following entry conflicts with snd-ctxfi driver,
2741 * as ctxfi driver mutates from HD-audio to native mode with
2742 * a special command sequence.
2744 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2745 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2746 .class_mask = 0xffffff,
2747 .driver_data = AZX_DRIVER_GENERIC },
2749 /* this entry seems still valid -- i.e. without emu20kx chip */
2750 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2752 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2753 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2754 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2755 .class_mask = 0xffffff,
2756 .driver_data = AZX_DRIVER_GENERIC },
2757 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2758 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2759 .class_mask = 0xffffff,
2760 .driver_data = AZX_DRIVER_GENERIC },
2763 MODULE_DEVICE_TABLE(pci, azx_ids);
2765 /* pci_driver definition */
2766 static struct pci_driver driver = {
2767 .name = "HDA Intel",
2768 .id_table = azx_ids,
2770 .remove = __devexit_p(azx_remove),
2772 .suspend = azx_suspend,
2773 .resume = azx_resume,
2777 static int __init alsa_card_azx_init(void)
2779 return pci_register_driver(&driver);
2782 static void __exit alsa_card_azx_exit(void)
2784 pci_unregister_driver(&driver);
2787 module_init(alsa_card_azx_init)
2788 module_exit(alsa_card_azx_exit)