sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38
  39 #ifdef CONFIG_X86
  40 /* for snoop control */
  41 #include <asm/pgtable.h>
  42 #include <asm/set_memory.h>
  43 #include <asm/cpufeature.h>
  44 #endif
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include <sound/hdaudio.h>
  48 #include <sound/hda_i915.h>
  49 #include <linux/vgaarb.h>
  50 #include <linux/vga_switcheroo.h>
  51 #include <linux/firmware.h>
  52 #include <sound/hda_codec.h>
  53 #include "hda_controller.h"
  54 #include "hda_intel.h"
  55
  56 #define CREATE_TRACE_POINTS
  57 #include "hda_intel_trace.h"
  58
  59 /* position fix mode */
  60 enum {
  61         POS_FIX_AUTO,
  62         POS_FIX_LPIB,
  63         POS_FIX_POSBUF,
  64         POS_FIX_VIACOMBO,
  65         POS_FIX_COMBO,
  66         POS_FIX_SKL,
  67 };
  68
  69 /* Defines for ATI HD Audio support in SB450 south bridge */
  70 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  71 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  72
  73 /* Defines for Nvidia HDA support */
  74 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  75 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  76 #define NVIDIA_HDA_ISTRM_COH          0x4d
  77 #define NVIDIA_HDA_OSTRM_COH          0x4c
  78 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  79
  80 /* Defines for Intel SCH HDA snoop control */
  81 #define INTEL_HDA_CGCTL  0x48
  82 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  83 #define INTEL_SCH_HDA_DEVC      0x78
  84 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  85
  86 /* Define IN stream 0 FIFO size offset in VIA controller */
  87 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
  88 /* Define VIA HD Audio Device ID*/
  89 #define VIA_HDAC_DEVICE_ID              0x3288
  90
  91 /* max number of SDs */
  92 /* ICH, ATI and VIA have 4 playback and 4 capture */
  93 #define ICH6_NUM_CAPTURE        4
  94 #define ICH6_NUM_PLAYBACK       4
  95
  96 /* ULI has 6 playback and 5 capture */
  97 #define ULI_NUM_CAPTURE         5
  98 #define ULI_NUM_PLAYBACK        6
  99
 100 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 101 #define ATIHDMI_NUM_CAPTURE     0
 102 #define ATIHDMI_NUM_PLAYBACK    8
 103
 104 /* TERA has 4 playback and 3 capture */
 105 #define TERA_NUM_CAPTURE        3
 106 #define TERA_NUM_PLAYBACK       4
 107
 108
 109 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 110 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 111 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 112 static char *model[SNDRV_CARDS];
 113 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 114 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_only[SNDRV_CARDS];
 117 static int jackpoll_ms[SNDRV_CARDS];
 118 static int single_cmd = -1;
 119 static int enable_msi = -1;
 120 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 121 static char *patch[SNDRV_CARDS];
 122 #endif
 123 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 124 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 125                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 126 #endif
 127
 128 module_param_array(index, int, NULL, 0444);
 129 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 130 module_param_array(id, charp, NULL, 0444);
 131 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 132 module_param_array(enable, bool, NULL, 0444);
 133 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 134 module_param_array(model, charp, NULL, 0444);
 135 MODULE_PARM_DESC(model, "Use the given board model.");
 136 module_param_array(position_fix, int, NULL, 0444);
 137 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 138                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
 139 module_param_array(bdl_pos_adj, int, NULL, 0644);
 140 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 141 module_param_array(probe_mask, int, NULL, 0444);
 142 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 143 module_param_array(probe_only, int, NULL, 0444);
 144 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 145 module_param_array(jackpoll_ms, int, NULL, 0444);
 146 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 147 module_param(single_cmd, bint, 0444);
 148 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 149                  "(for debugging only).");
 150 module_param(enable_msi, bint, 0444);
 151 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 152 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 153 module_param_array(patch, charp, NULL, 0444);
 154 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 155 #endif
 156 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 157 module_param_array(beep_mode, bool, NULL, 0444);
 158 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 159                             "(0=off, 1=on) (default=1).");
 160 #endif
 161
 162 #ifdef CONFIG_PM
 163 static int param_set_xint(const char *val, const struct kernel_param *kp);
 164 static const struct kernel_param_ops param_ops_xint = {
 165         .set = param_set_xint,
 166         .get = param_get_int,
 167 };
 168 #define param_check_xint param_check_int
 169
 170 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 171 module_param(power_save, xint, 0644);
 172 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 173                  "(in second, 0 = disable).");
 174
 175 static bool pm_blacklist = true;
 176 module_param(pm_blacklist, bool, 0644);
 177 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 178
 179 /* reset the HD-audio controller in power save mode.
 180  * this may give more power-saving, but will take longer time to
 181  * wake up.
 182  */
 183 static bool power_save_controller = 1;
 184 module_param(power_save_controller, bool, 0644);
 185 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 186 #else
 187 #define power_save      0
 188 #endif /* CONFIG_PM */
 189
 190 static int align_buffer_size = -1;
 191 module_param(align_buffer_size, bint, 0644);
 192 MODULE_PARM_DESC(align_buffer_size,
 193                 "Force buffer and period sizes to be multiple of 128 bytes.");
 194
 195 #ifdef CONFIG_X86
 196 static int hda_snoop = -1;
 197 module_param_named(snoop, hda_snoop, bint, 0444);
 198 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 199 #else
 200 #define hda_snoop               true
 201 #endif
 202
 203
 204 MODULE_LICENSE("GPL");
 205 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 206                          "{Intel, ICH6M},"
 207                          "{Intel, ICH7},"
 208                          "{Intel, ESB2},"
 209                          "{Intel, ICH8},"
 210                          "{Intel, ICH9},"
 211                          "{Intel, ICH10},"
 212                          "{Intel, PCH},"
 213                          "{Intel, CPT},"
 214                          "{Intel, PPT},"
 215                          "{Intel, LPT},"
 216                          "{Intel, LPT_LP},"
 217                          "{Intel, WPT_LP},"
 218                          "{Intel, SPT},"
 219                          "{Intel, SPT_LP},"
 220                          "{Intel, HPT},"
 221                          "{Intel, PBG},"
 222                          "{Intel, SCH},"
 223                          "{ATI, SB450},"
 224                          "{ATI, SB600},"
 225                          "{ATI, RS600},"
 226                          "{ATI, RS690},"
 227                          "{ATI, RS780},"
 228                          "{ATI, R600},"
 229                          "{ATI, RV630},"
 230                          "{ATI, RV610},"
 231                          "{ATI, RV670},"
 232                          "{ATI, RV635},"
 233                          "{ATI, RV620},"
 234                          "{ATI, RV770},"
 235                          "{VIA, VT8251},"
 236                          "{VIA, VT8237A},"
 237                          "{SiS, SIS966},"
 238                          "{ULI, M5461}}");
 239 MODULE_DESCRIPTION("Intel HDA driver");
 240
 241 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 242 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 243 #define SUPPORT_VGA_SWITCHEROO
 244 #endif
 245 #endif
 246
 247
 248 /*
 249  */
 250
 251 /* driver types */
 252 enum {
 253         AZX_DRIVER_ICH,
 254         AZX_DRIVER_PCH,
 255         AZX_DRIVER_SCH,
 256         AZX_DRIVER_SKL,
 257         AZX_DRIVER_HDMI,
 258         AZX_DRIVER_ATI,
 259         AZX_DRIVER_ATIHDMI,
 260         AZX_DRIVER_ATIHDMI_NS,
 261         AZX_DRIVER_VIA,
 262         AZX_DRIVER_SIS,
 263         AZX_DRIVER_ULI,
 264         AZX_DRIVER_NVIDIA,
 265         AZX_DRIVER_TERA,
 266         AZX_DRIVER_CTX,
 267         AZX_DRIVER_CTHDA,
 268         AZX_DRIVER_CMEDIA,
 269         AZX_DRIVER_GENERIC,
 270         AZX_NUM_DRIVERS, /* keep this as last entry */
 271 };
 272
 273 #define azx_get_snoop_type(chip) \
 274         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 275 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 276
 277 /* quirks for old Intel chipsets */
 278 #define AZX_DCAPS_INTEL_ICH \
 279         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 280
 281 /* quirks for Intel PCH */
 282 #define AZX_DCAPS_INTEL_PCH_BASE \
 283         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 284          AZX_DCAPS_SNOOP_TYPE(SCH))
 285
 286 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 287 #define AZX_DCAPS_INTEL_PCH_NOPM \
 288         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 289
 290 /* PCH for HSW/BDW; with runtime PM */
 291 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 292 #define AZX_DCAPS_INTEL_PCH \
 293         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 294
 295 /* HSW HDMI */
 296 #define AZX_DCAPS_INTEL_HASWELL \
 297         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 298          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 299          AZX_DCAPS_SNOOP_TYPE(SCH))
 300
 301 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 302 #define AZX_DCAPS_INTEL_BROADWELL \
 303         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 304          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 305          AZX_DCAPS_SNOOP_TYPE(SCH))
 306
 307 #define AZX_DCAPS_INTEL_BAYTRAIL \
 308         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 309
 310 #define AZX_DCAPS_INTEL_BRASWELL \
 311         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 312          AZX_DCAPS_I915_COMPONENT)
 313
 314 #define AZX_DCAPS_INTEL_SKYLAKE \
 315         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 316          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 317
 318 #define AZX_DCAPS_INTEL_BROXTON \
 319         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 320          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 321
 322 /* quirks for ATI SB / AMD Hudson */
 323 #define AZX_DCAPS_PRESET_ATI_SB \
 324         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 325          AZX_DCAPS_SNOOP_TYPE(ATI))
 326
 327 /* quirks for ATI/AMD HDMI */
 328 #define AZX_DCAPS_PRESET_ATI_HDMI \
 329         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 330          AZX_DCAPS_NO_MSI64)
 331
 332 /* quirks for ATI HDMI with snoop off */
 333 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 334         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 335
 336 /* quirks for Nvidia */
 337 #define AZX_DCAPS_PRESET_NVIDIA \
 338         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 339          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 340
 341 #define AZX_DCAPS_PRESET_CTHDA \
 342         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 343          AZX_DCAPS_NO_64BIT |\
 344          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 345
 346 /*
 347  * vga_switcheroo support
 348  */
 349 #ifdef SUPPORT_VGA_SWITCHEROO
 350 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 351 #define needs_eld_notify_link(chip)     ((chip)->need_eld_notify_link)
 352 #else
 353 #define use_vga_switcheroo(chip)        0
 354 #define needs_eld_notify_link(chip)     false
 355 #endif
 356
 357 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 358                                         ((pci)->device == 0x0c0c) || \
 359                                         ((pci)->device == 0x0d0c) || \
 360                                         ((pci)->device == 0x160c))
 361
 362 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 363 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 364 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 365
 366 static char *driver_short_names[] = {
 367         [AZX_DRIVER_ICH] = "HDA Intel",
 368         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 369         [AZX_DRIVER_SCH] = "HDA Intel MID",
 370         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 371         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 372         [AZX_DRIVER_ATI] = "HDA ATI SB",
 373         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 374         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 375         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 376         [AZX_DRIVER_SIS] = "HDA SIS966",
 377         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 378         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 379         [AZX_DRIVER_TERA] = "HDA Teradici",
 380         [AZX_DRIVER_CTX] = "HDA Creative",
 381         [AZX_DRIVER_CTHDA] = "HDA Creative",
 382         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 383         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 384 };
 385
 386 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 387 static void set_default_power_save(struct azx *chip);
 388
 389 /*
 390  * initialize the PCI registers
 391  */
 392 /* update bits in a PCI register byte */
 393 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 394                             unsigned char mask, unsigned char val)
 395 {
 396         unsigned char data;
 397
 398         pci_read_config_byte(pci, reg, &data);
 399         data &= ~mask;
 400         data |= (val & mask);
 401         pci_write_config_byte(pci, reg, data);
 402 }
 403
 404 static void azx_init_pci(struct azx *chip)
 405 {
 406         int snoop_type = azx_get_snoop_type(chip);
 407
 408         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 409          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 410          * Ensuring these bits are 0 clears playback static on some HD Audio
 411          * codecs.
 412          * The PCI register TCSEL is defined in the Intel manuals.
 413          */
 414         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 415                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 416                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 417         }
 418
 419         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 420          * we need to enable snoop.
 421          */
 422         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 423                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 424                         azx_snoop(chip));
 425                 update_pci_byte(chip->pci,
 426                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 427                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 428         }
 429
 430         /* For NVIDIA HDA, enable snoop */
 431         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 432                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 433                         azx_snoop(chip));
 434                 update_pci_byte(chip->pci,
 435                                 NVIDIA_HDA_TRANSREG_ADDR,
 436                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 437                 update_pci_byte(chip->pci,
 438                                 NVIDIA_HDA_ISTRM_COH,
 439                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 440                 update_pci_byte(chip->pci,
 441                                 NVIDIA_HDA_OSTRM_COH,
 442                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 443         }
 444
 445         /* Enable SCH/PCH snoop if needed */
 446         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 447                 unsigned short snoop;
 448                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 449                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 450                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 451                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 452                         if (!azx_snoop(chip))
 453                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 454                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 455                         pci_read_config_word(chip->pci,
 456                                 INTEL_SCH_HDA_DEVC, &snoop);
 457                 }
 458                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 459                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 460                         "Disabled" : "Enabled");
 461         }
 462 }
 463
 464 /*
 465  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 466  * and makes an audio stream sensitive to system latencies when
 467  * 24/32 bits are playing.
 468  * Adjusting threshold of DMA fifo to force the DMA request
 469  * sooner to improve latency tolerance at the expense of power.
 470  */
 471 static void bxt_reduce_dma_latency(struct azx *chip)
 472 {
 473         u32 val;
 474
 475         val = azx_readl(chip, VS_EM4L);
 476         val &= (0x3 << 20);
 477         azx_writel(chip, VS_EM4L, val);
 478 }
 479
 480 /*
 481  * ML_LCAP bits:
 482  *  bit 0: 6 MHz Supported
 483  *  bit 1: 12 MHz Supported
 484  *  bit 2: 24 MHz Supported
 485  *  bit 3: 48 MHz Supported
 486  *  bit 4: 96 MHz Supported
 487  *  bit 5: 192 MHz Supported
 488  */
 489 static int intel_get_lctl_scf(struct azx *chip)
 490 {
 491         struct hdac_bus *bus = azx_bus(chip);
 492         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 493         u32 val, t;
 494         int i;
 495
 496         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 497
 498         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 499                 t = preferred_bits[i];
 500                 if (val & (1 << t))
 501                         return t;
 502         }
 503
 504         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 505         return 0;
 506 }
 507
 508 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 509 {
 510         struct hdac_bus *bus = azx_bus(chip);
 511         u32 val;
 512         int timeout;
 513
 514         /*
 515          * the codecs are sharing the first link setting by default
 516          * If other links are enabled for stream, they need similar fix
 517          */
 518         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 519         val &= ~AZX_MLCTL_SPA;
 520         val |= state << AZX_MLCTL_SPA_SHIFT;
 521         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 522         /* wait for CPA */
 523         timeout = 50;
 524         while (timeout) {
 525                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 526                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 527                         return 0;
 528                 timeout--;
 529                 udelay(10);
 530         }
 531
 532         return -1;
 533 }
 534
 535 static void intel_init_lctl(struct azx *chip)
 536 {
 537         struct hdac_bus *bus = azx_bus(chip);
 538         u32 val;
 539         int ret;
 540
 541         /* 0. check lctl register value is correct or not */
 542         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 543         /* if SCF is already set, let's use it */
 544         if ((val & ML_LCTL_SCF_MASK) != 0)
 545                 return;
 546
 547         /*
 548          * Before operating on SPA, CPA must match SPA.
 549          * Any deviation may result in undefined behavior.
 550          */
 551         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 552                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 553                 return;
 554
 555         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 556         ret = intel_ml_lctl_set_power(chip, 0);
 557         udelay(100);
 558         if (ret)
 559                 goto set_spa;
 560
 561         /* 2. update SCF to select a properly audio clock*/
 562         val &= ~ML_LCTL_SCF_MASK;
 563         val |= intel_get_lctl_scf(chip);
 564         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 565
 566 set_spa:
 567         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 568         intel_ml_lctl_set_power(chip, 1);
 569         udelay(100);
 570 }
 571
 572 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 573 {
 574         struct hdac_bus *bus = azx_bus(chip);
 575         struct pci_dev *pci = chip->pci;
 576         u32 val;
 577
 578         snd_hdac_set_codec_wakeup(bus, true);
 579         if (chip->driver_type == AZX_DRIVER_SKL) {
 580                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 581                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 582                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 583         }
 584         azx_init_chip(chip, full_reset);
 585         if (chip->driver_type == AZX_DRIVER_SKL) {
 586                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 587                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 588                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 589         }
 590
 591         snd_hdac_set_codec_wakeup(bus, false);
 592
 593         /* reduce dma latency to avoid noise */
 594         if (IS_BXT(pci))
 595                 bxt_reduce_dma_latency(chip);
 596
 597         if (bus->mlcap != NULL)
 598                 intel_init_lctl(chip);
 599 }
 600
 601 /* calculate runtime delay from LPIB */
 602 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 603                                    unsigned int pos)
 604 {
 605         struct snd_pcm_substream *substream = azx_dev->core.substream;
 606         int stream = substream->stream;
 607         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 608         int delay;
 609
 610         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 611                 delay = pos - lpib_pos;
 612         else
 613                 delay = lpib_pos - pos;
 614         if (delay < 0) {
 615                 if (delay >= azx_dev->core.delay_negative_threshold)
 616                         delay = 0;
 617                 else
 618                         delay += azx_dev->core.bufsize;
 619         }
 620
 621         if (delay >= azx_dev->core.period_bytes) {
 622                 dev_info(chip->card->dev,
 623                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 624                          delay, azx_dev->core.period_bytes);
 625                 delay = 0;
 626                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 627                 chip->get_delay[stream] = NULL;
 628         }
 629
 630         return bytes_to_frames(substream->runtime, delay);
 631 }
 632
 633 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 634
 635 /* called from IRQ */
 636 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 637 {
 638         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 639         int ok;
 640
 641         ok = azx_position_ok(chip, azx_dev);
 642         if (ok == 1) {
 643                 azx_dev->irq_pending = 0;
 644                 return ok;
 645         } else if (ok == 0) {
 646                 /* bogus IRQ, process it later */
 647                 azx_dev->irq_pending = 1;
 648                 schedule_work(&hda->irq_pending_work);
 649         }
 650         return 0;
 651 }
 652
 653 #define display_power(chip, enable) \
 654         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 655
 656 /*
 657  * Check whether the current DMA position is acceptable for updating
 658  * periods.  Returns non-zero if it's OK.
 659  *
 660  * Many HD-audio controllers appear pretty inaccurate about
 661  * the update-IRQ timing.  The IRQ is issued before actually the
 662  * data is processed.  So, we need to process it afterwords in a
 663  * workqueue.
 664  */
 665 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 666 {
 667         struct snd_pcm_substream *substream = azx_dev->core.substream;
 668         int stream = substream->stream;
 669         u32 wallclk;
 670         unsigned int pos;
 671
 672         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 673         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 674                 return -1;      /* bogus (too early) interrupt */
 675
 676         if (chip->get_position[stream])
 677                 pos = chip->get_position[stream](chip, azx_dev);
 678         else { /* use the position buffer as default */
 679                 pos = azx_get_pos_posbuf(chip, azx_dev);
 680                 if (!pos || pos == (u32)-1) {
 681                         dev_info(chip->card->dev,
 682                                  "Invalid position buffer, using LPIB read method instead.\n");
 683                         chip->get_position[stream] = azx_get_pos_lpib;
 684                         if (chip->get_position[0] == azx_get_pos_lpib &&
 685                             chip->get_position[1] == azx_get_pos_lpib)
 686                                 azx_bus(chip)->use_posbuf = false;
 687                         pos = azx_get_pos_lpib(chip, azx_dev);
 688                         chip->get_delay[stream] = NULL;
 689                 } else {
 690                         chip->get_position[stream] = azx_get_pos_posbuf;
 691                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 692                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 693                 }
 694         }
 695
 696         if (pos >= azx_dev->core.bufsize)
 697                 pos = 0;
 698
 699         if (WARN_ONCE(!azx_dev->core.period_bytes,
 700                       "hda-intel: zero azx_dev->period_bytes"))
 701                 return -1; /* this shouldn't happen! */
 702         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 703             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 704                 /* NG - it's below the first next period boundary */
 705                 return chip->bdl_pos_adj ? 0 : -1;
 706         azx_dev->core.start_wallclk += wallclk;
 707         return 1; /* OK, it's fine */
 708 }
 709
 710 /*
 711  * The work for pending PCM period updates.
 712  */
 713 static void azx_irq_pending_work(struct work_struct *work)
 714 {
 715         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 716         struct azx *chip = &hda->chip;
 717         struct hdac_bus *bus = azx_bus(chip);
 718         struct hdac_stream *s;
 719         int pending, ok;
 720
 721         if (!hda->irq_pending_warned) {
 722                 dev_info(chip->card->dev,
 723                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 724                          chip->card->number);
 725                 hda->irq_pending_warned = 1;
 726         }
 727
 728         for (;;) {
 729                 pending = 0;
 730                 spin_lock_irq(&bus->reg_lock);
 731                 list_for_each_entry(s, &bus->stream_list, list) {
 732                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 733                         if (!azx_dev->irq_pending ||
 734                             !s->substream ||
 735                             !s->running)
 736                                 continue;
 737                         ok = azx_position_ok(chip, azx_dev);
 738                         if (ok > 0) {
 739                                 azx_dev->irq_pending = 0;
 740                                 spin_unlock(&bus->reg_lock);
 741                                 snd_pcm_period_elapsed(s->substream);
 742                                 spin_lock(&bus->reg_lock);
 743                         } else if (ok < 0) {
 744                                 pending = 0;    /* too early */
 745                         } else
 746                                 pending++;
 747                 }
 748                 spin_unlock_irq(&bus->reg_lock);
 749                 if (!pending)
 750                         return;
 751                 msleep(1);
 752         }
 753 }
 754
 755 /* clear irq_pending flags and assure no on-going workq */
 756 static void azx_clear_irq_pending(struct azx *chip)
 757 {
 758         struct hdac_bus *bus = azx_bus(chip);
 759         struct hdac_stream *s;
 760
 761         spin_lock_irq(&bus->reg_lock);
 762         list_for_each_entry(s, &bus->stream_list, list) {
 763                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 764                 azx_dev->irq_pending = 0;
 765         }
 766         spin_unlock_irq(&bus->reg_lock);
 767 }
 768
 769 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 770 {
 771         struct hdac_bus *bus = azx_bus(chip);
 772
 773         if (request_irq(chip->pci->irq, azx_interrupt,
 774                         chip->msi ? 0 : IRQF_SHARED,
 775                         chip->card->irq_descr, chip)) {
 776                 dev_err(chip->card->dev,
 777                         "unable to grab IRQ %d, disabling device\n",
 778                         chip->pci->irq);
 779                 if (do_disconnect)
 780                         snd_card_disconnect(chip->card);
 781                 return -1;
 782         }
 783         bus->irq = chip->pci->irq;
 784         pci_intx(chip->pci, !chip->msi);
 785         return 0;
 786 }
 787
 788 /* get the current DMA position with correction on VIA chips */
 789 static unsigned int azx_via_get_position(struct azx *chip,
 790                                          struct azx_dev *azx_dev)
 791 {
 792         unsigned int link_pos, mini_pos, bound_pos;
 793         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 794         unsigned int fifo_size;
 795
 796         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 797         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 798                 /* Playback, no problem using link position */
 799                 return link_pos;
 800         }
 801
 802         /* Capture */
 803         /* For new chipset,
 804          * use mod to get the DMA position just like old chipset
 805          */
 806         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 807         mod_dma_pos %= azx_dev->core.period_bytes;
 808
 809         /* azx_dev->fifo_size can't get FIFO size of in stream.
 810          * Get from base address + offset.
 811          */
 812         fifo_size = readw(azx_bus(chip)->remap_addr +
 813                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 814
 815         if (azx_dev->insufficient) {
 816                 /* Link position never gather than FIFO size */
 817                 if (link_pos <= fifo_size)
 818                         return 0;
 819
 820                 azx_dev->insufficient = 0;
 821         }
 822
 823         if (link_pos <= fifo_size)
 824                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 825         else
 826                 mini_pos = link_pos - fifo_size;
 827
 828         /* Find nearest previous boudary */
 829         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 830         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 831         if (mod_link_pos >= fifo_size)
 832                 bound_pos = link_pos - mod_link_pos;
 833         else if (mod_dma_pos >= mod_mini_pos)
 834                 bound_pos = mini_pos - mod_mini_pos;
 835         else {
 836                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 837                 if (bound_pos >= azx_dev->core.bufsize)
 838                         bound_pos = 0;
 839         }
 840
 841         /* Calculate real DMA position we want */
 842         return bound_pos + mod_dma_pos;
 843 }
 844
 845 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 846                                          struct azx_dev *azx_dev)
 847 {
 848         return _snd_hdac_chip_readl(azx_bus(chip),
 849                                     AZX_REG_VS_SDXDPIB_XBASE +
 850                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 851                                      azx_dev->core.index));
 852 }
 853
 854 /* get the current DMA position with correction on SKL+ chips */
 855 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 856 {
 857         /* DPIB register gives a more accurate position for playback */
 858         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 859                 return azx_skl_get_dpib_pos(chip, azx_dev);
 860
 861         /* For capture, we need to read posbuf, but it requires a delay
 862          * for the possible boundary overlap; the read of DPIB fetches the
 863          * actual posbuf
 864          */
 865         udelay(20);
 866         azx_skl_get_dpib_pos(chip, azx_dev);
 867         return azx_get_pos_posbuf(chip, azx_dev);
 868 }
 869
 870 #ifdef CONFIG_PM
 871 static DEFINE_MUTEX(card_list_lock);
 872 static LIST_HEAD(card_list);
 873
 874 static void azx_add_card_list(struct azx *chip)
 875 {
 876         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 877         mutex_lock(&card_list_lock);
 878         list_add(&hda->list, &card_list);
 879         mutex_unlock(&card_list_lock);
 880 }
 881
 882 static void azx_del_card_list(struct azx *chip)
 883 {
 884         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 885         mutex_lock(&card_list_lock);
 886         list_del_init(&hda->list);
 887         mutex_unlock(&card_list_lock);
 888 }
 889
 890 /* trigger power-save check at writing parameter */
 891 static int param_set_xint(const char *val, const struct kernel_param *kp)
 892 {
 893         struct hda_intel *hda;
 894         struct azx *chip;
 895         int prev = power_save;
 896         int ret = param_set_int(val, kp);
 897
 898         if (ret || prev == power_save)
 899                 return ret;
 900
 901         mutex_lock(&card_list_lock);
 902         list_for_each_entry(hda, &card_list, list) {
 903                 chip = &hda->chip;
 904                 if (!hda->probe_continued || chip->disabled)
 905                         continue;
 906                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 907         }
 908         mutex_unlock(&card_list_lock);
 909         return 0;
 910 }
 911
 912 /*
 913  * power management
 914  */
 915 static bool azx_is_pm_ready(struct snd_card *card)
 916 {
 917         struct azx *chip;
 918         struct hda_intel *hda;
 919
 920         if (!card)
 921                 return false;
 922         chip = card->private_data;
 923         hda = container_of(chip, struct hda_intel, chip);
 924         if (chip->disabled || hda->init_failed || !chip->running)
 925                 return false;
 926         return true;
 927 }
 928
 929 static void __azx_runtime_suspend(struct azx *chip)
 930 {
 931         azx_stop_chip(chip);
 932         azx_enter_link_reset(chip);
 933         azx_clear_irq_pending(chip);
 934         display_power(chip, false);
 935 }
 936
 937 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 938 {
 939         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 940         struct hdac_bus *bus = azx_bus(chip);
 941         struct hda_codec *codec;
 942         int status;
 943
 944         display_power(chip, true);
 945         if (hda->need_i915_power)
 946                 snd_hdac_i915_set_bclk(bus);
 947
 948         /* Read STATESTS before controller reset */
 949         status = azx_readw(chip, STATESTS);
 950
 951         azx_init_pci(chip);
 952         hda_intel_init_chip(chip, true);
 953
 954         if (status && from_rt) {
 955                 list_for_each_codec(codec, &chip->bus)
 956                         if (status & (1 << codec->addr))
 957                                 schedule_delayed_work(&codec->jackpoll_work,
 958                                                       codec->jackpoll_interval);
 959         }
 960
 961         /* power down again for link-controlled chips */
 962         if (!hda->need_i915_power)
 963                 display_power(chip, false);
 964 }
 965
 966 #ifdef CONFIG_PM_SLEEP
 967 static int azx_suspend(struct device *dev)
 968 {
 969         struct snd_card *card = dev_get_drvdata(dev);
 970         struct azx *chip;
 971         struct hdac_bus *bus;
 972
 973         if (!azx_is_pm_ready(card))
 974                 return 0;
 975
 976         chip = card->private_data;
 977         bus = azx_bus(chip);
 978         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 979         __azx_runtime_suspend(chip);
 980         if (bus->irq >= 0) {
 981                 free_irq(bus->irq, chip);
 982                 bus->irq = -1;
 983         }
 984
 985         if (chip->msi)
 986                 pci_disable_msi(chip->pci);
 987
 988         trace_azx_suspend(chip);
 989         return 0;
 990 }
 991
 992 static int azx_resume(struct device *dev)
 993 {
 994         struct snd_card *card = dev_get_drvdata(dev);
 995         struct azx *chip;
 996
 997         if (!azx_is_pm_ready(card))
 998                 return 0;
 999
1000         chip = card->private_data;
1001         if (chip->msi)
1002                 if (pci_enable_msi(chip->pci) < 0)
1003                         chip->msi = 0;
1004         if (azx_acquire_irq(chip, 1) < 0)
1005                 return -EIO;
1006         __azx_runtime_resume(chip, false);
1007         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1008
1009         trace_azx_resume(chip);
1010         return 0;
1011 }
1012
1013 /* put codec down to D3 at hibernation for Intel SKL+;
1014  * otherwise BIOS may still access the codec and screw up the driver
1015  */
1016 static int azx_freeze_noirq(struct device *dev)
1017 {
1018         struct snd_card *card = dev_get_drvdata(dev);
1019         struct azx *chip = card->private_data;
1020         struct pci_dev *pci = to_pci_dev(dev);
1021
1022         if (chip->driver_type == AZX_DRIVER_SKL)
1023                 pci_set_power_state(pci, PCI_D3hot);
1024
1025         return 0;
1026 }
1027
1028 static int azx_thaw_noirq(struct device *dev)
1029 {
1030         struct snd_card *card = dev_get_drvdata(dev);
1031         struct azx *chip = card->private_data;
1032         struct pci_dev *pci = to_pci_dev(dev);
1033
1034         if (chip->driver_type == AZX_DRIVER_SKL)
1035                 pci_set_power_state(pci, PCI_D0);
1036
1037         return 0;
1038 }
1039 #endif /* CONFIG_PM_SLEEP */
1040
1041 static int azx_runtime_suspend(struct device *dev)
1042 {
1043         struct snd_card *card = dev_get_drvdata(dev);
1044         struct azx *chip;
1045
1046         if (!azx_is_pm_ready(card))
1047                 return 0;
1048         chip = card->private_data;
1049         if (!azx_has_pm_runtime(chip))
1050                 return 0;
1051
1052         /* enable controller wake up event */
1053         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1054                   STATESTS_INT_MASK);
1055
1056         __azx_runtime_suspend(chip);
1057         trace_azx_runtime_suspend(chip);
1058         return 0;
1059 }
1060
1061 static int azx_runtime_resume(struct device *dev)
1062 {
1063         struct snd_card *card = dev_get_drvdata(dev);
1064         struct azx *chip;
1065
1066         if (!azx_is_pm_ready(card))
1067                 return 0;
1068         chip = card->private_data;
1069         if (!azx_has_pm_runtime(chip))
1070                 return 0;
1071         __azx_runtime_resume(chip, true);
1072
1073         /* disable controller Wake Up event*/
1074         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1075                         ~STATESTS_INT_MASK);
1076
1077         trace_azx_runtime_resume(chip);
1078         return 0;
1079 }
1080
1081 static int azx_runtime_idle(struct device *dev)
1082 {
1083         struct snd_card *card = dev_get_drvdata(dev);
1084         struct azx *chip;
1085         struct hda_intel *hda;
1086
1087         if (!card)
1088                 return 0;
1089
1090         chip = card->private_data;
1091         hda = container_of(chip, struct hda_intel, chip);
1092         if (chip->disabled || hda->init_failed)
1093                 return 0;
1094
1095         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1096             azx_bus(chip)->codec_powered || !chip->running)
1097                 return -EBUSY;
1098
1099         /* ELD notification gets broken when HD-audio bus is off */
1100         if (needs_eld_notify_link(hda))
1101                 return -EBUSY;
1102
1103         return 0;
1104 }
1105
1106 static const struct dev_pm_ops azx_pm = {
1107         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1108 #ifdef CONFIG_PM_SLEEP
1109         .freeze_noirq = azx_freeze_noirq,
1110         .thaw_noirq = azx_thaw_noirq,
1111 #endif
1112         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1113 };
1114
1115 #define AZX_PM_OPS      &azx_pm
1116 #else
1117 #define azx_add_card_list(chip) /* NOP */
1118 #define azx_del_card_list(chip) /* NOP */
1119 #define AZX_PM_OPS      NULL
1120 #endif /* CONFIG_PM */
1121
1122
1123 static int azx_probe_continue(struct azx *chip);
1124
1125 #ifdef SUPPORT_VGA_SWITCHEROO
1126 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1127
1128 static void azx_vs_set_state(struct pci_dev *pci,
1129                              enum vga_switcheroo_state state)
1130 {
1131         struct snd_card *card = pci_get_drvdata(pci);
1132         struct azx *chip = card->private_data;
1133         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1134         struct hda_codec *codec;
1135         bool disabled;
1136
1137         wait_for_completion(&hda->probe_wait);
1138         if (hda->init_failed)
1139                 return;
1140
1141         disabled = (state == VGA_SWITCHEROO_OFF);
1142         if (chip->disabled == disabled)
1143                 return;
1144
1145         if (!hda->probe_continued) {
1146                 chip->disabled = disabled;
1147                 if (!disabled) {
1148                         dev_info(chip->card->dev,
1149                                  "Start delayed initialization\n");
1150                         if (azx_probe_continue(chip) < 0) {
1151                                 dev_err(chip->card->dev, "initialization error\n");
1152                                 hda->init_failed = true;
1153                         }
1154                 }
1155         } else {
1156                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1157                          disabled ? "Disabling" : "Enabling");
1158                 if (disabled) {
1159                         list_for_each_codec(codec, &chip->bus) {
1160                                 pm_runtime_suspend(hda_codec_dev(codec));
1161                                 pm_runtime_disable(hda_codec_dev(codec));
1162                         }
1163                         pm_runtime_suspend(card->dev);
1164                         pm_runtime_disable(card->dev);
1165                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1166                          * however we have no ACPI handle, so pci/acpi can't put us there,
1167                          * put ourselves there */
1168                         pci->current_state = PCI_D3cold;
1169                         chip->disabled = true;
1170                         if (snd_hda_lock_devices(&chip->bus))
1171                                 dev_warn(chip->card->dev,
1172                                          "Cannot lock devices!\n");
1173                 } else {
1174                         snd_hda_unlock_devices(&chip->bus);
1175                         chip->disabled = false;
1176                         pm_runtime_enable(card->dev);
1177                         list_for_each_codec(codec, &chip->bus) {
1178                                 pm_runtime_enable(hda_codec_dev(codec));
1179                                 pm_runtime_resume(hda_codec_dev(codec));
1180                         }
1181                 }
1182         }
1183 }
1184
1185 static bool azx_vs_can_switch(struct pci_dev *pci)
1186 {
1187         struct snd_card *card = pci_get_drvdata(pci);
1188         struct azx *chip = card->private_data;
1189         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1190
1191         wait_for_completion(&hda->probe_wait);
1192         if (hda->init_failed)
1193                 return false;
1194         if (chip->disabled || !hda->probe_continued)
1195                 return true;
1196         if (snd_hda_lock_devices(&chip->bus))
1197                 return false;
1198         snd_hda_unlock_devices(&chip->bus);
1199         return true;
1200 }
1201
1202 /*
1203  * The discrete GPU cannot power down unless the HDA controller runtime
1204  * suspends, so activate runtime PM on codecs even if power_save == 0.
1205  */
1206 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1207 {
1208         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1209         struct hda_codec *codec;
1210
1211         if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1212                 list_for_each_codec(codec, &chip->bus)
1213                         codec->auto_runtime_pm = 1;
1214                 /* reset the power save setup */
1215                 if (chip->running)
1216                         set_default_power_save(chip);
1217         }
1218 }
1219
1220 static void azx_vs_gpu_bound(struct pci_dev *pci,
1221                              enum vga_switcheroo_client_id client_id)
1222 {
1223         struct snd_card *card = pci_get_drvdata(pci);
1224         struct azx *chip = card->private_data;
1225         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1226
1227         if (client_id == VGA_SWITCHEROO_DIS)
1228                 hda->need_eld_notify_link = 0;
1229         setup_vga_switcheroo_runtime_pm(chip);
1230 }
1231
1232 static void init_vga_switcheroo(struct azx *chip)
1233 {
1234         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1235         struct pci_dev *p = get_bound_vga(chip->pci);
1236         if (p) {
1237                 dev_info(chip->card->dev,
1238                          "Handle vga_switcheroo audio client\n");
1239                 hda->use_vga_switcheroo = 1;
1240                 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
1241                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1242                 pci_dev_put(p);
1243         }
1244 }
1245
1246 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1247         .set_gpu_state = azx_vs_set_state,
1248         .can_switch = azx_vs_can_switch,
1249         .gpu_bound = azx_vs_gpu_bound,
1250 };
1251
1252 static int register_vga_switcheroo(struct azx *chip)
1253 {
1254         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1255         struct pci_dev *p;
1256         int err;
1257
1258         if (!hda->use_vga_switcheroo)
1259                 return 0;
1260
1261         p = get_bound_vga(chip->pci);
1262         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1263         pci_dev_put(p);
1264
1265         if (err < 0)
1266                 return err;
1267         hda->vga_switcheroo_registered = 1;
1268
1269         return 0;
1270 }
1271 #else
1272 #define init_vga_switcheroo(chip)               /* NOP */
1273 #define register_vga_switcheroo(chip)           0
1274 #define check_hdmi_disabled(pci)        false
1275 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1276 #endif /* SUPPORT_VGA_SWITCHER */
1277
1278 /*
1279  * destructor
1280  */
1281 static int azx_free(struct azx *chip)
1282 {
1283         struct pci_dev *pci = chip->pci;
1284         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1285         struct hdac_bus *bus = azx_bus(chip);
1286
1287         if (azx_has_pm_runtime(chip) && chip->running)
1288                 pm_runtime_get_noresume(&pci->dev);
1289         chip->running = 0;
1290
1291         azx_del_card_list(chip);
1292
1293         hda->init_failed = 1; /* to be sure */
1294         complete_all(&hda->probe_wait);
1295
1296         if (use_vga_switcheroo(hda)) {
1297                 if (chip->disabled && hda->probe_continued)
1298                         snd_hda_unlock_devices(&chip->bus);
1299                 if (hda->vga_switcheroo_registered)
1300                         vga_switcheroo_unregister_client(chip->pci);
1301         }
1302
1303         if (bus->chip_init) {
1304                 azx_clear_irq_pending(chip);
1305                 azx_stop_all_streams(chip);
1306                 azx_stop_chip(chip);
1307         }
1308
1309         if (bus->irq >= 0)
1310                 free_irq(bus->irq, (void*)chip);
1311         if (chip->msi)
1312                 pci_disable_msi(chip->pci);
1313         iounmap(bus->remap_addr);
1314
1315         azx_free_stream_pages(chip);
1316         azx_free_streams(chip);
1317         snd_hdac_bus_exit(bus);
1318
1319         if (chip->region_requested)
1320                 pci_release_regions(chip->pci);
1321
1322         pci_disable_device(chip->pci);
1323 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1324         release_firmware(chip->fw);
1325 #endif
1326         display_power(chip, false);
1327
1328         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1329                 snd_hdac_i915_exit(bus);
1330         kfree(hda);
1331
1332         return 0;
1333 }
1334
1335 static int azx_dev_disconnect(struct snd_device *device)
1336 {
1337         struct azx *chip = device->device_data;
1338
1339         chip->bus.shutdown = 1;
1340         return 0;
1341 }
1342
1343 static int azx_dev_free(struct snd_device *device)
1344 {
1345         return azx_free(device->device_data);
1346 }
1347
1348 #ifdef SUPPORT_VGA_SWITCHEROO
1349 /*
1350  * Check of disabled HDMI controller by vga_switcheroo
1351  */
1352 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1353 {
1354         struct pci_dev *p;
1355
1356         /* check only discrete GPU */
1357         switch (pci->vendor) {
1358         case PCI_VENDOR_ID_ATI:
1359         case PCI_VENDOR_ID_AMD:
1360         case PCI_VENDOR_ID_NVIDIA:
1361                 if (pci->devfn == 1) {
1362                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1363                                                         pci->bus->number, 0);
1364                         if (p) {
1365                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1366                                         return p;
1367                                 pci_dev_put(p);
1368                         }
1369                 }
1370                 break;
1371         }
1372         return NULL;
1373 }
1374
1375 static bool check_hdmi_disabled(struct pci_dev *pci)
1376 {
1377         bool vga_inactive = false;
1378         struct pci_dev *p = get_bound_vga(pci);
1379
1380         if (p) {
1381                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1382                         vga_inactive = true;
1383                 pci_dev_put(p);
1384         }
1385         return vga_inactive;
1386 }
1387 #endif /* SUPPORT_VGA_SWITCHEROO */
1388
1389 /*
1390  * white/black-listing for position_fix
1391  */
1392 static struct snd_pci_quirk position_fix_list[] = {
1393         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1394         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1395         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1396         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1397         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1398         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1399         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1400         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1401         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1402         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1403         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1404         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1405         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1406         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1407         {}
1408 };
1409
1410 static int check_position_fix(struct azx *chip, int fix)
1411 {
1412         const struct snd_pci_quirk *q;
1413
1414         switch (fix) {
1415         case POS_FIX_AUTO:
1416         case POS_FIX_LPIB:
1417         case POS_FIX_POSBUF:
1418         case POS_FIX_VIACOMBO:
1419         case POS_FIX_COMBO:
1420         case POS_FIX_SKL:
1421                 return fix;
1422         }
1423
1424         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1425         if (q) {
1426                 dev_info(chip->card->dev,
1427                          "position_fix set to %d for device %04x:%04x\n",
1428                          q->value, q->subvendor, q->subdevice);
1429                 return q->value;
1430         }
1431
1432         /* Check VIA/ATI HD Audio Controller exist */
1433         if (chip->driver_type == AZX_DRIVER_VIA) {
1434                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1435                 return POS_FIX_VIACOMBO;
1436         }
1437         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1438                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1439                 return POS_FIX_LPIB;
1440         }
1441         if (chip->driver_type == AZX_DRIVER_SKL) {
1442                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1443                 return POS_FIX_SKL;
1444         }
1445         return POS_FIX_AUTO;
1446 }
1447
1448 static void assign_position_fix(struct azx *chip, int fix)
1449 {
1450         static azx_get_pos_callback_t callbacks[] = {
1451                 [POS_FIX_AUTO] = NULL,
1452                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1453                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1454                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1455                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1456                 [POS_FIX_SKL] = azx_get_pos_skl,
1457         };
1458
1459         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1460
1461         /* combo mode uses LPIB only for playback */
1462         if (fix == POS_FIX_COMBO)
1463                 chip->get_position[1] = NULL;
1464
1465         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1466             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1467                 chip->get_delay[0] = chip->get_delay[1] =
1468                         azx_get_delay_from_lpib;
1469         }
1470
1471 }
1472
1473 /*
1474  * black-lists for probe_mask
1475  */
1476 static struct snd_pci_quirk probe_mask_list[] = {
1477         /* Thinkpad often breaks the controller communication when accessing
1478          * to the non-working (or non-existing) modem codec slot.
1479          */
1480         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1481         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1482         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1483         /* broken BIOS */
1484         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1485         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1486         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1487         /* forced codec slots */
1488         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1489         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1490         /* WinFast VP200 H (Teradici) user reported broken communication */
1491         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1492         {}
1493 };
1494
1495 #define AZX_FORCE_CODEC_MASK    0x100
1496
1497 static void check_probe_mask(struct azx *chip, int dev)
1498 {
1499         const struct snd_pci_quirk *q;
1500
1501         chip->codec_probe_mask = probe_mask[dev];
1502         if (chip->codec_probe_mask == -1) {
1503                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1504                 if (q) {
1505                         dev_info(chip->card->dev,
1506                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1507                                  q->value, q->subvendor, q->subdevice);
1508                         chip->codec_probe_mask = q->value;
1509                 }
1510         }
1511
1512         /* check forced option */
1513         if (chip->codec_probe_mask != -1 &&
1514             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1515                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1516                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1517                          (int)azx_bus(chip)->codec_mask);
1518         }
1519 }
1520
1521 /*
1522  * white/black-list for enable_msi
1523  */
1524 static struct snd_pci_quirk msi_black_list[] = {
1525         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1526         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1527         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1528         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1529         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1530         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1531         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1532         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1533         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1534         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1535         {}
1536 };
1537
1538 static void check_msi(struct azx *chip)
1539 {
1540         const struct snd_pci_quirk *q;
1541
1542         if (enable_msi >= 0) {
1543                 chip->msi = !!enable_msi;
1544                 return;
1545         }
1546         chip->msi = 1;  /* enable MSI as default */
1547         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1548         if (q) {
1549                 dev_info(chip->card->dev,
1550                          "msi for device %04x:%04x set to %d\n",
1551                          q->subvendor, q->subdevice, q->value);
1552                 chip->msi = q->value;
1553                 return;
1554         }
1555
1556         /* NVidia chipsets seem to cause troubles with MSI */
1557         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1558                 dev_info(chip->card->dev, "Disabling MSI\n");
1559                 chip->msi = 0;
1560         }
1561 }
1562
1563 /* check the snoop mode availability */
1564 static void azx_check_snoop_available(struct azx *chip)
1565 {
1566         int snoop = hda_snoop;
1567
1568         if (snoop >= 0) {
1569                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1570                          snoop ? "snoop" : "non-snoop");
1571                 chip->snoop = snoop;
1572                 chip->uc_buffer = !snoop;
1573                 return;
1574         }
1575
1576         snoop = true;
1577         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1578             chip->driver_type == AZX_DRIVER_VIA) {
1579                 /* force to non-snoop mode for a new VIA controller
1580                  * when BIOS is set
1581                  */
1582                 u8 val;
1583                 pci_read_config_byte(chip->pci, 0x42, &val);
1584                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1585                                       chip->pci->revision == 0x20))
1586                         snoop = false;
1587         }
1588
1589         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1590                 snoop = false;
1591
1592         chip->snoop = snoop;
1593         if (!snoop) {
1594                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1595                 /* C-Media requires non-cached pages only for CORB/RIRB */
1596                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1597                         chip->uc_buffer = true;
1598         }
1599 }
1600
1601 static void azx_probe_work(struct work_struct *work)
1602 {
1603         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1604         azx_probe_continue(&hda->chip);
1605 }
1606
1607 static int default_bdl_pos_adj(struct azx *chip)
1608 {
1609         /* some exceptions: Atoms seem problematic with value 1 */
1610         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1611                 switch (chip->pci->device) {
1612                 case 0x0f04: /* Baytrail */
1613                 case 0x2284: /* Braswell */
1614                         return 32;
1615                 }
1616         }
1617
1618         switch (chip->driver_type) {
1619         case AZX_DRIVER_ICH:
1620         case AZX_DRIVER_PCH:
1621                 return 1;
1622         default:
1623                 return 32;
1624         }
1625 }
1626
1627 /*
1628  * constructor
1629  */
1630 static const struct hdac_io_ops pci_hda_io_ops;
1631 static const struct hda_controller_ops pci_hda_ops;
1632
1633 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1634                       int dev, unsigned int driver_caps,
1635                       struct azx **rchip)
1636 {
1637         static struct snd_device_ops ops = {
1638                 .dev_disconnect = azx_dev_disconnect,
1639                 .dev_free = azx_dev_free,
1640         };
1641         struct hda_intel *hda;
1642         struct azx *chip;
1643         int err;
1644
1645         *rchip = NULL;
1646
1647         err = pci_enable_device(pci);
1648         if (err < 0)
1649                 return err;
1650
1651         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1652         if (!hda) {
1653                 pci_disable_device(pci);
1654                 return -ENOMEM;
1655         }
1656
1657         chip = &hda->chip;
1658         mutex_init(&chip->open_mutex);
1659         chip->card = card;
1660         chip->pci = pci;
1661         chip->ops = &pci_hda_ops;
1662         chip->driver_caps = driver_caps;
1663         chip->driver_type = driver_caps & 0xff;
1664         check_msi(chip);
1665         chip->dev_index = dev;
1666         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1667                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1668         INIT_LIST_HEAD(&chip->pcm_list);
1669         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1670         INIT_LIST_HEAD(&hda->list);
1671         init_vga_switcheroo(chip);
1672         init_completion(&hda->probe_wait);
1673
1674         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1675
1676         check_probe_mask(chip, dev);
1677
1678         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1679                 chip->fallback_to_single_cmd = 1;
1680         else /* explicitly set to single_cmd or not */
1681                 chip->single_cmd = single_cmd;
1682
1683         azx_check_snoop_available(chip);
1684
1685         if (bdl_pos_adj[dev] < 0)
1686                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1687         else
1688                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1689
1690         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1691         if (err < 0) {
1692                 kfree(hda);
1693                 pci_disable_device(pci);
1694                 return err;
1695         }
1696
1697         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1698         if (IS_CFL(pci) || IS_CNL(pci))
1699                 azx_bus(chip)->polling_mode = 1;
1700
1701         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1702                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1703                 chip->bus.needs_damn_long_delay = 1;
1704         }
1705
1706         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1707         if (err < 0) {
1708                 dev_err(card->dev, "Error creating device [card]!\n");
1709                 azx_free(chip);
1710                 return err;
1711         }
1712
1713         /* continue probing in work context as may trigger request module */
1714         INIT_WORK(&hda->probe_work, azx_probe_work);
1715
1716         *rchip = chip;
1717
1718         return 0;
1719 }
1720
1721 static int azx_first_init(struct azx *chip)
1722 {
1723         int dev = chip->dev_index;
1724         struct pci_dev *pci = chip->pci;
1725         struct snd_card *card = chip->card;
1726         struct hdac_bus *bus = azx_bus(chip);
1727         int err;
1728         unsigned short gcap;
1729         unsigned int dma_bits = 64;
1730
1731 #if BITS_PER_LONG != 64
1732         /* Fix up base address on ULI M5461 */
1733         if (chip->driver_type == AZX_DRIVER_ULI) {
1734                 u16 tmp3;
1735                 pci_read_config_word(pci, 0x40, &tmp3);
1736                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1737                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1738         }
1739 #endif
1740
1741         err = pci_request_regions(pci, "ICH HD audio");
1742         if (err < 0)
1743                 return err;
1744         chip->region_requested = 1;
1745
1746         bus->addr = pci_resource_start(pci, 0);
1747         bus->remap_addr = pci_ioremap_bar(pci, 0);
1748         if (bus->remap_addr == NULL) {
1749                 dev_err(card->dev, "ioremap error\n");
1750                 return -ENXIO;
1751         }
1752
1753         if (chip->driver_type == AZX_DRIVER_SKL)
1754                 snd_hdac_bus_parse_capabilities(bus);
1755
1756         /*
1757          * Some Intel CPUs has always running timer (ART) feature and
1758          * controller may have Global time sync reporting capability, so
1759          * check both of these before declaring synchronized time reporting
1760          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1761          */
1762         chip->gts_present = false;
1763
1764 #ifdef CONFIG_X86
1765         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1766                 chip->gts_present = true;
1767 #endif
1768
1769         if (chip->msi) {
1770                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1771                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1772                         pci->no_64bit_msi = true;
1773                 }
1774                 if (pci_enable_msi(pci) < 0)
1775                         chip->msi = 0;
1776         }
1777
1778         pci_set_master(pci);
1779         synchronize_irq(bus->irq);
1780
1781         gcap = azx_readw(chip, GCAP);
1782         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1783
1784         /* AMD devices support 40 or 48bit DMA, take the safe one */
1785         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1786                 dma_bits = 40;
1787
1788         /* disable SB600 64bit support for safety */
1789         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1790                 struct pci_dev *p_smbus;
1791                 dma_bits = 40;
1792                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1793                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1794                                          NULL);
1795                 if (p_smbus) {
1796                         if (p_smbus->revision < 0x30)
1797                                 gcap &= ~AZX_GCAP_64OK;
1798                         pci_dev_put(p_smbus);
1799                 }
1800         }
1801
1802         /* NVidia hardware normally only supports up to 40 bits of DMA */
1803         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1804                 dma_bits = 40;
1805
1806         /* disable 64bit DMA address on some devices */
1807         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1808                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1809                 gcap &= ~AZX_GCAP_64OK;
1810         }
1811
1812         /* disable buffer size rounding to 128-byte multiples if supported */
1813         if (align_buffer_size >= 0)
1814                 chip->align_buffer_size = !!align_buffer_size;
1815         else {
1816                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1817                         chip->align_buffer_size = 0;
1818                 else
1819                         chip->align_buffer_size = 1;
1820         }
1821
1822         /* allow 64bit DMA address if supported by H/W */
1823         if (!(gcap & AZX_GCAP_64OK))
1824                 dma_bits = 32;
1825         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1826                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1827         } else {
1828                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1829                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1830         }
1831
1832         /* read number of streams from GCAP register instead of using
1833          * hardcoded value
1834          */
1835         chip->capture_streams = (gcap >> 8) & 0x0f;
1836         chip->playback_streams = (gcap >> 12) & 0x0f;
1837         if (!chip->playback_streams && !chip->capture_streams) {
1838                 /* gcap didn't give any info, switching to old method */
1839
1840                 switch (chip->driver_type) {
1841                 case AZX_DRIVER_ULI:
1842                         chip->playback_streams = ULI_NUM_PLAYBACK;
1843                         chip->capture_streams = ULI_NUM_CAPTURE;
1844                         break;
1845                 case AZX_DRIVER_ATIHDMI:
1846                 case AZX_DRIVER_ATIHDMI_NS:
1847                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1848                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1849                         break;
1850                 case AZX_DRIVER_GENERIC:
1851                 default:
1852                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1853                         chip->capture_streams = ICH6_NUM_CAPTURE;
1854                         break;
1855                 }
1856         }
1857         chip->capture_index_offset = 0;
1858         chip->playback_index_offset = chip->capture_streams;
1859         chip->num_streams = chip->playback_streams + chip->capture_streams;
1860
1861         /* sanity check for the SDxCTL.STRM field overflow */
1862         if (chip->num_streams > 15 &&
1863             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1864                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1865                          "forcing separate stream tags", chip->num_streams);
1866                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1867         }
1868
1869         /* initialize streams */
1870         err = azx_init_streams(chip);
1871         if (err < 0)
1872                 return err;
1873
1874         err = azx_alloc_stream_pages(chip);
1875         if (err < 0)
1876                 return err;
1877
1878         /* initialize chip */
1879         azx_init_pci(chip);
1880
1881         snd_hdac_i915_set_bclk(bus);
1882
1883         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1884
1885         /* codec detection */
1886         if (!azx_bus(chip)->codec_mask) {
1887                 dev_err(card->dev, "no codecs found!\n");
1888                 return -ENODEV;
1889         }
1890
1891         if (azx_acquire_irq(chip, 0) < 0)
1892                 return -EBUSY;
1893
1894         strcpy(card->driver, "HDA-Intel");
1895         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1896                 sizeof(card->shortname));
1897         snprintf(card->longname, sizeof(card->longname),
1898                  "%s at 0x%lx irq %i",
1899                  card->shortname, bus->addr, bus->irq);
1900
1901         return 0;
1902 }
1903
1904 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1905 /* callback from request_firmware_nowait() */
1906 static void azx_firmware_cb(const struct firmware *fw, void *context)
1907 {
1908         struct snd_card *card = context;
1909         struct azx *chip = card->private_data;
1910         struct pci_dev *pci = chip->pci;
1911
1912         if (!fw) {
1913                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1914                 goto error;
1915         }
1916
1917         chip->fw = fw;
1918         if (!chip->disabled) {
1919                 /* continue probing */
1920                 if (azx_probe_continue(chip))
1921                         goto error;
1922         }
1923         return; /* OK */
1924
1925  error:
1926         snd_card_free(card);
1927         pci_set_drvdata(pci, NULL);
1928 }
1929 #endif
1930
1931 /*
1932  * HDA controller ops.
1933  */
1934
1935 /* PCI register access. */
1936 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1937 {
1938         writel(value, addr);
1939 }
1940
1941 static u32 pci_azx_readl(u32 __iomem *addr)
1942 {
1943         return readl(addr);
1944 }
1945
1946 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1947 {
1948         writew(value, addr);
1949 }
1950
1951 static u16 pci_azx_readw(u16 __iomem *addr)
1952 {
1953         return readw(addr);
1954 }
1955
1956 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1957 {
1958         writeb(value, addr);
1959 }
1960
1961 static u8 pci_azx_readb(u8 __iomem *addr)
1962 {
1963         return readb(addr);
1964 }
1965
1966 static int disable_msi_reset_irq(struct azx *chip)
1967 {
1968         struct hdac_bus *bus = azx_bus(chip);
1969         int err;
1970
1971         free_irq(bus->irq, chip);
1972         bus->irq = -1;
1973         pci_disable_msi(chip->pci);
1974         chip->msi = 0;
1975         err = azx_acquire_irq(chip, 1);
1976         if (err < 0)
1977                 return err;
1978
1979         return 0;
1980 }
1981
1982 /* DMA page allocation helpers.  */
1983 static int dma_alloc_pages(struct hdac_bus *bus,
1984                            int type,
1985                            size_t size,
1986                            struct snd_dma_buffer *buf)
1987 {
1988         struct azx *chip = bus_to_azx(bus);
1989
1990         if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV)
1991                 type = SNDRV_DMA_TYPE_DEV_UC;
1992         return snd_dma_alloc_pages(type, bus->dev, size, buf);
1993 }
1994
1995 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1996 {
1997         snd_dma_free_pages(buf);
1998 }
1999
2000 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2001                              struct vm_area_struct *area)
2002 {
2003 #ifdef CONFIG_X86
2004         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2005         struct azx *chip = apcm->chip;
2006         if (chip->uc_buffer)
2007                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2008 #endif
2009 }
2010
2011 static const struct hdac_io_ops pci_hda_io_ops = {
2012         .reg_writel = pci_azx_writel,
2013         .reg_readl = pci_azx_readl,
2014         .reg_writew = pci_azx_writew,
2015         .reg_readw = pci_azx_readw,
2016         .reg_writeb = pci_azx_writeb,
2017         .reg_readb = pci_azx_readb,
2018         .dma_alloc_pages = dma_alloc_pages,
2019         .dma_free_pages = dma_free_pages,
2020 };
2021
2022 static const struct hda_controller_ops pci_hda_ops = {
2023         .disable_msi_reset_irq = disable_msi_reset_irq,
2024         .pcm_mmap_prepare = pcm_mmap_prepare,
2025         .position_check = azx_position_check,
2026 };
2027
2028 static int azx_probe(struct pci_dev *pci,
2029                      const struct pci_device_id *pci_id)
2030 {
2031         static int dev;
2032         struct snd_card *card;
2033         struct hda_intel *hda;
2034         struct azx *chip;
2035         bool schedule_probe;
2036         int err;
2037
2038         if (dev >= SNDRV_CARDS)
2039                 return -ENODEV;
2040         if (!enable[dev]) {
2041                 dev++;
2042                 return -ENOENT;
2043         }
2044
2045         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2046                            0, &card);
2047         if (err < 0) {
2048                 dev_err(&pci->dev, "Error creating card!\n");
2049                 return err;
2050         }
2051
2052         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2053         if (err < 0)
2054                 goto out_free;
2055         card->private_data = chip;
2056         hda = container_of(chip, struct hda_intel, chip);
2057
2058         pci_set_drvdata(pci, card);
2059
2060         err = register_vga_switcheroo(chip);
2061         if (err < 0) {
2062                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2063                 goto out_free;
2064         }
2065
2066         if (check_hdmi_disabled(pci)) {
2067                 dev_info(card->dev, "VGA controller is disabled\n");
2068                 dev_info(card->dev, "Delaying initialization\n");
2069                 chip->disabled = true;
2070         }
2071
2072         schedule_probe = !chip->disabled;
2073
2074 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2075         if (patch[dev] && *patch[dev]) {
2076                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2077                          patch[dev]);
2078                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2079                                               &pci->dev, GFP_KERNEL, card,
2080                                               azx_firmware_cb);
2081                 if (err < 0)
2082                         goto out_free;
2083                 schedule_probe = false; /* continued in azx_firmware_cb() */
2084         }
2085 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2086
2087 #ifndef CONFIG_SND_HDA_I915
2088         if (CONTROLLER_IN_GPU(pci))
2089                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2090 #endif
2091
2092         if (schedule_probe)
2093                 schedule_work(&hda->probe_work);
2094
2095         dev++;
2096         if (chip->disabled)
2097                 complete_all(&hda->probe_wait);
2098         return 0;
2099
2100 out_free:
2101         snd_card_free(card);
2102         return err;
2103 }
2104
2105 #ifdef CONFIG_PM
2106 /* On some boards setting power_save to a non 0 value leads to clicking /
2107  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2108  * figure out how to avoid these sounds, but that is not always feasible.
2109  * So we keep a list of devices where we disable powersaving as its known
2110  * to causes problems on these devices.
2111  */
2112 static struct snd_pci_quirk power_save_blacklist[] = {
2113         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2114         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2115         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2116         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2117         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2118         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2119         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2120         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2121         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2122         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2123         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2124         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2125         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2126         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2127         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2128         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2129         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2130         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2131         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2132         /* https://bugs.launchpad.net/bugs/1821663 */
2133         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2134         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2135         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2136         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2137         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2138         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2139         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2140         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2141         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2142         /* https://bugs.launchpad.net/bugs/1821663 */
2143         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2144         {}
2145 };
2146 #endif /* CONFIG_PM */
2147
2148 static void set_default_power_save(struct azx *chip)
2149 {
2150         int val = power_save;
2151
2152 #ifdef CONFIG_PM
2153         if (pm_blacklist) {
2154                 const struct snd_pci_quirk *q;
2155
2156                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2157                 if (q && val) {
2158                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2159                                  q->subvendor, q->subdevice);
2160                         val = 0;
2161                 }
2162         }
2163 #endif /* CONFIG_PM */
2164         snd_hda_set_power_save(&chip->bus, val * 1000);
2165 }
2166
2167 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2168 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2169         [AZX_DRIVER_NVIDIA] = 8,
2170         [AZX_DRIVER_TERA] = 1,
2171 };
2172
2173 static int azx_probe_continue(struct azx *chip)
2174 {
2175         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2176         struct hdac_bus *bus = azx_bus(chip);
2177         struct pci_dev *pci = chip->pci;
2178         int dev = chip->dev_index;
2179         int err;
2180
2181         to_hda_bus(bus)->bus_probing = 1;
2182         hda->probe_continued = 1;
2183
2184         /* bind with i915 if needed */
2185         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2186                 err = snd_hdac_i915_init(bus);
2187                 if (err < 0) {
2188                         /* if the controller is bound only with HDMI/DP
2189                          * (for HSW and BDW), we need to abort the probe;
2190                          * for other chips, still continue probing as other
2191                          * codecs can be on the same link.
2192                          */
2193                         if (CONTROLLER_IN_GPU(pci)) {
2194                                 dev_err(chip->card->dev,
2195                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2196                                 goto out_free;
2197                         } else {
2198                                 /* don't bother any longer */
2199                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2200                         }
2201                 }
2202
2203                 /* HSW/BDW controllers need this power */
2204                 if (CONTROLLER_IN_GPU(pci))
2205                         hda->need_i915_power = 1;
2206         }
2207
2208         /* Request display power well for the HDA controller or codec. For
2209          * Haswell/Broadwell, both the display HDA controller and codec need
2210          * this power. For other platforms, like Baytrail/Braswell, only the
2211          * display codec needs the power and it can be released after probe.
2212          */
2213         display_power(chip, true);
2214
2215         err = azx_first_init(chip);
2216         if (err < 0)
2217                 goto out_free;
2218
2219 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2220         chip->beep_mode = beep_mode[dev];
2221 #endif
2222
2223         /* create codec instances */
2224         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2225         if (err < 0)
2226                 goto out_free;
2227
2228 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2229         if (chip->fw) {
2230                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2231                                          chip->fw->data);
2232                 if (err < 0)
2233                         goto out_free;
2234 #ifndef CONFIG_PM
2235                 release_firmware(chip->fw); /* no longer needed */
2236                 chip->fw = NULL;
2237 #endif
2238         }
2239 #endif
2240         if ((probe_only[dev] & 1) == 0) {
2241                 err = azx_codec_configure(chip);
2242                 if (err < 0)
2243                         goto out_free;
2244         }
2245
2246         err = snd_card_register(chip->card);
2247         if (err < 0)
2248                 goto out_free;
2249
2250         setup_vga_switcheroo_runtime_pm(chip);
2251
2252         chip->running = 1;
2253         azx_add_card_list(chip);
2254
2255         set_default_power_save(chip);
2256
2257         if (azx_has_pm_runtime(chip))
2258                 pm_runtime_put_autosuspend(&pci->dev);
2259
2260 out_free:
2261         if (err < 0 || !hda->need_i915_power)
2262                 display_power(chip, false);
2263         if (err < 0)
2264                 hda->init_failed = 1;
2265         complete_all(&hda->probe_wait);
2266         to_hda_bus(bus)->bus_probing = 0;
2267         return err;
2268 }
2269
2270 static void azx_remove(struct pci_dev *pci)
2271 {
2272         struct snd_card *card = pci_get_drvdata(pci);
2273         struct azx *chip;
2274         struct hda_intel *hda;
2275
2276         if (card) {
2277                 /* cancel the pending probing work */
2278                 chip = card->private_data;
2279                 hda = container_of(chip, struct hda_intel, chip);
2280                 /* FIXME: below is an ugly workaround.
2281                  * Both device_release_driver() and driver_probe_device()
2282                  * take *both* the device's and its parent's lock before
2283                  * calling the remove() and probe() callbacks.  The codec
2284                  * probe takes the locks of both the codec itself and its
2285                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2286                  * the PCI controller is unbound, it takes its lock, too
2287                  * ==> ouch, a deadlock!
2288                  * As a workaround, we unlock temporarily here the controller
2289                  * device during cancel_work_sync() call.
2290                  */
2291                 device_unlock(&pci->dev);
2292                 cancel_work_sync(&hda->probe_work);
2293                 device_lock(&pci->dev);
2294
2295                 snd_card_free(card);
2296         }
2297 }
2298
2299 static void azx_shutdown(struct pci_dev *pci)
2300 {
2301         struct snd_card *card = pci_get_drvdata(pci);
2302         struct azx *chip;
2303
2304         if (!card)
2305                 return;
2306         chip = card->private_data;
2307         if (chip && chip->running)
2308                 azx_stop_chip(chip);
2309 }
2310
2311 /* PCI IDs */
2312 static const struct pci_device_id azx_ids[] = {
2313         /* CPT */
2314         { PCI_DEVICE(0x8086, 0x1c20),
2315           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2316         /* PBG */
2317         { PCI_DEVICE(0x8086, 0x1d20),
2318           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2319         /* Panther Point */
2320         { PCI_DEVICE(0x8086, 0x1e20),
2321           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2322         /* Lynx Point */
2323         { PCI_DEVICE(0x8086, 0x8c20),
2324           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2325         /* 9 Series */
2326         { PCI_DEVICE(0x8086, 0x8ca0),
2327           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2328         /* Wellsburg */
2329         { PCI_DEVICE(0x8086, 0x8d20),
2330           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2331         { PCI_DEVICE(0x8086, 0x8d21),
2332           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2333         /* Lewisburg */
2334         { PCI_DEVICE(0x8086, 0xa1f0),
2335           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2336         { PCI_DEVICE(0x8086, 0xa270),
2337           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2338         /* Lynx Point-LP */
2339         { PCI_DEVICE(0x8086, 0x9c20),
2340           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2341         /* Lynx Point-LP */
2342         { PCI_DEVICE(0x8086, 0x9c21),
2343           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2344         /* Wildcat Point-LP */
2345         { PCI_DEVICE(0x8086, 0x9ca0),
2346           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2347         /* Sunrise Point */
2348         { PCI_DEVICE(0x8086, 0xa170),
2349           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2350         /* Sunrise Point-LP */
2351         { PCI_DEVICE(0x8086, 0x9d70),
2352           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2353         /* Kabylake */
2354         { PCI_DEVICE(0x8086, 0xa171),
2355           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2356         /* Kabylake-LP */
2357         { PCI_DEVICE(0x8086, 0x9d71),
2358           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2359         /* Kabylake-H */
2360         { PCI_DEVICE(0x8086, 0xa2f0),
2361           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2362         /* Coffelake */
2363         { PCI_DEVICE(0x8086, 0xa348),
2364           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2365         /* Cannonlake */
2366         { PCI_DEVICE(0x8086, 0x9dc8),
2367           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2368         /* CometLake-LP */
2369         { PCI_DEVICE(0x8086, 0x02C8),
2370           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2371         /* CometLake-H */
2372         { PCI_DEVICE(0x8086, 0x06C8),
2373           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2374         /* Icelake */
2375         { PCI_DEVICE(0x8086, 0x34c8),
2376           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2377         /* Elkhart Lake */
2378         { PCI_DEVICE(0x8086, 0x4b55),
2379           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2380         /* Broxton-P(Apollolake) */
2381         { PCI_DEVICE(0x8086, 0x5a98),
2382           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2383         /* Broxton-T */
2384         { PCI_DEVICE(0x8086, 0x1a98),
2385           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2386         /* Gemini-Lake */
2387         { PCI_DEVICE(0x8086, 0x3198),
2388           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2389         /* Haswell */
2390         { PCI_DEVICE(0x8086, 0x0a0c),
2391           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2392         { PCI_DEVICE(0x8086, 0x0c0c),
2393           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2394         { PCI_DEVICE(0x8086, 0x0d0c),
2395           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2396         /* Broadwell */
2397         { PCI_DEVICE(0x8086, 0x160c),
2398           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2399         /* 5 Series/3400 */
2400         { PCI_DEVICE(0x8086, 0x3b56),
2401           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2402         /* Poulsbo */
2403         { PCI_DEVICE(0x8086, 0x811b),
2404           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2405         /* Oaktrail */
2406         { PCI_DEVICE(0x8086, 0x080a),
2407           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2408         /* BayTrail */
2409         { PCI_DEVICE(0x8086, 0x0f04),
2410           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2411         /* Braswell */
2412         { PCI_DEVICE(0x8086, 0x2284),
2413           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2414         /* ICH6 */
2415         { PCI_DEVICE(0x8086, 0x2668),
2416           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2417         /* ICH7 */
2418         { PCI_DEVICE(0x8086, 0x27d8),
2419           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2420         /* ESB2 */
2421         { PCI_DEVICE(0x8086, 0x269a),
2422           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2423         /* ICH8 */
2424         { PCI_DEVICE(0x8086, 0x284b),
2425           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2426         /* ICH9 */
2427         { PCI_DEVICE(0x8086, 0x293e),
2428           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2429         /* ICH9 */
2430         { PCI_DEVICE(0x8086, 0x293f),
2431           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2432         /* ICH10 */
2433         { PCI_DEVICE(0x8086, 0x3a3e),
2434           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2435         /* ICH10 */
2436         { PCI_DEVICE(0x8086, 0x3a6e),
2437           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2438         /* Generic Intel */
2439         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2440           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2441           .class_mask = 0xffffff,
2442           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2443         /* ATI SB 450/600/700/800/900 */
2444         { PCI_DEVICE(0x1002, 0x437b),
2445           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2446         { PCI_DEVICE(0x1002, 0x4383),
2447           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2448         /* AMD Hudson */
2449         { PCI_DEVICE(0x1022, 0x780d),
2450           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2451         /* AMD Stoney */
2452         { PCI_DEVICE(0x1022, 0x157a),
2453           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2454                          AZX_DCAPS_PM_RUNTIME },
2455         /* AMD Raven */
2456         { PCI_DEVICE(0x1022, 0x15e3),
2457           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2458                          AZX_DCAPS_PM_RUNTIME },
2459         /* ATI HDMI */
2460         { PCI_DEVICE(0x1002, 0x0002),
2461           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2462         { PCI_DEVICE(0x1002, 0x1308),
2463           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2464         { PCI_DEVICE(0x1002, 0x157a),
2465           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2466         { PCI_DEVICE(0x1002, 0x15b3),
2467           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2468         { PCI_DEVICE(0x1002, 0x793b),
2469           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2470         { PCI_DEVICE(0x1002, 0x7919),
2471           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2472         { PCI_DEVICE(0x1002, 0x960f),
2473           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2474         { PCI_DEVICE(0x1002, 0x970f),
2475           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2476         { PCI_DEVICE(0x1002, 0x9840),
2477           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2478         { PCI_DEVICE(0x1002, 0xaa00),
2479           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2480         { PCI_DEVICE(0x1002, 0xaa08),
2481           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2482         { PCI_DEVICE(0x1002, 0xaa10),
2483           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2484         { PCI_DEVICE(0x1002, 0xaa18),
2485           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2486         { PCI_DEVICE(0x1002, 0xaa20),
2487           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2488         { PCI_DEVICE(0x1002, 0xaa28),
2489           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2490         { PCI_DEVICE(0x1002, 0xaa30),
2491           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2492         { PCI_DEVICE(0x1002, 0xaa38),
2493           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2494         { PCI_DEVICE(0x1002, 0xaa40),
2495           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2496         { PCI_DEVICE(0x1002, 0xaa48),
2497           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2498         { PCI_DEVICE(0x1002, 0xaa50),
2499           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2500         { PCI_DEVICE(0x1002, 0xaa58),
2501           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2502         { PCI_DEVICE(0x1002, 0xaa60),
2503           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2504         { PCI_DEVICE(0x1002, 0xaa68),
2505           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2506         { PCI_DEVICE(0x1002, 0xaa80),
2507           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2508         { PCI_DEVICE(0x1002, 0xaa88),
2509           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510         { PCI_DEVICE(0x1002, 0xaa90),
2511           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512         { PCI_DEVICE(0x1002, 0xaa98),
2513           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2514         { PCI_DEVICE(0x1002, 0x9902),
2515           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2516         { PCI_DEVICE(0x1002, 0xaaa0),
2517           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2518         { PCI_DEVICE(0x1002, 0xaaa8),
2519           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2520         { PCI_DEVICE(0x1002, 0xaab0),
2521           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2522         { PCI_DEVICE(0x1002, 0xaac0),
2523           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2524         { PCI_DEVICE(0x1002, 0xaac8),
2525           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2526         { PCI_DEVICE(0x1002, 0xaad8),
2527           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2528         { PCI_DEVICE(0x1002, 0xaae8),
2529           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2530         { PCI_DEVICE(0x1002, 0xaae0),
2531           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2532         { PCI_DEVICE(0x1002, 0xaaf0),
2533           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2534         /* VIA VT8251/VT8237A */
2535         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2536         /* VIA GFX VT7122/VX900 */
2537         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2538         /* VIA GFX VT6122/VX11 */
2539         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2540         /* SIS966 */
2541         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2542         /* ULI M5461 */
2543         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2544         /* NVIDIA MCP */
2545         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2546           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2547           .class_mask = 0xffffff,
2548           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2549         /* Teradici */
2550         { PCI_DEVICE(0x6549, 0x1200),
2551           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2552         { PCI_DEVICE(0x6549, 0x2200),
2553           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2554         /* Creative X-Fi (CA0110-IBG) */
2555         /* CTHDA chips */
2556         { PCI_DEVICE(0x1102, 0x0010),
2557           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2558         { PCI_DEVICE(0x1102, 0x0012),
2559           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2560 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2561         /* the following entry conflicts with snd-ctxfi driver,
2562          * as ctxfi driver mutates from HD-audio to native mode with
2563          * a special command sequence.
2564          */
2565         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2566           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2567           .class_mask = 0xffffff,
2568           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2569           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2570 #else
2571         /* this entry seems still valid -- i.e. without emu20kx chip */
2572         { PCI_DEVICE(0x1102, 0x0009),
2573           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2574           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2575 #endif
2576         /* CM8888 */
2577         { PCI_DEVICE(0x13f6, 0x5011),
2578           .driver_data = AZX_DRIVER_CMEDIA |
2579           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2580         /* Vortex86MX */
2581         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2582         /* VMware HDAudio */
2583         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2584         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2585         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2586           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2587           .class_mask = 0xffffff,
2588           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2589         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2590           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2591           .class_mask = 0xffffff,
2592           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2593         { 0, }
2594 };
2595 MODULE_DEVICE_TABLE(pci, azx_ids);
2596
2597 /* pci_driver definition */
2598 static struct pci_driver azx_driver = {
2599         .name = KBUILD_MODNAME,
2600         .id_table = azx_ids,
2601         .probe = azx_probe,
2602         .remove = azx_remove,
2603         .shutdown = azx_shutdown,
2604         .driver = {
2605                 .pm = AZX_PM_OPS,
2606         },
2607 };
2608
2609 module_pci_driver(azx_driver);