sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38
  39 #ifdef CONFIG_X86
  40 /* for snoop control */
  41 #include <asm/pgtable.h>
  42 #include <asm/set_memory.h>
  43 #include <asm/cpufeature.h>
  44 #endif
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include <sound/hdaudio.h>
  48 #include <sound/hda_i915.h>
  49 #include <sound/intel-dsp-config.h>
  50 #include <linux/vgaarb.h>
  51 #include <linux/vga_switcheroo.h>
  52 #include <linux/firmware.h>
  53 #include <sound/hda_codec.h>
  54 #include "hda_controller.h"
  55 #include "hda_intel.h"
  56
  57 #define CREATE_TRACE_POINTS
  58 #include "hda_intel_trace.h"
  59
  60 /* position fix mode */
  61 enum {
  62         POS_FIX_AUTO,
  63         POS_FIX_LPIB,
  64         POS_FIX_POSBUF,
  65         POS_FIX_VIACOMBO,
  66         POS_FIX_COMBO,
  67         POS_FIX_SKL,
  68         POS_FIX_FIFO,
  69 };
  70
  71 /* Defines for ATI HD Audio support in SB450 south bridge */
  72 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  73 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  74
  75 /* Defines for Nvidia HDA support */
  76 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  77 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  78 #define NVIDIA_HDA_ISTRM_COH          0x4d
  79 #define NVIDIA_HDA_OSTRM_COH          0x4c
  80 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  81
  82 /* Defines for Intel SCH HDA snoop control */
  83 #define INTEL_HDA_CGCTL  0x48
  84 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  85 #define INTEL_SCH_HDA_DEVC      0x78
  86 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  87
  88 /* Define VIA HD Audio Device ID*/
  89 #define VIA_HDAC_DEVICE_ID              0x3288
  90
  91 /* max number of SDs */
  92 /* ICH, ATI and VIA have 4 playback and 4 capture */
  93 #define ICH6_NUM_CAPTURE        4
  94 #define ICH6_NUM_PLAYBACK       4
  95
  96 /* ULI has 6 playback and 5 capture */
  97 #define ULI_NUM_CAPTURE         5
  98 #define ULI_NUM_PLAYBACK        6
  99
 100 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 101 #define ATIHDMI_NUM_CAPTURE     0
 102 #define ATIHDMI_NUM_PLAYBACK    8
 103
 104 /* TERA has 4 playback and 3 capture */
 105 #define TERA_NUM_CAPTURE        3
 106 #define TERA_NUM_PLAYBACK       4
 107
 108
 109 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 110 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 111 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 112 static char *model[SNDRV_CARDS];
 113 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 114 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_only[SNDRV_CARDS];
 117 static int jackpoll_ms[SNDRV_CARDS];
 118 static int single_cmd = -1;
 119 static int enable_msi = -1;
 120 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 121 static char *patch[SNDRV_CARDS];
 122 #endif
 123 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 124 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 125                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 126 #endif
 127 static bool dsp_driver = 1;
 128
 129 module_param_array(index, int, NULL, 0444);
 130 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 131 module_param_array(id, charp, NULL, 0444);
 132 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 133 module_param_array(enable, bool, NULL, 0444);
 134 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 135 module_param_array(model, charp, NULL, 0444);
 136 MODULE_PARM_DESC(model, "Use the given board model.");
 137 module_param_array(position_fix, int, NULL, 0444);
 138 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 139                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 140 module_param_array(bdl_pos_adj, int, NULL, 0644);
 141 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 142 module_param_array(probe_mask, int, NULL, 0444);
 143 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 144 module_param_array(probe_only, int, NULL, 0444);
 145 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 146 module_param_array(jackpoll_ms, int, NULL, 0444);
 147 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 148 module_param(single_cmd, bint, 0444);
 149 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 150                  "(for debugging only).");
 151 module_param(enable_msi, bint, 0444);
 152 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 153 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 154 module_param_array(patch, charp, NULL, 0444);
 155 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 156 #endif
 157 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 158 module_param_array(beep_mode, bool, NULL, 0444);
 159 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 160                             "(0=off, 1=on) (default=1).");
 161 #endif
 162 module_param(dsp_driver, bool, 0444);
 163 MODULE_PARM_DESC(dsp_driver, "Allow DSP driver selection (bypass this driver) "
 164                              "(0=off, 1=on) (default=1)");
 165
 166 #ifdef CONFIG_PM
 167 static int param_set_xint(const char *val, const struct kernel_param *kp);
 168 static const struct kernel_param_ops param_ops_xint = {
 169         .set = param_set_xint,
 170         .get = param_get_int,
 171 };
 172 #define param_check_xint param_check_int
 173
 174 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 175 module_param(power_save, xint, 0644);
 176 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 177                  "(in second, 0 = disable).");
 178
 179 static bool pm_blacklist = true;
 180 module_param(pm_blacklist, bool, 0644);
 181 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 182
 183 /* reset the HD-audio controller in power save mode.
 184  * this may give more power-saving, but will take longer time to
 185  * wake up.
 186  */
 187 static bool power_save_controller = 1;
 188 module_param(power_save_controller, bool, 0644);
 189 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 190 #else
 191 #define power_save      0
 192 #endif /* CONFIG_PM */
 193
 194 static int align_buffer_size = -1;
 195 module_param(align_buffer_size, bint, 0644);
 196 MODULE_PARM_DESC(align_buffer_size,
 197                 "Force buffer and period sizes to be multiple of 128 bytes.");
 198
 199 #ifdef CONFIG_X86
 200 static int hda_snoop = -1;
 201 module_param_named(snoop, hda_snoop, bint, 0444);
 202 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 203 #else
 204 #define hda_snoop               true
 205 #endif
 206
 207
 208 MODULE_LICENSE("GPL");
 209 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 210                          "{Intel, ICH6M},"
 211                          "{Intel, ICH7},"
 212                          "{Intel, ESB2},"
 213                          "{Intel, ICH8},"
 214                          "{Intel, ICH9},"
 215                          "{Intel, ICH10},"
 216                          "{Intel, PCH},"
 217                          "{Intel, CPT},"
 218                          "{Intel, PPT},"
 219                          "{Intel, LPT},"
 220                          "{Intel, LPT_LP},"
 221                          "{Intel, WPT_LP},"
 222                          "{Intel, SPT},"
 223                          "{Intel, SPT_LP},"
 224                          "{Intel, HPT},"
 225                          "{Intel, PBG},"
 226                          "{Intel, SCH},"
 227                          "{ATI, SB450},"
 228                          "{ATI, SB600},"
 229                          "{ATI, RS600},"
 230                          "{ATI, RS690},"
 231                          "{ATI, RS780},"
 232                          "{ATI, R600},"
 233                          "{ATI, RV630},"
 234                          "{ATI, RV610},"
 235                          "{ATI, RV670},"
 236                          "{ATI, RV635},"
 237                          "{ATI, RV620},"
 238                          "{ATI, RV770},"
 239                          "{VIA, VT8251},"
 240                          "{VIA, VT8237A},"
 241                          "{SiS, SIS966},"
 242                          "{ULI, M5461}}");
 243 MODULE_DESCRIPTION("Intel HDA driver");
 244
 245 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 246 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 247 #define SUPPORT_VGA_SWITCHEROO
 248 #endif
 249 #endif
 250
 251
 252 /*
 253  */
 254
 255 /* driver types */
 256 enum {
 257         AZX_DRIVER_ICH,
 258         AZX_DRIVER_PCH,
 259         AZX_DRIVER_SCH,
 260         AZX_DRIVER_SKL,
 261         AZX_DRIVER_HDMI,
 262         AZX_DRIVER_ATI,
 263         AZX_DRIVER_ATIHDMI,
 264         AZX_DRIVER_ATIHDMI_NS,
 265         AZX_DRIVER_VIA,
 266         AZX_DRIVER_SIS,
 267         AZX_DRIVER_ULI,
 268         AZX_DRIVER_NVIDIA,
 269         AZX_DRIVER_TERA,
 270         AZX_DRIVER_CTX,
 271         AZX_DRIVER_CTHDA,
 272         AZX_DRIVER_CMEDIA,
 273         AZX_DRIVER_ZHAOXIN,
 274         AZX_DRIVER_GENERIC,
 275         AZX_NUM_DRIVERS, /* keep this as last entry */
 276 };
 277
 278 #define azx_get_snoop_type(chip) \
 279         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 281
 282 /* quirks for old Intel chipsets */
 283 #define AZX_DCAPS_INTEL_ICH \
 284         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 285
 286 /* quirks for Intel PCH */
 287 #define AZX_DCAPS_INTEL_PCH_BASE \
 288         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 289          AZX_DCAPS_SNOOP_TYPE(SCH))
 290
 291 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 292 #define AZX_DCAPS_INTEL_PCH_NOPM \
 293         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 294
 295 /* PCH for HSW/BDW; with runtime PM */
 296 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 297 #define AZX_DCAPS_INTEL_PCH \
 298         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 299
 300 /* HSW HDMI */
 301 #define AZX_DCAPS_INTEL_HASWELL \
 302         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 303          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 304          AZX_DCAPS_SNOOP_TYPE(SCH))
 305
 306 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 307 #define AZX_DCAPS_INTEL_BROADWELL \
 308         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 309          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 310          AZX_DCAPS_SNOOP_TYPE(SCH))
 311
 312 #define AZX_DCAPS_INTEL_BAYTRAIL \
 313         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 314
 315 #define AZX_DCAPS_INTEL_BRASWELL \
 316         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 317          AZX_DCAPS_I915_COMPONENT)
 318
 319 #define AZX_DCAPS_INTEL_SKYLAKE \
 320         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 321          AZX_DCAPS_SYNC_WRITE |\
 322          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 323
 324 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 325
 326 /* quirks for ATI SB / AMD Hudson */
 327 #define AZX_DCAPS_PRESET_ATI_SB \
 328         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 329          AZX_DCAPS_SNOOP_TYPE(ATI))
 330
 331 /* quirks for ATI/AMD HDMI */
 332 #define AZX_DCAPS_PRESET_ATI_HDMI \
 333         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 334          AZX_DCAPS_NO_MSI64)
 335
 336 /* quirks for ATI HDMI with snoop off */
 337 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 338         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 339
 340 /* quirks for AMD SB */
 341 #define AZX_DCAPS_PRESET_AMD_SB \
 342         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
 343          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 344
 345 /* quirks for Nvidia */
 346 #define AZX_DCAPS_PRESET_NVIDIA \
 347         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 348          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 349
 350 #define AZX_DCAPS_PRESET_CTHDA \
 351         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 352          AZX_DCAPS_NO_64BIT |\
 353          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 354
 355 /*
 356  * vga_switcheroo support
 357  */
 358 #ifdef SUPPORT_VGA_SWITCHEROO
 359 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 360 #define needs_eld_notify_link(chip)     ((chip)->bus.keep_power)
 361 #else
 362 #define use_vga_switcheroo(chip)        0
 363 #define needs_eld_notify_link(chip)     false
 364 #endif
 365
 366 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 367                                         ((pci)->device == 0x0c0c) || \
 368                                         ((pci)->device == 0x0d0c) || \
 369                                         ((pci)->device == 0x160c))
 370
 371 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 372 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 373 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 374
 375 static char *driver_short_names[] = {
 376         [AZX_DRIVER_ICH] = "HDA Intel",
 377         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 378         [AZX_DRIVER_SCH] = "HDA Intel MID",
 379         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 380         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 381         [AZX_DRIVER_ATI] = "HDA ATI SB",
 382         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 383         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 384         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 385         [AZX_DRIVER_SIS] = "HDA SIS966",
 386         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 387         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 388         [AZX_DRIVER_TERA] = "HDA Teradici",
 389         [AZX_DRIVER_CTX] = "HDA Creative",
 390         [AZX_DRIVER_CTHDA] = "HDA Creative",
 391         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 392         [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
 393         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 394 };
 395
 396 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 397 static void set_default_power_save(struct azx *chip);
 398
 399 /*
 400  * initialize the PCI registers
 401  */
 402 /* update bits in a PCI register byte */
 403 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 404                             unsigned char mask, unsigned char val)
 405 {
 406         unsigned char data;
 407
 408         pci_read_config_byte(pci, reg, &data);
 409         data &= ~mask;
 410         data |= (val & mask);
 411         pci_write_config_byte(pci, reg, data);
 412 }
 413
 414 static void azx_init_pci(struct azx *chip)
 415 {
 416         int snoop_type = azx_get_snoop_type(chip);
 417
 418         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 419          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 420          * Ensuring these bits are 0 clears playback static on some HD Audio
 421          * codecs.
 422          * The PCI register TCSEL is defined in the Intel manuals.
 423          */
 424         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 425                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 426                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 427         }
 428
 429         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 430          * we need to enable snoop.
 431          */
 432         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 433                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 434                         azx_snoop(chip));
 435                 update_pci_byte(chip->pci,
 436                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 437                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 438         }
 439
 440         /* For NVIDIA HDA, enable snoop */
 441         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 442                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 443                         azx_snoop(chip));
 444                 update_pci_byte(chip->pci,
 445                                 NVIDIA_HDA_TRANSREG_ADDR,
 446                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 447                 update_pci_byte(chip->pci,
 448                                 NVIDIA_HDA_ISTRM_COH,
 449                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 450                 update_pci_byte(chip->pci,
 451                                 NVIDIA_HDA_OSTRM_COH,
 452                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 453         }
 454
 455         /* Enable SCH/PCH snoop if needed */
 456         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 457                 unsigned short snoop;
 458                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 459                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 460                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 461                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 462                         if (!azx_snoop(chip))
 463                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 464                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 465                         pci_read_config_word(chip->pci,
 466                                 INTEL_SCH_HDA_DEVC, &snoop);
 467                 }
 468                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 469                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 470                         "Disabled" : "Enabled");
 471         }
 472 }
 473
 474 /*
 475  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 476  * and makes an audio stream sensitive to system latencies when
 477  * 24/32 bits are playing.
 478  * Adjusting threshold of DMA fifo to force the DMA request
 479  * sooner to improve latency tolerance at the expense of power.
 480  */
 481 static void bxt_reduce_dma_latency(struct azx *chip)
 482 {
 483         u32 val;
 484
 485         val = azx_readl(chip, VS_EM4L);
 486         val &= (0x3 << 20);
 487         azx_writel(chip, VS_EM4L, val);
 488 }
 489
 490 /*
 491  * ML_LCAP bits:
 492  *  bit 0: 6 MHz Supported
 493  *  bit 1: 12 MHz Supported
 494  *  bit 2: 24 MHz Supported
 495  *  bit 3: 48 MHz Supported
 496  *  bit 4: 96 MHz Supported
 497  *  bit 5: 192 MHz Supported
 498  */
 499 static int intel_get_lctl_scf(struct azx *chip)
 500 {
 501         struct hdac_bus *bus = azx_bus(chip);
 502         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 503         u32 val, t;
 504         int i;
 505
 506         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 507
 508         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 509                 t = preferred_bits[i];
 510                 if (val & (1 << t))
 511                         return t;
 512         }
 513
 514         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 515         return 0;
 516 }
 517
 518 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 519 {
 520         struct hdac_bus *bus = azx_bus(chip);
 521         u32 val;
 522         int timeout;
 523
 524         /*
 525          * the codecs are sharing the first link setting by default
 526          * If other links are enabled for stream, they need similar fix
 527          */
 528         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 529         val &= ~AZX_MLCTL_SPA;
 530         val |= state << AZX_MLCTL_SPA_SHIFT;
 531         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 532         /* wait for CPA */
 533         timeout = 50;
 534         while (timeout) {
 535                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 536                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 537                         return 0;
 538                 timeout--;
 539                 udelay(10);
 540         }
 541
 542         return -1;
 543 }
 544
 545 static void intel_init_lctl(struct azx *chip)
 546 {
 547         struct hdac_bus *bus = azx_bus(chip);
 548         u32 val;
 549         int ret;
 550
 551         /* 0. check lctl register value is correct or not */
 552         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 553         /* if SCF is already set, let's use it */
 554         if ((val & ML_LCTL_SCF_MASK) != 0)
 555                 return;
 556
 557         /*
 558          * Before operating on SPA, CPA must match SPA.
 559          * Any deviation may result in undefined behavior.
 560          */
 561         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 562                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 563                 return;
 564
 565         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 566         ret = intel_ml_lctl_set_power(chip, 0);
 567         udelay(100);
 568         if (ret)
 569                 goto set_spa;
 570
 571         /* 2. update SCF to select a properly audio clock*/
 572         val &= ~ML_LCTL_SCF_MASK;
 573         val |= intel_get_lctl_scf(chip);
 574         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 575
 576 set_spa:
 577         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 578         intel_ml_lctl_set_power(chip, 1);
 579         udelay(100);
 580 }
 581
 582 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 583 {
 584         struct hdac_bus *bus = azx_bus(chip);
 585         struct pci_dev *pci = chip->pci;
 586         u32 val;
 587
 588         snd_hdac_set_codec_wakeup(bus, true);
 589         if (chip->driver_type == AZX_DRIVER_SKL) {
 590                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 591                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 592                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 593         }
 594         azx_init_chip(chip, full_reset);
 595         if (chip->driver_type == AZX_DRIVER_SKL) {
 596                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 597                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 598                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 599         }
 600
 601         snd_hdac_set_codec_wakeup(bus, false);
 602
 603         /* reduce dma latency to avoid noise */
 604         if (IS_BXT(pci))
 605                 bxt_reduce_dma_latency(chip);
 606
 607         if (bus->mlcap != NULL)
 608                 intel_init_lctl(chip);
 609 }
 610
 611 /* calculate runtime delay from LPIB */
 612 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 613                                    unsigned int pos)
 614 {
 615         struct snd_pcm_substream *substream = azx_dev->core.substream;
 616         int stream = substream->stream;
 617         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 618         int delay;
 619
 620         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 621                 delay = pos - lpib_pos;
 622         else
 623                 delay = lpib_pos - pos;
 624         if (delay < 0) {
 625                 if (delay >= azx_dev->core.delay_negative_threshold)
 626                         delay = 0;
 627                 else
 628                         delay += azx_dev->core.bufsize;
 629         }
 630
 631         if (delay >= azx_dev->core.period_bytes) {
 632                 dev_info(chip->card->dev,
 633                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 634                          delay, azx_dev->core.period_bytes);
 635                 delay = 0;
 636                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 637                 chip->get_delay[stream] = NULL;
 638         }
 639
 640         return bytes_to_frames(substream->runtime, delay);
 641 }
 642
 643 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 644
 645 /* called from IRQ */
 646 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 647 {
 648         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 649         int ok;
 650
 651         ok = azx_position_ok(chip, azx_dev);
 652         if (ok == 1) {
 653                 azx_dev->irq_pending = 0;
 654                 return ok;
 655         } else if (ok == 0) {
 656                 /* bogus IRQ, process it later */
 657                 azx_dev->irq_pending = 1;
 658                 schedule_work(&hda->irq_pending_work);
 659         }
 660         return 0;
 661 }
 662
 663 #define display_power(chip, enable) \
 664         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 665
 666 /*
 667  * Check whether the current DMA position is acceptable for updating
 668  * periods.  Returns non-zero if it's OK.
 669  *
 670  * Many HD-audio controllers appear pretty inaccurate about
 671  * the update-IRQ timing.  The IRQ is issued before actually the
 672  * data is processed.  So, we need to process it afterwords in a
 673  * workqueue.
 674  */
 675 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 676 {
 677         struct snd_pcm_substream *substream = azx_dev->core.substream;
 678         int stream = substream->stream;
 679         u32 wallclk;
 680         unsigned int pos;
 681
 682         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 683         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 684                 return -1;      /* bogus (too early) interrupt */
 685
 686         if (chip->get_position[stream])
 687                 pos = chip->get_position[stream](chip, azx_dev);
 688         else { /* use the position buffer as default */
 689                 pos = azx_get_pos_posbuf(chip, azx_dev);
 690                 if (!pos || pos == (u32)-1) {
 691                         dev_info(chip->card->dev,
 692                                  "Invalid position buffer, using LPIB read method instead.\n");
 693                         chip->get_position[stream] = azx_get_pos_lpib;
 694                         if (chip->get_position[0] == azx_get_pos_lpib &&
 695                             chip->get_position[1] == azx_get_pos_lpib)
 696                                 azx_bus(chip)->use_posbuf = false;
 697                         pos = azx_get_pos_lpib(chip, azx_dev);
 698                         chip->get_delay[stream] = NULL;
 699                 } else {
 700                         chip->get_position[stream] = azx_get_pos_posbuf;
 701                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 702                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 703                 }
 704         }
 705
 706         if (pos >= azx_dev->core.bufsize)
 707                 pos = 0;
 708
 709         if (WARN_ONCE(!azx_dev->core.period_bytes,
 710                       "hda-intel: zero azx_dev->period_bytes"))
 711                 return -1; /* this shouldn't happen! */
 712         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 713             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 714                 /* NG - it's below the first next period boundary */
 715                 return chip->bdl_pos_adj ? 0 : -1;
 716         azx_dev->core.start_wallclk += wallclk;
 717         return 1; /* OK, it's fine */
 718 }
 719
 720 /*
 721  * The work for pending PCM period updates.
 722  */
 723 static void azx_irq_pending_work(struct work_struct *work)
 724 {
 725         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 726         struct azx *chip = &hda->chip;
 727         struct hdac_bus *bus = azx_bus(chip);
 728         struct hdac_stream *s;
 729         int pending, ok;
 730
 731         if (!hda->irq_pending_warned) {
 732                 dev_info(chip->card->dev,
 733                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 734                          chip->card->number);
 735                 hda->irq_pending_warned = 1;
 736         }
 737
 738         for (;;) {
 739                 pending = 0;
 740                 spin_lock_irq(&bus->reg_lock);
 741                 list_for_each_entry(s, &bus->stream_list, list) {
 742                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 743                         if (!azx_dev->irq_pending ||
 744                             !s->substream ||
 745                             !s->running)
 746                                 continue;
 747                         ok = azx_position_ok(chip, azx_dev);
 748                         if (ok > 0) {
 749                                 azx_dev->irq_pending = 0;
 750                                 spin_unlock(&bus->reg_lock);
 751                                 snd_pcm_period_elapsed(s->substream);
 752                                 spin_lock(&bus->reg_lock);
 753                         } else if (ok < 0) {
 754                                 pending = 0;    /* too early */
 755                         } else
 756                                 pending++;
 757                 }
 758                 spin_unlock_irq(&bus->reg_lock);
 759                 if (!pending)
 760                         return;
 761                 msleep(1);
 762         }
 763 }
 764
 765 /* clear irq_pending flags and assure no on-going workq */
 766 static void azx_clear_irq_pending(struct azx *chip)
 767 {
 768         struct hdac_bus *bus = azx_bus(chip);
 769         struct hdac_stream *s;
 770
 771         spin_lock_irq(&bus->reg_lock);
 772         list_for_each_entry(s, &bus->stream_list, list) {
 773                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 774                 azx_dev->irq_pending = 0;
 775         }
 776         spin_unlock_irq(&bus->reg_lock);
 777 }
 778
 779 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 780 {
 781         struct hdac_bus *bus = azx_bus(chip);
 782
 783         if (request_irq(chip->pci->irq, azx_interrupt,
 784                         chip->msi ? 0 : IRQF_SHARED,
 785                         chip->card->irq_descr, chip)) {
 786                 dev_err(chip->card->dev,
 787                         "unable to grab IRQ %d, disabling device\n",
 788                         chip->pci->irq);
 789                 if (do_disconnect)
 790                         snd_card_disconnect(chip->card);
 791                 return -1;
 792         }
 793         bus->irq = chip->pci->irq;
 794         pci_intx(chip->pci, !chip->msi);
 795         return 0;
 796 }
 797
 798 /* get the current DMA position with correction on VIA chips */
 799 static unsigned int azx_via_get_position(struct azx *chip,
 800                                          struct azx_dev *azx_dev)
 801 {
 802         unsigned int link_pos, mini_pos, bound_pos;
 803         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 804         unsigned int fifo_size;
 805
 806         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 807         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 808                 /* Playback, no problem using link position */
 809                 return link_pos;
 810         }
 811
 812         /* Capture */
 813         /* For new chipset,
 814          * use mod to get the DMA position just like old chipset
 815          */
 816         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 817         mod_dma_pos %= azx_dev->core.period_bytes;
 818
 819         fifo_size = azx_stream(azx_dev)->fifo_size - 1;
 820
 821         if (azx_dev->insufficient) {
 822                 /* Link position never gather than FIFO size */
 823                 if (link_pos <= fifo_size)
 824                         return 0;
 825
 826                 azx_dev->insufficient = 0;
 827         }
 828
 829         if (link_pos <= fifo_size)
 830                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 831         else
 832                 mini_pos = link_pos - fifo_size;
 833
 834         /* Find nearest previous boudary */
 835         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 836         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 837         if (mod_link_pos >= fifo_size)
 838                 bound_pos = link_pos - mod_link_pos;
 839         else if (mod_dma_pos >= mod_mini_pos)
 840                 bound_pos = mini_pos - mod_mini_pos;
 841         else {
 842                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 843                 if (bound_pos >= azx_dev->core.bufsize)
 844                         bound_pos = 0;
 845         }
 846
 847         /* Calculate real DMA position we want */
 848         return bound_pos + mod_dma_pos;
 849 }
 850
 851 #define AMD_FIFO_SIZE   32
 852
 853 /* get the current DMA position with FIFO size correction */
 854 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 855 {
 856         struct snd_pcm_substream *substream = azx_dev->core.substream;
 857         struct snd_pcm_runtime *runtime = substream->runtime;
 858         unsigned int pos, delay;
 859
 860         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 861         if (!runtime)
 862                 return pos;
 863
 864         runtime->delay = AMD_FIFO_SIZE;
 865         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 866         if (azx_dev->insufficient) {
 867                 if (pos < delay) {
 868                         delay = pos;
 869                         runtime->delay = bytes_to_frames(runtime, pos);
 870                 } else {
 871                         azx_dev->insufficient = 0;
 872                 }
 873         }
 874
 875         /* correct the DMA position for capture stream */
 876         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 877                 if (pos < delay)
 878                         pos += azx_dev->core.bufsize;
 879                 pos -= delay;
 880         }
 881
 882         return pos;
 883 }
 884
 885 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 886                                    unsigned int pos)
 887 {
 888         struct snd_pcm_substream *substream = azx_dev->core.substream;
 889
 890         /* just read back the calculated value in the above */
 891         return substream->runtime->delay;
 892 }
 893
 894 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 895                                          struct azx_dev *azx_dev)
 896 {
 897         return _snd_hdac_chip_readl(azx_bus(chip),
 898                                     AZX_REG_VS_SDXDPIB_XBASE +
 899                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 900                                      azx_dev->core.index));
 901 }
 902
 903 /* get the current DMA position with correction on SKL+ chips */
 904 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 905 {
 906         /* DPIB register gives a more accurate position for playback */
 907         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 908                 return azx_skl_get_dpib_pos(chip, azx_dev);
 909
 910         /* For capture, we need to read posbuf, but it requires a delay
 911          * for the possible boundary overlap; the read of DPIB fetches the
 912          * actual posbuf
 913          */
 914         udelay(20);
 915         azx_skl_get_dpib_pos(chip, azx_dev);
 916         return azx_get_pos_posbuf(chip, azx_dev);
 917 }
 918
 919 #ifdef CONFIG_PM
 920 static DEFINE_MUTEX(card_list_lock);
 921 static LIST_HEAD(card_list);
 922
 923 static void azx_add_card_list(struct azx *chip)
 924 {
 925         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 926         mutex_lock(&card_list_lock);
 927         list_add(&hda->list, &card_list);
 928         mutex_unlock(&card_list_lock);
 929 }
 930
 931 static void azx_del_card_list(struct azx *chip)
 932 {
 933         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 934         mutex_lock(&card_list_lock);
 935         list_del_init(&hda->list);
 936         mutex_unlock(&card_list_lock);
 937 }
 938
 939 /* trigger power-save check at writing parameter */
 940 static int param_set_xint(const char *val, const struct kernel_param *kp)
 941 {
 942         struct hda_intel *hda;
 943         struct azx *chip;
 944         int prev = power_save;
 945         int ret = param_set_int(val, kp);
 946
 947         if (ret || prev == power_save)
 948                 return ret;
 949
 950         mutex_lock(&card_list_lock);
 951         list_for_each_entry(hda, &card_list, list) {
 952                 chip = &hda->chip;
 953                 if (!hda->probe_continued || chip->disabled)
 954                         continue;
 955                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 956         }
 957         mutex_unlock(&card_list_lock);
 958         return 0;
 959 }
 960
 961 /*
 962  * power management
 963  */
 964 static bool azx_is_pm_ready(struct snd_card *card)
 965 {
 966         struct azx *chip;
 967         struct hda_intel *hda;
 968
 969         if (!card)
 970                 return false;
 971         chip = card->private_data;
 972         hda = container_of(chip, struct hda_intel, chip);
 973         if (chip->disabled || hda->init_failed || !chip->running)
 974                 return false;
 975         return true;
 976 }
 977
 978 static void __azx_runtime_suspend(struct azx *chip)
 979 {
 980         azx_stop_chip(chip);
 981         azx_enter_link_reset(chip);
 982         azx_clear_irq_pending(chip);
 983         display_power(chip, false);
 984 }
 985
 986 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 987 {
 988         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 989         struct hdac_bus *bus = azx_bus(chip);
 990         struct hda_codec *codec;
 991         int status;
 992
 993         display_power(chip, true);
 994         if (hda->need_i915_power)
 995                 snd_hdac_i915_set_bclk(bus);
 996
 997         /* Read STATESTS before controller reset */
 998         status = azx_readw(chip, STATESTS);
 999
1000         azx_init_pci(chip);
1001         hda_intel_init_chip(chip, true);
1002
1003         if (status && from_rt) {
1004                 list_for_each_codec(codec, &chip->bus)
1005                         if (status & (1 << codec->addr))
1006                                 schedule_delayed_work(&codec->jackpoll_work,
1007                                                       codec->jackpoll_interval);
1008         }
1009
1010         /* power down again for link-controlled chips */
1011         if (!hda->need_i915_power)
1012                 display_power(chip, false);
1013 }
1014
1015 #ifdef CONFIG_PM_SLEEP
1016 static int azx_suspend(struct device *dev)
1017 {
1018         struct snd_card *card = dev_get_drvdata(dev);
1019         struct azx *chip;
1020         struct hdac_bus *bus;
1021
1022         if (!azx_is_pm_ready(card))
1023                 return 0;
1024
1025         chip = card->private_data;
1026         bus = azx_bus(chip);
1027         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1028         __azx_runtime_suspend(chip);
1029         if (bus->irq >= 0) {
1030                 free_irq(bus->irq, chip);
1031                 bus->irq = -1;
1032         }
1033
1034         if (chip->msi)
1035                 pci_disable_msi(chip->pci);
1036
1037         trace_azx_suspend(chip);
1038         return 0;
1039 }
1040
1041 static int azx_resume(struct device *dev)
1042 {
1043         struct snd_card *card = dev_get_drvdata(dev);
1044         struct azx *chip;
1045
1046         if (!azx_is_pm_ready(card))
1047                 return 0;
1048
1049         chip = card->private_data;
1050         if (chip->msi)
1051                 if (pci_enable_msi(chip->pci) < 0)
1052                         chip->msi = 0;
1053         if (azx_acquire_irq(chip, 1) < 0)
1054                 return -EIO;
1055         __azx_runtime_resume(chip, false);
1056         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1057
1058         trace_azx_resume(chip);
1059         return 0;
1060 }
1061
1062 /* put codec down to D3 at hibernation for Intel SKL+;
1063  * otherwise BIOS may still access the codec and screw up the driver
1064  */
1065 static int azx_freeze_noirq(struct device *dev)
1066 {
1067         struct snd_card *card = dev_get_drvdata(dev);
1068         struct azx *chip = card->private_data;
1069         struct pci_dev *pci = to_pci_dev(dev);
1070
1071         if (chip->driver_type == AZX_DRIVER_SKL)
1072                 pci_set_power_state(pci, PCI_D3hot);
1073
1074         return 0;
1075 }
1076
1077 static int azx_thaw_noirq(struct device *dev)
1078 {
1079         struct snd_card *card = dev_get_drvdata(dev);
1080         struct azx *chip = card->private_data;
1081         struct pci_dev *pci = to_pci_dev(dev);
1082
1083         if (chip->driver_type == AZX_DRIVER_SKL)
1084                 pci_set_power_state(pci, PCI_D0);
1085
1086         return 0;
1087 }
1088 #endif /* CONFIG_PM_SLEEP */
1089
1090 static int azx_runtime_suspend(struct device *dev)
1091 {
1092         struct snd_card *card = dev_get_drvdata(dev);
1093         struct azx *chip;
1094
1095         if (!azx_is_pm_ready(card))
1096                 return 0;
1097         chip = card->private_data;
1098         if (!azx_has_pm_runtime(chip))
1099                 return 0;
1100
1101         /* enable controller wake up event */
1102         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1103                   STATESTS_INT_MASK);
1104
1105         __azx_runtime_suspend(chip);
1106         trace_azx_runtime_suspend(chip);
1107         return 0;
1108 }
1109
1110 static int azx_runtime_resume(struct device *dev)
1111 {
1112         struct snd_card *card = dev_get_drvdata(dev);
1113         struct azx *chip;
1114
1115         if (!azx_is_pm_ready(card))
1116                 return 0;
1117         chip = card->private_data;
1118         if (!azx_has_pm_runtime(chip))
1119                 return 0;
1120         __azx_runtime_resume(chip, true);
1121
1122         /* disable controller Wake Up event*/
1123         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1124                         ~STATESTS_INT_MASK);
1125
1126         trace_azx_runtime_resume(chip);
1127         return 0;
1128 }
1129
1130 static int azx_runtime_idle(struct device *dev)
1131 {
1132         struct snd_card *card = dev_get_drvdata(dev);
1133         struct azx *chip;
1134         struct hda_intel *hda;
1135
1136         if (!card)
1137                 return 0;
1138
1139         chip = card->private_data;
1140         hda = container_of(chip, struct hda_intel, chip);
1141         if (chip->disabled || hda->init_failed)
1142                 return 0;
1143
1144         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1145             azx_bus(chip)->codec_powered || !chip->running)
1146                 return -EBUSY;
1147
1148         /* ELD notification gets broken when HD-audio bus is off */
1149         if (needs_eld_notify_link(chip))
1150                 return -EBUSY;
1151
1152         return 0;
1153 }
1154
1155 static const struct dev_pm_ops azx_pm = {
1156         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1157 #ifdef CONFIG_PM_SLEEP
1158         .freeze_noirq = azx_freeze_noirq,
1159         .thaw_noirq = azx_thaw_noirq,
1160 #endif
1161         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1162 };
1163
1164 #define AZX_PM_OPS      &azx_pm
1165 #else
1166 #define azx_add_card_list(chip) /* NOP */
1167 #define azx_del_card_list(chip) /* NOP */
1168 #define AZX_PM_OPS      NULL
1169 #endif /* CONFIG_PM */
1170
1171
1172 static int azx_probe_continue(struct azx *chip);
1173
1174 #ifdef SUPPORT_VGA_SWITCHEROO
1175 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1176
1177 static void azx_vs_set_state(struct pci_dev *pci,
1178                              enum vga_switcheroo_state state)
1179 {
1180         struct snd_card *card = pci_get_drvdata(pci);
1181         struct azx *chip = card->private_data;
1182         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1183         struct hda_codec *codec;
1184         bool disabled;
1185
1186         wait_for_completion(&hda->probe_wait);
1187         if (hda->init_failed)
1188                 return;
1189
1190         disabled = (state == VGA_SWITCHEROO_OFF);
1191         if (chip->disabled == disabled)
1192                 return;
1193
1194         if (!hda->probe_continued) {
1195                 chip->disabled = disabled;
1196                 if (!disabled) {
1197                         dev_info(chip->card->dev,
1198                                  "Start delayed initialization\n");
1199                         if (azx_probe_continue(chip) < 0) {
1200                                 dev_err(chip->card->dev, "initialization error\n");
1201                                 hda->init_failed = true;
1202                         }
1203                 }
1204         } else {
1205                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1206                          disabled ? "Disabling" : "Enabling");
1207                 if (disabled) {
1208                         list_for_each_codec(codec, &chip->bus) {
1209                                 pm_runtime_suspend(hda_codec_dev(codec));
1210                                 pm_runtime_disable(hda_codec_dev(codec));
1211                         }
1212                         pm_runtime_suspend(card->dev);
1213                         pm_runtime_disable(card->dev);
1214                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1215                          * however we have no ACPI handle, so pci/acpi can't put us there,
1216                          * put ourselves there */
1217                         pci->current_state = PCI_D3cold;
1218                         chip->disabled = true;
1219                         if (snd_hda_lock_devices(&chip->bus))
1220                                 dev_warn(chip->card->dev,
1221                                          "Cannot lock devices!\n");
1222                 } else {
1223                         snd_hda_unlock_devices(&chip->bus);
1224                         chip->disabled = false;
1225                         pm_runtime_enable(card->dev);
1226                         list_for_each_codec(codec, &chip->bus) {
1227                                 pm_runtime_enable(hda_codec_dev(codec));
1228                                 pm_runtime_resume(hda_codec_dev(codec));
1229                         }
1230                 }
1231         }
1232 }
1233
1234 static bool azx_vs_can_switch(struct pci_dev *pci)
1235 {
1236         struct snd_card *card = pci_get_drvdata(pci);
1237         struct azx *chip = card->private_data;
1238         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1239
1240         wait_for_completion(&hda->probe_wait);
1241         if (hda->init_failed)
1242                 return false;
1243         if (chip->disabled || !hda->probe_continued)
1244                 return true;
1245         if (snd_hda_lock_devices(&chip->bus))
1246                 return false;
1247         snd_hda_unlock_devices(&chip->bus);
1248         return true;
1249 }
1250
1251 /*
1252  * The discrete GPU cannot power down unless the HDA controller runtime
1253  * suspends, so activate runtime PM on codecs even if power_save == 0.
1254  */
1255 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1256 {
1257         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1258         struct hda_codec *codec;
1259
1260         if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1261                 list_for_each_codec(codec, &chip->bus)
1262                         codec->auto_runtime_pm = 1;
1263                 /* reset the power save setup */
1264                 if (chip->running)
1265                         set_default_power_save(chip);
1266         }
1267 }
1268
1269 static void azx_vs_gpu_bound(struct pci_dev *pci,
1270                              enum vga_switcheroo_client_id client_id)
1271 {
1272         struct snd_card *card = pci_get_drvdata(pci);
1273         struct azx *chip = card->private_data;
1274
1275         if (client_id == VGA_SWITCHEROO_DIS)
1276                 chip->bus.keep_power = 0;
1277         setup_vga_switcheroo_runtime_pm(chip);
1278 }
1279
1280 static void init_vga_switcheroo(struct azx *chip)
1281 {
1282         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1283         struct pci_dev *p = get_bound_vga(chip->pci);
1284         struct pci_dev *parent;
1285         if (p) {
1286                 dev_info(chip->card->dev,
1287                          "Handle vga_switcheroo audio client\n");
1288                 hda->use_vga_switcheroo = 1;
1289
1290                 /* cleared in either gpu_bound op or codec probe, or when its
1291                  * upstream port has _PR3 (i.e. dGPU).
1292                  */
1293                 parent = pci_upstream_bridge(p);
1294                 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1295                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1296                 pci_dev_put(p);
1297         }
1298 }
1299
1300 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1301         .set_gpu_state = azx_vs_set_state,
1302         .can_switch = azx_vs_can_switch,
1303         .gpu_bound = azx_vs_gpu_bound,
1304 };
1305
1306 static int register_vga_switcheroo(struct azx *chip)
1307 {
1308         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1309         struct pci_dev *p;
1310         int err;
1311
1312         if (!hda->use_vga_switcheroo)
1313                 return 0;
1314
1315         p = get_bound_vga(chip->pci);
1316         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1317         pci_dev_put(p);
1318
1319         if (err < 0)
1320                 return err;
1321         hda->vga_switcheroo_registered = 1;
1322
1323         return 0;
1324 }
1325 #else
1326 #define init_vga_switcheroo(chip)               /* NOP */
1327 #define register_vga_switcheroo(chip)           0
1328 #define check_hdmi_disabled(pci)        false
1329 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1330 #endif /* SUPPORT_VGA_SWITCHER */
1331
1332 /*
1333  * destructor
1334  */
1335 static int azx_free(struct azx *chip)
1336 {
1337         struct pci_dev *pci = chip->pci;
1338         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1339         struct hdac_bus *bus = azx_bus(chip);
1340
1341         if (azx_has_pm_runtime(chip) && chip->running)
1342                 pm_runtime_get_noresume(&pci->dev);
1343         chip->running = 0;
1344
1345         azx_del_card_list(chip);
1346
1347         hda->init_failed = 1; /* to be sure */
1348         complete_all(&hda->probe_wait);
1349
1350         if (use_vga_switcheroo(hda)) {
1351                 if (chip->disabled && hda->probe_continued)
1352                         snd_hda_unlock_devices(&chip->bus);
1353                 if (hda->vga_switcheroo_registered)
1354                         vga_switcheroo_unregister_client(chip->pci);
1355         }
1356
1357         if (bus->chip_init) {
1358                 azx_clear_irq_pending(chip);
1359                 azx_stop_all_streams(chip);
1360                 azx_stop_chip(chip);
1361         }
1362
1363         if (bus->irq >= 0)
1364                 free_irq(bus->irq, (void*)chip);
1365         if (chip->msi)
1366                 pci_disable_msi(chip->pci);
1367         iounmap(bus->remap_addr);
1368
1369         azx_free_stream_pages(chip);
1370         azx_free_streams(chip);
1371         snd_hdac_bus_exit(bus);
1372
1373         if (chip->region_requested)
1374                 pci_release_regions(chip->pci);
1375
1376         pci_disable_device(chip->pci);
1377 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1378         release_firmware(chip->fw);
1379 #endif
1380         display_power(chip, false);
1381
1382         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1383                 snd_hdac_i915_exit(bus);
1384         kfree(hda);
1385
1386         return 0;
1387 }
1388
1389 static int azx_dev_disconnect(struct snd_device *device)
1390 {
1391         struct azx *chip = device->device_data;
1392         struct hdac_bus *bus = azx_bus(chip);
1393
1394         chip->bus.shutdown = 1;
1395         cancel_work_sync(&bus->unsol_work);
1396
1397         return 0;
1398 }
1399
1400 static int azx_dev_free(struct snd_device *device)
1401 {
1402         return azx_free(device->device_data);
1403 }
1404
1405 #ifdef SUPPORT_VGA_SWITCHEROO
1406 /*
1407  * Check of disabled HDMI controller by vga_switcheroo
1408  */
1409 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1410 {
1411         struct pci_dev *p;
1412
1413         /* check only discrete GPU */
1414         switch (pci->vendor) {
1415         case PCI_VENDOR_ID_ATI:
1416         case PCI_VENDOR_ID_AMD:
1417         case PCI_VENDOR_ID_NVIDIA:
1418                 if (pci->devfn == 1) {
1419                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1420                                                         pci->bus->number, 0);
1421                         if (p) {
1422                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1423                                         return p;
1424                                 pci_dev_put(p);
1425                         }
1426                 }
1427                 break;
1428         }
1429         return NULL;
1430 }
1431
1432 static bool check_hdmi_disabled(struct pci_dev *pci)
1433 {
1434         bool vga_inactive = false;
1435         struct pci_dev *p = get_bound_vga(pci);
1436
1437         if (p) {
1438                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1439                         vga_inactive = true;
1440                 pci_dev_put(p);
1441         }
1442         return vga_inactive;
1443 }
1444 #endif /* SUPPORT_VGA_SWITCHEROO */
1445
1446 /*
1447  * white/black-listing for position_fix
1448  */
1449 static struct snd_pci_quirk position_fix_list[] = {
1450         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1451         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1452         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1453         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1454         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1455         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1456         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1457         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1458         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1459         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1460         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1461         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1462         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1463         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1464         {}
1465 };
1466
1467 static int check_position_fix(struct azx *chip, int fix)
1468 {
1469         const struct snd_pci_quirk *q;
1470
1471         switch (fix) {
1472         case POS_FIX_AUTO:
1473         case POS_FIX_LPIB:
1474         case POS_FIX_POSBUF:
1475         case POS_FIX_VIACOMBO:
1476         case POS_FIX_COMBO:
1477         case POS_FIX_SKL:
1478         case POS_FIX_FIFO:
1479                 return fix;
1480         }
1481
1482         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1483         if (q) {
1484                 dev_info(chip->card->dev,
1485                          "position_fix set to %d for device %04x:%04x\n",
1486                          q->value, q->subvendor, q->subdevice);
1487                 return q->value;
1488         }
1489
1490         /* Check VIA/ATI HD Audio Controller exist */
1491         if (chip->driver_type == AZX_DRIVER_VIA) {
1492                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1493                 return POS_FIX_VIACOMBO;
1494         }
1495         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1496                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1497                 return POS_FIX_FIFO;
1498         }
1499         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1500                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1501                 return POS_FIX_LPIB;
1502         }
1503         if (chip->driver_type == AZX_DRIVER_SKL) {
1504                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1505                 return POS_FIX_SKL;
1506         }
1507         return POS_FIX_AUTO;
1508 }
1509
1510 static void assign_position_fix(struct azx *chip, int fix)
1511 {
1512         static azx_get_pos_callback_t callbacks[] = {
1513                 [POS_FIX_AUTO] = NULL,
1514                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1515                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1516                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1517                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1518                 [POS_FIX_SKL] = azx_get_pos_skl,
1519                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1520         };
1521
1522         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1523
1524         /* combo mode uses LPIB only for playback */
1525         if (fix == POS_FIX_COMBO)
1526                 chip->get_position[1] = NULL;
1527
1528         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1529             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1530                 chip->get_delay[0] = chip->get_delay[1] =
1531                         azx_get_delay_from_lpib;
1532         }
1533
1534         if (fix == POS_FIX_FIFO)
1535                 chip->get_delay[0] = chip->get_delay[1] =
1536                         azx_get_delay_from_fifo;
1537 }
1538
1539 /*
1540  * black-lists for probe_mask
1541  */
1542 static struct snd_pci_quirk probe_mask_list[] = {
1543         /* Thinkpad often breaks the controller communication when accessing
1544          * to the non-working (or non-existing) modem codec slot.
1545          */
1546         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1547         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1548         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1549         /* broken BIOS */
1550         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1551         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1552         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1553         /* forced codec slots */
1554         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1555         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1556         /* WinFast VP200 H (Teradici) user reported broken communication */
1557         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1558         {}
1559 };
1560
1561 #define AZX_FORCE_CODEC_MASK    0x100
1562
1563 static void check_probe_mask(struct azx *chip, int dev)
1564 {
1565         const struct snd_pci_quirk *q;
1566
1567         chip->codec_probe_mask = probe_mask[dev];
1568         if (chip->codec_probe_mask == -1) {
1569                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1570                 if (q) {
1571                         dev_info(chip->card->dev,
1572                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1573                                  q->value, q->subvendor, q->subdevice);
1574                         chip->codec_probe_mask = q->value;
1575                 }
1576         }
1577
1578         /* check forced option */
1579         if (chip->codec_probe_mask != -1 &&
1580             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1581                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1582                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1583                          (int)azx_bus(chip)->codec_mask);
1584         }
1585 }
1586
1587 /*
1588  * white/black-list for enable_msi
1589  */
1590 static struct snd_pci_quirk msi_black_list[] = {
1591         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1592         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1593         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1594         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1595         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1596         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1597         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1598         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1599         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1600         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1601         {}
1602 };
1603
1604 static void check_msi(struct azx *chip)
1605 {
1606         const struct snd_pci_quirk *q;
1607
1608         if (enable_msi >= 0) {
1609                 chip->msi = !!enable_msi;
1610                 return;
1611         }
1612         chip->msi = 1;  /* enable MSI as default */
1613         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1614         if (q) {
1615                 dev_info(chip->card->dev,
1616                          "msi for device %04x:%04x set to %d\n",
1617                          q->subvendor, q->subdevice, q->value);
1618                 chip->msi = q->value;
1619                 return;
1620         }
1621
1622         /* NVidia chipsets seem to cause troubles with MSI */
1623         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1624                 dev_info(chip->card->dev, "Disabling MSI\n");
1625                 chip->msi = 0;
1626         }
1627 }
1628
1629 /* check the snoop mode availability */
1630 static void azx_check_snoop_available(struct azx *chip)
1631 {
1632         int snoop = hda_snoop;
1633
1634         if (snoop >= 0) {
1635                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1636                          snoop ? "snoop" : "non-snoop");
1637                 chip->snoop = snoop;
1638                 chip->uc_buffer = !snoop;
1639                 return;
1640         }
1641
1642         snoop = true;
1643         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1644             chip->driver_type == AZX_DRIVER_VIA) {
1645                 /* force to non-snoop mode for a new VIA controller
1646                  * when BIOS is set
1647                  */
1648                 u8 val;
1649                 pci_read_config_byte(chip->pci, 0x42, &val);
1650                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1651                                       chip->pci->revision == 0x20))
1652                         snoop = false;
1653         }
1654
1655         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1656                 snoop = false;
1657
1658         chip->snoop = snoop;
1659         if (!snoop) {
1660                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1661                 /* C-Media requires non-cached pages only for CORB/RIRB */
1662                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1663                         chip->uc_buffer = true;
1664         }
1665 }
1666
1667 static void azx_probe_work(struct work_struct *work)
1668 {
1669         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1670         azx_probe_continue(&hda->chip);
1671 }
1672
1673 static int default_bdl_pos_adj(struct azx *chip)
1674 {
1675         /* some exceptions: Atoms seem problematic with value 1 */
1676         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1677                 switch (chip->pci->device) {
1678                 case 0x0f04: /* Baytrail */
1679                 case 0x2284: /* Braswell */
1680                         return 32;
1681                 }
1682         }
1683
1684         switch (chip->driver_type) {
1685         case AZX_DRIVER_ICH:
1686         case AZX_DRIVER_PCH:
1687                 return 1;
1688         default:
1689                 return 32;
1690         }
1691 }
1692
1693 /*
1694  * constructor
1695  */
1696 static const struct hda_controller_ops pci_hda_ops;
1697
1698 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1699                       int dev, unsigned int driver_caps,
1700                       struct azx **rchip)
1701 {
1702         static struct snd_device_ops ops = {
1703                 .dev_disconnect = azx_dev_disconnect,
1704                 .dev_free = azx_dev_free,
1705         };
1706         struct hda_intel *hda;
1707         struct azx *chip;
1708         int err;
1709
1710         *rchip = NULL;
1711
1712         err = pci_enable_device(pci);
1713         if (err < 0)
1714                 return err;
1715
1716         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1717         if (!hda) {
1718                 pci_disable_device(pci);
1719                 return -ENOMEM;
1720         }
1721
1722         chip = &hda->chip;
1723         mutex_init(&chip->open_mutex);
1724         chip->card = card;
1725         chip->pci = pci;
1726         chip->ops = &pci_hda_ops;
1727         chip->driver_caps = driver_caps;
1728         chip->driver_type = driver_caps & 0xff;
1729         check_msi(chip);
1730         chip->dev_index = dev;
1731         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1732                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1733         INIT_LIST_HEAD(&chip->pcm_list);
1734         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1735         INIT_LIST_HEAD(&hda->list);
1736         init_vga_switcheroo(chip);
1737         init_completion(&hda->probe_wait);
1738
1739         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1740
1741         check_probe_mask(chip, dev);
1742
1743         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1744                 chip->fallback_to_single_cmd = 1;
1745         else /* explicitly set to single_cmd or not */
1746                 chip->single_cmd = single_cmd;
1747
1748         azx_check_snoop_available(chip);
1749
1750         if (bdl_pos_adj[dev] < 0)
1751                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1752         else
1753                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1754
1755         err = azx_bus_init(chip, model[dev]);
1756         if (err < 0) {
1757                 kfree(hda);
1758                 pci_disable_device(pci);
1759                 return err;
1760         }
1761
1762         /* use the non-cached pages in non-snoop mode */
1763         if (!azx_snoop(chip))
1764                 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1765
1766         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1767         if (IS_CFL(pci) || IS_CNL(pci))
1768                 azx_bus(chip)->polling_mode = 1;
1769
1770         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1771                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1772                 chip->bus.needs_damn_long_delay = 1;
1773         }
1774
1775         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1776         if (err < 0) {
1777                 dev_err(card->dev, "Error creating device [card]!\n");
1778                 azx_free(chip);
1779                 return err;
1780         }
1781
1782         /* continue probing in work context as may trigger request module */
1783         INIT_WORK(&hda->probe_work, azx_probe_work);
1784
1785         *rchip = chip;
1786
1787         return 0;
1788 }
1789
1790 static int azx_first_init(struct azx *chip)
1791 {
1792         int dev = chip->dev_index;
1793         struct pci_dev *pci = chip->pci;
1794         struct snd_card *card = chip->card;
1795         struct hdac_bus *bus = azx_bus(chip);
1796         int err;
1797         unsigned short gcap;
1798         unsigned int dma_bits = 64;
1799
1800 #if BITS_PER_LONG != 64
1801         /* Fix up base address on ULI M5461 */
1802         if (chip->driver_type == AZX_DRIVER_ULI) {
1803                 u16 tmp3;
1804                 pci_read_config_word(pci, 0x40, &tmp3);
1805                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1806                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1807         }
1808 #endif
1809
1810         err = pci_request_regions(pci, "ICH HD audio");
1811         if (err < 0)
1812                 return err;
1813         chip->region_requested = 1;
1814
1815         bus->addr = pci_resource_start(pci, 0);
1816         bus->remap_addr = pci_ioremap_bar(pci, 0);
1817         if (bus->remap_addr == NULL) {
1818                 dev_err(card->dev, "ioremap error\n");
1819                 return -ENXIO;
1820         }
1821
1822         if (chip->driver_type == AZX_DRIVER_SKL)
1823                 snd_hdac_bus_parse_capabilities(bus);
1824
1825         /*
1826          * Some Intel CPUs has always running timer (ART) feature and
1827          * controller may have Global time sync reporting capability, so
1828          * check both of these before declaring synchronized time reporting
1829          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1830          */
1831         chip->gts_present = false;
1832
1833 #ifdef CONFIG_X86
1834         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1835                 chip->gts_present = true;
1836 #endif
1837
1838         if (chip->msi) {
1839                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1840                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1841                         pci->no_64bit_msi = true;
1842                 }
1843                 if (pci_enable_msi(pci) < 0)
1844                         chip->msi = 0;
1845         }
1846
1847         pci_set_master(pci);
1848         synchronize_irq(bus->irq);
1849
1850         gcap = azx_readw(chip, GCAP);
1851         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1852
1853         /* AMD devices support 40 or 48bit DMA, take the safe one */
1854         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1855                 dma_bits = 40;
1856
1857         /* disable SB600 64bit support for safety */
1858         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1859                 struct pci_dev *p_smbus;
1860                 dma_bits = 40;
1861                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1862                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1863                                          NULL);
1864                 if (p_smbus) {
1865                         if (p_smbus->revision < 0x30)
1866                                 gcap &= ~AZX_GCAP_64OK;
1867                         pci_dev_put(p_smbus);
1868                 }
1869         }
1870
1871         /* NVidia hardware normally only supports up to 40 bits of DMA */
1872         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1873                 dma_bits = 40;
1874
1875         /* disable 64bit DMA address on some devices */
1876         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1877                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1878                 gcap &= ~AZX_GCAP_64OK;
1879         }
1880
1881         /* disable buffer size rounding to 128-byte multiples if supported */
1882         if (align_buffer_size >= 0)
1883                 chip->align_buffer_size = !!align_buffer_size;
1884         else {
1885                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1886                         chip->align_buffer_size = 0;
1887                 else
1888                         chip->align_buffer_size = 1;
1889         }
1890
1891         /* allow 64bit DMA address if supported by H/W */
1892         if (!(gcap & AZX_GCAP_64OK))
1893                 dma_bits = 32;
1894         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1895                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1896         } else {
1897                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1898                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1899         }
1900
1901         /* read number of streams from GCAP register instead of using
1902          * hardcoded value
1903          */
1904         chip->capture_streams = (gcap >> 8) & 0x0f;
1905         chip->playback_streams = (gcap >> 12) & 0x0f;
1906         if (!chip->playback_streams && !chip->capture_streams) {
1907                 /* gcap didn't give any info, switching to old method */
1908
1909                 switch (chip->driver_type) {
1910                 case AZX_DRIVER_ULI:
1911                         chip->playback_streams = ULI_NUM_PLAYBACK;
1912                         chip->capture_streams = ULI_NUM_CAPTURE;
1913                         break;
1914                 case AZX_DRIVER_ATIHDMI:
1915                 case AZX_DRIVER_ATIHDMI_NS:
1916                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1917                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1918                         break;
1919                 case AZX_DRIVER_GENERIC:
1920                 default:
1921                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1922                         chip->capture_streams = ICH6_NUM_CAPTURE;
1923                         break;
1924                 }
1925         }
1926         chip->capture_index_offset = 0;
1927         chip->playback_index_offset = chip->capture_streams;
1928         chip->num_streams = chip->playback_streams + chip->capture_streams;
1929
1930         /* sanity check for the SDxCTL.STRM field overflow */
1931         if (chip->num_streams > 15 &&
1932             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1933                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1934                          "forcing separate stream tags", chip->num_streams);
1935                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1936         }
1937
1938         /* initialize streams */
1939         err = azx_init_streams(chip);
1940         if (err < 0)
1941                 return err;
1942
1943         err = azx_alloc_stream_pages(chip);
1944         if (err < 0)
1945                 return err;
1946
1947         /* initialize chip */
1948         azx_init_pci(chip);
1949
1950         snd_hdac_i915_set_bclk(bus);
1951
1952         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1953
1954         /* codec detection */
1955         if (!azx_bus(chip)->codec_mask) {
1956                 dev_err(card->dev, "no codecs found!\n");
1957                 return -ENODEV;
1958         }
1959
1960         if (azx_acquire_irq(chip, 0) < 0)
1961                 return -EBUSY;
1962
1963         strcpy(card->driver, "HDA-Intel");
1964         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1965                 sizeof(card->shortname));
1966         snprintf(card->longname, sizeof(card->longname),
1967                  "%s at 0x%lx irq %i",
1968                  card->shortname, bus->addr, bus->irq);
1969
1970         return 0;
1971 }
1972
1973 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1974 /* callback from request_firmware_nowait() */
1975 static void azx_firmware_cb(const struct firmware *fw, void *context)
1976 {
1977         struct snd_card *card = context;
1978         struct azx *chip = card->private_data;
1979         struct pci_dev *pci = chip->pci;
1980
1981         if (!fw) {
1982                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1983                 goto error;
1984         }
1985
1986         chip->fw = fw;
1987         if (!chip->disabled) {
1988                 /* continue probing */
1989                 if (azx_probe_continue(chip))
1990                         goto error;
1991         }
1992         return; /* OK */
1993
1994  error:
1995         snd_card_free(card);
1996         pci_set_drvdata(pci, NULL);
1997 }
1998 #endif
1999
2000 static int disable_msi_reset_irq(struct azx *chip)
2001 {
2002         struct hdac_bus *bus = azx_bus(chip);
2003         int err;
2004
2005         free_irq(bus->irq, chip);
2006         bus->irq = -1;
2007         pci_disable_msi(chip->pci);
2008         chip->msi = 0;
2009         err = azx_acquire_irq(chip, 1);
2010         if (err < 0)
2011                 return err;
2012
2013         return 0;
2014 }
2015
2016 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2017                              struct vm_area_struct *area)
2018 {
2019 #ifdef CONFIG_X86
2020         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2021         struct azx *chip = apcm->chip;
2022         if (chip->uc_buffer)
2023                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2024 #endif
2025 }
2026
2027 static const struct hda_controller_ops pci_hda_ops = {
2028         .disable_msi_reset_irq = disable_msi_reset_irq,
2029         .pcm_mmap_prepare = pcm_mmap_prepare,
2030         .position_check = azx_position_check,
2031 };
2032
2033 static int azx_probe(struct pci_dev *pci,
2034                      const struct pci_device_id *pci_id)
2035 {
2036         static int dev;
2037         struct snd_card *card;
2038         struct hda_intel *hda;
2039         struct azx *chip;
2040         bool schedule_probe;
2041         int err;
2042
2043         if (dev >= SNDRV_CARDS)
2044                 return -ENODEV;
2045         if (!enable[dev]) {
2046                 dev++;
2047                 return -ENOENT;
2048         }
2049
2050         /*
2051          * stop probe if another Intel's DSP driver should be activated
2052          */
2053         if (dsp_driver) {
2054                 err = snd_intel_dsp_driver_probe(pci);
2055                 if (err != SND_INTEL_DSP_DRIVER_ANY &&
2056                     err != SND_INTEL_DSP_DRIVER_LEGACY)
2057                         return -ENODEV;
2058         }
2059
2060         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2061                            0, &card);
2062         if (err < 0) {
2063                 dev_err(&pci->dev, "Error creating card!\n");
2064                 return err;
2065         }
2066
2067         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2068         if (err < 0)
2069                 goto out_free;
2070         card->private_data = chip;
2071         hda = container_of(chip, struct hda_intel, chip);
2072
2073         pci_set_drvdata(pci, card);
2074
2075         err = register_vga_switcheroo(chip);
2076         if (err < 0) {
2077                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2078                 goto out_free;
2079         }
2080
2081         if (check_hdmi_disabled(pci)) {
2082                 dev_info(card->dev, "VGA controller is disabled\n");
2083                 dev_info(card->dev, "Delaying initialization\n");
2084                 chip->disabled = true;
2085         }
2086
2087         schedule_probe = !chip->disabled;
2088
2089 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2090         if (patch[dev] && *patch[dev]) {
2091                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2092                          patch[dev]);
2093                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2094                                               &pci->dev, GFP_KERNEL, card,
2095                                               azx_firmware_cb);
2096                 if (err < 0)
2097                         goto out_free;
2098                 schedule_probe = false; /* continued in azx_firmware_cb() */
2099         }
2100 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2101
2102 #ifndef CONFIG_SND_HDA_I915
2103         if (CONTROLLER_IN_GPU(pci))
2104                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2105 #endif
2106
2107         if (schedule_probe)
2108                 schedule_work(&hda->probe_work);
2109
2110         dev++;
2111         if (chip->disabled)
2112                 complete_all(&hda->probe_wait);
2113         return 0;
2114
2115 out_free:
2116         snd_card_free(card);
2117         return err;
2118 }
2119
2120 #ifdef CONFIG_PM
2121 /* On some boards setting power_save to a non 0 value leads to clicking /
2122  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2123  * figure out how to avoid these sounds, but that is not always feasible.
2124  * So we keep a list of devices where we disable powersaving as its known
2125  * to causes problems on these devices.
2126  */
2127 static struct snd_pci_quirk power_save_blacklist[] = {
2128         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2129         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2130         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2131         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2132         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2133         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2134         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2135         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2136         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2137         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2138         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2139         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2140         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2141         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2142         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2143         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2144         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2145         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2146         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2147         /* https://bugs.launchpad.net/bugs/1821663 */
2148         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2149         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2150         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2151         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2152         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2153         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2154         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2155         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2156         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2157         /* https://bugs.launchpad.net/bugs/1821663 */
2158         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2159         {}
2160 };
2161 #endif /* CONFIG_PM */
2162
2163 static void set_default_power_save(struct azx *chip)
2164 {
2165         int val = power_save;
2166
2167 #ifdef CONFIG_PM
2168         if (pm_blacklist) {
2169                 const struct snd_pci_quirk *q;
2170
2171                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2172                 if (q && val) {
2173                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2174                                  q->subvendor, q->subdevice);
2175                         val = 0;
2176                 }
2177         }
2178 #endif /* CONFIG_PM */
2179         snd_hda_set_power_save(&chip->bus, val * 1000);
2180 }
2181
2182 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2183 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2184         [AZX_DRIVER_NVIDIA] = 8,
2185         [AZX_DRIVER_TERA] = 1,
2186 };
2187
2188 static int azx_probe_continue(struct azx *chip)
2189 {
2190         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2191         struct hdac_bus *bus = azx_bus(chip);
2192         struct pci_dev *pci = chip->pci;
2193         int dev = chip->dev_index;
2194         int err;
2195
2196         to_hda_bus(bus)->bus_probing = 1;
2197         hda->probe_continued = 1;
2198
2199         /* bind with i915 if needed */
2200         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2201                 err = snd_hdac_i915_init(bus);
2202                 if (err < 0) {
2203                         /* if the controller is bound only with HDMI/DP
2204                          * (for HSW and BDW), we need to abort the probe;
2205                          * for other chips, still continue probing as other
2206                          * codecs can be on the same link.
2207                          */
2208                         if (CONTROLLER_IN_GPU(pci)) {
2209                                 dev_err(chip->card->dev,
2210                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2211                                 goto out_free;
2212                         } else {
2213                                 /* don't bother any longer */
2214                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2215                         }
2216                 }
2217
2218                 /* HSW/BDW controllers need this power */
2219                 if (CONTROLLER_IN_GPU(pci))
2220                         hda->need_i915_power = 1;
2221         }
2222
2223         /* Request display power well for the HDA controller or codec. For
2224          * Haswell/Broadwell, both the display HDA controller and codec need
2225          * this power. For other platforms, like Baytrail/Braswell, only the
2226          * display codec needs the power and it can be released after probe.
2227          */
2228         display_power(chip, true);
2229
2230         err = azx_first_init(chip);
2231         if (err < 0)
2232                 goto out_free;
2233
2234 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2235         chip->beep_mode = beep_mode[dev];
2236 #endif
2237
2238         /* create codec instances */
2239         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2240         if (err < 0)
2241                 goto out_free;
2242
2243 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2244         if (chip->fw) {
2245                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2246                                          chip->fw->data);
2247                 if (err < 0)
2248                         goto out_free;
2249 #ifndef CONFIG_PM
2250                 release_firmware(chip->fw); /* no longer needed */
2251                 chip->fw = NULL;
2252 #endif
2253         }
2254 #endif
2255         if ((probe_only[dev] & 1) == 0) {
2256                 err = azx_codec_configure(chip);
2257                 if (err < 0)
2258                         goto out_free;
2259         }
2260
2261         err = snd_card_register(chip->card);
2262         if (err < 0)
2263                 goto out_free;
2264
2265         setup_vga_switcheroo_runtime_pm(chip);
2266
2267         chip->running = 1;
2268         azx_add_card_list(chip);
2269
2270         set_default_power_save(chip);
2271
2272         if (azx_has_pm_runtime(chip))
2273                 pm_runtime_put_autosuspend(&pci->dev);
2274
2275 out_free:
2276         if (err < 0 || !hda->need_i915_power)
2277                 display_power(chip, false);
2278         if (err < 0)
2279                 hda->init_failed = 1;
2280         complete_all(&hda->probe_wait);
2281         to_hda_bus(bus)->bus_probing = 0;
2282         return err;
2283 }
2284
2285 static void azx_remove(struct pci_dev *pci)
2286 {
2287         struct snd_card *card = pci_get_drvdata(pci);
2288         struct azx *chip;
2289         struct hda_intel *hda;
2290
2291         if (card) {
2292                 /* cancel the pending probing work */
2293                 chip = card->private_data;
2294                 hda = container_of(chip, struct hda_intel, chip);
2295                 /* FIXME: below is an ugly workaround.
2296                  * Both device_release_driver() and driver_probe_device()
2297                  * take *both* the device's and its parent's lock before
2298                  * calling the remove() and probe() callbacks.  The codec
2299                  * probe takes the locks of both the codec itself and its
2300                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2301                  * the PCI controller is unbound, it takes its lock, too
2302                  * ==> ouch, a deadlock!
2303                  * As a workaround, we unlock temporarily here the controller
2304                  * device during cancel_work_sync() call.
2305                  */
2306                 device_unlock(&pci->dev);
2307                 cancel_work_sync(&hda->probe_work);
2308                 device_lock(&pci->dev);
2309
2310                 snd_card_free(card);
2311         }
2312 }
2313
2314 static void azx_shutdown(struct pci_dev *pci)
2315 {
2316         struct snd_card *card = pci_get_drvdata(pci);
2317         struct azx *chip;
2318
2319         if (!card)
2320                 return;
2321         chip = card->private_data;
2322         if (chip && chip->running)
2323                 azx_stop_chip(chip);
2324 }
2325
2326 /* PCI IDs */
2327 static const struct pci_device_id azx_ids[] = {
2328         /* CPT */
2329         { PCI_DEVICE(0x8086, 0x1c20),
2330           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2331         /* PBG */
2332         { PCI_DEVICE(0x8086, 0x1d20),
2333           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2334         /* Panther Point */
2335         { PCI_DEVICE(0x8086, 0x1e20),
2336           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2337         /* Lynx Point */
2338         { PCI_DEVICE(0x8086, 0x8c20),
2339           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2340         /* 9 Series */
2341         { PCI_DEVICE(0x8086, 0x8ca0),
2342           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2343         /* Wellsburg */
2344         { PCI_DEVICE(0x8086, 0x8d20),
2345           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2346         { PCI_DEVICE(0x8086, 0x8d21),
2347           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2348         /* Lewisburg */
2349         { PCI_DEVICE(0x8086, 0xa1f0),
2350           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2351         { PCI_DEVICE(0x8086, 0xa270),
2352           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2353         /* Lynx Point-LP */
2354         { PCI_DEVICE(0x8086, 0x9c20),
2355           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2356         /* Lynx Point-LP */
2357         { PCI_DEVICE(0x8086, 0x9c21),
2358           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2359         /* Wildcat Point-LP */
2360         { PCI_DEVICE(0x8086, 0x9ca0),
2361           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2362         /* Sunrise Point */
2363         { PCI_DEVICE(0x8086, 0xa170),
2364           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2365         /* Sunrise Point-LP */
2366         { PCI_DEVICE(0x8086, 0x9d70),
2367           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2368         /* Kabylake */
2369         { PCI_DEVICE(0x8086, 0xa171),
2370           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2371         /* Kabylake-LP */
2372         { PCI_DEVICE(0x8086, 0x9d71),
2373           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2374         /* Kabylake-H */
2375         { PCI_DEVICE(0x8086, 0xa2f0),
2376           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2377         /* Coffelake */
2378         { PCI_DEVICE(0x8086, 0xa348),
2379           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2380         /* Cannonlake */
2381         { PCI_DEVICE(0x8086, 0x9dc8),
2382           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2383         /* CometLake-LP */
2384         { PCI_DEVICE(0x8086, 0x02C8),
2385           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2386         /* CometLake-H */
2387         { PCI_DEVICE(0x8086, 0x06C8),
2388           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2389         /* CometLake-S */
2390         { PCI_DEVICE(0x8086, 0xa3f0),
2391           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2392         /* Icelake */
2393         { PCI_DEVICE(0x8086, 0x34c8),
2394           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2395         /* Jasperlake */
2396         { PCI_DEVICE(0x8086, 0x38c8),
2397           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2398         /* Tigerlake */
2399         { PCI_DEVICE(0x8086, 0xa0c8),
2400           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2401         /* Elkhart Lake */
2402         { PCI_DEVICE(0x8086, 0x4b55),
2403           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2404         /* Broxton-P(Apollolake) */
2405         { PCI_DEVICE(0x8086, 0x5a98),
2406           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2407         /* Broxton-T */
2408         { PCI_DEVICE(0x8086, 0x1a98),
2409           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2410         /* Gemini-Lake */
2411         { PCI_DEVICE(0x8086, 0x3198),
2412           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2413         /* Haswell */
2414         { PCI_DEVICE(0x8086, 0x0a0c),
2415           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2416         { PCI_DEVICE(0x8086, 0x0c0c),
2417           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2418         { PCI_DEVICE(0x8086, 0x0d0c),
2419           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2420         /* Broadwell */
2421         { PCI_DEVICE(0x8086, 0x160c),
2422           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2423         /* 5 Series/3400 */
2424         { PCI_DEVICE(0x8086, 0x3b56),
2425           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2426         /* Poulsbo */
2427         { PCI_DEVICE(0x8086, 0x811b),
2428           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2429         /* Oaktrail */
2430         { PCI_DEVICE(0x8086, 0x080a),
2431           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2432         /* BayTrail */
2433         { PCI_DEVICE(0x8086, 0x0f04),
2434           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2435         /* Braswell */
2436         { PCI_DEVICE(0x8086, 0x2284),
2437           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2438         /* ICH6 */
2439         { PCI_DEVICE(0x8086, 0x2668),
2440           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2441         /* ICH7 */
2442         { PCI_DEVICE(0x8086, 0x27d8),
2443           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2444         /* ESB2 */
2445         { PCI_DEVICE(0x8086, 0x269a),
2446           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2447         /* ICH8 */
2448         { PCI_DEVICE(0x8086, 0x284b),
2449           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2450         /* ICH9 */
2451         { PCI_DEVICE(0x8086, 0x293e),
2452           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2453         /* ICH9 */
2454         { PCI_DEVICE(0x8086, 0x293f),
2455           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2456         /* ICH10 */
2457         { PCI_DEVICE(0x8086, 0x3a3e),
2458           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2459         /* ICH10 */
2460         { PCI_DEVICE(0x8086, 0x3a6e),
2461           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2462         /* Generic Intel */
2463         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2464           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2465           .class_mask = 0xffffff,
2466           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2467         /* ATI SB 450/600/700/800/900 */
2468         { PCI_DEVICE(0x1002, 0x437b),
2469           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2470         { PCI_DEVICE(0x1002, 0x4383),
2471           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2472         /* AMD Hudson */
2473         { PCI_DEVICE(0x1022, 0x780d),
2474           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2475         /* AMD, X370 & co */
2476         { PCI_DEVICE(0x1022, 0x1457),
2477           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2478         /* AMD, X570 & co */
2479         { PCI_DEVICE(0x1022, 0x1487),
2480           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2481         /* AMD Stoney */
2482         { PCI_DEVICE(0x1022, 0x157a),
2483           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2484                          AZX_DCAPS_PM_RUNTIME },
2485         /* AMD Raven */
2486         { PCI_DEVICE(0x1022, 0x15e3),
2487           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2488         /* ATI HDMI */
2489         { PCI_DEVICE(0x1002, 0x0002),
2490           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2491         { PCI_DEVICE(0x1002, 0x1308),
2492           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2493         { PCI_DEVICE(0x1002, 0x157a),
2494           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2495         { PCI_DEVICE(0x1002, 0x15b3),
2496           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2497         { PCI_DEVICE(0x1002, 0x793b),
2498           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2499         { PCI_DEVICE(0x1002, 0x7919),
2500           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2501         { PCI_DEVICE(0x1002, 0x960f),
2502           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2503         { PCI_DEVICE(0x1002, 0x970f),
2504           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2505         { PCI_DEVICE(0x1002, 0x9840),
2506           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2507         { PCI_DEVICE(0x1002, 0xaa00),
2508           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2509         { PCI_DEVICE(0x1002, 0xaa08),
2510           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2511         { PCI_DEVICE(0x1002, 0xaa10),
2512           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2513         { PCI_DEVICE(0x1002, 0xaa18),
2514           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2515         { PCI_DEVICE(0x1002, 0xaa20),
2516           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2517         { PCI_DEVICE(0x1002, 0xaa28),
2518           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2519         { PCI_DEVICE(0x1002, 0xaa30),
2520           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2521         { PCI_DEVICE(0x1002, 0xaa38),
2522           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2523         { PCI_DEVICE(0x1002, 0xaa40),
2524           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2525         { PCI_DEVICE(0x1002, 0xaa48),
2526           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2527         { PCI_DEVICE(0x1002, 0xaa50),
2528           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2529         { PCI_DEVICE(0x1002, 0xaa58),
2530           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2531         { PCI_DEVICE(0x1002, 0xaa60),
2532           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2533         { PCI_DEVICE(0x1002, 0xaa68),
2534           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2535         { PCI_DEVICE(0x1002, 0xaa80),
2536           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2537         { PCI_DEVICE(0x1002, 0xaa88),
2538           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2539         { PCI_DEVICE(0x1002, 0xaa90),
2540           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2541         { PCI_DEVICE(0x1002, 0xaa98),
2542           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2543         { PCI_DEVICE(0x1002, 0x9902),
2544           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2545         { PCI_DEVICE(0x1002, 0xaaa0),
2546           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2547         { PCI_DEVICE(0x1002, 0xaaa8),
2548           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2549         { PCI_DEVICE(0x1002, 0xaab0),
2550           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2551         { PCI_DEVICE(0x1002, 0xaac0),
2552           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2553         { PCI_DEVICE(0x1002, 0xaac8),
2554           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2555         { PCI_DEVICE(0x1002, 0xaad8),
2556           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2557         { PCI_DEVICE(0x1002, 0xaae8),
2558           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2559         { PCI_DEVICE(0x1002, 0xaae0),
2560           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2561         { PCI_DEVICE(0x1002, 0xaaf0),
2562           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2563         /* VIA VT8251/VT8237A */
2564         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2565         /* VIA GFX VT7122/VX900 */
2566         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2567         /* VIA GFX VT6122/VX11 */
2568         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2569         /* SIS966 */
2570         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2571         /* ULI M5461 */
2572         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2573         /* NVIDIA MCP */
2574         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2575           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2576           .class_mask = 0xffffff,
2577           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2578         /* Teradici */
2579         { PCI_DEVICE(0x6549, 0x1200),
2580           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2581         { PCI_DEVICE(0x6549, 0x2200),
2582           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2583         /* Creative X-Fi (CA0110-IBG) */
2584         /* CTHDA chips */
2585         { PCI_DEVICE(0x1102, 0x0010),
2586           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2587         { PCI_DEVICE(0x1102, 0x0012),
2588           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2589 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2590         /* the following entry conflicts with snd-ctxfi driver,
2591          * as ctxfi driver mutates from HD-audio to native mode with
2592          * a special command sequence.
2593          */
2594         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2595           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2596           .class_mask = 0xffffff,
2597           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2598           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2599 #else
2600         /* this entry seems still valid -- i.e. without emu20kx chip */
2601         { PCI_DEVICE(0x1102, 0x0009),
2602           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2603           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2604 #endif
2605         /* CM8888 */
2606         { PCI_DEVICE(0x13f6, 0x5011),
2607           .driver_data = AZX_DRIVER_CMEDIA |
2608           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2609         /* Vortex86MX */
2610         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2611         /* VMware HDAudio */
2612         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2613         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2614         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2615           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2616           .class_mask = 0xffffff,
2617           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2618         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2619           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2620           .class_mask = 0xffffff,
2621           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2622         /* Zhaoxin */
2623         { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2624         { 0, }
2625 };
2626 MODULE_DEVICE_TABLE(pci, azx_ids);
2627
2628 /* pci_driver definition */
2629 static struct pci_driver azx_driver = {
2630         .name = KBUILD_MODNAME,
2631         .id_table = azx_ids,
2632         .probe = azx_probe,
2633         .remove = azx_remove,
2634         .shutdown = azx_shutdown,
2635         .driver = {
2636                 .pm = AZX_PM_OPS,
2637         },
2638 };
2639
2640 module_pci_driver(azx_driver);