sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38
  39 #ifdef CONFIG_X86
  40 /* for snoop control */
  41 #include <asm/pgtable.h>
  42 #include <asm/set_memory.h>
  43 #include <asm/cpufeature.h>
  44 #endif
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include <sound/hdaudio.h>
  48 #include <sound/hda_i915.h>
  49 #include <sound/intel-nhlt.h>
  50 #include <linux/vgaarb.h>
  51 #include <linux/vga_switcheroo.h>
  52 #include <linux/firmware.h>
  53 #include <sound/hda_codec.h>
  54 #include "hda_controller.h"
  55 #include "hda_intel.h"
  56
  57 #define CREATE_TRACE_POINTS
  58 #include "hda_intel_trace.h"
  59
  60 /* position fix mode */
  61 enum {
  62         POS_FIX_AUTO,
  63         POS_FIX_LPIB,
  64         POS_FIX_POSBUF,
  65         POS_FIX_VIACOMBO,
  66         POS_FIX_COMBO,
  67         POS_FIX_SKL,
  68 };
  69
  70 /* Defines for ATI HD Audio support in SB450 south bridge */
  71 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  72 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  73
  74 /* Defines for Nvidia HDA support */
  75 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  76 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  77 #define NVIDIA_HDA_ISTRM_COH          0x4d
  78 #define NVIDIA_HDA_OSTRM_COH          0x4c
  79 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  80
  81 /* Defines for Intel SCH HDA snoop control */
  82 #define INTEL_HDA_CGCTL  0x48
  83 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  84 #define INTEL_SCH_HDA_DEVC      0x78
  85 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  86
  87 /* Define IN stream 0 FIFO size offset in VIA controller */
  88 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
  89 /* Define VIA HD Audio Device ID*/
  90 #define VIA_HDAC_DEVICE_ID              0x3288
  91
  92 /* max number of SDs */
  93 /* ICH, ATI and VIA have 4 playback and 4 capture */
  94 #define ICH6_NUM_CAPTURE        4
  95 #define ICH6_NUM_PLAYBACK       4
  96
  97 /* ULI has 6 playback and 5 capture */
  98 #define ULI_NUM_CAPTURE         5
  99 #define ULI_NUM_PLAYBACK        6
 100
 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 102 #define ATIHDMI_NUM_CAPTURE     0
 103 #define ATIHDMI_NUM_PLAYBACK    8
 104
 105 /* TERA has 4 playback and 3 capture */
 106 #define TERA_NUM_CAPTURE        3
 107 #define TERA_NUM_PLAYBACK       4
 108
 109
 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 113 static char *model[SNDRV_CARDS];
 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 117 static int probe_only[SNDRV_CARDS];
 118 static int jackpoll_ms[SNDRV_CARDS];
 119 static int single_cmd = -1;
 120 static int enable_msi = -1;
 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 122 static char *patch[SNDRV_CARDS];
 123 #endif
 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 126                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 127 #endif
 128 static bool dmic_detect = IS_ENABLED(CONFIG_SND_HDA_INTEL_DETECT_DMIC);
 129
 130 module_param_array(index, int, NULL, 0444);
 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 132 module_param_array(id, charp, NULL, 0444);
 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 134 module_param_array(enable, bool, NULL, 0444);
 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 136 module_param_array(model, charp, NULL, 0444);
 137 MODULE_PARM_DESC(model, "Use the given board model.");
 138 module_param_array(position_fix, int, NULL, 0444);
 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 140                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
 141 module_param_array(bdl_pos_adj, int, NULL, 0644);
 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 143 module_param_array(probe_mask, int, NULL, 0444);
 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 145 module_param_array(probe_only, int, NULL, 0444);
 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 147 module_param_array(jackpoll_ms, int, NULL, 0444);
 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 149 module_param(single_cmd, bint, 0444);
 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 151                  "(for debugging only).");
 152 module_param(enable_msi, bint, 0444);
 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 155 module_param_array(patch, charp, NULL, 0444);
 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 157 #endif
 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 159 module_param_array(beep_mode, bool, NULL, 0444);
 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 161                             "(0=off, 1=on) (default=1).");
 162 #endif
 163 module_param(dmic_detect, bool, 0444);
 164 MODULE_PARM_DESC(dmic_detect, "DMIC detect on SKL+ platforms");
 165
 166 #ifdef CONFIG_PM
 167 static int param_set_xint(const char *val, const struct kernel_param *kp);
 168 static const struct kernel_param_ops param_ops_xint = {
 169         .set = param_set_xint,
 170         .get = param_get_int,
 171 };
 172 #define param_check_xint param_check_int
 173
 174 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 175 module_param(power_save, xint, 0644);
 176 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 177                  "(in second, 0 = disable).");
 178
 179 static bool pm_blacklist = true;
 180 module_param(pm_blacklist, bool, 0644);
 181 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 182
 183 /* reset the HD-audio controller in power save mode.
 184  * this may give more power-saving, but will take longer time to
 185  * wake up.
 186  */
 187 static bool power_save_controller = 1;
 188 module_param(power_save_controller, bool, 0644);
 189 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 190 #else
 191 #define power_save      0
 192 #endif /* CONFIG_PM */
 193
 194 static int align_buffer_size = -1;
 195 module_param(align_buffer_size, bint, 0644);
 196 MODULE_PARM_DESC(align_buffer_size,
 197                 "Force buffer and period sizes to be multiple of 128 bytes.");
 198
 199 #ifdef CONFIG_X86
 200 static int hda_snoop = -1;
 201 module_param_named(snoop, hda_snoop, bint, 0444);
 202 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 203 #else
 204 #define hda_snoop               true
 205 #endif
 206
 207
 208 MODULE_LICENSE("GPL");
 209 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 210                          "{Intel, ICH6M},"
 211                          "{Intel, ICH7},"
 212                          "{Intel, ESB2},"
 213                          "{Intel, ICH8},"
 214                          "{Intel, ICH9},"
 215                          "{Intel, ICH10},"
 216                          "{Intel, PCH},"
 217                          "{Intel, CPT},"
 218                          "{Intel, PPT},"
 219                          "{Intel, LPT},"
 220                          "{Intel, LPT_LP},"
 221                          "{Intel, WPT_LP},"
 222                          "{Intel, SPT},"
 223                          "{Intel, SPT_LP},"
 224                          "{Intel, HPT},"
 225                          "{Intel, PBG},"
 226                          "{Intel, SCH},"
 227                          "{ATI, SB450},"
 228                          "{ATI, SB600},"
 229                          "{ATI, RS600},"
 230                          "{ATI, RS690},"
 231                          "{ATI, RS780},"
 232                          "{ATI, R600},"
 233                          "{ATI, RV630},"
 234                          "{ATI, RV610},"
 235                          "{ATI, RV670},"
 236                          "{ATI, RV635},"
 237                          "{ATI, RV620},"
 238                          "{ATI, RV770},"
 239                          "{VIA, VT8251},"
 240                          "{VIA, VT8237A},"
 241                          "{SiS, SIS966},"
 242                          "{ULI, M5461}}");
 243 MODULE_DESCRIPTION("Intel HDA driver");
 244
 245 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 246 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 247 #define SUPPORT_VGA_SWITCHEROO
 248 #endif
 249 #endif
 250
 251
 252 /*
 253  */
 254
 255 /* driver types */
 256 enum {
 257         AZX_DRIVER_ICH,
 258         AZX_DRIVER_PCH,
 259         AZX_DRIVER_SCH,
 260         AZX_DRIVER_SKL,
 261         AZX_DRIVER_HDMI,
 262         AZX_DRIVER_ATI,
 263         AZX_DRIVER_ATIHDMI,
 264         AZX_DRIVER_ATIHDMI_NS,
 265         AZX_DRIVER_VIA,
 266         AZX_DRIVER_SIS,
 267         AZX_DRIVER_ULI,
 268         AZX_DRIVER_NVIDIA,
 269         AZX_DRIVER_TERA,
 270         AZX_DRIVER_CTX,
 271         AZX_DRIVER_CTHDA,
 272         AZX_DRIVER_CMEDIA,
 273         AZX_DRIVER_GENERIC,
 274         AZX_NUM_DRIVERS, /* keep this as last entry */
 275 };
 276
 277 #define azx_get_snoop_type(chip) \
 278         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 279 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 280
 281 /* quirks for old Intel chipsets */
 282 #define AZX_DCAPS_INTEL_ICH \
 283         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 284
 285 /* quirks for Intel PCH */
 286 #define AZX_DCAPS_INTEL_PCH_BASE \
 287         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 288          AZX_DCAPS_SNOOP_TYPE(SCH))
 289
 290 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 291 #define AZX_DCAPS_INTEL_PCH_NOPM \
 292         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 293
 294 /* PCH for HSW/BDW; with runtime PM */
 295 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 296 #define AZX_DCAPS_INTEL_PCH \
 297         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 298
 299 /* HSW HDMI */
 300 #define AZX_DCAPS_INTEL_HASWELL \
 301         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 302          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 303          AZX_DCAPS_SNOOP_TYPE(SCH))
 304
 305 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 306 #define AZX_DCAPS_INTEL_BROADWELL \
 307         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 308          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 309          AZX_DCAPS_SNOOP_TYPE(SCH))
 310
 311 #define AZX_DCAPS_INTEL_BAYTRAIL \
 312         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 313
 314 #define AZX_DCAPS_INTEL_BRASWELL \
 315         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 316          AZX_DCAPS_I915_COMPONENT)
 317
 318 #define AZX_DCAPS_INTEL_SKYLAKE \
 319         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 320          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 321
 322 #define AZX_DCAPS_INTEL_BROXTON \
 323         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 324          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 325
 326 /* quirks for ATI SB / AMD Hudson */
 327 #define AZX_DCAPS_PRESET_ATI_SB \
 328         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 329          AZX_DCAPS_SNOOP_TYPE(ATI))
 330
 331 /* quirks for ATI/AMD HDMI */
 332 #define AZX_DCAPS_PRESET_ATI_HDMI \
 333         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 334          AZX_DCAPS_NO_MSI64)
 335
 336 /* quirks for ATI HDMI with snoop off */
 337 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 338         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 339
 340 /* quirks for Nvidia */
 341 #define AZX_DCAPS_PRESET_NVIDIA \
 342         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 343          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 344
 345 #define AZX_DCAPS_PRESET_CTHDA \
 346         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 347          AZX_DCAPS_NO_64BIT |\
 348          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 349
 350 /*
 351  * vga_switcheroo support
 352  */
 353 #ifdef SUPPORT_VGA_SWITCHEROO
 354 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 355 #define needs_eld_notify_link(chip)     ((chip)->need_eld_notify_link)
 356 #else
 357 #define use_vga_switcheroo(chip)        0
 358 #define needs_eld_notify_link(chip)     false
 359 #endif
 360
 361 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 362                                         ((pci)->device == 0x0c0c) || \
 363                                         ((pci)->device == 0x0d0c) || \
 364                                         ((pci)->device == 0x160c))
 365
 366 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 367 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 368 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 369
 370 static char *driver_short_names[] = {
 371         [AZX_DRIVER_ICH] = "HDA Intel",
 372         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 373         [AZX_DRIVER_SCH] = "HDA Intel MID",
 374         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 375         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 376         [AZX_DRIVER_ATI] = "HDA ATI SB",
 377         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 378         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 379         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 380         [AZX_DRIVER_SIS] = "HDA SIS966",
 381         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 382         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 383         [AZX_DRIVER_TERA] = "HDA Teradici",
 384         [AZX_DRIVER_CTX] = "HDA Creative",
 385         [AZX_DRIVER_CTHDA] = "HDA Creative",
 386         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 387         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 388 };
 389
 390 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 391 static void set_default_power_save(struct azx *chip);
 392
 393 /*
 394  * initialize the PCI registers
 395  */
 396 /* update bits in a PCI register byte */
 397 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 398                             unsigned char mask, unsigned char val)
 399 {
 400         unsigned char data;
 401
 402         pci_read_config_byte(pci, reg, &data);
 403         data &= ~mask;
 404         data |= (val & mask);
 405         pci_write_config_byte(pci, reg, data);
 406 }
 407
 408 static void azx_init_pci(struct azx *chip)
 409 {
 410         int snoop_type = azx_get_snoop_type(chip);
 411
 412         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 413          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 414          * Ensuring these bits are 0 clears playback static on some HD Audio
 415          * codecs.
 416          * The PCI register TCSEL is defined in the Intel manuals.
 417          */
 418         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 419                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 420                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 421         }
 422
 423         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 424          * we need to enable snoop.
 425          */
 426         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 427                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 428                         azx_snoop(chip));
 429                 update_pci_byte(chip->pci,
 430                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 431                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 432         }
 433
 434         /* For NVIDIA HDA, enable snoop */
 435         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 436                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 437                         azx_snoop(chip));
 438                 update_pci_byte(chip->pci,
 439                                 NVIDIA_HDA_TRANSREG_ADDR,
 440                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 441                 update_pci_byte(chip->pci,
 442                                 NVIDIA_HDA_ISTRM_COH,
 443                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 444                 update_pci_byte(chip->pci,
 445                                 NVIDIA_HDA_OSTRM_COH,
 446                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 447         }
 448
 449         /* Enable SCH/PCH snoop if needed */
 450         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 451                 unsigned short snoop;
 452                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 453                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 454                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 455                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 456                         if (!azx_snoop(chip))
 457                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 458                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 459                         pci_read_config_word(chip->pci,
 460                                 INTEL_SCH_HDA_DEVC, &snoop);
 461                 }
 462                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 463                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 464                         "Disabled" : "Enabled");
 465         }
 466 }
 467
 468 /*
 469  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 470  * and makes an audio stream sensitive to system latencies when
 471  * 24/32 bits are playing.
 472  * Adjusting threshold of DMA fifo to force the DMA request
 473  * sooner to improve latency tolerance at the expense of power.
 474  */
 475 static void bxt_reduce_dma_latency(struct azx *chip)
 476 {
 477         u32 val;
 478
 479         val = azx_readl(chip, VS_EM4L);
 480         val &= (0x3 << 20);
 481         azx_writel(chip, VS_EM4L, val);
 482 }
 483
 484 /*
 485  * ML_LCAP bits:
 486  *  bit 0: 6 MHz Supported
 487  *  bit 1: 12 MHz Supported
 488  *  bit 2: 24 MHz Supported
 489  *  bit 3: 48 MHz Supported
 490  *  bit 4: 96 MHz Supported
 491  *  bit 5: 192 MHz Supported
 492  */
 493 static int intel_get_lctl_scf(struct azx *chip)
 494 {
 495         struct hdac_bus *bus = azx_bus(chip);
 496         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 497         u32 val, t;
 498         int i;
 499
 500         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 501
 502         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 503                 t = preferred_bits[i];
 504                 if (val & (1 << t))
 505                         return t;
 506         }
 507
 508         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 509         return 0;
 510 }
 511
 512 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 513 {
 514         struct hdac_bus *bus = azx_bus(chip);
 515         u32 val;
 516         int timeout;
 517
 518         /*
 519          * the codecs are sharing the first link setting by default
 520          * If other links are enabled for stream, they need similar fix
 521          */
 522         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 523         val &= ~AZX_MLCTL_SPA;
 524         val |= state << AZX_MLCTL_SPA_SHIFT;
 525         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 526         /* wait for CPA */
 527         timeout = 50;
 528         while (timeout) {
 529                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 530                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 531                         return 0;
 532                 timeout--;
 533                 udelay(10);
 534         }
 535
 536         return -1;
 537 }
 538
 539 static void intel_init_lctl(struct azx *chip)
 540 {
 541         struct hdac_bus *bus = azx_bus(chip);
 542         u32 val;
 543         int ret;
 544
 545         /* 0. check lctl register value is correct or not */
 546         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 547         /* if SCF is already set, let's use it */
 548         if ((val & ML_LCTL_SCF_MASK) != 0)
 549                 return;
 550
 551         /*
 552          * Before operating on SPA, CPA must match SPA.
 553          * Any deviation may result in undefined behavior.
 554          */
 555         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 556                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 557                 return;
 558
 559         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 560         ret = intel_ml_lctl_set_power(chip, 0);
 561         udelay(100);
 562         if (ret)
 563                 goto set_spa;
 564
 565         /* 2. update SCF to select a properly audio clock*/
 566         val &= ~ML_LCTL_SCF_MASK;
 567         val |= intel_get_lctl_scf(chip);
 568         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 569
 570 set_spa:
 571         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 572         intel_ml_lctl_set_power(chip, 1);
 573         udelay(100);
 574 }
 575
 576 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 577 {
 578         struct hdac_bus *bus = azx_bus(chip);
 579         struct pci_dev *pci = chip->pci;
 580         u32 val;
 581
 582         snd_hdac_set_codec_wakeup(bus, true);
 583         if (chip->driver_type == AZX_DRIVER_SKL) {
 584                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 585                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 586                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 587         }
 588         azx_init_chip(chip, full_reset);
 589         if (chip->driver_type == AZX_DRIVER_SKL) {
 590                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 591                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 592                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 593         }
 594
 595         snd_hdac_set_codec_wakeup(bus, false);
 596
 597         /* reduce dma latency to avoid noise */
 598         if (IS_BXT(pci))
 599                 bxt_reduce_dma_latency(chip);
 600
 601         if (bus->mlcap != NULL)
 602                 intel_init_lctl(chip);
 603 }
 604
 605 /* calculate runtime delay from LPIB */
 606 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 607                                    unsigned int pos)
 608 {
 609         struct snd_pcm_substream *substream = azx_dev->core.substream;
 610         int stream = substream->stream;
 611         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 612         int delay;
 613
 614         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 615                 delay = pos - lpib_pos;
 616         else
 617                 delay = lpib_pos - pos;
 618         if (delay < 0) {
 619                 if (delay >= azx_dev->core.delay_negative_threshold)
 620                         delay = 0;
 621                 else
 622                         delay += azx_dev->core.bufsize;
 623         }
 624
 625         if (delay >= azx_dev->core.period_bytes) {
 626                 dev_info(chip->card->dev,
 627                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 628                          delay, azx_dev->core.period_bytes);
 629                 delay = 0;
 630                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 631                 chip->get_delay[stream] = NULL;
 632         }
 633
 634         return bytes_to_frames(substream->runtime, delay);
 635 }
 636
 637 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 638
 639 /* called from IRQ */
 640 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 641 {
 642         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 643         int ok;
 644
 645         ok = azx_position_ok(chip, azx_dev);
 646         if (ok == 1) {
 647                 azx_dev->irq_pending = 0;
 648                 return ok;
 649         } else if (ok == 0) {
 650                 /* bogus IRQ, process it later */
 651                 azx_dev->irq_pending = 1;
 652                 schedule_work(&hda->irq_pending_work);
 653         }
 654         return 0;
 655 }
 656
 657 #define display_power(chip, enable) \
 658         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 659
 660 /*
 661  * Check whether the current DMA position is acceptable for updating
 662  * periods.  Returns non-zero if it's OK.
 663  *
 664  * Many HD-audio controllers appear pretty inaccurate about
 665  * the update-IRQ timing.  The IRQ is issued before actually the
 666  * data is processed.  So, we need to process it afterwords in a
 667  * workqueue.
 668  */
 669 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 670 {
 671         struct snd_pcm_substream *substream = azx_dev->core.substream;
 672         int stream = substream->stream;
 673         u32 wallclk;
 674         unsigned int pos;
 675
 676         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 677         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 678                 return -1;      /* bogus (too early) interrupt */
 679
 680         if (chip->get_position[stream])
 681                 pos = chip->get_position[stream](chip, azx_dev);
 682         else { /* use the position buffer as default */
 683                 pos = azx_get_pos_posbuf(chip, azx_dev);
 684                 if (!pos || pos == (u32)-1) {
 685                         dev_info(chip->card->dev,
 686                                  "Invalid position buffer, using LPIB read method instead.\n");
 687                         chip->get_position[stream] = azx_get_pos_lpib;
 688                         if (chip->get_position[0] == azx_get_pos_lpib &&
 689                             chip->get_position[1] == azx_get_pos_lpib)
 690                                 azx_bus(chip)->use_posbuf = false;
 691                         pos = azx_get_pos_lpib(chip, azx_dev);
 692                         chip->get_delay[stream] = NULL;
 693                 } else {
 694                         chip->get_position[stream] = azx_get_pos_posbuf;
 695                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 696                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 697                 }
 698         }
 699
 700         if (pos >= azx_dev->core.bufsize)
 701                 pos = 0;
 702
 703         if (WARN_ONCE(!azx_dev->core.period_bytes,
 704                       "hda-intel: zero azx_dev->period_bytes"))
 705                 return -1; /* this shouldn't happen! */
 706         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 707             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 708                 /* NG - it's below the first next period boundary */
 709                 return chip->bdl_pos_adj ? 0 : -1;
 710         azx_dev->core.start_wallclk += wallclk;
 711         return 1; /* OK, it's fine */
 712 }
 713
 714 /*
 715  * The work for pending PCM period updates.
 716  */
 717 static void azx_irq_pending_work(struct work_struct *work)
 718 {
 719         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 720         struct azx *chip = &hda->chip;
 721         struct hdac_bus *bus = azx_bus(chip);
 722         struct hdac_stream *s;
 723         int pending, ok;
 724
 725         if (!hda->irq_pending_warned) {
 726                 dev_info(chip->card->dev,
 727                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 728                          chip->card->number);
 729                 hda->irq_pending_warned = 1;
 730         }
 731
 732         for (;;) {
 733                 pending = 0;
 734                 spin_lock_irq(&bus->reg_lock);
 735                 list_for_each_entry(s, &bus->stream_list, list) {
 736                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 737                         if (!azx_dev->irq_pending ||
 738                             !s->substream ||
 739                             !s->running)
 740                                 continue;
 741                         ok = azx_position_ok(chip, azx_dev);
 742                         if (ok > 0) {
 743                                 azx_dev->irq_pending = 0;
 744                                 spin_unlock(&bus->reg_lock);
 745                                 snd_pcm_period_elapsed(s->substream);
 746                                 spin_lock(&bus->reg_lock);
 747                         } else if (ok < 0) {
 748                                 pending = 0;    /* too early */
 749                         } else
 750                                 pending++;
 751                 }
 752                 spin_unlock_irq(&bus->reg_lock);
 753                 if (!pending)
 754                         return;
 755                 msleep(1);
 756         }
 757 }
 758
 759 /* clear irq_pending flags and assure no on-going workq */
 760 static void azx_clear_irq_pending(struct azx *chip)
 761 {
 762         struct hdac_bus *bus = azx_bus(chip);
 763         struct hdac_stream *s;
 764
 765         spin_lock_irq(&bus->reg_lock);
 766         list_for_each_entry(s, &bus->stream_list, list) {
 767                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 768                 azx_dev->irq_pending = 0;
 769         }
 770         spin_unlock_irq(&bus->reg_lock);
 771 }
 772
 773 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 774 {
 775         struct hdac_bus *bus = azx_bus(chip);
 776
 777         if (request_irq(chip->pci->irq, azx_interrupt,
 778                         chip->msi ? 0 : IRQF_SHARED,
 779                         chip->card->irq_descr, chip)) {
 780                 dev_err(chip->card->dev,
 781                         "unable to grab IRQ %d, disabling device\n",
 782                         chip->pci->irq);
 783                 if (do_disconnect)
 784                         snd_card_disconnect(chip->card);
 785                 return -1;
 786         }
 787         bus->irq = chip->pci->irq;
 788         pci_intx(chip->pci, !chip->msi);
 789         return 0;
 790 }
 791
 792 /* get the current DMA position with correction on VIA chips */
 793 static unsigned int azx_via_get_position(struct azx *chip,
 794                                          struct azx_dev *azx_dev)
 795 {
 796         unsigned int link_pos, mini_pos, bound_pos;
 797         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 798         unsigned int fifo_size;
 799
 800         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 801         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 802                 /* Playback, no problem using link position */
 803                 return link_pos;
 804         }
 805
 806         /* Capture */
 807         /* For new chipset,
 808          * use mod to get the DMA position just like old chipset
 809          */
 810         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 811         mod_dma_pos %= azx_dev->core.period_bytes;
 812
 813         /* azx_dev->fifo_size can't get FIFO size of in stream.
 814          * Get from base address + offset.
 815          */
 816         fifo_size = readw(azx_bus(chip)->remap_addr +
 817                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 818
 819         if (azx_dev->insufficient) {
 820                 /* Link position never gather than FIFO size */
 821                 if (link_pos <= fifo_size)
 822                         return 0;
 823
 824                 azx_dev->insufficient = 0;
 825         }
 826
 827         if (link_pos <= fifo_size)
 828                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 829         else
 830                 mini_pos = link_pos - fifo_size;
 831
 832         /* Find nearest previous boudary */
 833         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 834         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 835         if (mod_link_pos >= fifo_size)
 836                 bound_pos = link_pos - mod_link_pos;
 837         else if (mod_dma_pos >= mod_mini_pos)
 838                 bound_pos = mini_pos - mod_mini_pos;
 839         else {
 840                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 841                 if (bound_pos >= azx_dev->core.bufsize)
 842                         bound_pos = 0;
 843         }
 844
 845         /* Calculate real DMA position we want */
 846         return bound_pos + mod_dma_pos;
 847 }
 848
 849 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 850                                          struct azx_dev *azx_dev)
 851 {
 852         return _snd_hdac_chip_readl(azx_bus(chip),
 853                                     AZX_REG_VS_SDXDPIB_XBASE +
 854                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 855                                      azx_dev->core.index));
 856 }
 857
 858 /* get the current DMA position with correction on SKL+ chips */
 859 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 860 {
 861         /* DPIB register gives a more accurate position for playback */
 862         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 863                 return azx_skl_get_dpib_pos(chip, azx_dev);
 864
 865         /* For capture, we need to read posbuf, but it requires a delay
 866          * for the possible boundary overlap; the read of DPIB fetches the
 867          * actual posbuf
 868          */
 869         udelay(20);
 870         azx_skl_get_dpib_pos(chip, azx_dev);
 871         return azx_get_pos_posbuf(chip, azx_dev);
 872 }
 873
 874 #ifdef CONFIG_PM
 875 static DEFINE_MUTEX(card_list_lock);
 876 static LIST_HEAD(card_list);
 877
 878 static void azx_add_card_list(struct azx *chip)
 879 {
 880         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 881         mutex_lock(&card_list_lock);
 882         list_add(&hda->list, &card_list);
 883         mutex_unlock(&card_list_lock);
 884 }
 885
 886 static void azx_del_card_list(struct azx *chip)
 887 {
 888         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 889         mutex_lock(&card_list_lock);
 890         list_del_init(&hda->list);
 891         mutex_unlock(&card_list_lock);
 892 }
 893
 894 /* trigger power-save check at writing parameter */
 895 static int param_set_xint(const char *val, const struct kernel_param *kp)
 896 {
 897         struct hda_intel *hda;
 898         struct azx *chip;
 899         int prev = power_save;
 900         int ret = param_set_int(val, kp);
 901
 902         if (ret || prev == power_save)
 903                 return ret;
 904
 905         mutex_lock(&card_list_lock);
 906         list_for_each_entry(hda, &card_list, list) {
 907                 chip = &hda->chip;
 908                 if (!hda->probe_continued || chip->disabled)
 909                         continue;
 910                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 911         }
 912         mutex_unlock(&card_list_lock);
 913         return 0;
 914 }
 915
 916 /*
 917  * power management
 918  */
 919 static bool azx_is_pm_ready(struct snd_card *card)
 920 {
 921         struct azx *chip;
 922         struct hda_intel *hda;
 923
 924         if (!card)
 925                 return false;
 926         chip = card->private_data;
 927         hda = container_of(chip, struct hda_intel, chip);
 928         if (chip->disabled || hda->init_failed || !chip->running)
 929                 return false;
 930         return true;
 931 }
 932
 933 static void __azx_runtime_suspend(struct azx *chip)
 934 {
 935         azx_stop_chip(chip);
 936         azx_enter_link_reset(chip);
 937         azx_clear_irq_pending(chip);
 938         display_power(chip, false);
 939 }
 940
 941 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 942 {
 943         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 944         struct hdac_bus *bus = azx_bus(chip);
 945         struct hda_codec *codec;
 946         int status;
 947
 948         display_power(chip, true);
 949         if (hda->need_i915_power)
 950                 snd_hdac_i915_set_bclk(bus);
 951
 952         /* Read STATESTS before controller reset */
 953         status = azx_readw(chip, STATESTS);
 954
 955         azx_init_pci(chip);
 956         hda_intel_init_chip(chip, true);
 957
 958         if (status && from_rt) {
 959                 list_for_each_codec(codec, &chip->bus)
 960                         if (status & (1 << codec->addr))
 961                                 schedule_delayed_work(&codec->jackpoll_work,
 962                                                       codec->jackpoll_interval);
 963         }
 964
 965         /* power down again for link-controlled chips */
 966         if (!hda->need_i915_power)
 967                 display_power(chip, false);
 968 }
 969
 970 #ifdef CONFIG_PM_SLEEP
 971 static int azx_suspend(struct device *dev)
 972 {
 973         struct snd_card *card = dev_get_drvdata(dev);
 974         struct azx *chip;
 975         struct hdac_bus *bus;
 976
 977         if (!azx_is_pm_ready(card))
 978                 return 0;
 979
 980         chip = card->private_data;
 981         bus = azx_bus(chip);
 982         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 983         __azx_runtime_suspend(chip);
 984         if (bus->irq >= 0) {
 985                 free_irq(bus->irq, chip);
 986                 bus->irq = -1;
 987         }
 988
 989         if (chip->msi)
 990                 pci_disable_msi(chip->pci);
 991
 992         trace_azx_suspend(chip);
 993         return 0;
 994 }
 995
 996 static int azx_resume(struct device *dev)
 997 {
 998         struct snd_card *card = dev_get_drvdata(dev);
 999         struct azx *chip;
1000
1001         if (!azx_is_pm_ready(card))
1002                 return 0;
1003
1004         chip = card->private_data;
1005         if (chip->msi)
1006                 if (pci_enable_msi(chip->pci) < 0)
1007                         chip->msi = 0;
1008         if (azx_acquire_irq(chip, 1) < 0)
1009                 return -EIO;
1010         __azx_runtime_resume(chip, false);
1011         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1012
1013         trace_azx_resume(chip);
1014         return 0;
1015 }
1016
1017 /* put codec down to D3 at hibernation for Intel SKL+;
1018  * otherwise BIOS may still access the codec and screw up the driver
1019  */
1020 static int azx_freeze_noirq(struct device *dev)
1021 {
1022         struct snd_card *card = dev_get_drvdata(dev);
1023         struct azx *chip = card->private_data;
1024         struct pci_dev *pci = to_pci_dev(dev);
1025
1026         if (chip->driver_type == AZX_DRIVER_SKL)
1027                 pci_set_power_state(pci, PCI_D3hot);
1028
1029         return 0;
1030 }
1031
1032 static int azx_thaw_noirq(struct device *dev)
1033 {
1034         struct snd_card *card = dev_get_drvdata(dev);
1035         struct azx *chip = card->private_data;
1036         struct pci_dev *pci = to_pci_dev(dev);
1037
1038         if (chip->driver_type == AZX_DRIVER_SKL)
1039                 pci_set_power_state(pci, PCI_D0);
1040
1041         return 0;
1042 }
1043 #endif /* CONFIG_PM_SLEEP */
1044
1045 static int azx_runtime_suspend(struct device *dev)
1046 {
1047         struct snd_card *card = dev_get_drvdata(dev);
1048         struct azx *chip;
1049
1050         if (!azx_is_pm_ready(card))
1051                 return 0;
1052         chip = card->private_data;
1053         if (!azx_has_pm_runtime(chip))
1054                 return 0;
1055
1056         /* enable controller wake up event */
1057         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1058                   STATESTS_INT_MASK);
1059
1060         __azx_runtime_suspend(chip);
1061         trace_azx_runtime_suspend(chip);
1062         return 0;
1063 }
1064
1065 static int azx_runtime_resume(struct device *dev)
1066 {
1067         struct snd_card *card = dev_get_drvdata(dev);
1068         struct azx *chip;
1069
1070         if (!azx_is_pm_ready(card))
1071                 return 0;
1072         chip = card->private_data;
1073         if (!azx_has_pm_runtime(chip))
1074                 return 0;
1075         __azx_runtime_resume(chip, true);
1076
1077         /* disable controller Wake Up event*/
1078         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1079                         ~STATESTS_INT_MASK);
1080
1081         trace_azx_runtime_resume(chip);
1082         return 0;
1083 }
1084
1085 static int azx_runtime_idle(struct device *dev)
1086 {
1087         struct snd_card *card = dev_get_drvdata(dev);
1088         struct azx *chip;
1089         struct hda_intel *hda;
1090
1091         if (!card)
1092                 return 0;
1093
1094         chip = card->private_data;
1095         hda = container_of(chip, struct hda_intel, chip);
1096         if (chip->disabled || hda->init_failed)
1097                 return 0;
1098
1099         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1100             azx_bus(chip)->codec_powered || !chip->running)
1101                 return -EBUSY;
1102
1103         /* ELD notification gets broken when HD-audio bus is off */
1104         if (needs_eld_notify_link(hda))
1105                 return -EBUSY;
1106
1107         return 0;
1108 }
1109
1110 static const struct dev_pm_ops azx_pm = {
1111         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1112 #ifdef CONFIG_PM_SLEEP
1113         .freeze_noirq = azx_freeze_noirq,
1114         .thaw_noirq = azx_thaw_noirq,
1115 #endif
1116         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1117 };
1118
1119 #define AZX_PM_OPS      &azx_pm
1120 #else
1121 #define azx_add_card_list(chip) /* NOP */
1122 #define azx_del_card_list(chip) /* NOP */
1123 #define AZX_PM_OPS      NULL
1124 #endif /* CONFIG_PM */
1125
1126
1127 static int azx_probe_continue(struct azx *chip);
1128
1129 #ifdef SUPPORT_VGA_SWITCHEROO
1130 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1131
1132 static void azx_vs_set_state(struct pci_dev *pci,
1133                              enum vga_switcheroo_state state)
1134 {
1135         struct snd_card *card = pci_get_drvdata(pci);
1136         struct azx *chip = card->private_data;
1137         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1138         struct hda_codec *codec;
1139         bool disabled;
1140
1141         wait_for_completion(&hda->probe_wait);
1142         if (hda->init_failed)
1143                 return;
1144
1145         disabled = (state == VGA_SWITCHEROO_OFF);
1146         if (chip->disabled == disabled)
1147                 return;
1148
1149         if (!hda->probe_continued) {
1150                 chip->disabled = disabled;
1151                 if (!disabled) {
1152                         dev_info(chip->card->dev,
1153                                  "Start delayed initialization\n");
1154                         if (azx_probe_continue(chip) < 0) {
1155                                 dev_err(chip->card->dev, "initialization error\n");
1156                                 hda->init_failed = true;
1157                         }
1158                 }
1159         } else {
1160                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1161                          disabled ? "Disabling" : "Enabling");
1162                 if (disabled) {
1163                         list_for_each_codec(codec, &chip->bus) {
1164                                 pm_runtime_suspend(hda_codec_dev(codec));
1165                                 pm_runtime_disable(hda_codec_dev(codec));
1166                         }
1167                         pm_runtime_suspend(card->dev);
1168                         pm_runtime_disable(card->dev);
1169                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1170                          * however we have no ACPI handle, so pci/acpi can't put us there,
1171                          * put ourselves there */
1172                         pci->current_state = PCI_D3cold;
1173                         chip->disabled = true;
1174                         if (snd_hda_lock_devices(&chip->bus))
1175                                 dev_warn(chip->card->dev,
1176                                          "Cannot lock devices!\n");
1177                 } else {
1178                         snd_hda_unlock_devices(&chip->bus);
1179                         chip->disabled = false;
1180                         pm_runtime_enable(card->dev);
1181                         list_for_each_codec(codec, &chip->bus) {
1182                                 pm_runtime_enable(hda_codec_dev(codec));
1183                                 pm_runtime_resume(hda_codec_dev(codec));
1184                         }
1185                 }
1186         }
1187 }
1188
1189 static bool azx_vs_can_switch(struct pci_dev *pci)
1190 {
1191         struct snd_card *card = pci_get_drvdata(pci);
1192         struct azx *chip = card->private_data;
1193         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1194
1195         wait_for_completion(&hda->probe_wait);
1196         if (hda->init_failed)
1197                 return false;
1198         if (chip->disabled || !hda->probe_continued)
1199                 return true;
1200         if (snd_hda_lock_devices(&chip->bus))
1201                 return false;
1202         snd_hda_unlock_devices(&chip->bus);
1203         return true;
1204 }
1205
1206 /*
1207  * The discrete GPU cannot power down unless the HDA controller runtime
1208  * suspends, so activate runtime PM on codecs even if power_save == 0.
1209  */
1210 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1211 {
1212         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1213         struct hda_codec *codec;
1214
1215         if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1216                 list_for_each_codec(codec, &chip->bus)
1217                         codec->auto_runtime_pm = 1;
1218                 /* reset the power save setup */
1219                 if (chip->running)
1220                         set_default_power_save(chip);
1221         }
1222 }
1223
1224 static void azx_vs_gpu_bound(struct pci_dev *pci,
1225                              enum vga_switcheroo_client_id client_id)
1226 {
1227         struct snd_card *card = pci_get_drvdata(pci);
1228         struct azx *chip = card->private_data;
1229         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1230
1231         if (client_id == VGA_SWITCHEROO_DIS)
1232                 hda->need_eld_notify_link = 0;
1233         setup_vga_switcheroo_runtime_pm(chip);
1234 }
1235
1236 static void init_vga_switcheroo(struct azx *chip)
1237 {
1238         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1239         struct pci_dev *p = get_bound_vga(chip->pci);
1240         if (p) {
1241                 dev_info(chip->card->dev,
1242                          "Handle vga_switcheroo audio client\n");
1243                 hda->use_vga_switcheroo = 1;
1244                 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
1245                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1246                 pci_dev_put(p);
1247         }
1248 }
1249
1250 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1251         .set_gpu_state = azx_vs_set_state,
1252         .can_switch = azx_vs_can_switch,
1253         .gpu_bound = azx_vs_gpu_bound,
1254 };
1255
1256 static int register_vga_switcheroo(struct azx *chip)
1257 {
1258         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1259         struct pci_dev *p;
1260         int err;
1261
1262         if (!hda->use_vga_switcheroo)
1263                 return 0;
1264
1265         p = get_bound_vga(chip->pci);
1266         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1267         pci_dev_put(p);
1268
1269         if (err < 0)
1270                 return err;
1271         hda->vga_switcheroo_registered = 1;
1272
1273         return 0;
1274 }
1275 #else
1276 #define init_vga_switcheroo(chip)               /* NOP */
1277 #define register_vga_switcheroo(chip)           0
1278 #define check_hdmi_disabled(pci)        false
1279 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1280 #endif /* SUPPORT_VGA_SWITCHER */
1281
1282 /*
1283  * destructor
1284  */
1285 static int azx_free(struct azx *chip)
1286 {
1287         struct pci_dev *pci = chip->pci;
1288         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1289         struct hdac_bus *bus = azx_bus(chip);
1290
1291         if (azx_has_pm_runtime(chip) && chip->running)
1292                 pm_runtime_get_noresume(&pci->dev);
1293         chip->running = 0;
1294
1295         azx_del_card_list(chip);
1296
1297         hda->init_failed = 1; /* to be sure */
1298         complete_all(&hda->probe_wait);
1299
1300         if (use_vga_switcheroo(hda)) {
1301                 if (chip->disabled && hda->probe_continued)
1302                         snd_hda_unlock_devices(&chip->bus);
1303                 if (hda->vga_switcheroo_registered)
1304                         vga_switcheroo_unregister_client(chip->pci);
1305         }
1306
1307         if (bus->chip_init) {
1308                 azx_stop_chip(chip);
1309                 azx_clear_irq_pending(chip);
1310                 azx_stop_all_streams(chip);
1311         }
1312
1313         if (bus->irq >= 0)
1314                 free_irq(bus->irq, (void*)chip);
1315         if (chip->msi)
1316                 pci_disable_msi(chip->pci);
1317         iounmap(bus->remap_addr);
1318
1319         azx_free_stream_pages(chip);
1320         azx_free_streams(chip);
1321         snd_hdac_bus_exit(bus);
1322
1323         if (chip->region_requested)
1324                 pci_release_regions(chip->pci);
1325
1326         pci_disable_device(chip->pci);
1327 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1328         release_firmware(chip->fw);
1329 #endif
1330         display_power(chip, false);
1331
1332         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1333                 snd_hdac_i915_exit(bus);
1334         kfree(hda);
1335
1336         return 0;
1337 }
1338
1339 static int azx_dev_disconnect(struct snd_device *device)
1340 {
1341         struct azx *chip = device->device_data;
1342
1343         chip->bus.shutdown = 1;
1344         return 0;
1345 }
1346
1347 static int azx_dev_free(struct snd_device *device)
1348 {
1349         return azx_free(device->device_data);
1350 }
1351
1352 #ifdef SUPPORT_VGA_SWITCHEROO
1353 /*
1354  * Check of disabled HDMI controller by vga_switcheroo
1355  */
1356 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1357 {
1358         struct pci_dev *p;
1359
1360         /* check only discrete GPU */
1361         switch (pci->vendor) {
1362         case PCI_VENDOR_ID_ATI:
1363         case PCI_VENDOR_ID_AMD:
1364         case PCI_VENDOR_ID_NVIDIA:
1365                 if (pci->devfn == 1) {
1366                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1367                                                         pci->bus->number, 0);
1368                         if (p) {
1369                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1370                                         return p;
1371                                 pci_dev_put(p);
1372                         }
1373                 }
1374                 break;
1375         }
1376         return NULL;
1377 }
1378
1379 static bool check_hdmi_disabled(struct pci_dev *pci)
1380 {
1381         bool vga_inactive = false;
1382         struct pci_dev *p = get_bound_vga(pci);
1383
1384         if (p) {
1385                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1386                         vga_inactive = true;
1387                 pci_dev_put(p);
1388         }
1389         return vga_inactive;
1390 }
1391 #endif /* SUPPORT_VGA_SWITCHEROO */
1392
1393 /*
1394  * white/black-listing for position_fix
1395  */
1396 static struct snd_pci_quirk position_fix_list[] = {
1397         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1398         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1399         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1400         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1401         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1402         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1403         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1404         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1405         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1406         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1407         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1408         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1409         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1410         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1411         {}
1412 };
1413
1414 static int check_position_fix(struct azx *chip, int fix)
1415 {
1416         const struct snd_pci_quirk *q;
1417
1418         switch (fix) {
1419         case POS_FIX_AUTO:
1420         case POS_FIX_LPIB:
1421         case POS_FIX_POSBUF:
1422         case POS_FIX_VIACOMBO:
1423         case POS_FIX_COMBO:
1424         case POS_FIX_SKL:
1425                 return fix;
1426         }
1427
1428         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1429         if (q) {
1430                 dev_info(chip->card->dev,
1431                          "position_fix set to %d for device %04x:%04x\n",
1432                          q->value, q->subvendor, q->subdevice);
1433                 return q->value;
1434         }
1435
1436         /* Check VIA/ATI HD Audio Controller exist */
1437         if (chip->driver_type == AZX_DRIVER_VIA) {
1438                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1439                 return POS_FIX_VIACOMBO;
1440         }
1441         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1442                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1443                 return POS_FIX_LPIB;
1444         }
1445         if (chip->driver_type == AZX_DRIVER_SKL) {
1446                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1447                 return POS_FIX_SKL;
1448         }
1449         return POS_FIX_AUTO;
1450 }
1451
1452 static void assign_position_fix(struct azx *chip, int fix)
1453 {
1454         static azx_get_pos_callback_t callbacks[] = {
1455                 [POS_FIX_AUTO] = NULL,
1456                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1457                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1458                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1459                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1460                 [POS_FIX_SKL] = azx_get_pos_skl,
1461         };
1462
1463         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1464
1465         /* combo mode uses LPIB only for playback */
1466         if (fix == POS_FIX_COMBO)
1467                 chip->get_position[1] = NULL;
1468
1469         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1470             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1471                 chip->get_delay[0] = chip->get_delay[1] =
1472                         azx_get_delay_from_lpib;
1473         }
1474
1475 }
1476
1477 /*
1478  * black-lists for probe_mask
1479  */
1480 static struct snd_pci_quirk probe_mask_list[] = {
1481         /* Thinkpad often breaks the controller communication when accessing
1482          * to the non-working (or non-existing) modem codec slot.
1483          */
1484         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1485         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1486         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1487         /* broken BIOS */
1488         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1489         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1490         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1491         /* forced codec slots */
1492         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1493         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1494         /* WinFast VP200 H (Teradici) user reported broken communication */
1495         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1496         {}
1497 };
1498
1499 #define AZX_FORCE_CODEC_MASK    0x100
1500
1501 static void check_probe_mask(struct azx *chip, int dev)
1502 {
1503         const struct snd_pci_quirk *q;
1504
1505         chip->codec_probe_mask = probe_mask[dev];
1506         if (chip->codec_probe_mask == -1) {
1507                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1508                 if (q) {
1509                         dev_info(chip->card->dev,
1510                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1511                                  q->value, q->subvendor, q->subdevice);
1512                         chip->codec_probe_mask = q->value;
1513                 }
1514         }
1515
1516         /* check forced option */
1517         if (chip->codec_probe_mask != -1 &&
1518             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1519                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1520                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1521                          (int)azx_bus(chip)->codec_mask);
1522         }
1523 }
1524
1525 /*
1526  * white/black-list for enable_msi
1527  */
1528 static struct snd_pci_quirk msi_black_list[] = {
1529         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1530         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1531         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1532         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1533         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1534         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1535         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1536         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1537         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1538         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1539         {}
1540 };
1541
1542 static void check_msi(struct azx *chip)
1543 {
1544         const struct snd_pci_quirk *q;
1545
1546         if (enable_msi >= 0) {
1547                 chip->msi = !!enable_msi;
1548                 return;
1549         }
1550         chip->msi = 1;  /* enable MSI as default */
1551         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1552         if (q) {
1553                 dev_info(chip->card->dev,
1554                          "msi for device %04x:%04x set to %d\n",
1555                          q->subvendor, q->subdevice, q->value);
1556                 chip->msi = q->value;
1557                 return;
1558         }
1559
1560         /* NVidia chipsets seem to cause troubles with MSI */
1561         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1562                 dev_info(chip->card->dev, "Disabling MSI\n");
1563                 chip->msi = 0;
1564         }
1565 }
1566
1567 /* check the snoop mode availability */
1568 static void azx_check_snoop_available(struct azx *chip)
1569 {
1570         int snoop = hda_snoop;
1571
1572         if (snoop >= 0) {
1573                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1574                          snoop ? "snoop" : "non-snoop");
1575                 chip->snoop = snoop;
1576                 chip->uc_buffer = !snoop;
1577                 return;
1578         }
1579
1580         snoop = true;
1581         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1582             chip->driver_type == AZX_DRIVER_VIA) {
1583                 /* force to non-snoop mode for a new VIA controller
1584                  * when BIOS is set
1585                  */
1586                 u8 val;
1587                 pci_read_config_byte(chip->pci, 0x42, &val);
1588                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1589                                       chip->pci->revision == 0x20))
1590                         snoop = false;
1591         }
1592
1593         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1594                 snoop = false;
1595
1596         chip->snoop = snoop;
1597         if (!snoop) {
1598                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1599                 /* C-Media requires non-cached pages only for CORB/RIRB */
1600                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1601                         chip->uc_buffer = true;
1602         }
1603 }
1604
1605 static void azx_probe_work(struct work_struct *work)
1606 {
1607         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1608         azx_probe_continue(&hda->chip);
1609 }
1610
1611 static int default_bdl_pos_adj(struct azx *chip)
1612 {
1613         /* some exceptions: Atoms seem problematic with value 1 */
1614         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1615                 switch (chip->pci->device) {
1616                 case 0x0f04: /* Baytrail */
1617                 case 0x2284: /* Braswell */
1618                         return 32;
1619                 }
1620         }
1621
1622         switch (chip->driver_type) {
1623         case AZX_DRIVER_ICH:
1624         case AZX_DRIVER_PCH:
1625                 return 1;
1626         default:
1627                 return 32;
1628         }
1629 }
1630
1631 /*
1632  * constructor
1633  */
1634 static const struct hdac_io_ops pci_hda_io_ops;
1635 static const struct hda_controller_ops pci_hda_ops;
1636
1637 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1638                       int dev, unsigned int driver_caps,
1639                       struct azx **rchip)
1640 {
1641         static struct snd_device_ops ops = {
1642                 .dev_disconnect = azx_dev_disconnect,
1643                 .dev_free = azx_dev_free,
1644         };
1645         struct hda_intel *hda;
1646         struct azx *chip;
1647         int err;
1648
1649         *rchip = NULL;
1650
1651         err = pci_enable_device(pci);
1652         if (err < 0)
1653                 return err;
1654
1655         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1656         if (!hda) {
1657                 pci_disable_device(pci);
1658                 return -ENOMEM;
1659         }
1660
1661         chip = &hda->chip;
1662         mutex_init(&chip->open_mutex);
1663         chip->card = card;
1664         chip->pci = pci;
1665         chip->ops = &pci_hda_ops;
1666         chip->driver_caps = driver_caps;
1667         chip->driver_type = driver_caps & 0xff;
1668         check_msi(chip);
1669         chip->dev_index = dev;
1670         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1671                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1672         INIT_LIST_HEAD(&chip->pcm_list);
1673         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1674         INIT_LIST_HEAD(&hda->list);
1675         init_vga_switcheroo(chip);
1676         init_completion(&hda->probe_wait);
1677
1678         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1679
1680         check_probe_mask(chip, dev);
1681
1682         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1683                 chip->fallback_to_single_cmd = 1;
1684         else /* explicitly set to single_cmd or not */
1685                 chip->single_cmd = single_cmd;
1686
1687         azx_check_snoop_available(chip);
1688
1689         if (bdl_pos_adj[dev] < 0)
1690                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1691         else
1692                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1693
1694         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1695         if (err < 0) {
1696                 kfree(hda);
1697                 pci_disable_device(pci);
1698                 return err;
1699         }
1700
1701         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1702         if (IS_CFL(pci) || IS_CNL(pci))
1703                 azx_bus(chip)->polling_mode = 1;
1704
1705         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1706                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1707                 chip->bus.needs_damn_long_delay = 1;
1708         }
1709
1710         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1711         if (err < 0) {
1712                 dev_err(card->dev, "Error creating device [card]!\n");
1713                 azx_free(chip);
1714                 return err;
1715         }
1716
1717         /* continue probing in work context as may trigger request module */
1718         INIT_WORK(&hda->probe_work, azx_probe_work);
1719
1720         *rchip = chip;
1721
1722         return 0;
1723 }
1724
1725 static int azx_first_init(struct azx *chip)
1726 {
1727         int dev = chip->dev_index;
1728         struct pci_dev *pci = chip->pci;
1729         struct snd_card *card = chip->card;
1730         struct hdac_bus *bus = azx_bus(chip);
1731         int err;
1732         unsigned short gcap;
1733         unsigned int dma_bits = 64;
1734
1735 #if BITS_PER_LONG != 64
1736         /* Fix up base address on ULI M5461 */
1737         if (chip->driver_type == AZX_DRIVER_ULI) {
1738                 u16 tmp3;
1739                 pci_read_config_word(pci, 0x40, &tmp3);
1740                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1741                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1742         }
1743 #endif
1744
1745         err = pci_request_regions(pci, "ICH HD audio");
1746         if (err < 0)
1747                 return err;
1748         chip->region_requested = 1;
1749
1750         bus->addr = pci_resource_start(pci, 0);
1751         bus->remap_addr = pci_ioremap_bar(pci, 0);
1752         if (bus->remap_addr == NULL) {
1753                 dev_err(card->dev, "ioremap error\n");
1754                 return -ENXIO;
1755         }
1756
1757         if (chip->driver_type == AZX_DRIVER_SKL)
1758                 snd_hdac_bus_parse_capabilities(bus);
1759
1760         /*
1761          * Some Intel CPUs has always running timer (ART) feature and
1762          * controller may have Global time sync reporting capability, so
1763          * check both of these before declaring synchronized time reporting
1764          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1765          */
1766         chip->gts_present = false;
1767
1768 #ifdef CONFIG_X86
1769         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1770                 chip->gts_present = true;
1771 #endif
1772
1773         if (chip->msi) {
1774                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1775                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1776                         pci->no_64bit_msi = true;
1777                 }
1778                 if (pci_enable_msi(pci) < 0)
1779                         chip->msi = 0;
1780         }
1781
1782         pci_set_master(pci);
1783         synchronize_irq(bus->irq);
1784
1785         gcap = azx_readw(chip, GCAP);
1786         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1787
1788         /* AMD devices support 40 or 48bit DMA, take the safe one */
1789         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1790                 dma_bits = 40;
1791
1792         /* disable SB600 64bit support for safety */
1793         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1794                 struct pci_dev *p_smbus;
1795                 dma_bits = 40;
1796                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1797                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1798                                          NULL);
1799                 if (p_smbus) {
1800                         if (p_smbus->revision < 0x30)
1801                                 gcap &= ~AZX_GCAP_64OK;
1802                         pci_dev_put(p_smbus);
1803                 }
1804         }
1805
1806         /* NVidia hardware normally only supports up to 40 bits of DMA */
1807         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1808                 dma_bits = 40;
1809
1810         /* disable 64bit DMA address on some devices */
1811         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1812                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1813                 gcap &= ~AZX_GCAP_64OK;
1814         }
1815
1816         /* disable buffer size rounding to 128-byte multiples if supported */
1817         if (align_buffer_size >= 0)
1818                 chip->align_buffer_size = !!align_buffer_size;
1819         else {
1820                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1821                         chip->align_buffer_size = 0;
1822                 else
1823                         chip->align_buffer_size = 1;
1824         }
1825
1826         /* allow 64bit DMA address if supported by H/W */
1827         if (!(gcap & AZX_GCAP_64OK))
1828                 dma_bits = 32;
1829         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1830                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1831         } else {
1832                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1833                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1834         }
1835
1836         /* read number of streams from GCAP register instead of using
1837          * hardcoded value
1838          */
1839         chip->capture_streams = (gcap >> 8) & 0x0f;
1840         chip->playback_streams = (gcap >> 12) & 0x0f;
1841         if (!chip->playback_streams && !chip->capture_streams) {
1842                 /* gcap didn't give any info, switching to old method */
1843
1844                 switch (chip->driver_type) {
1845                 case AZX_DRIVER_ULI:
1846                         chip->playback_streams = ULI_NUM_PLAYBACK;
1847                         chip->capture_streams = ULI_NUM_CAPTURE;
1848                         break;
1849                 case AZX_DRIVER_ATIHDMI:
1850                 case AZX_DRIVER_ATIHDMI_NS:
1851                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1852                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1853                         break;
1854                 case AZX_DRIVER_GENERIC:
1855                 default:
1856                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1857                         chip->capture_streams = ICH6_NUM_CAPTURE;
1858                         break;
1859                 }
1860         }
1861         chip->capture_index_offset = 0;
1862         chip->playback_index_offset = chip->capture_streams;
1863         chip->num_streams = chip->playback_streams + chip->capture_streams;
1864
1865         /* sanity check for the SDxCTL.STRM field overflow */
1866         if (chip->num_streams > 15 &&
1867             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1868                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1869                          "forcing separate stream tags", chip->num_streams);
1870                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1871         }
1872
1873         /* initialize streams */
1874         err = azx_init_streams(chip);
1875         if (err < 0)
1876                 return err;
1877
1878         err = azx_alloc_stream_pages(chip);
1879         if (err < 0)
1880                 return err;
1881
1882         /* initialize chip */
1883         azx_init_pci(chip);
1884
1885         snd_hdac_i915_set_bclk(bus);
1886
1887         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1888
1889         /* codec detection */
1890         if (!azx_bus(chip)->codec_mask) {
1891                 dev_err(card->dev, "no codecs found!\n");
1892                 return -ENODEV;
1893         }
1894
1895         if (azx_acquire_irq(chip, 0) < 0)
1896                 return -EBUSY;
1897
1898         strcpy(card->driver, "HDA-Intel");
1899         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1900                 sizeof(card->shortname));
1901         snprintf(card->longname, sizeof(card->longname),
1902                  "%s at 0x%lx irq %i",
1903                  card->shortname, bus->addr, bus->irq);
1904
1905         return 0;
1906 }
1907
1908 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1909 /* callback from request_firmware_nowait() */
1910 static void azx_firmware_cb(const struct firmware *fw, void *context)
1911 {
1912         struct snd_card *card = context;
1913         struct azx *chip = card->private_data;
1914         struct pci_dev *pci = chip->pci;
1915
1916         if (!fw) {
1917                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1918                 goto error;
1919         }
1920
1921         chip->fw = fw;
1922         if (!chip->disabled) {
1923                 /* continue probing */
1924                 if (azx_probe_continue(chip))
1925                         goto error;
1926         }
1927         return; /* OK */
1928
1929  error:
1930         snd_card_free(card);
1931         pci_set_drvdata(pci, NULL);
1932 }
1933 #endif
1934
1935 /*
1936  * HDA controller ops.
1937  */
1938
1939 /* PCI register access. */
1940 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1941 {
1942         writel(value, addr);
1943 }
1944
1945 static u32 pci_azx_readl(u32 __iomem *addr)
1946 {
1947         return readl(addr);
1948 }
1949
1950 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1951 {
1952         writew(value, addr);
1953 }
1954
1955 static u16 pci_azx_readw(u16 __iomem *addr)
1956 {
1957         return readw(addr);
1958 }
1959
1960 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1961 {
1962         writeb(value, addr);
1963 }
1964
1965 static u8 pci_azx_readb(u8 __iomem *addr)
1966 {
1967         return readb(addr);
1968 }
1969
1970 static int disable_msi_reset_irq(struct azx *chip)
1971 {
1972         struct hdac_bus *bus = azx_bus(chip);
1973         int err;
1974
1975         free_irq(bus->irq, chip);
1976         bus->irq = -1;
1977         pci_disable_msi(chip->pci);
1978         chip->msi = 0;
1979         err = azx_acquire_irq(chip, 1);
1980         if (err < 0)
1981                 return err;
1982
1983         return 0;
1984 }
1985
1986 /* DMA page allocation helpers.  */
1987 static int dma_alloc_pages(struct hdac_bus *bus,
1988                            int type,
1989                            size_t size,
1990                            struct snd_dma_buffer *buf)
1991 {
1992         struct azx *chip = bus_to_azx(bus);
1993
1994         if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV)
1995                 type = SNDRV_DMA_TYPE_DEV_UC;
1996         return snd_dma_alloc_pages(type, bus->dev, size, buf);
1997 }
1998
1999 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2000 {
2001         snd_dma_free_pages(buf);
2002 }
2003
2004 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2005                              struct vm_area_struct *area)
2006 {
2007 #ifdef CONFIG_X86
2008         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2009         struct azx *chip = apcm->chip;
2010         if (chip->uc_buffer)
2011                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2012 #endif
2013 }
2014
2015 static const struct hdac_io_ops pci_hda_io_ops = {
2016         .reg_writel = pci_azx_writel,
2017         .reg_readl = pci_azx_readl,
2018         .reg_writew = pci_azx_writew,
2019         .reg_readw = pci_azx_readw,
2020         .reg_writeb = pci_azx_writeb,
2021         .reg_readb = pci_azx_readb,
2022         .dma_alloc_pages = dma_alloc_pages,
2023         .dma_free_pages = dma_free_pages,
2024 };
2025
2026 static const struct hda_controller_ops pci_hda_ops = {
2027         .disable_msi_reset_irq = disable_msi_reset_irq,
2028         .pcm_mmap_prepare = pcm_mmap_prepare,
2029         .position_check = azx_position_check,
2030 };
2031
2032 static int azx_check_dmic(struct pci_dev *pci, struct azx *chip)
2033 {
2034         struct nhlt_acpi_table *nhlt;
2035         int ret = 0;
2036
2037         if (chip->driver_type == AZX_DRIVER_SKL &&
2038             pci->class != 0x040300) {
2039                 nhlt = intel_nhlt_init(&pci->dev);
2040                 if (nhlt) {
2041                         if (intel_nhlt_get_dmic_geo(&pci->dev, nhlt)) {
2042                                 ret = -ENODEV;
2043                                 dev_info(&pci->dev, "Digital mics found on Skylake+ platform, aborting probe\n");
2044                         }
2045                         intel_nhlt_free(nhlt);
2046                 }
2047         }
2048         return ret;
2049 }
2050
2051 static int azx_probe(struct pci_dev *pci,
2052                      const struct pci_device_id *pci_id)
2053 {
2054         static int dev;
2055         struct snd_card *card;
2056         struct hda_intel *hda;
2057         struct azx *chip;
2058         bool schedule_probe;
2059         int err;
2060
2061         if (dev >= SNDRV_CARDS)
2062                 return -ENODEV;
2063         if (!enable[dev]) {
2064                 dev++;
2065                 return -ENOENT;
2066         }
2067
2068         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2069                            0, &card);
2070         if (err < 0) {
2071                 dev_err(&pci->dev, "Error creating card!\n");
2072                 return err;
2073         }
2074
2075         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2076         if (err < 0)
2077                 goto out_free;
2078         card->private_data = chip;
2079         hda = container_of(chip, struct hda_intel, chip);
2080
2081         /*
2082          * stop probe if digital microphones detected on Skylake+ platform
2083          * with the DSP enabled. This is an opt-in behavior defined at build
2084          * time or at run-time with a module parameter
2085          */
2086         if (dmic_detect) {
2087                 err = azx_check_dmic(pci, chip);
2088                 if (err < 0)
2089                         goto out_free;
2090         }
2091
2092         pci_set_drvdata(pci, card);
2093
2094         err = register_vga_switcheroo(chip);
2095         if (err < 0) {
2096                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2097                 goto out_free;
2098         }
2099
2100         if (check_hdmi_disabled(pci)) {
2101                 dev_info(card->dev, "VGA controller is disabled\n");
2102                 dev_info(card->dev, "Delaying initialization\n");
2103                 chip->disabled = true;
2104         }
2105
2106         schedule_probe = !chip->disabled;
2107
2108 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2109         if (patch[dev] && *patch[dev]) {
2110                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2111                          patch[dev]);
2112                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2113                                               &pci->dev, GFP_KERNEL, card,
2114                                               azx_firmware_cb);
2115                 if (err < 0)
2116                         goto out_free;
2117                 schedule_probe = false; /* continued in azx_firmware_cb() */
2118         }
2119 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2120
2121 #ifndef CONFIG_SND_HDA_I915
2122         if (CONTROLLER_IN_GPU(pci))
2123                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2124 #endif
2125
2126         if (schedule_probe)
2127                 schedule_work(&hda->probe_work);
2128
2129         dev++;
2130         if (chip->disabled)
2131                 complete_all(&hda->probe_wait);
2132         return 0;
2133
2134 out_free:
2135         snd_card_free(card);
2136         return err;
2137 }
2138
2139 #ifdef CONFIG_PM
2140 /* On some boards setting power_save to a non 0 value leads to clicking /
2141  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2142  * figure out how to avoid these sounds, but that is not always feasible.
2143  * So we keep a list of devices where we disable powersaving as its known
2144  * to causes problems on these devices.
2145  */
2146 static struct snd_pci_quirk power_save_blacklist[] = {
2147         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2148         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2149         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2150         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2151         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2152         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2153         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2154         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2155         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2156         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2157         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2158         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2159         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2160         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2161         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2162         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2163         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2164         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2165         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2166         /* https://bugs.launchpad.net/bugs/1821663 */
2167         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2168         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2169         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2170         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2171         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2172         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2173         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2174         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2175         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2176         /* https://bugs.launchpad.net/bugs/1821663 */
2177         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2178         {}
2179 };
2180 #endif /* CONFIG_PM */
2181
2182 static void set_default_power_save(struct azx *chip)
2183 {
2184         int val = power_save;
2185
2186 #ifdef CONFIG_PM
2187         if (pm_blacklist) {
2188                 const struct snd_pci_quirk *q;
2189
2190                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2191                 if (q && val) {
2192                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2193                                  q->subvendor, q->subdevice);
2194                         val = 0;
2195                 }
2196         }
2197 #endif /* CONFIG_PM */
2198         snd_hda_set_power_save(&chip->bus, val * 1000);
2199 }
2200
2201 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2202 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2203         [AZX_DRIVER_NVIDIA] = 8,
2204         [AZX_DRIVER_TERA] = 1,
2205 };
2206
2207 static int azx_probe_continue(struct azx *chip)
2208 {
2209         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2210         struct hdac_bus *bus = azx_bus(chip);
2211         struct pci_dev *pci = chip->pci;
2212         int dev = chip->dev_index;
2213         int err;
2214
2215         to_hda_bus(bus)->bus_probing = 1;
2216         hda->probe_continued = 1;
2217
2218         /* bind with i915 if needed */
2219         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2220                 err = snd_hdac_i915_init(bus);
2221                 if (err < 0) {
2222                         /* if the controller is bound only with HDMI/DP
2223                          * (for HSW and BDW), we need to abort the probe;
2224                          * for other chips, still continue probing as other
2225                          * codecs can be on the same link.
2226                          */
2227                         if (CONTROLLER_IN_GPU(pci)) {
2228                                 dev_err(chip->card->dev,
2229                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2230                                 goto out_free;
2231                         } else {
2232                                 /* don't bother any longer */
2233                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2234                         }
2235                 }
2236
2237                 /* HSW/BDW controllers need this power */
2238                 if (CONTROLLER_IN_GPU(pci))
2239                         hda->need_i915_power = 1;
2240         }
2241
2242         /* Request display power well for the HDA controller or codec. For
2243          * Haswell/Broadwell, both the display HDA controller and codec need
2244          * this power. For other platforms, like Baytrail/Braswell, only the
2245          * display codec needs the power and it can be released after probe.
2246          */
2247         display_power(chip, true);
2248
2249         err = azx_first_init(chip);
2250         if (err < 0)
2251                 goto out_free;
2252
2253 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2254         chip->beep_mode = beep_mode[dev];
2255 #endif
2256
2257         /* create codec instances */
2258         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2259         if (err < 0)
2260                 goto out_free;
2261
2262 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2263         if (chip->fw) {
2264                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2265                                          chip->fw->data);
2266                 if (err < 0)
2267                         goto out_free;
2268 #ifndef CONFIG_PM
2269                 release_firmware(chip->fw); /* no longer needed */
2270                 chip->fw = NULL;
2271 #endif
2272         }
2273 #endif
2274         if ((probe_only[dev] & 1) == 0) {
2275                 err = azx_codec_configure(chip);
2276                 if (err < 0)
2277                         goto out_free;
2278         }
2279
2280         err = snd_card_register(chip->card);
2281         if (err < 0)
2282                 goto out_free;
2283
2284         setup_vga_switcheroo_runtime_pm(chip);
2285
2286         chip->running = 1;
2287         azx_add_card_list(chip);
2288
2289         set_default_power_save(chip);
2290
2291         if (azx_has_pm_runtime(chip))
2292                 pm_runtime_put_autosuspend(&pci->dev);
2293
2294 out_free:
2295         if (err < 0 || !hda->need_i915_power)
2296                 display_power(chip, false);
2297         if (err < 0)
2298                 hda->init_failed = 1;
2299         complete_all(&hda->probe_wait);
2300         to_hda_bus(bus)->bus_probing = 0;
2301         return err;
2302 }
2303
2304 static void azx_remove(struct pci_dev *pci)
2305 {
2306         struct snd_card *card = pci_get_drvdata(pci);
2307         struct azx *chip;
2308         struct hda_intel *hda;
2309
2310         if (card) {
2311                 /* cancel the pending probing work */
2312                 chip = card->private_data;
2313                 hda = container_of(chip, struct hda_intel, chip);
2314                 /* FIXME: below is an ugly workaround.
2315                  * Both device_release_driver() and driver_probe_device()
2316                  * take *both* the device's and its parent's lock before
2317                  * calling the remove() and probe() callbacks.  The codec
2318                  * probe takes the locks of both the codec itself and its
2319                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2320                  * the PCI controller is unbound, it takes its lock, too
2321                  * ==> ouch, a deadlock!
2322                  * As a workaround, we unlock temporarily here the controller
2323                  * device during cancel_work_sync() call.
2324                  */
2325                 device_unlock(&pci->dev);
2326                 cancel_work_sync(&hda->probe_work);
2327                 device_lock(&pci->dev);
2328
2329                 snd_card_free(card);
2330         }
2331 }
2332
2333 static void azx_shutdown(struct pci_dev *pci)
2334 {
2335         struct snd_card *card = pci_get_drvdata(pci);
2336         struct azx *chip;
2337
2338         if (!card)
2339                 return;
2340         chip = card->private_data;
2341         if (chip && chip->running)
2342                 azx_stop_chip(chip);
2343 }
2344
2345 /* PCI IDs */
2346 static const struct pci_device_id azx_ids[] = {
2347         /* CPT */
2348         { PCI_DEVICE(0x8086, 0x1c20),
2349           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2350         /* PBG */
2351         { PCI_DEVICE(0x8086, 0x1d20),
2352           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2353         /* Panther Point */
2354         { PCI_DEVICE(0x8086, 0x1e20),
2355           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2356         /* Lynx Point */
2357         { PCI_DEVICE(0x8086, 0x8c20),
2358           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2359         /* 9 Series */
2360         { PCI_DEVICE(0x8086, 0x8ca0),
2361           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2362         /* Wellsburg */
2363         { PCI_DEVICE(0x8086, 0x8d20),
2364           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2365         { PCI_DEVICE(0x8086, 0x8d21),
2366           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2367         /* Lewisburg */
2368         { PCI_DEVICE(0x8086, 0xa1f0),
2369           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2370         { PCI_DEVICE(0x8086, 0xa270),
2371           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2372         /* Lynx Point-LP */
2373         { PCI_DEVICE(0x8086, 0x9c20),
2374           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2375         /* Lynx Point-LP */
2376         { PCI_DEVICE(0x8086, 0x9c21),
2377           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2378         /* Wildcat Point-LP */
2379         { PCI_DEVICE(0x8086, 0x9ca0),
2380           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2381         /* Sunrise Point */
2382         { PCI_DEVICE(0x8086, 0xa170),
2383           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2384         /* Sunrise Point-LP */
2385         { PCI_DEVICE(0x8086, 0x9d70),
2386           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2387         /* Kabylake */
2388         { PCI_DEVICE(0x8086, 0xa171),
2389           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2390         /* Kabylake-LP */
2391         { PCI_DEVICE(0x8086, 0x9d71),
2392           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2393         /* Kabylake-H */
2394         { PCI_DEVICE(0x8086, 0xa2f0),
2395           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2396         /* Coffelake */
2397         { PCI_DEVICE(0x8086, 0xa348),
2398           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2399         /* Cannonlake */
2400         { PCI_DEVICE(0x8086, 0x9dc8),
2401           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2402         /* CometLake-LP */
2403         { PCI_DEVICE(0x8086, 0x02C8),
2404           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2405         /* CometLake-H */
2406         { PCI_DEVICE(0x8086, 0x06C8),
2407           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2408         /* Icelake */
2409         { PCI_DEVICE(0x8086, 0x34c8),
2410           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2411         /* Elkhart Lake */
2412         { PCI_DEVICE(0x8086, 0x4b55),
2413           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2414         /* Broxton-P(Apollolake) */
2415         { PCI_DEVICE(0x8086, 0x5a98),
2416           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2417         /* Broxton-T */
2418         { PCI_DEVICE(0x8086, 0x1a98),
2419           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2420         /* Gemini-Lake */
2421         { PCI_DEVICE(0x8086, 0x3198),
2422           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2423         /* Haswell */
2424         { PCI_DEVICE(0x8086, 0x0a0c),
2425           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2426         { PCI_DEVICE(0x8086, 0x0c0c),
2427           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2428         { PCI_DEVICE(0x8086, 0x0d0c),
2429           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2430         /* Broadwell */
2431         { PCI_DEVICE(0x8086, 0x160c),
2432           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2433         /* 5 Series/3400 */
2434         { PCI_DEVICE(0x8086, 0x3b56),
2435           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2436         /* Poulsbo */
2437         { PCI_DEVICE(0x8086, 0x811b),
2438           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2439         /* Oaktrail */
2440         { PCI_DEVICE(0x8086, 0x080a),
2441           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2442         /* BayTrail */
2443         { PCI_DEVICE(0x8086, 0x0f04),
2444           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2445         /* Braswell */
2446         { PCI_DEVICE(0x8086, 0x2284),
2447           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2448         /* ICH6 */
2449         { PCI_DEVICE(0x8086, 0x2668),
2450           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2451         /* ICH7 */
2452         { PCI_DEVICE(0x8086, 0x27d8),
2453           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2454         /* ESB2 */
2455         { PCI_DEVICE(0x8086, 0x269a),
2456           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2457         /* ICH8 */
2458         { PCI_DEVICE(0x8086, 0x284b),
2459           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2460         /* ICH9 */
2461         { PCI_DEVICE(0x8086, 0x293e),
2462           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2463         /* ICH9 */
2464         { PCI_DEVICE(0x8086, 0x293f),
2465           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2466         /* ICH10 */
2467         { PCI_DEVICE(0x8086, 0x3a3e),
2468           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2469         /* ICH10 */
2470         { PCI_DEVICE(0x8086, 0x3a6e),
2471           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2472         /* Generic Intel */
2473         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2474           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2475           .class_mask = 0xffffff,
2476           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2477         /* ATI SB 450/600/700/800/900 */
2478         { PCI_DEVICE(0x1002, 0x437b),
2479           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2480         { PCI_DEVICE(0x1002, 0x4383),
2481           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2482         /* AMD Hudson */
2483         { PCI_DEVICE(0x1022, 0x780d),
2484           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2485         /* AMD Stoney */
2486         { PCI_DEVICE(0x1022, 0x157a),
2487           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2488                          AZX_DCAPS_PM_RUNTIME },
2489         /* AMD Raven */
2490         { PCI_DEVICE(0x1022, 0x15e3),
2491           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2492                          AZX_DCAPS_PM_RUNTIME },
2493         /* ATI HDMI */
2494         { PCI_DEVICE(0x1002, 0x0002),
2495           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2496         { PCI_DEVICE(0x1002, 0x1308),
2497           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2498         { PCI_DEVICE(0x1002, 0x157a),
2499           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2500         { PCI_DEVICE(0x1002, 0x15b3),
2501           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2502         { PCI_DEVICE(0x1002, 0x793b),
2503           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2504         { PCI_DEVICE(0x1002, 0x7919),
2505           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2506         { PCI_DEVICE(0x1002, 0x960f),
2507           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2508         { PCI_DEVICE(0x1002, 0x970f),
2509           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510         { PCI_DEVICE(0x1002, 0x9840),
2511           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2512         { PCI_DEVICE(0x1002, 0xaa00),
2513           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2514         { PCI_DEVICE(0x1002, 0xaa08),
2515           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2516         { PCI_DEVICE(0x1002, 0xaa10),
2517           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2518         { PCI_DEVICE(0x1002, 0xaa18),
2519           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2520         { PCI_DEVICE(0x1002, 0xaa20),
2521           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2522         { PCI_DEVICE(0x1002, 0xaa28),
2523           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2524         { PCI_DEVICE(0x1002, 0xaa30),
2525           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2526         { PCI_DEVICE(0x1002, 0xaa38),
2527           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2528         { PCI_DEVICE(0x1002, 0xaa40),
2529           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2530         { PCI_DEVICE(0x1002, 0xaa48),
2531           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2532         { PCI_DEVICE(0x1002, 0xaa50),
2533           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2534         { PCI_DEVICE(0x1002, 0xaa58),
2535           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2536         { PCI_DEVICE(0x1002, 0xaa60),
2537           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2538         { PCI_DEVICE(0x1002, 0xaa68),
2539           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2540         { PCI_DEVICE(0x1002, 0xaa80),
2541           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2542         { PCI_DEVICE(0x1002, 0xaa88),
2543           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2544         { PCI_DEVICE(0x1002, 0xaa90),
2545           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2546         { PCI_DEVICE(0x1002, 0xaa98),
2547           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2548         { PCI_DEVICE(0x1002, 0x9902),
2549           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2550         { PCI_DEVICE(0x1002, 0xaaa0),
2551           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2552         { PCI_DEVICE(0x1002, 0xaaa8),
2553           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2554         { PCI_DEVICE(0x1002, 0xaab0),
2555           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2556         { PCI_DEVICE(0x1002, 0xaac0),
2557           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2558         { PCI_DEVICE(0x1002, 0xaac8),
2559           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2560         { PCI_DEVICE(0x1002, 0xaad8),
2561           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2562         { PCI_DEVICE(0x1002, 0xaae8),
2563           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2564         { PCI_DEVICE(0x1002, 0xaae0),
2565           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2566         { PCI_DEVICE(0x1002, 0xaaf0),
2567           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2568         /* VIA VT8251/VT8237A */
2569         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2570         /* VIA GFX VT7122/VX900 */
2571         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2572         /* VIA GFX VT6122/VX11 */
2573         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2574         /* SIS966 */
2575         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2576         /* ULI M5461 */
2577         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2578         /* NVIDIA MCP */
2579         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2580           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2581           .class_mask = 0xffffff,
2582           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2583         /* Teradici */
2584         { PCI_DEVICE(0x6549, 0x1200),
2585           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2586         { PCI_DEVICE(0x6549, 0x2200),
2587           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2588         /* Creative X-Fi (CA0110-IBG) */
2589         /* CTHDA chips */
2590         { PCI_DEVICE(0x1102, 0x0010),
2591           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2592         { PCI_DEVICE(0x1102, 0x0012),
2593           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2594 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2595         /* the following entry conflicts with snd-ctxfi driver,
2596          * as ctxfi driver mutates from HD-audio to native mode with
2597          * a special command sequence.
2598          */
2599         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2600           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2601           .class_mask = 0xffffff,
2602           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2603           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2604 #else
2605         /* this entry seems still valid -- i.e. without emu20kx chip */
2606         { PCI_DEVICE(0x1102, 0x0009),
2607           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2608           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2609 #endif
2610         /* CM8888 */
2611         { PCI_DEVICE(0x13f6, 0x5011),
2612           .driver_data = AZX_DRIVER_CMEDIA |
2613           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2614         /* Vortex86MX */
2615         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2616         /* VMware HDAudio */
2617         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2618         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2619         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2620           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2621           .class_mask = 0xffffff,
2622           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2623         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2624           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2625           .class_mask = 0xffffff,
2626           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2627         { 0, }
2628 };
2629 MODULE_DEVICE_TABLE(pci, azx_ids);
2630
2631 /* pci_driver definition */
2632 static struct pci_driver azx_driver = {
2633         .name = KBUILD_MODNAME,
2634         .id_table = azx_ids,
2635         .probe = azx_probe,
2636         .remove = azx_remove,
2637         .shutdown = azx_shutdown,
2638         .driver = {
2639                 .pm = AZX_PM_OPS,
2640         },
2641 };
2642
2643 module_pci_driver(azx_driver);