sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38
  39 #ifdef CONFIG_X86
  40 /* for snoop control */
  41 #include <asm/pgtable.h>
  42 #include <asm/set_memory.h>
  43 #include <asm/cpufeature.h>
  44 #endif
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include <sound/hdaudio.h>
  48 #include <sound/hda_i915.h>
  49 #include <sound/intel-nhlt.h>
  50 #include <linux/vgaarb.h>
  51 #include <linux/vga_switcheroo.h>
  52 #include <linux/firmware.h>
  53 #include <sound/hda_codec.h>
  54 #include "hda_controller.h"
  55 #include "hda_intel.h"
  56
  57 #define CREATE_TRACE_POINTS
  58 #include "hda_intel_trace.h"
  59
  60 /* position fix mode */
  61 enum {
  62         POS_FIX_AUTO,
  63         POS_FIX_LPIB,
  64         POS_FIX_POSBUF,
  65         POS_FIX_VIACOMBO,
  66         POS_FIX_COMBO,
  67         POS_FIX_SKL,
  68 };
  69
  70 /* Defines for ATI HD Audio support in SB450 south bridge */
  71 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  72 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  73
  74 /* Defines for Nvidia HDA support */
  75 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  76 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  77 #define NVIDIA_HDA_ISTRM_COH          0x4d
  78 #define NVIDIA_HDA_OSTRM_COH          0x4c
  79 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  80
  81 /* Defines for Intel SCH HDA snoop control */
  82 #define INTEL_HDA_CGCTL  0x48
  83 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  84 #define INTEL_SCH_HDA_DEVC      0x78
  85 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  86
  87 /* Define IN stream 0 FIFO size offset in VIA controller */
  88 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
  89 /* Define VIA HD Audio Device ID*/
  90 #define VIA_HDAC_DEVICE_ID              0x3288
  91
  92 /* max number of SDs */
  93 /* ICH, ATI and VIA have 4 playback and 4 capture */
  94 #define ICH6_NUM_CAPTURE        4
  95 #define ICH6_NUM_PLAYBACK       4
  96
  97 /* ULI has 6 playback and 5 capture */
  98 #define ULI_NUM_CAPTURE         5
  99 #define ULI_NUM_PLAYBACK        6
 100
 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 102 #define ATIHDMI_NUM_CAPTURE     0
 103 #define ATIHDMI_NUM_PLAYBACK    8
 104
 105 /* TERA has 4 playback and 3 capture */
 106 #define TERA_NUM_CAPTURE        3
 107 #define TERA_NUM_PLAYBACK       4
 108
 109
 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 113 static char *model[SNDRV_CARDS];
 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 117 static int probe_only[SNDRV_CARDS];
 118 static int jackpoll_ms[SNDRV_CARDS];
 119 static int single_cmd = -1;
 120 static int enable_msi = -1;
 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 122 static char *patch[SNDRV_CARDS];
 123 #endif
 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 126                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 127 #endif
 128 static bool dmic_detect = IS_ENABLED(CONFIG_SND_HDA_INTEL_DETECT_DMIC);
 129
 130 module_param_array(index, int, NULL, 0444);
 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 132 module_param_array(id, charp, NULL, 0444);
 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 134 module_param_array(enable, bool, NULL, 0444);
 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 136 module_param_array(model, charp, NULL, 0444);
 137 MODULE_PARM_DESC(model, "Use the given board model.");
 138 module_param_array(position_fix, int, NULL, 0444);
 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 140                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
 141 module_param_array(bdl_pos_adj, int, NULL, 0644);
 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 143 module_param_array(probe_mask, int, NULL, 0444);
 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 145 module_param_array(probe_only, int, NULL, 0444);
 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 147 module_param_array(jackpoll_ms, int, NULL, 0444);
 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 149 module_param(single_cmd, bint, 0444);
 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 151                  "(for debugging only).");
 152 module_param(enable_msi, bint, 0444);
 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 155 module_param_array(patch, charp, NULL, 0444);
 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 157 #endif
 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 159 module_param_array(beep_mode, bool, NULL, 0444);
 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 161                             "(0=off, 1=on) (default=1).");
 162 #endif
 163 module_param(dmic_detect, bool, 0444);
 164 MODULE_PARM_DESC(dmic_detect, "DMIC detect on SKL+ platforms");
 165
 166 #ifdef CONFIG_PM
 167 static int param_set_xint(const char *val, const struct kernel_param *kp);
 168 static const struct kernel_param_ops param_ops_xint = {
 169         .set = param_set_xint,
 170         .get = param_get_int,
 171 };
 172 #define param_check_xint param_check_int
 173
 174 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 175 module_param(power_save, xint, 0644);
 176 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 177                  "(in second, 0 = disable).");
 178
 179 static bool pm_blacklist = true;
 180 module_param(pm_blacklist, bool, 0644);
 181 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 182
 183 /* reset the HD-audio controller in power save mode.
 184  * this may give more power-saving, but will take longer time to
 185  * wake up.
 186  */
 187 static bool power_save_controller = 1;
 188 module_param(power_save_controller, bool, 0644);
 189 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 190 #else
 191 #define power_save      0
 192 #endif /* CONFIG_PM */
 193
 194 static int align_buffer_size = -1;
 195 module_param(align_buffer_size, bint, 0644);
 196 MODULE_PARM_DESC(align_buffer_size,
 197                 "Force buffer and period sizes to be multiple of 128 bytes.");
 198
 199 #ifdef CONFIG_X86
 200 static int hda_snoop = -1;
 201 module_param_named(snoop, hda_snoop, bint, 0444);
 202 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 203 #else
 204 #define hda_snoop               true
 205 #endif
 206
 207
 208 MODULE_LICENSE("GPL");
 209 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 210                          "{Intel, ICH6M},"
 211                          "{Intel, ICH7},"
 212                          "{Intel, ESB2},"
 213                          "{Intel, ICH8},"
 214                          "{Intel, ICH9},"
 215                          "{Intel, ICH10},"
 216                          "{Intel, PCH},"
 217                          "{Intel, CPT},"
 218                          "{Intel, PPT},"
 219                          "{Intel, LPT},"
 220                          "{Intel, LPT_LP},"
 221                          "{Intel, WPT_LP},"
 222                          "{Intel, SPT},"
 223                          "{Intel, SPT_LP},"
 224                          "{Intel, HPT},"
 225                          "{Intel, PBG},"
 226                          "{Intel, SCH},"
 227                          "{ATI, SB450},"
 228                          "{ATI, SB600},"
 229                          "{ATI, RS600},"
 230                          "{ATI, RS690},"
 231                          "{ATI, RS780},"
 232                          "{ATI, R600},"
 233                          "{ATI, RV630},"
 234                          "{ATI, RV610},"
 235                          "{ATI, RV670},"
 236                          "{ATI, RV635},"
 237                          "{ATI, RV620},"
 238                          "{ATI, RV770},"
 239                          "{VIA, VT8251},"
 240                          "{VIA, VT8237A},"
 241                          "{SiS, SIS966},"
 242                          "{ULI, M5461}}");
 243 MODULE_DESCRIPTION("Intel HDA driver");
 244
 245 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 246 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 247 #define SUPPORT_VGA_SWITCHEROO
 248 #endif
 249 #endif
 250
 251
 252 /*
 253  */
 254
 255 /* driver types */
 256 enum {
 257         AZX_DRIVER_ICH,
 258         AZX_DRIVER_PCH,
 259         AZX_DRIVER_SCH,
 260         AZX_DRIVER_SKL,
 261         AZX_DRIVER_HDMI,
 262         AZX_DRIVER_ATI,
 263         AZX_DRIVER_ATIHDMI,
 264         AZX_DRIVER_ATIHDMI_NS,
 265         AZX_DRIVER_VIA,
 266         AZX_DRIVER_SIS,
 267         AZX_DRIVER_ULI,
 268         AZX_DRIVER_NVIDIA,
 269         AZX_DRIVER_TERA,
 270         AZX_DRIVER_CTX,
 271         AZX_DRIVER_CTHDA,
 272         AZX_DRIVER_CMEDIA,
 273         AZX_DRIVER_ZHAOXIN,
 274         AZX_DRIVER_GENERIC,
 275         AZX_NUM_DRIVERS, /* keep this as last entry */
 276 };
 277
 278 #define azx_get_snoop_type(chip) \
 279         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 281
 282 /* quirks for old Intel chipsets */
 283 #define AZX_DCAPS_INTEL_ICH \
 284         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 285
 286 /* quirks for Intel PCH */
 287 #define AZX_DCAPS_INTEL_PCH_BASE \
 288         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 289          AZX_DCAPS_SNOOP_TYPE(SCH))
 290
 291 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 292 #define AZX_DCAPS_INTEL_PCH_NOPM \
 293         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 294
 295 /* PCH for HSW/BDW; with runtime PM */
 296 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 297 #define AZX_DCAPS_INTEL_PCH \
 298         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 299
 300 /* HSW HDMI */
 301 #define AZX_DCAPS_INTEL_HASWELL \
 302         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 303          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 304          AZX_DCAPS_SNOOP_TYPE(SCH))
 305
 306 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 307 #define AZX_DCAPS_INTEL_BROADWELL \
 308         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 309          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 310          AZX_DCAPS_SNOOP_TYPE(SCH))
 311
 312 #define AZX_DCAPS_INTEL_BAYTRAIL \
 313         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 314
 315 #define AZX_DCAPS_INTEL_BRASWELL \
 316         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 317          AZX_DCAPS_I915_COMPONENT)
 318
 319 #define AZX_DCAPS_INTEL_SKYLAKE \
 320         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 321          AZX_DCAPS_SYNC_WRITE |\
 322          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 323
 324 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 325
 326 /* quirks for ATI SB / AMD Hudson */
 327 #define AZX_DCAPS_PRESET_ATI_SB \
 328         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 329          AZX_DCAPS_SNOOP_TYPE(ATI))
 330
 331 /* quirks for ATI/AMD HDMI */
 332 #define AZX_DCAPS_PRESET_ATI_HDMI \
 333         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 334          AZX_DCAPS_NO_MSI64)
 335
 336 /* quirks for ATI HDMI with snoop off */
 337 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 338         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 339
 340 /* quirks for Nvidia */
 341 #define AZX_DCAPS_PRESET_NVIDIA \
 342         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 343          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 344
 345 #define AZX_DCAPS_PRESET_CTHDA \
 346         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 347          AZX_DCAPS_NO_64BIT |\
 348          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 349
 350 /*
 351  * vga_switcheroo support
 352  */
 353 #ifdef SUPPORT_VGA_SWITCHEROO
 354 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 355 #define needs_eld_notify_link(chip)     ((chip)->need_eld_notify_link)
 356 #else
 357 #define use_vga_switcheroo(chip)        0
 358 #define needs_eld_notify_link(chip)     false
 359 #endif
 360
 361 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 362                                         ((pci)->device == 0x0c0c) || \
 363                                         ((pci)->device == 0x0d0c) || \
 364                                         ((pci)->device == 0x160c))
 365
 366 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 367 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 368 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 369
 370 static char *driver_short_names[] = {
 371         [AZX_DRIVER_ICH] = "HDA Intel",
 372         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 373         [AZX_DRIVER_SCH] = "HDA Intel MID",
 374         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 375         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 376         [AZX_DRIVER_ATI] = "HDA ATI SB",
 377         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 378         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 379         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 380         [AZX_DRIVER_SIS] = "HDA SIS966",
 381         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 382         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 383         [AZX_DRIVER_TERA] = "HDA Teradici",
 384         [AZX_DRIVER_CTX] = "HDA Creative",
 385         [AZX_DRIVER_CTHDA] = "HDA Creative",
 386         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 387         [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
 388         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 389 };
 390
 391 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 392 static void set_default_power_save(struct azx *chip);
 393
 394 /*
 395  * initialize the PCI registers
 396  */
 397 /* update bits in a PCI register byte */
 398 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 399                             unsigned char mask, unsigned char val)
 400 {
 401         unsigned char data;
 402
 403         pci_read_config_byte(pci, reg, &data);
 404         data &= ~mask;
 405         data |= (val & mask);
 406         pci_write_config_byte(pci, reg, data);
 407 }
 408
 409 static void azx_init_pci(struct azx *chip)
 410 {
 411         int snoop_type = azx_get_snoop_type(chip);
 412
 413         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 414          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 415          * Ensuring these bits are 0 clears playback static on some HD Audio
 416          * codecs.
 417          * The PCI register TCSEL is defined in the Intel manuals.
 418          */
 419         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 420                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 421                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 422         }
 423
 424         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 425          * we need to enable snoop.
 426          */
 427         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 428                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 429                         azx_snoop(chip));
 430                 update_pci_byte(chip->pci,
 431                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 432                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 433         }
 434
 435         /* For NVIDIA HDA, enable snoop */
 436         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 437                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 438                         azx_snoop(chip));
 439                 update_pci_byte(chip->pci,
 440                                 NVIDIA_HDA_TRANSREG_ADDR,
 441                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 442                 update_pci_byte(chip->pci,
 443                                 NVIDIA_HDA_ISTRM_COH,
 444                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 445                 update_pci_byte(chip->pci,
 446                                 NVIDIA_HDA_OSTRM_COH,
 447                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 448         }
 449
 450         /* Enable SCH/PCH snoop if needed */
 451         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 452                 unsigned short snoop;
 453                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 454                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 455                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 456                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 457                         if (!azx_snoop(chip))
 458                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 459                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 460                         pci_read_config_word(chip->pci,
 461                                 INTEL_SCH_HDA_DEVC, &snoop);
 462                 }
 463                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 464                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 465                         "Disabled" : "Enabled");
 466         }
 467 }
 468
 469 /*
 470  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 471  * and makes an audio stream sensitive to system latencies when
 472  * 24/32 bits are playing.
 473  * Adjusting threshold of DMA fifo to force the DMA request
 474  * sooner to improve latency tolerance at the expense of power.
 475  */
 476 static void bxt_reduce_dma_latency(struct azx *chip)
 477 {
 478         u32 val;
 479
 480         val = azx_readl(chip, VS_EM4L);
 481         val &= (0x3 << 20);
 482         azx_writel(chip, VS_EM4L, val);
 483 }
 484
 485 /*
 486  * ML_LCAP bits:
 487  *  bit 0: 6 MHz Supported
 488  *  bit 1: 12 MHz Supported
 489  *  bit 2: 24 MHz Supported
 490  *  bit 3: 48 MHz Supported
 491  *  bit 4: 96 MHz Supported
 492  *  bit 5: 192 MHz Supported
 493  */
 494 static int intel_get_lctl_scf(struct azx *chip)
 495 {
 496         struct hdac_bus *bus = azx_bus(chip);
 497         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 498         u32 val, t;
 499         int i;
 500
 501         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 502
 503         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 504                 t = preferred_bits[i];
 505                 if (val & (1 << t))
 506                         return t;
 507         }
 508
 509         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 510         return 0;
 511 }
 512
 513 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 514 {
 515         struct hdac_bus *bus = azx_bus(chip);
 516         u32 val;
 517         int timeout;
 518
 519         /*
 520          * the codecs are sharing the first link setting by default
 521          * If other links are enabled for stream, they need similar fix
 522          */
 523         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 524         val &= ~AZX_MLCTL_SPA;
 525         val |= state << AZX_MLCTL_SPA_SHIFT;
 526         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 527         /* wait for CPA */
 528         timeout = 50;
 529         while (timeout) {
 530                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 531                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 532                         return 0;
 533                 timeout--;
 534                 udelay(10);
 535         }
 536
 537         return -1;
 538 }
 539
 540 static void intel_init_lctl(struct azx *chip)
 541 {
 542         struct hdac_bus *bus = azx_bus(chip);
 543         u32 val;
 544         int ret;
 545
 546         /* 0. check lctl register value is correct or not */
 547         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 548         /* if SCF is already set, let's use it */
 549         if ((val & ML_LCTL_SCF_MASK) != 0)
 550                 return;
 551
 552         /*
 553          * Before operating on SPA, CPA must match SPA.
 554          * Any deviation may result in undefined behavior.
 555          */
 556         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 557                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 558                 return;
 559
 560         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 561         ret = intel_ml_lctl_set_power(chip, 0);
 562         udelay(100);
 563         if (ret)
 564                 goto set_spa;
 565
 566         /* 2. update SCF to select a properly audio clock*/
 567         val &= ~ML_LCTL_SCF_MASK;
 568         val |= intel_get_lctl_scf(chip);
 569         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 570
 571 set_spa:
 572         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 573         intel_ml_lctl_set_power(chip, 1);
 574         udelay(100);
 575 }
 576
 577 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 578 {
 579         struct hdac_bus *bus = azx_bus(chip);
 580         struct pci_dev *pci = chip->pci;
 581         u32 val;
 582
 583         snd_hdac_set_codec_wakeup(bus, true);
 584         if (chip->driver_type == AZX_DRIVER_SKL) {
 585                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 586                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 587                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 588         }
 589         azx_init_chip(chip, full_reset);
 590         if (chip->driver_type == AZX_DRIVER_SKL) {
 591                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 592                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 593                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 594         }
 595
 596         snd_hdac_set_codec_wakeup(bus, false);
 597
 598         /* reduce dma latency to avoid noise */
 599         if (IS_BXT(pci))
 600                 bxt_reduce_dma_latency(chip);
 601
 602         if (bus->mlcap != NULL)
 603                 intel_init_lctl(chip);
 604 }
 605
 606 /* calculate runtime delay from LPIB */
 607 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 608                                    unsigned int pos)
 609 {
 610         struct snd_pcm_substream *substream = azx_dev->core.substream;
 611         int stream = substream->stream;
 612         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 613         int delay;
 614
 615         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 616                 delay = pos - lpib_pos;
 617         else
 618                 delay = lpib_pos - pos;
 619         if (delay < 0) {
 620                 if (delay >= azx_dev->core.delay_negative_threshold)
 621                         delay = 0;
 622                 else
 623                         delay += azx_dev->core.bufsize;
 624         }
 625
 626         if (delay >= azx_dev->core.period_bytes) {
 627                 dev_info(chip->card->dev,
 628                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 629                          delay, azx_dev->core.period_bytes);
 630                 delay = 0;
 631                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 632                 chip->get_delay[stream] = NULL;
 633         }
 634
 635         return bytes_to_frames(substream->runtime, delay);
 636 }
 637
 638 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 639
 640 /* called from IRQ */
 641 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 642 {
 643         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 644         int ok;
 645
 646         ok = azx_position_ok(chip, azx_dev);
 647         if (ok == 1) {
 648                 azx_dev->irq_pending = 0;
 649                 return ok;
 650         } else if (ok == 0) {
 651                 /* bogus IRQ, process it later */
 652                 azx_dev->irq_pending = 1;
 653                 schedule_work(&hda->irq_pending_work);
 654         }
 655         return 0;
 656 }
 657
 658 #define display_power(chip, enable) \
 659         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 660
 661 /*
 662  * Check whether the current DMA position is acceptable for updating
 663  * periods.  Returns non-zero if it's OK.
 664  *
 665  * Many HD-audio controllers appear pretty inaccurate about
 666  * the update-IRQ timing.  The IRQ is issued before actually the
 667  * data is processed.  So, we need to process it afterwords in a
 668  * workqueue.
 669  */
 670 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 671 {
 672         struct snd_pcm_substream *substream = azx_dev->core.substream;
 673         int stream = substream->stream;
 674         u32 wallclk;
 675         unsigned int pos;
 676
 677         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 678         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 679                 return -1;      /* bogus (too early) interrupt */
 680
 681         if (chip->get_position[stream])
 682                 pos = chip->get_position[stream](chip, azx_dev);
 683         else { /* use the position buffer as default */
 684                 pos = azx_get_pos_posbuf(chip, azx_dev);
 685                 if (!pos || pos == (u32)-1) {
 686                         dev_info(chip->card->dev,
 687                                  "Invalid position buffer, using LPIB read method instead.\n");
 688                         chip->get_position[stream] = azx_get_pos_lpib;
 689                         if (chip->get_position[0] == azx_get_pos_lpib &&
 690                             chip->get_position[1] == azx_get_pos_lpib)
 691                                 azx_bus(chip)->use_posbuf = false;
 692                         pos = azx_get_pos_lpib(chip, azx_dev);
 693                         chip->get_delay[stream] = NULL;
 694                 } else {
 695                         chip->get_position[stream] = azx_get_pos_posbuf;
 696                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 697                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 698                 }
 699         }
 700
 701         if (pos >= azx_dev->core.bufsize)
 702                 pos = 0;
 703
 704         if (WARN_ONCE(!azx_dev->core.period_bytes,
 705                       "hda-intel: zero azx_dev->period_bytes"))
 706                 return -1; /* this shouldn't happen! */
 707         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 708             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 709                 /* NG - it's below the first next period boundary */
 710                 return chip->bdl_pos_adj ? 0 : -1;
 711         azx_dev->core.start_wallclk += wallclk;
 712         return 1; /* OK, it's fine */
 713 }
 714
 715 /*
 716  * The work for pending PCM period updates.
 717  */
 718 static void azx_irq_pending_work(struct work_struct *work)
 719 {
 720         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 721         struct azx *chip = &hda->chip;
 722         struct hdac_bus *bus = azx_bus(chip);
 723         struct hdac_stream *s;
 724         int pending, ok;
 725
 726         if (!hda->irq_pending_warned) {
 727                 dev_info(chip->card->dev,
 728                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 729                          chip->card->number);
 730                 hda->irq_pending_warned = 1;
 731         }
 732
 733         for (;;) {
 734                 pending = 0;
 735                 spin_lock_irq(&bus->reg_lock);
 736                 list_for_each_entry(s, &bus->stream_list, list) {
 737                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 738                         if (!azx_dev->irq_pending ||
 739                             !s->substream ||
 740                             !s->running)
 741                                 continue;
 742                         ok = azx_position_ok(chip, azx_dev);
 743                         if (ok > 0) {
 744                                 azx_dev->irq_pending = 0;
 745                                 spin_unlock(&bus->reg_lock);
 746                                 snd_pcm_period_elapsed(s->substream);
 747                                 spin_lock(&bus->reg_lock);
 748                         } else if (ok < 0) {
 749                                 pending = 0;    /* too early */
 750                         } else
 751                                 pending++;
 752                 }
 753                 spin_unlock_irq(&bus->reg_lock);
 754                 if (!pending)
 755                         return;
 756                 msleep(1);
 757         }
 758 }
 759
 760 /* clear irq_pending flags and assure no on-going workq */
 761 static void azx_clear_irq_pending(struct azx *chip)
 762 {
 763         struct hdac_bus *bus = azx_bus(chip);
 764         struct hdac_stream *s;
 765
 766         spin_lock_irq(&bus->reg_lock);
 767         list_for_each_entry(s, &bus->stream_list, list) {
 768                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 769                 azx_dev->irq_pending = 0;
 770         }
 771         spin_unlock_irq(&bus->reg_lock);
 772 }
 773
 774 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 775 {
 776         struct hdac_bus *bus = azx_bus(chip);
 777
 778         if (request_irq(chip->pci->irq, azx_interrupt,
 779                         chip->msi ? 0 : IRQF_SHARED,
 780                         chip->card->irq_descr, chip)) {
 781                 dev_err(chip->card->dev,
 782                         "unable to grab IRQ %d, disabling device\n",
 783                         chip->pci->irq);
 784                 if (do_disconnect)
 785                         snd_card_disconnect(chip->card);
 786                 return -1;
 787         }
 788         bus->irq = chip->pci->irq;
 789         pci_intx(chip->pci, !chip->msi);
 790         return 0;
 791 }
 792
 793 /* get the current DMA position with correction on VIA chips */
 794 static unsigned int azx_via_get_position(struct azx *chip,
 795                                          struct azx_dev *azx_dev)
 796 {
 797         unsigned int link_pos, mini_pos, bound_pos;
 798         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 799         unsigned int fifo_size;
 800
 801         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 802         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 803                 /* Playback, no problem using link position */
 804                 return link_pos;
 805         }
 806
 807         /* Capture */
 808         /* For new chipset,
 809          * use mod to get the DMA position just like old chipset
 810          */
 811         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 812         mod_dma_pos %= azx_dev->core.period_bytes;
 813
 814         /* azx_dev->fifo_size can't get FIFO size of in stream.
 815          * Get from base address + offset.
 816          */
 817         fifo_size = readw(azx_bus(chip)->remap_addr +
 818                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 819
 820         if (azx_dev->insufficient) {
 821                 /* Link position never gather than FIFO size */
 822                 if (link_pos <= fifo_size)
 823                         return 0;
 824
 825                 azx_dev->insufficient = 0;
 826         }
 827
 828         if (link_pos <= fifo_size)
 829                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 830         else
 831                 mini_pos = link_pos - fifo_size;
 832
 833         /* Find nearest previous boudary */
 834         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 835         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 836         if (mod_link_pos >= fifo_size)
 837                 bound_pos = link_pos - mod_link_pos;
 838         else if (mod_dma_pos >= mod_mini_pos)
 839                 bound_pos = mini_pos - mod_mini_pos;
 840         else {
 841                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 842                 if (bound_pos >= azx_dev->core.bufsize)
 843                         bound_pos = 0;
 844         }
 845
 846         /* Calculate real DMA position we want */
 847         return bound_pos + mod_dma_pos;
 848 }
 849
 850 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 851                                          struct azx_dev *azx_dev)
 852 {
 853         return _snd_hdac_chip_readl(azx_bus(chip),
 854                                     AZX_REG_VS_SDXDPIB_XBASE +
 855                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 856                                      azx_dev->core.index));
 857 }
 858
 859 /* get the current DMA position with correction on SKL+ chips */
 860 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 861 {
 862         /* DPIB register gives a more accurate position for playback */
 863         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 864                 return azx_skl_get_dpib_pos(chip, azx_dev);
 865
 866         /* For capture, we need to read posbuf, but it requires a delay
 867          * for the possible boundary overlap; the read of DPIB fetches the
 868          * actual posbuf
 869          */
 870         udelay(20);
 871         azx_skl_get_dpib_pos(chip, azx_dev);
 872         return azx_get_pos_posbuf(chip, azx_dev);
 873 }
 874
 875 #ifdef CONFIG_PM
 876 static DEFINE_MUTEX(card_list_lock);
 877 static LIST_HEAD(card_list);
 878
 879 static void azx_add_card_list(struct azx *chip)
 880 {
 881         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 882         mutex_lock(&card_list_lock);
 883         list_add(&hda->list, &card_list);
 884         mutex_unlock(&card_list_lock);
 885 }
 886
 887 static void azx_del_card_list(struct azx *chip)
 888 {
 889         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 890         mutex_lock(&card_list_lock);
 891         list_del_init(&hda->list);
 892         mutex_unlock(&card_list_lock);
 893 }
 894
 895 /* trigger power-save check at writing parameter */
 896 static int param_set_xint(const char *val, const struct kernel_param *kp)
 897 {
 898         struct hda_intel *hda;
 899         struct azx *chip;
 900         int prev = power_save;
 901         int ret = param_set_int(val, kp);
 902
 903         if (ret || prev == power_save)
 904                 return ret;
 905
 906         mutex_lock(&card_list_lock);
 907         list_for_each_entry(hda, &card_list, list) {
 908                 chip = &hda->chip;
 909                 if (!hda->probe_continued || chip->disabled)
 910                         continue;
 911                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 912         }
 913         mutex_unlock(&card_list_lock);
 914         return 0;
 915 }
 916
 917 /*
 918  * power management
 919  */
 920 static bool azx_is_pm_ready(struct snd_card *card)
 921 {
 922         struct azx *chip;
 923         struct hda_intel *hda;
 924
 925         if (!card)
 926                 return false;
 927         chip = card->private_data;
 928         hda = container_of(chip, struct hda_intel, chip);
 929         if (chip->disabled || hda->init_failed || !chip->running)
 930                 return false;
 931         return true;
 932 }
 933
 934 static void __azx_runtime_suspend(struct azx *chip)
 935 {
 936         azx_stop_chip(chip);
 937         azx_enter_link_reset(chip);
 938         azx_clear_irq_pending(chip);
 939         display_power(chip, false);
 940 }
 941
 942 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 943 {
 944         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 945         struct hdac_bus *bus = azx_bus(chip);
 946         struct hda_codec *codec;
 947         int status;
 948
 949         display_power(chip, true);
 950         if (hda->need_i915_power)
 951                 snd_hdac_i915_set_bclk(bus);
 952
 953         /* Read STATESTS before controller reset */
 954         status = azx_readw(chip, STATESTS);
 955
 956         azx_init_pci(chip);
 957         hda_intel_init_chip(chip, true);
 958
 959         if (status && from_rt) {
 960                 list_for_each_codec(codec, &chip->bus)
 961                         if (status & (1 << codec->addr))
 962                                 schedule_delayed_work(&codec->jackpoll_work,
 963                                                       codec->jackpoll_interval);
 964         }
 965
 966         /* power down again for link-controlled chips */
 967         if (!hda->need_i915_power)
 968                 display_power(chip, false);
 969 }
 970
 971 #ifdef CONFIG_PM_SLEEP
 972 static int azx_suspend(struct device *dev)
 973 {
 974         struct snd_card *card = dev_get_drvdata(dev);
 975         struct azx *chip;
 976         struct hdac_bus *bus;
 977
 978         if (!azx_is_pm_ready(card))
 979                 return 0;
 980
 981         chip = card->private_data;
 982         bus = azx_bus(chip);
 983         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 984         __azx_runtime_suspend(chip);
 985         if (bus->irq >= 0) {
 986                 free_irq(bus->irq, chip);
 987                 bus->irq = -1;
 988         }
 989
 990         if (chip->msi)
 991                 pci_disable_msi(chip->pci);
 992
 993         trace_azx_suspend(chip);
 994         return 0;
 995 }
 996
 997 static int azx_resume(struct device *dev)
 998 {
 999         struct snd_card *card = dev_get_drvdata(dev);
1000         struct azx *chip;
1001
1002         if (!azx_is_pm_ready(card))
1003                 return 0;
1004
1005         chip = card->private_data;
1006         if (chip->msi)
1007                 if (pci_enable_msi(chip->pci) < 0)
1008                         chip->msi = 0;
1009         if (azx_acquire_irq(chip, 1) < 0)
1010                 return -EIO;
1011         __azx_runtime_resume(chip, false);
1012         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1013
1014         trace_azx_resume(chip);
1015         return 0;
1016 }
1017
1018 /* put codec down to D3 at hibernation for Intel SKL+;
1019  * otherwise BIOS may still access the codec and screw up the driver
1020  */
1021 static int azx_freeze_noirq(struct device *dev)
1022 {
1023         struct snd_card *card = dev_get_drvdata(dev);
1024         struct azx *chip = card->private_data;
1025         struct pci_dev *pci = to_pci_dev(dev);
1026
1027         if (chip->driver_type == AZX_DRIVER_SKL)
1028                 pci_set_power_state(pci, PCI_D3hot);
1029
1030         return 0;
1031 }
1032
1033 static int azx_thaw_noirq(struct device *dev)
1034 {
1035         struct snd_card *card = dev_get_drvdata(dev);
1036         struct azx *chip = card->private_data;
1037         struct pci_dev *pci = to_pci_dev(dev);
1038
1039         if (chip->driver_type == AZX_DRIVER_SKL)
1040                 pci_set_power_state(pci, PCI_D0);
1041
1042         return 0;
1043 }
1044 #endif /* CONFIG_PM_SLEEP */
1045
1046 static int azx_runtime_suspend(struct device *dev)
1047 {
1048         struct snd_card *card = dev_get_drvdata(dev);
1049         struct azx *chip;
1050
1051         if (!azx_is_pm_ready(card))
1052                 return 0;
1053         chip = card->private_data;
1054         if (!azx_has_pm_runtime(chip))
1055                 return 0;
1056
1057         /* enable controller wake up event */
1058         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1059                   STATESTS_INT_MASK);
1060
1061         __azx_runtime_suspend(chip);
1062         trace_azx_runtime_suspend(chip);
1063         return 0;
1064 }
1065
1066 static int azx_runtime_resume(struct device *dev)
1067 {
1068         struct snd_card *card = dev_get_drvdata(dev);
1069         struct azx *chip;
1070
1071         if (!azx_is_pm_ready(card))
1072                 return 0;
1073         chip = card->private_data;
1074         if (!azx_has_pm_runtime(chip))
1075                 return 0;
1076         __azx_runtime_resume(chip, true);
1077
1078         /* disable controller Wake Up event*/
1079         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1080                         ~STATESTS_INT_MASK);
1081
1082         trace_azx_runtime_resume(chip);
1083         return 0;
1084 }
1085
1086 static int azx_runtime_idle(struct device *dev)
1087 {
1088         struct snd_card *card = dev_get_drvdata(dev);
1089         struct azx *chip;
1090         struct hda_intel *hda;
1091
1092         if (!card)
1093                 return 0;
1094
1095         chip = card->private_data;
1096         hda = container_of(chip, struct hda_intel, chip);
1097         if (chip->disabled || hda->init_failed)
1098                 return 0;
1099
1100         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1101             azx_bus(chip)->codec_powered || !chip->running)
1102                 return -EBUSY;
1103
1104         /* ELD notification gets broken when HD-audio bus is off */
1105         if (needs_eld_notify_link(hda))
1106                 return -EBUSY;
1107
1108         return 0;
1109 }
1110
1111 static const struct dev_pm_ops azx_pm = {
1112         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1113 #ifdef CONFIG_PM_SLEEP
1114         .freeze_noirq = azx_freeze_noirq,
1115         .thaw_noirq = azx_thaw_noirq,
1116 #endif
1117         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1118 };
1119
1120 #define AZX_PM_OPS      &azx_pm
1121 #else
1122 #define azx_add_card_list(chip) /* NOP */
1123 #define azx_del_card_list(chip) /* NOP */
1124 #define AZX_PM_OPS      NULL
1125 #endif /* CONFIG_PM */
1126
1127
1128 static int azx_probe_continue(struct azx *chip);
1129
1130 #ifdef SUPPORT_VGA_SWITCHEROO
1131 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1132
1133 static void azx_vs_set_state(struct pci_dev *pci,
1134                              enum vga_switcheroo_state state)
1135 {
1136         struct snd_card *card = pci_get_drvdata(pci);
1137         struct azx *chip = card->private_data;
1138         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1139         struct hda_codec *codec;
1140         bool disabled;
1141
1142         wait_for_completion(&hda->probe_wait);
1143         if (hda->init_failed)
1144                 return;
1145
1146         disabled = (state == VGA_SWITCHEROO_OFF);
1147         if (chip->disabled == disabled)
1148                 return;
1149
1150         if (!hda->probe_continued) {
1151                 chip->disabled = disabled;
1152                 if (!disabled) {
1153                         dev_info(chip->card->dev,
1154                                  "Start delayed initialization\n");
1155                         if (azx_probe_continue(chip) < 0) {
1156                                 dev_err(chip->card->dev, "initialization error\n");
1157                                 hda->init_failed = true;
1158                         }
1159                 }
1160         } else {
1161                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1162                          disabled ? "Disabling" : "Enabling");
1163                 if (disabled) {
1164                         list_for_each_codec(codec, &chip->bus) {
1165                                 pm_runtime_suspend(hda_codec_dev(codec));
1166                                 pm_runtime_disable(hda_codec_dev(codec));
1167                         }
1168                         pm_runtime_suspend(card->dev);
1169                         pm_runtime_disable(card->dev);
1170                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1171                          * however we have no ACPI handle, so pci/acpi can't put us there,
1172                          * put ourselves there */
1173                         pci->current_state = PCI_D3cold;
1174                         chip->disabled = true;
1175                         if (snd_hda_lock_devices(&chip->bus))
1176                                 dev_warn(chip->card->dev,
1177                                          "Cannot lock devices!\n");
1178                 } else {
1179                         snd_hda_unlock_devices(&chip->bus);
1180                         chip->disabled = false;
1181                         pm_runtime_enable(card->dev);
1182                         list_for_each_codec(codec, &chip->bus) {
1183                                 pm_runtime_enable(hda_codec_dev(codec));
1184                                 pm_runtime_resume(hda_codec_dev(codec));
1185                         }
1186                 }
1187         }
1188 }
1189
1190 static bool azx_vs_can_switch(struct pci_dev *pci)
1191 {
1192         struct snd_card *card = pci_get_drvdata(pci);
1193         struct azx *chip = card->private_data;
1194         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1195
1196         wait_for_completion(&hda->probe_wait);
1197         if (hda->init_failed)
1198                 return false;
1199         if (chip->disabled || !hda->probe_continued)
1200                 return true;
1201         if (snd_hda_lock_devices(&chip->bus))
1202                 return false;
1203         snd_hda_unlock_devices(&chip->bus);
1204         return true;
1205 }
1206
1207 /*
1208  * The discrete GPU cannot power down unless the HDA controller runtime
1209  * suspends, so activate runtime PM on codecs even if power_save == 0.
1210  */
1211 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1212 {
1213         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1214         struct hda_codec *codec;
1215
1216         if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1217                 list_for_each_codec(codec, &chip->bus)
1218                         codec->auto_runtime_pm = 1;
1219                 /* reset the power save setup */
1220                 if (chip->running)
1221                         set_default_power_save(chip);
1222         }
1223 }
1224
1225 static void azx_vs_gpu_bound(struct pci_dev *pci,
1226                              enum vga_switcheroo_client_id client_id)
1227 {
1228         struct snd_card *card = pci_get_drvdata(pci);
1229         struct azx *chip = card->private_data;
1230         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1231
1232         if (client_id == VGA_SWITCHEROO_DIS)
1233                 hda->need_eld_notify_link = 0;
1234         setup_vga_switcheroo_runtime_pm(chip);
1235 }
1236
1237 static void init_vga_switcheroo(struct azx *chip)
1238 {
1239         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1240         struct pci_dev *p = get_bound_vga(chip->pci);
1241         if (p) {
1242                 dev_info(chip->card->dev,
1243                          "Handle vga_switcheroo audio client\n");
1244                 hda->use_vga_switcheroo = 1;
1245                 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
1246                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1247                 pci_dev_put(p);
1248         }
1249 }
1250
1251 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1252         .set_gpu_state = azx_vs_set_state,
1253         .can_switch = azx_vs_can_switch,
1254         .gpu_bound = azx_vs_gpu_bound,
1255 };
1256
1257 static int register_vga_switcheroo(struct azx *chip)
1258 {
1259         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1260         struct pci_dev *p;
1261         int err;
1262
1263         if (!hda->use_vga_switcheroo)
1264                 return 0;
1265
1266         p = get_bound_vga(chip->pci);
1267         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1268         pci_dev_put(p);
1269
1270         if (err < 0)
1271                 return err;
1272         hda->vga_switcheroo_registered = 1;
1273
1274         return 0;
1275 }
1276 #else
1277 #define init_vga_switcheroo(chip)               /* NOP */
1278 #define register_vga_switcheroo(chip)           0
1279 #define check_hdmi_disabled(pci)        false
1280 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1281 #endif /* SUPPORT_VGA_SWITCHER */
1282
1283 /*
1284  * destructor
1285  */
1286 static int azx_free(struct azx *chip)
1287 {
1288         struct pci_dev *pci = chip->pci;
1289         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1290         struct hdac_bus *bus = azx_bus(chip);
1291
1292         if (azx_has_pm_runtime(chip) && chip->running)
1293                 pm_runtime_get_noresume(&pci->dev);
1294         chip->running = 0;
1295
1296         azx_del_card_list(chip);
1297
1298         hda->init_failed = 1; /* to be sure */
1299         complete_all(&hda->probe_wait);
1300
1301         if (use_vga_switcheroo(hda)) {
1302                 if (chip->disabled && hda->probe_continued)
1303                         snd_hda_unlock_devices(&chip->bus);
1304                 if (hda->vga_switcheroo_registered)
1305                         vga_switcheroo_unregister_client(chip->pci);
1306         }
1307
1308         if (bus->chip_init) {
1309                 azx_stop_chip(chip);
1310                 azx_clear_irq_pending(chip);
1311                 azx_stop_all_streams(chip);
1312         }
1313
1314         if (bus->irq >= 0)
1315                 free_irq(bus->irq, (void*)chip);
1316         if (chip->msi)
1317                 pci_disable_msi(chip->pci);
1318         iounmap(bus->remap_addr);
1319
1320         azx_free_stream_pages(chip);
1321         azx_free_streams(chip);
1322         snd_hdac_bus_exit(bus);
1323
1324         if (chip->region_requested)
1325                 pci_release_regions(chip->pci);
1326
1327         pci_disable_device(chip->pci);
1328 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1329         release_firmware(chip->fw);
1330 #endif
1331         display_power(chip, false);
1332
1333         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1334                 snd_hdac_i915_exit(bus);
1335         kfree(hda);
1336
1337         return 0;
1338 }
1339
1340 static int azx_dev_disconnect(struct snd_device *device)
1341 {
1342         struct azx *chip = device->device_data;
1343
1344         chip->bus.shutdown = 1;
1345         return 0;
1346 }
1347
1348 static int azx_dev_free(struct snd_device *device)
1349 {
1350         return azx_free(device->device_data);
1351 }
1352
1353 #ifdef SUPPORT_VGA_SWITCHEROO
1354 /*
1355  * Check of disabled HDMI controller by vga_switcheroo
1356  */
1357 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1358 {
1359         struct pci_dev *p;
1360
1361         /* check only discrete GPU */
1362         switch (pci->vendor) {
1363         case PCI_VENDOR_ID_ATI:
1364         case PCI_VENDOR_ID_AMD:
1365         case PCI_VENDOR_ID_NVIDIA:
1366                 if (pci->devfn == 1) {
1367                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1368                                                         pci->bus->number, 0);
1369                         if (p) {
1370                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1371                                         return p;
1372                                 pci_dev_put(p);
1373                         }
1374                 }
1375                 break;
1376         }
1377         return NULL;
1378 }
1379
1380 static bool check_hdmi_disabled(struct pci_dev *pci)
1381 {
1382         bool vga_inactive = false;
1383         struct pci_dev *p = get_bound_vga(pci);
1384
1385         if (p) {
1386                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1387                         vga_inactive = true;
1388                 pci_dev_put(p);
1389         }
1390         return vga_inactive;
1391 }
1392 #endif /* SUPPORT_VGA_SWITCHEROO */
1393
1394 /*
1395  * white/black-listing for position_fix
1396  */
1397 static struct snd_pci_quirk position_fix_list[] = {
1398         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1399         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1400         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1401         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1402         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1403         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1404         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1405         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1406         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1407         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1408         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1409         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1410         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1411         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1412         {}
1413 };
1414
1415 static int check_position_fix(struct azx *chip, int fix)
1416 {
1417         const struct snd_pci_quirk *q;
1418
1419         switch (fix) {
1420         case POS_FIX_AUTO:
1421         case POS_FIX_LPIB:
1422         case POS_FIX_POSBUF:
1423         case POS_FIX_VIACOMBO:
1424         case POS_FIX_COMBO:
1425         case POS_FIX_SKL:
1426                 return fix;
1427         }
1428
1429         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1430         if (q) {
1431                 dev_info(chip->card->dev,
1432                          "position_fix set to %d for device %04x:%04x\n",
1433                          q->value, q->subvendor, q->subdevice);
1434                 return q->value;
1435         }
1436
1437         /* Check VIA/ATI HD Audio Controller exist */
1438         if (chip->driver_type == AZX_DRIVER_VIA) {
1439                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1440                 return POS_FIX_VIACOMBO;
1441         }
1442         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1443                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1444                 return POS_FIX_LPIB;
1445         }
1446         if (chip->driver_type == AZX_DRIVER_SKL) {
1447                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1448                 return POS_FIX_SKL;
1449         }
1450         return POS_FIX_AUTO;
1451 }
1452
1453 static void assign_position_fix(struct azx *chip, int fix)
1454 {
1455         static azx_get_pos_callback_t callbacks[] = {
1456                 [POS_FIX_AUTO] = NULL,
1457                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1458                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1459                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1460                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1461                 [POS_FIX_SKL] = azx_get_pos_skl,
1462         };
1463
1464         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1465
1466         /* combo mode uses LPIB only for playback */
1467         if (fix == POS_FIX_COMBO)
1468                 chip->get_position[1] = NULL;
1469
1470         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1471             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1472                 chip->get_delay[0] = chip->get_delay[1] =
1473                         azx_get_delay_from_lpib;
1474         }
1475
1476 }
1477
1478 /*
1479  * black-lists for probe_mask
1480  */
1481 static struct snd_pci_quirk probe_mask_list[] = {
1482         /* Thinkpad often breaks the controller communication when accessing
1483          * to the non-working (or non-existing) modem codec slot.
1484          */
1485         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1486         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1487         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1488         /* broken BIOS */
1489         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1490         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1491         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1492         /* forced codec slots */
1493         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1494         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1495         /* WinFast VP200 H (Teradici) user reported broken communication */
1496         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1497         {}
1498 };
1499
1500 #define AZX_FORCE_CODEC_MASK    0x100
1501
1502 static void check_probe_mask(struct azx *chip, int dev)
1503 {
1504         const struct snd_pci_quirk *q;
1505
1506         chip->codec_probe_mask = probe_mask[dev];
1507         if (chip->codec_probe_mask == -1) {
1508                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1509                 if (q) {
1510                         dev_info(chip->card->dev,
1511                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1512                                  q->value, q->subvendor, q->subdevice);
1513                         chip->codec_probe_mask = q->value;
1514                 }
1515         }
1516
1517         /* check forced option */
1518         if (chip->codec_probe_mask != -1 &&
1519             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1520                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1521                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1522                          (int)azx_bus(chip)->codec_mask);
1523         }
1524 }
1525
1526 /*
1527  * white/black-list for enable_msi
1528  */
1529 static struct snd_pci_quirk msi_black_list[] = {
1530         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1531         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1532         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1533         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1534         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1535         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1536         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1537         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1538         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1539         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1540         {}
1541 };
1542
1543 static void check_msi(struct azx *chip)
1544 {
1545         const struct snd_pci_quirk *q;
1546
1547         if (enable_msi >= 0) {
1548                 chip->msi = !!enable_msi;
1549                 return;
1550         }
1551         chip->msi = 1;  /* enable MSI as default */
1552         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1553         if (q) {
1554                 dev_info(chip->card->dev,
1555                          "msi for device %04x:%04x set to %d\n",
1556                          q->subvendor, q->subdevice, q->value);
1557                 chip->msi = q->value;
1558                 return;
1559         }
1560
1561         /* NVidia chipsets seem to cause troubles with MSI */
1562         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1563                 dev_info(chip->card->dev, "Disabling MSI\n");
1564                 chip->msi = 0;
1565         }
1566 }
1567
1568 /* check the snoop mode availability */
1569 static void azx_check_snoop_available(struct azx *chip)
1570 {
1571         int snoop = hda_snoop;
1572
1573         if (snoop >= 0) {
1574                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1575                          snoop ? "snoop" : "non-snoop");
1576                 chip->snoop = snoop;
1577                 chip->uc_buffer = !snoop;
1578                 return;
1579         }
1580
1581         snoop = true;
1582         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1583             chip->driver_type == AZX_DRIVER_VIA) {
1584                 /* force to non-snoop mode for a new VIA controller
1585                  * when BIOS is set
1586                  */
1587                 u8 val;
1588                 pci_read_config_byte(chip->pci, 0x42, &val);
1589                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1590                                       chip->pci->revision == 0x20))
1591                         snoop = false;
1592         }
1593
1594         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1595                 snoop = false;
1596
1597         chip->snoop = snoop;
1598         if (!snoop) {
1599                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1600                 /* C-Media requires non-cached pages only for CORB/RIRB */
1601                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1602                         chip->uc_buffer = true;
1603         }
1604 }
1605
1606 static void azx_probe_work(struct work_struct *work)
1607 {
1608         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1609         azx_probe_continue(&hda->chip);
1610 }
1611
1612 static int default_bdl_pos_adj(struct azx *chip)
1613 {
1614         /* some exceptions: Atoms seem problematic with value 1 */
1615         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1616                 switch (chip->pci->device) {
1617                 case 0x0f04: /* Baytrail */
1618                 case 0x2284: /* Braswell */
1619                         return 32;
1620                 }
1621         }
1622
1623         switch (chip->driver_type) {
1624         case AZX_DRIVER_ICH:
1625         case AZX_DRIVER_PCH:
1626                 return 1;
1627         default:
1628                 return 32;
1629         }
1630 }
1631
1632 /*
1633  * constructor
1634  */
1635 static const struct hdac_io_ops pci_hda_io_ops;
1636 static const struct hda_controller_ops pci_hda_ops;
1637
1638 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1639                       int dev, unsigned int driver_caps,
1640                       struct azx **rchip)
1641 {
1642         static struct snd_device_ops ops = {
1643                 .dev_disconnect = azx_dev_disconnect,
1644                 .dev_free = azx_dev_free,
1645         };
1646         struct hda_intel *hda;
1647         struct azx *chip;
1648         int err;
1649
1650         *rchip = NULL;
1651
1652         err = pci_enable_device(pci);
1653         if (err < 0)
1654                 return err;
1655
1656         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1657         if (!hda) {
1658                 pci_disable_device(pci);
1659                 return -ENOMEM;
1660         }
1661
1662         chip = &hda->chip;
1663         mutex_init(&chip->open_mutex);
1664         chip->card = card;
1665         chip->pci = pci;
1666         chip->ops = &pci_hda_ops;
1667         chip->driver_caps = driver_caps;
1668         chip->driver_type = driver_caps & 0xff;
1669         check_msi(chip);
1670         chip->dev_index = dev;
1671         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1672                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1673         INIT_LIST_HEAD(&chip->pcm_list);
1674         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1675         INIT_LIST_HEAD(&hda->list);
1676         init_vga_switcheroo(chip);
1677         init_completion(&hda->probe_wait);
1678
1679         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1680
1681         check_probe_mask(chip, dev);
1682
1683         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1684                 chip->fallback_to_single_cmd = 1;
1685         else /* explicitly set to single_cmd or not */
1686                 chip->single_cmd = single_cmd;
1687
1688         azx_check_snoop_available(chip);
1689
1690         if (bdl_pos_adj[dev] < 0)
1691                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1692         else
1693                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1694
1695         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1696         if (err < 0) {
1697                 kfree(hda);
1698                 pci_disable_device(pci);
1699                 return err;
1700         }
1701
1702         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1703         if (IS_CFL(pci) || IS_CNL(pci))
1704                 azx_bus(chip)->polling_mode = 1;
1705
1706         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1707                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1708                 chip->bus.needs_damn_long_delay = 1;
1709         }
1710
1711         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1712         if (err < 0) {
1713                 dev_err(card->dev, "Error creating device [card]!\n");
1714                 azx_free(chip);
1715                 return err;
1716         }
1717
1718         /* continue probing in work context as may trigger request module */
1719         INIT_WORK(&hda->probe_work, azx_probe_work);
1720
1721         *rchip = chip;
1722
1723         return 0;
1724 }
1725
1726 static int azx_first_init(struct azx *chip)
1727 {
1728         int dev = chip->dev_index;
1729         struct pci_dev *pci = chip->pci;
1730         struct snd_card *card = chip->card;
1731         struct hdac_bus *bus = azx_bus(chip);
1732         int err;
1733         unsigned short gcap;
1734         unsigned int dma_bits = 64;
1735
1736 #if BITS_PER_LONG != 64
1737         /* Fix up base address on ULI M5461 */
1738         if (chip->driver_type == AZX_DRIVER_ULI) {
1739                 u16 tmp3;
1740                 pci_read_config_word(pci, 0x40, &tmp3);
1741                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1742                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1743         }
1744 #endif
1745
1746         err = pci_request_regions(pci, "ICH HD audio");
1747         if (err < 0)
1748                 return err;
1749         chip->region_requested = 1;
1750
1751         bus->addr = pci_resource_start(pci, 0);
1752         bus->remap_addr = pci_ioremap_bar(pci, 0);
1753         if (bus->remap_addr == NULL) {
1754                 dev_err(card->dev, "ioremap error\n");
1755                 return -ENXIO;
1756         }
1757
1758         if (chip->driver_type == AZX_DRIVER_SKL)
1759                 snd_hdac_bus_parse_capabilities(bus);
1760
1761         /*
1762          * Some Intel CPUs has always running timer (ART) feature and
1763          * controller may have Global time sync reporting capability, so
1764          * check both of these before declaring synchronized time reporting
1765          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1766          */
1767         chip->gts_present = false;
1768
1769 #ifdef CONFIG_X86
1770         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1771                 chip->gts_present = true;
1772 #endif
1773
1774         if (chip->msi) {
1775                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1776                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1777                         pci->no_64bit_msi = true;
1778                 }
1779                 if (pci_enable_msi(pci) < 0)
1780                         chip->msi = 0;
1781         }
1782
1783         pci_set_master(pci);
1784         synchronize_irq(bus->irq);
1785
1786         gcap = azx_readw(chip, GCAP);
1787         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1788
1789         /* AMD devices support 40 or 48bit DMA, take the safe one */
1790         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1791                 dma_bits = 40;
1792
1793         /* disable SB600 64bit support for safety */
1794         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1795                 struct pci_dev *p_smbus;
1796                 dma_bits = 40;
1797                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1798                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1799                                          NULL);
1800                 if (p_smbus) {
1801                         if (p_smbus->revision < 0x30)
1802                                 gcap &= ~AZX_GCAP_64OK;
1803                         pci_dev_put(p_smbus);
1804                 }
1805         }
1806
1807         /* NVidia hardware normally only supports up to 40 bits of DMA */
1808         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1809                 dma_bits = 40;
1810
1811         /* disable 64bit DMA address on some devices */
1812         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1813                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1814                 gcap &= ~AZX_GCAP_64OK;
1815         }
1816
1817         /* disable buffer size rounding to 128-byte multiples if supported */
1818         if (align_buffer_size >= 0)
1819                 chip->align_buffer_size = !!align_buffer_size;
1820         else {
1821                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1822                         chip->align_buffer_size = 0;
1823                 else
1824                         chip->align_buffer_size = 1;
1825         }
1826
1827         /* allow 64bit DMA address if supported by H/W */
1828         if (!(gcap & AZX_GCAP_64OK))
1829                 dma_bits = 32;
1830         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1831                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1832         } else {
1833                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1834                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1835         }
1836
1837         /* read number of streams from GCAP register instead of using
1838          * hardcoded value
1839          */
1840         chip->capture_streams = (gcap >> 8) & 0x0f;
1841         chip->playback_streams = (gcap >> 12) & 0x0f;
1842         if (!chip->playback_streams && !chip->capture_streams) {
1843                 /* gcap didn't give any info, switching to old method */
1844
1845                 switch (chip->driver_type) {
1846                 case AZX_DRIVER_ULI:
1847                         chip->playback_streams = ULI_NUM_PLAYBACK;
1848                         chip->capture_streams = ULI_NUM_CAPTURE;
1849                         break;
1850                 case AZX_DRIVER_ATIHDMI:
1851                 case AZX_DRIVER_ATIHDMI_NS:
1852                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1853                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1854                         break;
1855                 case AZX_DRIVER_GENERIC:
1856                 default:
1857                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1858                         chip->capture_streams = ICH6_NUM_CAPTURE;
1859                         break;
1860                 }
1861         }
1862         chip->capture_index_offset = 0;
1863         chip->playback_index_offset = chip->capture_streams;
1864         chip->num_streams = chip->playback_streams + chip->capture_streams;
1865
1866         /* sanity check for the SDxCTL.STRM field overflow */
1867         if (chip->num_streams > 15 &&
1868             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1869                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1870                          "forcing separate stream tags", chip->num_streams);
1871                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1872         }
1873
1874         /* initialize streams */
1875         err = azx_init_streams(chip);
1876         if (err < 0)
1877                 return err;
1878
1879         err = azx_alloc_stream_pages(chip);
1880         if (err < 0)
1881                 return err;
1882
1883         /* initialize chip */
1884         azx_init_pci(chip);
1885
1886         snd_hdac_i915_set_bclk(bus);
1887
1888         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1889
1890         /* codec detection */
1891         if (!azx_bus(chip)->codec_mask) {
1892                 dev_err(card->dev, "no codecs found!\n");
1893                 return -ENODEV;
1894         }
1895
1896         if (azx_acquire_irq(chip, 0) < 0)
1897                 return -EBUSY;
1898
1899         strcpy(card->driver, "HDA-Intel");
1900         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1901                 sizeof(card->shortname));
1902         snprintf(card->longname, sizeof(card->longname),
1903                  "%s at 0x%lx irq %i",
1904                  card->shortname, bus->addr, bus->irq);
1905
1906         return 0;
1907 }
1908
1909 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1910 /* callback from request_firmware_nowait() */
1911 static void azx_firmware_cb(const struct firmware *fw, void *context)
1912 {
1913         struct snd_card *card = context;
1914         struct azx *chip = card->private_data;
1915         struct pci_dev *pci = chip->pci;
1916
1917         if (!fw) {
1918                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1919                 goto error;
1920         }
1921
1922         chip->fw = fw;
1923         if (!chip->disabled) {
1924                 /* continue probing */
1925                 if (azx_probe_continue(chip))
1926                         goto error;
1927         }
1928         return; /* OK */
1929
1930  error:
1931         snd_card_free(card);
1932         pci_set_drvdata(pci, NULL);
1933 }
1934 #endif
1935
1936 /*
1937  * HDA controller ops.
1938  */
1939
1940 /* PCI register access. */
1941 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1942 {
1943         writel(value, addr);
1944 }
1945
1946 static u32 pci_azx_readl(u32 __iomem *addr)
1947 {
1948         return readl(addr);
1949 }
1950
1951 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1952 {
1953         writew(value, addr);
1954 }
1955
1956 static u16 pci_azx_readw(u16 __iomem *addr)
1957 {
1958         return readw(addr);
1959 }
1960
1961 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1962 {
1963         writeb(value, addr);
1964 }
1965
1966 static u8 pci_azx_readb(u8 __iomem *addr)
1967 {
1968         return readb(addr);
1969 }
1970
1971 static int disable_msi_reset_irq(struct azx *chip)
1972 {
1973         struct hdac_bus *bus = azx_bus(chip);
1974         int err;
1975
1976         free_irq(bus->irq, chip);
1977         bus->irq = -1;
1978         pci_disable_msi(chip->pci);
1979         chip->msi = 0;
1980         err = azx_acquire_irq(chip, 1);
1981         if (err < 0)
1982                 return err;
1983
1984         return 0;
1985 }
1986
1987 /* DMA page allocation helpers.  */
1988 static int dma_alloc_pages(struct hdac_bus *bus,
1989                            int type,
1990                            size_t size,
1991                            struct snd_dma_buffer *buf)
1992 {
1993         struct azx *chip = bus_to_azx(bus);
1994
1995         if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV)
1996                 type = SNDRV_DMA_TYPE_DEV_UC;
1997         return snd_dma_alloc_pages(type, bus->dev, size, buf);
1998 }
1999
2000 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2001 {
2002         snd_dma_free_pages(buf);
2003 }
2004
2005 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2006                              struct vm_area_struct *area)
2007 {
2008 #ifdef CONFIG_X86
2009         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2010         struct azx *chip = apcm->chip;
2011         if (chip->uc_buffer)
2012                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2013 #endif
2014 }
2015
2016 static const struct hdac_io_ops pci_hda_io_ops = {
2017         .reg_writel = pci_azx_writel,
2018         .reg_readl = pci_azx_readl,
2019         .reg_writew = pci_azx_writew,
2020         .reg_readw = pci_azx_readw,
2021         .reg_writeb = pci_azx_writeb,
2022         .reg_readb = pci_azx_readb,
2023         .dma_alloc_pages = dma_alloc_pages,
2024         .dma_free_pages = dma_free_pages,
2025 };
2026
2027 static const struct hda_controller_ops pci_hda_ops = {
2028         .disable_msi_reset_irq = disable_msi_reset_irq,
2029         .pcm_mmap_prepare = pcm_mmap_prepare,
2030         .position_check = azx_position_check,
2031 };
2032
2033 static int azx_check_dmic(struct pci_dev *pci, struct azx *chip)
2034 {
2035         struct nhlt_acpi_table *nhlt;
2036         int ret = 0;
2037
2038         if (chip->driver_type == AZX_DRIVER_SKL &&
2039             pci->class != 0x040300) {
2040                 nhlt = intel_nhlt_init(&pci->dev);
2041                 if (nhlt) {
2042                         if (intel_nhlt_get_dmic_geo(&pci->dev, nhlt)) {
2043                                 ret = -ENODEV;
2044                                 dev_info(&pci->dev, "Digital mics found on Skylake+ platform, aborting probe\n");
2045                         }
2046                         intel_nhlt_free(nhlt);
2047                 }
2048         }
2049         return ret;
2050 }
2051
2052 static int azx_probe(struct pci_dev *pci,
2053                      const struct pci_device_id *pci_id)
2054 {
2055         static int dev;
2056         struct snd_card *card;
2057         struct hda_intel *hda;
2058         struct azx *chip;
2059         bool schedule_probe;
2060         int err;
2061
2062         if (dev >= SNDRV_CARDS)
2063                 return -ENODEV;
2064         if (!enable[dev]) {
2065                 dev++;
2066                 return -ENOENT;
2067         }
2068
2069         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2070                            0, &card);
2071         if (err < 0) {
2072                 dev_err(&pci->dev, "Error creating card!\n");
2073                 return err;
2074         }
2075
2076         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2077         if (err < 0)
2078                 goto out_free;
2079         card->private_data = chip;
2080         hda = container_of(chip, struct hda_intel, chip);
2081
2082         /*
2083          * stop probe if digital microphones detected on Skylake+ platform
2084          * with the DSP enabled. This is an opt-in behavior defined at build
2085          * time or at run-time with a module parameter
2086          */
2087         if (dmic_detect) {
2088                 err = azx_check_dmic(pci, chip);
2089                 if (err < 0)
2090                         goto out_free;
2091         }
2092
2093         pci_set_drvdata(pci, card);
2094
2095         err = register_vga_switcheroo(chip);
2096         if (err < 0) {
2097                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2098                 goto out_free;
2099         }
2100
2101         if (check_hdmi_disabled(pci)) {
2102                 dev_info(card->dev, "VGA controller is disabled\n");
2103                 dev_info(card->dev, "Delaying initialization\n");
2104                 chip->disabled = true;
2105         }
2106
2107         schedule_probe = !chip->disabled;
2108
2109 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2110         if (patch[dev] && *patch[dev]) {
2111                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2112                          patch[dev]);
2113                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2114                                               &pci->dev, GFP_KERNEL, card,
2115                                               azx_firmware_cb);
2116                 if (err < 0)
2117                         goto out_free;
2118                 schedule_probe = false; /* continued in azx_firmware_cb() */
2119         }
2120 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2121
2122 #ifndef CONFIG_SND_HDA_I915
2123         if (CONTROLLER_IN_GPU(pci))
2124                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2125 #endif
2126
2127         if (schedule_probe)
2128                 schedule_work(&hda->probe_work);
2129
2130         dev++;
2131         if (chip->disabled)
2132                 complete_all(&hda->probe_wait);
2133         return 0;
2134
2135 out_free:
2136         snd_card_free(card);
2137         return err;
2138 }
2139
2140 #ifdef CONFIG_PM
2141 /* On some boards setting power_save to a non 0 value leads to clicking /
2142  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2143  * figure out how to avoid these sounds, but that is not always feasible.
2144  * So we keep a list of devices where we disable powersaving as its known
2145  * to causes problems on these devices.
2146  */
2147 static struct snd_pci_quirk power_save_blacklist[] = {
2148         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2149         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2150         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2151         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2152         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2153         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2154         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2155         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2156         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2157         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2158         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2159         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2160         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2161         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2162         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2163         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2164         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2165         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2166         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2167         /* https://bugs.launchpad.net/bugs/1821663 */
2168         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2169         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2170         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2171         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2172         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2173         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2174         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2175         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2176         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2177         /* https://bugs.launchpad.net/bugs/1821663 */
2178         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2179         {}
2180 };
2181 #endif /* CONFIG_PM */
2182
2183 static void set_default_power_save(struct azx *chip)
2184 {
2185         int val = power_save;
2186
2187 #ifdef CONFIG_PM
2188         if (pm_blacklist) {
2189                 const struct snd_pci_quirk *q;
2190
2191                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2192                 if (q && val) {
2193                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2194                                  q->subvendor, q->subdevice);
2195                         val = 0;
2196                 }
2197         }
2198 #endif /* CONFIG_PM */
2199         snd_hda_set_power_save(&chip->bus, val * 1000);
2200 }
2201
2202 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2203 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2204         [AZX_DRIVER_NVIDIA] = 8,
2205         [AZX_DRIVER_TERA] = 1,
2206 };
2207
2208 static int azx_probe_continue(struct azx *chip)
2209 {
2210         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2211         struct hdac_bus *bus = azx_bus(chip);
2212         struct pci_dev *pci = chip->pci;
2213         int dev = chip->dev_index;
2214         int err;
2215
2216         to_hda_bus(bus)->bus_probing = 1;
2217         hda->probe_continued = 1;
2218
2219         /* bind with i915 if needed */
2220         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2221                 err = snd_hdac_i915_init(bus);
2222                 if (err < 0) {
2223                         /* if the controller is bound only with HDMI/DP
2224                          * (for HSW and BDW), we need to abort the probe;
2225                          * for other chips, still continue probing as other
2226                          * codecs can be on the same link.
2227                          */
2228                         if (CONTROLLER_IN_GPU(pci)) {
2229                                 dev_err(chip->card->dev,
2230                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2231                                 goto out_free;
2232                         } else {
2233                                 /* don't bother any longer */
2234                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2235                         }
2236                 }
2237
2238                 /* HSW/BDW controllers need this power */
2239                 if (CONTROLLER_IN_GPU(pci))
2240                         hda->need_i915_power = 1;
2241         }
2242
2243         /* Request display power well for the HDA controller or codec. For
2244          * Haswell/Broadwell, both the display HDA controller and codec need
2245          * this power. For other platforms, like Baytrail/Braswell, only the
2246          * display codec needs the power and it can be released after probe.
2247          */
2248         display_power(chip, true);
2249
2250         err = azx_first_init(chip);
2251         if (err < 0)
2252                 goto out_free;
2253
2254 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2255         chip->beep_mode = beep_mode[dev];
2256 #endif
2257
2258         /* create codec instances */
2259         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2260         if (err < 0)
2261                 goto out_free;
2262
2263 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2264         if (chip->fw) {
2265                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2266                                          chip->fw->data);
2267                 if (err < 0)
2268                         goto out_free;
2269 #ifndef CONFIG_PM
2270                 release_firmware(chip->fw); /* no longer needed */
2271                 chip->fw = NULL;
2272 #endif
2273         }
2274 #endif
2275         if ((probe_only[dev] & 1) == 0) {
2276                 err = azx_codec_configure(chip);
2277                 if (err < 0)
2278                         goto out_free;
2279         }
2280
2281         err = snd_card_register(chip->card);
2282         if (err < 0)
2283                 goto out_free;
2284
2285         setup_vga_switcheroo_runtime_pm(chip);
2286
2287         chip->running = 1;
2288         azx_add_card_list(chip);
2289
2290         set_default_power_save(chip);
2291
2292         if (azx_has_pm_runtime(chip))
2293                 pm_runtime_put_autosuspend(&pci->dev);
2294
2295 out_free:
2296         if (err < 0 || !hda->need_i915_power)
2297                 display_power(chip, false);
2298         if (err < 0)
2299                 hda->init_failed = 1;
2300         complete_all(&hda->probe_wait);
2301         to_hda_bus(bus)->bus_probing = 0;
2302         return err;
2303 }
2304
2305 static void azx_remove(struct pci_dev *pci)
2306 {
2307         struct snd_card *card = pci_get_drvdata(pci);
2308         struct azx *chip;
2309         struct hda_intel *hda;
2310
2311         if (card) {
2312                 /* cancel the pending probing work */
2313                 chip = card->private_data;
2314                 hda = container_of(chip, struct hda_intel, chip);
2315                 /* FIXME: below is an ugly workaround.
2316                  * Both device_release_driver() and driver_probe_device()
2317                  * take *both* the device's and its parent's lock before
2318                  * calling the remove() and probe() callbacks.  The codec
2319                  * probe takes the locks of both the codec itself and its
2320                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2321                  * the PCI controller is unbound, it takes its lock, too
2322                  * ==> ouch, a deadlock!
2323                  * As a workaround, we unlock temporarily here the controller
2324                  * device during cancel_work_sync() call.
2325                  */
2326                 device_unlock(&pci->dev);
2327                 cancel_work_sync(&hda->probe_work);
2328                 device_lock(&pci->dev);
2329
2330                 snd_card_free(card);
2331         }
2332 }
2333
2334 static void azx_shutdown(struct pci_dev *pci)
2335 {
2336         struct snd_card *card = pci_get_drvdata(pci);
2337         struct azx *chip;
2338
2339         if (!card)
2340                 return;
2341         chip = card->private_data;
2342         if (chip && chip->running)
2343                 azx_stop_chip(chip);
2344 }
2345
2346 /* PCI IDs */
2347 static const struct pci_device_id azx_ids[] = {
2348         /* CPT */
2349         { PCI_DEVICE(0x8086, 0x1c20),
2350           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2351         /* PBG */
2352         { PCI_DEVICE(0x8086, 0x1d20),
2353           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2354         /* Panther Point */
2355         { PCI_DEVICE(0x8086, 0x1e20),
2356           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2357         /* Lynx Point */
2358         { PCI_DEVICE(0x8086, 0x8c20),
2359           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2360         /* 9 Series */
2361         { PCI_DEVICE(0x8086, 0x8ca0),
2362           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2363         /* Wellsburg */
2364         { PCI_DEVICE(0x8086, 0x8d20),
2365           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2366         { PCI_DEVICE(0x8086, 0x8d21),
2367           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2368         /* Lewisburg */
2369         { PCI_DEVICE(0x8086, 0xa1f0),
2370           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2371         { PCI_DEVICE(0x8086, 0xa270),
2372           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2373         /* Lynx Point-LP */
2374         { PCI_DEVICE(0x8086, 0x9c20),
2375           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2376         /* Lynx Point-LP */
2377         { PCI_DEVICE(0x8086, 0x9c21),
2378           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2379         /* Wildcat Point-LP */
2380         { PCI_DEVICE(0x8086, 0x9ca0),
2381           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2382         /* Sunrise Point */
2383         { PCI_DEVICE(0x8086, 0xa170),
2384           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2385         /* Sunrise Point-LP */
2386         { PCI_DEVICE(0x8086, 0x9d70),
2387           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2388         /* Kabylake */
2389         { PCI_DEVICE(0x8086, 0xa171),
2390           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2391         /* Kabylake-LP */
2392         { PCI_DEVICE(0x8086, 0x9d71),
2393           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2394         /* Kabylake-H */
2395         { PCI_DEVICE(0x8086, 0xa2f0),
2396           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2397         /* Coffelake */
2398         { PCI_DEVICE(0x8086, 0xa348),
2399           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2400         /* Cannonlake */
2401         { PCI_DEVICE(0x8086, 0x9dc8),
2402           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2403         /* CometLake-LP */
2404         { PCI_DEVICE(0x8086, 0x02C8),
2405           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2406         /* CometLake-H */
2407         { PCI_DEVICE(0x8086, 0x06C8),
2408           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2409         /* Icelake */
2410         { PCI_DEVICE(0x8086, 0x34c8),
2411           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2412         /* Elkhart Lake */
2413         { PCI_DEVICE(0x8086, 0x4b55),
2414           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2415         /* Broxton-P(Apollolake) */
2416         { PCI_DEVICE(0x8086, 0x5a98),
2417           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2418         /* Broxton-T */
2419         { PCI_DEVICE(0x8086, 0x1a98),
2420           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2421         /* Gemini-Lake */
2422         { PCI_DEVICE(0x8086, 0x3198),
2423           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2424         /* Haswell */
2425         { PCI_DEVICE(0x8086, 0x0a0c),
2426           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2427         { PCI_DEVICE(0x8086, 0x0c0c),
2428           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2429         { PCI_DEVICE(0x8086, 0x0d0c),
2430           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2431         /* Broadwell */
2432         { PCI_DEVICE(0x8086, 0x160c),
2433           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2434         /* 5 Series/3400 */
2435         { PCI_DEVICE(0x8086, 0x3b56),
2436           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2437         /* Poulsbo */
2438         { PCI_DEVICE(0x8086, 0x811b),
2439           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2440         /* Oaktrail */
2441         { PCI_DEVICE(0x8086, 0x080a),
2442           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2443         /* BayTrail */
2444         { PCI_DEVICE(0x8086, 0x0f04),
2445           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2446         /* Braswell */
2447         { PCI_DEVICE(0x8086, 0x2284),
2448           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2449         /* ICH6 */
2450         { PCI_DEVICE(0x8086, 0x2668),
2451           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2452         /* ICH7 */
2453         { PCI_DEVICE(0x8086, 0x27d8),
2454           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2455         /* ESB2 */
2456         { PCI_DEVICE(0x8086, 0x269a),
2457           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2458         /* ICH8 */
2459         { PCI_DEVICE(0x8086, 0x284b),
2460           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2461         /* ICH9 */
2462         { PCI_DEVICE(0x8086, 0x293e),
2463           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2464         /* ICH9 */
2465         { PCI_DEVICE(0x8086, 0x293f),
2466           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2467         /* ICH10 */
2468         { PCI_DEVICE(0x8086, 0x3a3e),
2469           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2470         /* ICH10 */
2471         { PCI_DEVICE(0x8086, 0x3a6e),
2472           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2473         /* Generic Intel */
2474         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2475           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2476           .class_mask = 0xffffff,
2477           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2478         /* ATI SB 450/600/700/800/900 */
2479         { PCI_DEVICE(0x1002, 0x437b),
2480           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2481         { PCI_DEVICE(0x1002, 0x4383),
2482           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2483         /* AMD Hudson */
2484         { PCI_DEVICE(0x1022, 0x780d),
2485           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2486         /* AMD Stoney */
2487         { PCI_DEVICE(0x1022, 0x157a),
2488           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2489                          AZX_DCAPS_PM_RUNTIME },
2490         /* AMD Raven */
2491         { PCI_DEVICE(0x1022, 0x15e3),
2492           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2493                          AZX_DCAPS_PM_RUNTIME },
2494         /* ATI HDMI */
2495         { PCI_DEVICE(0x1002, 0x0002),
2496           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2497         { PCI_DEVICE(0x1002, 0x1308),
2498           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2499         { PCI_DEVICE(0x1002, 0x157a),
2500           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2501         { PCI_DEVICE(0x1002, 0x15b3),
2502           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2503         { PCI_DEVICE(0x1002, 0x793b),
2504           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2505         { PCI_DEVICE(0x1002, 0x7919),
2506           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2507         { PCI_DEVICE(0x1002, 0x960f),
2508           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2509         { PCI_DEVICE(0x1002, 0x970f),
2510           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2511         { PCI_DEVICE(0x1002, 0x9840),
2512           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2513         { PCI_DEVICE(0x1002, 0xaa00),
2514           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2515         { PCI_DEVICE(0x1002, 0xaa08),
2516           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2517         { PCI_DEVICE(0x1002, 0xaa10),
2518           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2519         { PCI_DEVICE(0x1002, 0xaa18),
2520           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2521         { PCI_DEVICE(0x1002, 0xaa20),
2522           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2523         { PCI_DEVICE(0x1002, 0xaa28),
2524           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2525         { PCI_DEVICE(0x1002, 0xaa30),
2526           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2527         { PCI_DEVICE(0x1002, 0xaa38),
2528           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2529         { PCI_DEVICE(0x1002, 0xaa40),
2530           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2531         { PCI_DEVICE(0x1002, 0xaa48),
2532           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2533         { PCI_DEVICE(0x1002, 0xaa50),
2534           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2535         { PCI_DEVICE(0x1002, 0xaa58),
2536           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2537         { PCI_DEVICE(0x1002, 0xaa60),
2538           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2539         { PCI_DEVICE(0x1002, 0xaa68),
2540           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2541         { PCI_DEVICE(0x1002, 0xaa80),
2542           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2543         { PCI_DEVICE(0x1002, 0xaa88),
2544           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2545         { PCI_DEVICE(0x1002, 0xaa90),
2546           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2547         { PCI_DEVICE(0x1002, 0xaa98),
2548           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2549         { PCI_DEVICE(0x1002, 0x9902),
2550           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2551         { PCI_DEVICE(0x1002, 0xaaa0),
2552           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2553         { PCI_DEVICE(0x1002, 0xaaa8),
2554           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2555         { PCI_DEVICE(0x1002, 0xaab0),
2556           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2557         { PCI_DEVICE(0x1002, 0xaac0),
2558           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2559         { PCI_DEVICE(0x1002, 0xaac8),
2560           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2561         { PCI_DEVICE(0x1002, 0xaad8),
2562           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2563         { PCI_DEVICE(0x1002, 0xaae8),
2564           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2565         { PCI_DEVICE(0x1002, 0xaae0),
2566           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2567         { PCI_DEVICE(0x1002, 0xaaf0),
2568           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2569         /* VIA VT8251/VT8237A */
2570         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2571         /* VIA GFX VT7122/VX900 */
2572         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2573         /* VIA GFX VT6122/VX11 */
2574         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2575         /* SIS966 */
2576         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2577         /* ULI M5461 */
2578         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2579         /* NVIDIA MCP */
2580         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2581           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2582           .class_mask = 0xffffff,
2583           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2584         /* Teradici */
2585         { PCI_DEVICE(0x6549, 0x1200),
2586           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2587         { PCI_DEVICE(0x6549, 0x2200),
2588           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2589         /* Creative X-Fi (CA0110-IBG) */
2590         /* CTHDA chips */
2591         { PCI_DEVICE(0x1102, 0x0010),
2592           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2593         { PCI_DEVICE(0x1102, 0x0012),
2594           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2595 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2596         /* the following entry conflicts with snd-ctxfi driver,
2597          * as ctxfi driver mutates from HD-audio to native mode with
2598          * a special command sequence.
2599          */
2600         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2601           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2602           .class_mask = 0xffffff,
2603           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2604           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2605 #else
2606         /* this entry seems still valid -- i.e. without emu20kx chip */
2607         { PCI_DEVICE(0x1102, 0x0009),
2608           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2609           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2610 #endif
2611         /* CM8888 */
2612         { PCI_DEVICE(0x13f6, 0x5011),
2613           .driver_data = AZX_DRIVER_CMEDIA |
2614           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2615         /* Vortex86MX */
2616         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2617         /* VMware HDAudio */
2618         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2619         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2620         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2621           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2622           .class_mask = 0xffffff,
2623           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2624         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2625           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2626           .class_mask = 0xffffff,
2627           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2628         /* Zhaoxin */
2629         { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2630         { 0, }
2631 };
2632 MODULE_DEVICE_TABLE(pci, azx_ids);
2633
2634 /* pci_driver definition */
2635 static struct pci_driver azx_driver = {
2636         .name = KBUILD_MODNAME,
2637         .id_table = azx_ids,
2638         .probe = azx_probe,
2639         .remove = azx_remove,
2640         .shutdown = azx_shutdown,
2641         .driver = {
2642                 .pm = AZX_PM_OPS,
2643         },
2644 };
2645
2646 module_pci_driver(azx_driver);