sound/pci/hda/hda_controller.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  Implementation of primary alsa driver code base for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  */
  11
  12 #include <linux/clocksource.h>
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/slab.h>
  19
  20 #ifdef CONFIG_X86
  21 /* for art-tsc conversion */
  22 #include <asm/tsc.h>
  23 #endif
  24
  25 #include <sound/core.h>
  26 #include <sound/initval.h>
  27 #include "hda_controller.h"
  28 #include "hda_local.h"
  29
  30 #define CREATE_TRACE_POINTS
  31 #include "hda_controller_trace.h"
  32
  33 /* DSP lock helpers */
  34 #define dsp_lock(dev)           snd_hdac_dsp_lock(azx_stream(dev))
  35 #define dsp_unlock(dev)         snd_hdac_dsp_unlock(azx_stream(dev))
  36 #define dsp_is_locked(dev)      snd_hdac_stream_is_locked(azx_stream(dev))
  37
  38 /* assign a stream for the PCM */
  39 static inline struct azx_dev *
  40 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
  41 {
  42         struct hdac_stream *s;
  43
  44         s = snd_hdac_stream_assign(azx_bus(chip), substream);
  45         if (!s)
  46                 return NULL;
  47         return stream_to_azx_dev(s);
  48 }
  49
  50 /* release the assigned stream */
  51 static inline void azx_release_device(struct azx_dev *azx_dev)
  52 {
  53         snd_hdac_stream_release(azx_stream(azx_dev));
  54 }
  55
  56 static inline struct hda_pcm_stream *
  57 to_hda_pcm_stream(struct snd_pcm_substream *substream)
  58 {
  59         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  60         return &apcm->info->stream[substream->stream];
  61 }
  62
  63 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
  64                                 u64 nsec)
  65 {
  66         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  67         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
  68         u64 codec_frames, codec_nsecs;
  69
  70         if (!hinfo->ops.get_delay)
  71                 return nsec;
  72
  73         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
  74         codec_nsecs = div_u64(codec_frames * 1000000000LL,
  75                               substream->runtime->rate);
  76
  77         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  78                 return nsec + codec_nsecs;
  79
  80         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
  81 }
  82
  83 /*
  84  * PCM ops
  85  */
  86
  87 static int azx_pcm_close(struct snd_pcm_substream *substream)
  88 {
  89         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  90         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
  91         struct azx *chip = apcm->chip;
  92         struct azx_dev *azx_dev = get_azx_dev(substream);
  93
  94         trace_azx_pcm_close(chip, azx_dev);
  95         mutex_lock(&chip->open_mutex);
  96         azx_release_device(azx_dev);
  97         if (hinfo->ops.close)
  98                 hinfo->ops.close(hinfo, apcm->codec, substream);
  99         snd_hda_power_down(apcm->codec);
 100         mutex_unlock(&chip->open_mutex);
 101         snd_hda_codec_pcm_put(apcm->info);
 102         return 0;
 103 }
 104
 105 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
 106                              struct snd_pcm_hw_params *hw_params)
 107 {
 108         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 109         struct azx *chip = apcm->chip;
 110         struct azx_dev *azx_dev = get_azx_dev(substream);
 111         int ret = 0;
 112
 113         trace_azx_pcm_hw_params(chip, azx_dev);
 114         dsp_lock(azx_dev);
 115         if (dsp_is_locked(azx_dev)) {
 116                 ret = -EBUSY;
 117                 goto unlock;
 118         }
 119
 120         azx_dev->core.bufsize = 0;
 121         azx_dev->core.period_bytes = 0;
 122         azx_dev->core.format_val = 0;
 123
 124 unlock:
 125         dsp_unlock(azx_dev);
 126         return ret;
 127 }
 128
 129 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
 130 {
 131         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 132         struct azx_dev *azx_dev = get_azx_dev(substream);
 133         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 134
 135         /* reset BDL address */
 136         dsp_lock(azx_dev);
 137         if (!dsp_is_locked(azx_dev))
 138                 snd_hdac_stream_cleanup(azx_stream(azx_dev));
 139
 140         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
 141
 142         azx_stream(azx_dev)->prepared = 0;
 143         dsp_unlock(azx_dev);
 144         return 0;
 145 }
 146
 147 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
 148 {
 149         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 150         struct azx *chip = apcm->chip;
 151         struct azx_dev *azx_dev = get_azx_dev(substream);
 152         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 153         struct snd_pcm_runtime *runtime = substream->runtime;
 154         unsigned int format_val, stream_tag, bits;
 155         int err;
 156         struct hda_spdif_out *spdif =
 157                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
 158         unsigned short ctls = spdif ? spdif->ctls : 0;
 159
 160         trace_azx_pcm_prepare(chip, azx_dev);
 161         dsp_lock(azx_dev);
 162         if (dsp_is_locked(azx_dev)) {
 163                 err = -EBUSY;
 164                 goto unlock;
 165         }
 166
 167         snd_hdac_stream_reset(azx_stream(azx_dev));
 168         bits = snd_hdac_stream_format_bits(runtime->format, SNDRV_PCM_SUBFORMAT_STD, hinfo->maxbps);
 169
 170         format_val = snd_hdac_spdif_stream_format(runtime->channels, bits, runtime->rate, ctls);
 171         if (!format_val) {
 172                 dev_err(chip->card->dev,
 173                         "invalid format_val, rate=%d, ch=%d, format=%d\n",
 174                         runtime->rate, runtime->channels, runtime->format);
 175                 err = -EINVAL;
 176                 goto unlock;
 177         }
 178
 179         err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val);
 180         if (err < 0)
 181                 goto unlock;
 182
 183         snd_hdac_stream_setup(azx_stream(azx_dev), false);
 184
 185         stream_tag = azx_dev->core.stream_tag;
 186         /* CA-IBG chips need the playback stream starting from 1 */
 187         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
 188             stream_tag > chip->capture_streams)
 189                 stream_tag -= chip->capture_streams;
 190         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
 191                                      azx_dev->core.format_val, substream);
 192
 193  unlock:
 194         if (!err)
 195                 azx_stream(azx_dev)->prepared = 1;
 196         dsp_unlock(azx_dev);
 197         return err;
 198 }
 199
 200 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 201 {
 202         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 203         struct azx *chip = apcm->chip;
 204         struct hdac_bus *bus = azx_bus(chip);
 205         struct azx_dev *azx_dev;
 206         struct snd_pcm_substream *s;
 207         struct hdac_stream *hstr;
 208         bool start;
 209         int sbits = 0;
 210         int sync_reg;
 211
 212         azx_dev = get_azx_dev(substream);
 213         trace_azx_pcm_trigger(chip, azx_dev, cmd);
 214
 215         hstr = azx_stream(azx_dev);
 216         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
 217                 sync_reg = AZX_REG_OLD_SSYNC;
 218         else
 219                 sync_reg = AZX_REG_SSYNC;
 220
 221         if (dsp_is_locked(azx_dev) || !hstr->prepared)
 222                 return -EPIPE;
 223
 224         switch (cmd) {
 225         case SNDRV_PCM_TRIGGER_START:
 226         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 227         case SNDRV_PCM_TRIGGER_RESUME:
 228                 start = true;
 229                 break;
 230         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 231         case SNDRV_PCM_TRIGGER_SUSPEND:
 232         case SNDRV_PCM_TRIGGER_STOP:
 233                 start = false;
 234                 break;
 235         default:
 236                 return -EINVAL;
 237         }
 238
 239         snd_pcm_group_for_each_entry(s, substream) {
 240                 if (s->pcm->card != substream->pcm->card)
 241                         continue;
 242                 azx_dev = get_azx_dev(s);
 243                 sbits |= 1 << azx_dev->core.index;
 244                 snd_pcm_trigger_done(s, substream);
 245         }
 246
 247         spin_lock(&bus->reg_lock);
 248
 249         /* first, set SYNC bits of corresponding streams */
 250         snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
 251
 252         snd_pcm_group_for_each_entry(s, substream) {
 253                 if (s->pcm->card != substream->pcm->card)
 254                         continue;
 255                 azx_dev = get_azx_dev(s);
 256                 if (start) {
 257                         azx_dev->insufficient = 1;
 258                         snd_hdac_stream_start(azx_stream(azx_dev));
 259                 } else {
 260                         snd_hdac_stream_stop(azx_stream(azx_dev));
 261                 }
 262         }
 263         spin_unlock(&bus->reg_lock);
 264
 265         snd_hdac_stream_sync(hstr, start, sbits);
 266
 267         spin_lock(&bus->reg_lock);
 268         /* reset SYNC bits */
 269         snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
 270         if (start)
 271                 snd_hdac_stream_timecounter_init(hstr, sbits);
 272         spin_unlock(&bus->reg_lock);
 273         return 0;
 274 }
 275
 276 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
 277 {
 278         return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 279 }
 280 EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
 281
 282 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
 283 {
 284         return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev));
 285 }
 286 EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
 287
 288 unsigned int azx_get_position(struct azx *chip,
 289                               struct azx_dev *azx_dev)
 290 {
 291         struct snd_pcm_substream *substream = azx_dev->core.substream;
 292         unsigned int pos;
 293         int stream = substream->stream;
 294         int delay = 0;
 295
 296         if (chip->get_position[stream])
 297                 pos = chip->get_position[stream](chip, azx_dev);
 298         else /* use the position buffer as default */
 299                 pos = azx_get_pos_posbuf(chip, azx_dev);
 300
 301         if (pos >= azx_dev->core.bufsize)
 302                 pos = 0;
 303
 304         if (substream->runtime) {
 305                 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 306                 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 307
 308                 if (chip->get_delay[stream])
 309                         delay += chip->get_delay[stream](chip, azx_dev, pos);
 310                 if (hinfo->ops.get_delay)
 311                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
 312                                                       substream);
 313                 substream->runtime->delay = delay;
 314         }
 315
 316         trace_azx_get_position(chip, azx_dev, pos, delay);
 317         return pos;
 318 }
 319 EXPORT_SYMBOL_GPL(azx_get_position);
 320
 321 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
 322 {
 323         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 324         struct azx *chip = apcm->chip;
 325         struct azx_dev *azx_dev = get_azx_dev(substream);
 326         return bytes_to_frames(substream->runtime,
 327                                azx_get_position(chip, azx_dev));
 328 }
 329
 330 /*
 331  * azx_scale64: Scale base by mult/div while not overflowing sanely
 332  *
 333  * Derived from scale64_check_overflow in kernel/time/timekeeping.c
 334  *
 335  * The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which
 336  * is about 384307 ie ~4.5 days.
 337  *
 338  * This scales the calculation so that overflow will happen but after 2^64 /
 339  * 48000 secs, which is pretty large!
 340  *
 341  * In caln below:
 342  *      base may overflow, but since there isn’t any additional division
 343  *      performed on base it’s OK
 344  *      rem can’t overflow because both are 32-bit values
 345  */
 346
 347 #ifdef CONFIG_X86
 348 static u64 azx_scale64(u64 base, u32 num, u32 den)
 349 {
 350         u64 rem;
 351
 352         rem = do_div(base, den);
 353
 354         base *= num;
 355         rem *= num;
 356
 357         do_div(rem, den);
 358
 359         return base + rem;
 360 }
 361
 362 static int azx_get_sync_time(ktime_t *device,
 363                 struct system_counterval_t *system, void *ctx)
 364 {
 365         struct snd_pcm_substream *substream = ctx;
 366         struct azx_dev *azx_dev = get_azx_dev(substream);
 367         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 368         struct azx *chip = apcm->chip;
 369         struct snd_pcm_runtime *runtime;
 370         u64 ll_counter, ll_counter_l, ll_counter_h;
 371         u64 tsc_counter, tsc_counter_l, tsc_counter_h;
 372         u32 wallclk_ctr, wallclk_cycles;
 373         bool direction;
 374         u32 dma_select;
 375         u32 timeout;
 376         u32 retry_count = 0;
 377
 378         runtime = substream->runtime;
 379
 380         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 381                 direction = 1;
 382         else
 383                 direction = 0;
 384
 385         /* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */
 386         do {
 387                 timeout = 100;
 388                 dma_select = (direction << GTSCC_CDMAS_DMA_DIR_SHIFT) |
 389                                         (azx_dev->core.stream_tag - 1);
 390                 snd_hdac_chip_writel(azx_bus(chip), GTSCC, dma_select);
 391
 392                 /* Enable the capture */
 393                 snd_hdac_chip_updatel(azx_bus(chip), GTSCC, 0, GTSCC_TSCCI_MASK);
 394
 395                 while (timeout) {
 396                         if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) &
 397                                                 GTSCC_TSCCD_MASK)
 398                                 break;
 399
 400                         timeout--;
 401                 }
 402
 403                 if (!timeout) {
 404                         dev_err(chip->card->dev, "GTSCC capture Timedout!\n");
 405                         return -EIO;
 406                 }
 407
 408                 /* Read wall clock counter */
 409                 wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC);
 410
 411                 /* Read TSC counter */
 412                 tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL);
 413                 tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU);
 414
 415                 /* Read Link counter */
 416                 ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL);
 417                 ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU);
 418
 419                 /* Ack: registers read done */
 420                 snd_hdac_chip_writel(azx_bus(chip), GTSCC, GTSCC_TSCCD_SHIFT);
 421
 422                 tsc_counter = (tsc_counter_h << TSCCU_CCU_SHIFT) |
 423                                                 tsc_counter_l;
 424
 425                 ll_counter = (ll_counter_h << LLPC_CCU_SHIFT) | ll_counter_l;
 426                 wallclk_cycles = wallclk_ctr & WALFCC_CIF_MASK;
 427
 428                 /*
 429                  * An error occurs near frame "rollover". The clocks in
 430                  * frame value indicates whether this error may have
 431                  * occurred. Here we use the value of 10 i.e.,
 432                  * HDA_MAX_CYCLE_OFFSET
 433                  */
 434                 if (wallclk_cycles < HDA_MAX_CYCLE_VALUE - HDA_MAX_CYCLE_OFFSET
 435                                         && wallclk_cycles > HDA_MAX_CYCLE_OFFSET)
 436                         break;
 437
 438                 /*
 439                  * Sleep before we read again, else we may again get
 440                  * value near to MAX_CYCLE. Try to sleep for different
 441                  * amount of time so we dont hit the same number again
 442                  */
 443                 udelay(retry_count++);
 444
 445         } while (retry_count != HDA_MAX_CYCLE_READ_RETRY);
 446
 447         if (retry_count == HDA_MAX_CYCLE_READ_RETRY) {
 448                 dev_err_ratelimited(chip->card->dev,
 449                         "Error in WALFCC cycle count\n");
 450                 return -EIO;
 451         }
 452
 453         *device = ns_to_ktime(azx_scale64(ll_counter,
 454                                 NSEC_PER_SEC, runtime->rate));
 455         *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) /
 456                                ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate));
 457
 458         *system = convert_art_to_tsc(tsc_counter);
 459
 460         return 0;
 461 }
 462
 463 #else
 464 static int azx_get_sync_time(ktime_t *device,
 465                 struct system_counterval_t *system, void *ctx)
 466 {
 467         return -ENXIO;
 468 }
 469 #endif
 470
 471 static int azx_get_crosststamp(struct snd_pcm_substream *substream,
 472                               struct system_device_crosststamp *xtstamp)
 473 {
 474         return get_device_system_crosststamp(azx_get_sync_time,
 475                                         substream, NULL, xtstamp);
 476 }
 477
 478 static inline bool is_link_time_supported(struct snd_pcm_runtime *runtime,
 479                                 struct snd_pcm_audio_tstamp_config *ts)
 480 {
 481         if (runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME)
 482                 if (ts->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED)
 483                         return true;
 484
 485         return false;
 486 }
 487
 488 static int azx_get_time_info(struct snd_pcm_substream *substream,
 489                         struct timespec64 *system_ts, struct timespec64 *audio_ts,
 490                         struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
 491                         struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
 492 {
 493         struct azx_dev *azx_dev = get_azx_dev(substream);
 494         struct snd_pcm_runtime *runtime = substream->runtime;
 495         struct system_device_crosststamp xtstamp;
 496         int ret;
 497         u64 nsec;
 498
 499         if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
 500                 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
 501
 502                 snd_pcm_gettime(substream->runtime, system_ts);
 503
 504                 nsec = timecounter_read(&azx_dev->core.tc);
 505                 if (audio_tstamp_config->report_delay)
 506                         nsec = azx_adjust_codec_delay(substream, nsec);
 507
 508                 *audio_ts = ns_to_timespec64(nsec);
 509
 510                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
 511                 audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
 512                 audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */
 513
 514         } else if (is_link_time_supported(runtime, audio_tstamp_config)) {
 515
 516                 ret = azx_get_crosststamp(substream, &xtstamp);
 517                 if (ret)
 518                         return ret;
 519
 520                 switch (runtime->tstamp_type) {
 521                 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC:
 522                         return -EINVAL;
 523
 524                 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW:
 525                         *system_ts = ktime_to_timespec64(xtstamp.sys_monoraw);
 526                         break;
 527
 528                 default:
 529                         *system_ts = ktime_to_timespec64(xtstamp.sys_realtime);
 530                         break;
 531
 532                 }
 533
 534                 *audio_ts = ktime_to_timespec64(xtstamp.device);
 535
 536                 audio_tstamp_report->actual_type =
 537                         SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED;
 538                 audio_tstamp_report->accuracy_report = 1;
 539                 /* 24 MHz WallClock == 42ns resolution */
 540                 audio_tstamp_report->accuracy = 42;
 541
 542         } else {
 543                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
 544         }
 545
 546         return 0;
 547 }
 548
 549 static const struct snd_pcm_hardware azx_pcm_hw = {
 550         .info =                 (SNDRV_PCM_INFO_MMAP |
 551                                  SNDRV_PCM_INFO_INTERLEAVED |
 552                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 553                                  SNDRV_PCM_INFO_MMAP_VALID |
 554                                  /* No full-resume yet implemented */
 555                                  /* SNDRV_PCM_INFO_RESUME |*/
 556                                  SNDRV_PCM_INFO_PAUSE |
 557                                  SNDRV_PCM_INFO_SYNC_START |
 558                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
 559                                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
 560                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
 561         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 562         .rates =                SNDRV_PCM_RATE_48000,
 563         .rate_min =             48000,
 564         .rate_max =             48000,
 565         .channels_min =         2,
 566         .channels_max =         2,
 567         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
 568         .period_bytes_min =     128,
 569         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
 570         .periods_min =          2,
 571         .periods_max =          AZX_MAX_FRAG,
 572         .fifo_size =            0,
 573 };
 574
 575 static int azx_pcm_open(struct snd_pcm_substream *substream)
 576 {
 577         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 578         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 579         struct azx *chip = apcm->chip;
 580         struct azx_dev *azx_dev;
 581         struct snd_pcm_runtime *runtime = substream->runtime;
 582         int err;
 583         int buff_step;
 584
 585         snd_hda_codec_pcm_get(apcm->info);
 586         mutex_lock(&chip->open_mutex);
 587         azx_dev = azx_assign_device(chip, substream);
 588         trace_azx_pcm_open(chip, azx_dev);
 589         if (azx_dev == NULL) {
 590                 err = -EBUSY;
 591                 goto unlock;
 592         }
 593         runtime->private_data = azx_dev;
 594
 595         runtime->hw = azx_pcm_hw;
 596         if (chip->gts_present)
 597                 runtime->hw.info |= SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME;
 598         runtime->hw.channels_min = hinfo->channels_min;
 599         runtime->hw.channels_max = hinfo->channels_max;
 600         runtime->hw.formats = hinfo->formats;
 601         runtime->hw.rates = hinfo->rates;
 602         snd_pcm_limit_hw_rates(runtime);
 603         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 604
 605         /* avoid wrap-around with wall-clock */
 606         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
 607                                      20,
 608                                      178000000);
 609
 610         if (chip->align_buffer_size)
 611                 /* constrain buffer sizes to be multiple of 128
 612                    bytes. This is more efficient in terms of memory
 613                    access but isn't required by the HDA spec and
 614                    prevents users from specifying exact period/buffer
 615                    sizes. For example for 44.1kHz, a period size set
 616                    to 20ms will be rounded to 19.59ms. */
 617                 buff_step = 128;
 618         else
 619                 /* Don't enforce steps on buffer sizes, still need to
 620                    be multiple of 4 bytes (HDA spec). Tested on Intel
 621                    HDA controllers, may not work on all devices where
 622                    option needs to be disabled */
 623                 buff_step = 4;
 624
 625         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 626                                    buff_step);
 627         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 628                                    buff_step);
 629         snd_hda_power_up(apcm->codec);
 630         if (hinfo->ops.open)
 631                 err = hinfo->ops.open(hinfo, apcm->codec, substream);
 632         else
 633                 err = -ENODEV;
 634         if (err < 0) {
 635                 azx_release_device(azx_dev);
 636                 goto powerdown;
 637         }
 638         snd_pcm_limit_hw_rates(runtime);
 639         /* sanity check */
 640         if (snd_BUG_ON(!runtime->hw.channels_min) ||
 641             snd_BUG_ON(!runtime->hw.channels_max) ||
 642             snd_BUG_ON(!runtime->hw.formats) ||
 643             snd_BUG_ON(!runtime->hw.rates)) {
 644                 azx_release_device(azx_dev);
 645                 if (hinfo->ops.close)
 646                         hinfo->ops.close(hinfo, apcm->codec, substream);
 647                 err = -EINVAL;
 648                 goto powerdown;
 649         }
 650
 651         /* disable LINK_ATIME timestamps for capture streams
 652            until we figure out how to handle digital inputs */
 653         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 654                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
 655                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
 656         }
 657
 658         snd_pcm_set_sync(substream);
 659         mutex_unlock(&chip->open_mutex);
 660         return 0;
 661
 662  powerdown:
 663         snd_hda_power_down(apcm->codec);
 664  unlock:
 665         mutex_unlock(&chip->open_mutex);
 666         snd_hda_codec_pcm_put(apcm->info);
 667         return err;
 668 }
 669
 670 static const struct snd_pcm_ops azx_pcm_ops = {
 671         .open = azx_pcm_open,
 672         .close = azx_pcm_close,
 673         .hw_params = azx_pcm_hw_params,
 674         .hw_free = azx_pcm_hw_free,
 675         .prepare = azx_pcm_prepare,
 676         .trigger = azx_pcm_trigger,
 677         .pointer = azx_pcm_pointer,
 678         .get_time_info =  azx_get_time_info,
 679 };
 680
 681 static void azx_pcm_free(struct snd_pcm *pcm)
 682 {
 683         struct azx_pcm *apcm = pcm->private_data;
 684         if (apcm) {
 685                 list_del(&apcm->list);
 686                 apcm->info->pcm = NULL;
 687                 kfree(apcm);
 688         }
 689 }
 690
 691 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
 692
 693 int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec,
 694                               struct hda_pcm *cpcm)
 695 {
 696         struct hdac_bus *bus = &_bus->core;
 697         struct azx *chip = bus_to_azx(bus);
 698         struct snd_pcm *pcm;
 699         struct azx_pcm *apcm;
 700         int pcm_dev = cpcm->device;
 701         unsigned int size;
 702         int s, err;
 703         int type = SNDRV_DMA_TYPE_DEV_SG;
 704
 705         list_for_each_entry(apcm, &chip->pcm_list, list) {
 706                 if (apcm->pcm->device == pcm_dev) {
 707                         dev_err(chip->card->dev, "PCM %d already exists\n",
 708                                 pcm_dev);
 709                         return -EBUSY;
 710                 }
 711         }
 712         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
 713                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
 714                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
 715                           &pcm);
 716         if (err < 0)
 717                 return err;
 718         strscpy(pcm->name, cpcm->name, sizeof(pcm->name));
 719         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
 720         if (apcm == NULL) {
 721                 snd_device_free(chip->card, pcm);
 722                 return -ENOMEM;
 723         }
 724         apcm->chip = chip;
 725         apcm->pcm = pcm;
 726         apcm->codec = codec;
 727         apcm->info = cpcm;
 728         pcm->private_data = apcm;
 729         pcm->private_free = azx_pcm_free;
 730         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
 731                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
 732         list_add_tail(&apcm->list, &chip->pcm_list);
 733         cpcm->pcm = pcm;
 734         for (s = 0; s < 2; s++) {
 735                 if (cpcm->stream[s].substreams)
 736                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
 737         }
 738         /* buffer pre-allocation */
 739         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
 740         if (size > MAX_PREALLOC_SIZE)
 741                 size = MAX_PREALLOC_SIZE;
 742         if (chip->uc_buffer)
 743                 type = SNDRV_DMA_TYPE_DEV_WC_SG;
 744         snd_pcm_set_managed_buffer_all(pcm, type, chip->card->dev,
 745                                        size, MAX_PREALLOC_SIZE);
 746         return 0;
 747 }
 748
 749 static unsigned int azx_command_addr(u32 cmd)
 750 {
 751         unsigned int addr = cmd >> 28;
 752
 753         if (addr >= AZX_MAX_CODECS) {
 754                 snd_BUG();
 755                 addr = 0;
 756         }
 757
 758         return addr;
 759 }
 760
 761 /* receive a response */
 762 static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
 763                                  unsigned int *res)
 764 {
 765         struct azx *chip = bus_to_azx(bus);
 766         struct hda_bus *hbus = &chip->bus;
 767         int err;
 768
 769  again:
 770         err = snd_hdac_bus_get_response(bus, addr, res);
 771         if (!err)
 772                 return 0;
 773
 774         if (hbus->no_response_fallback)
 775                 return -EIO;
 776
 777         if (!bus->polling_mode) {
 778                 dev_warn(chip->card->dev,
 779                          "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
 780                          bus->last_cmd[addr]);
 781                 bus->polling_mode = 1;
 782                 goto again;
 783         }
 784
 785         if (chip->msi) {
 786                 dev_warn(chip->card->dev,
 787                          "No response from codec, disabling MSI: last cmd=0x%08x\n",
 788                          bus->last_cmd[addr]);
 789                 if (chip->ops->disable_msi_reset_irq &&
 790                     chip->ops->disable_msi_reset_irq(chip) < 0)
 791                         return -EIO;
 792                 goto again;
 793         }
 794
 795         if (chip->probing) {
 796                 /* If this critical timeout happens during the codec probing
 797                  * phase, this is likely an access to a non-existing codec
 798                  * slot.  Better to return an error and reset the system.
 799                  */
 800                 return -EIO;
 801         }
 802
 803         /* no fallback mechanism? */
 804         if (!chip->fallback_to_single_cmd)
 805                 return -EIO;
 806
 807         /* a fatal communication error; need either to reset or to fallback
 808          * to the single_cmd mode
 809          */
 810         if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) {
 811                 hbus->response_reset = 1;
 812                 dev_err(chip->card->dev,
 813                         "No response from codec, resetting bus: last cmd=0x%08x\n",
 814                         bus->last_cmd[addr]);
 815                 return -EAGAIN; /* give a chance to retry */
 816         }
 817
 818         dev_err(chip->card->dev,
 819                 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
 820                 bus->last_cmd[addr]);
 821         chip->single_cmd = 1;
 822         hbus->response_reset = 0;
 823         snd_hdac_bus_stop_cmd_io(bus);
 824         return -EIO;
 825 }
 826
 827 /*
 828  * Use the single immediate command instead of CORB/RIRB for simplicity
 829  *
 830  * Note: according to Intel, this is not preferred use.  The command was
 831  *       intended for the BIOS only, and may get confused with unsolicited
 832  *       responses.  So, we shouldn't use it for normal operation from the
 833  *       driver.
 834  *       I left the codes, however, for debugging/testing purposes.
 835  */
 836
 837 /* receive a response */
 838 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 839 {
 840         int timeout = 50;
 841
 842         while (timeout--) {
 843                 /* check IRV busy bit */
 844                 if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
 845                         /* reuse rirb.res as the response return value */
 846                         azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
 847                         return 0;
 848                 }
 849                 udelay(1);
 850         }
 851         if (printk_ratelimit())
 852                 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
 853                         azx_readw(chip, IRS));
 854         azx_bus(chip)->rirb.res[addr] = -1;
 855         return -EIO;
 856 }
 857
 858 /* send a command */
 859 static int azx_single_send_cmd(struct hdac_bus *bus, u32 val)
 860 {
 861         struct azx *chip = bus_to_azx(bus);
 862         unsigned int addr = azx_command_addr(val);
 863         int timeout = 50;
 864
 865         bus->last_cmd[azx_command_addr(val)] = val;
 866         while (timeout--) {
 867                 /* check ICB busy bit */
 868                 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
 869                         /* Clear IRV valid bit */
 870                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 871                                    AZX_IRS_VALID);
 872                         azx_writel(chip, IC, val);
 873                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 874                                    AZX_IRS_BUSY);
 875                         return azx_single_wait_for_response(chip, addr);
 876                 }
 877                 udelay(1);
 878         }
 879         if (printk_ratelimit())
 880                 dev_dbg(chip->card->dev,
 881                         "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 882                         azx_readw(chip, IRS), val);
 883         return -EIO;
 884 }
 885
 886 /* receive a response */
 887 static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr,
 888                                    unsigned int *res)
 889 {
 890         if (res)
 891                 *res = bus->rirb.res[addr];
 892         return 0;
 893 }
 894
 895 /*
 896  * The below are the main callbacks from hda_codec.
 897  *
 898  * They are just the skeleton to call sub-callbacks according to the
 899  * current setting of chip->single_cmd.
 900  */
 901
 902 /* send a command */
 903 static int azx_send_cmd(struct hdac_bus *bus, unsigned int val)
 904 {
 905         struct azx *chip = bus_to_azx(bus);
 906
 907         if (chip->disabled)
 908                 return 0;
 909         if (chip->single_cmd)
 910                 return azx_single_send_cmd(bus, val);
 911         else
 912                 return snd_hdac_bus_send_cmd(bus, val);
 913 }
 914
 915 /* get a response */
 916 static int azx_get_response(struct hdac_bus *bus, unsigned int addr,
 917                             unsigned int *res)
 918 {
 919         struct azx *chip = bus_to_azx(bus);
 920
 921         if (chip->disabled)
 922                 return 0;
 923         if (chip->single_cmd)
 924                 return azx_single_get_response(bus, addr, res);
 925         else
 926                 return azx_rirb_get_response(bus, addr, res);
 927 }
 928
 929 static const struct hdac_bus_ops bus_core_ops = {
 930         .command = azx_send_cmd,
 931         .get_response = azx_get_response,
 932 };
 933
 934 #ifdef CONFIG_SND_HDA_DSP_LOADER
 935 /*
 936  * DSP loading code (e.g. for CA0132)
 937  */
 938
 939 /* use the first stream for loading DSP */
 940 static struct azx_dev *
 941 azx_get_dsp_loader_dev(struct azx *chip)
 942 {
 943         struct hdac_bus *bus = azx_bus(chip);
 944         struct hdac_stream *s;
 945
 946         list_for_each_entry(s, &bus->stream_list, list)
 947                 if (s->index == chip->playback_index_offset)
 948                         return stream_to_azx_dev(s);
 949
 950         return NULL;
 951 }
 952
 953 int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
 954                                    unsigned int byte_size,
 955                                    struct snd_dma_buffer *bufp)
 956 {
 957         struct hdac_bus *bus = &codec->bus->core;
 958         struct azx *chip = bus_to_azx(bus);
 959         struct azx_dev *azx_dev;
 960         struct hdac_stream *hstr;
 961         bool saved = false;
 962         int err;
 963
 964         azx_dev = azx_get_dsp_loader_dev(chip);
 965         hstr = azx_stream(azx_dev);
 966         spin_lock_irq(&bus->reg_lock);
 967         if (hstr->opened) {
 968                 chip->saved_azx_dev = *azx_dev;
 969                 saved = true;
 970         }
 971         spin_unlock_irq(&bus->reg_lock);
 972
 973         err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
 974         if (err < 0) {
 975                 spin_lock_irq(&bus->reg_lock);
 976                 if (saved)
 977                         *azx_dev = chip->saved_azx_dev;
 978                 spin_unlock_irq(&bus->reg_lock);
 979                 return err;
 980         }
 981
 982         hstr->prepared = 0;
 983         return err;
 984 }
 985 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare);
 986
 987 void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start)
 988 {
 989         struct hdac_bus *bus = &codec->bus->core;
 990         struct azx *chip = bus_to_azx(bus);
 991         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
 992
 993         snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
 994 }
 995 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger);
 996
 997 void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
 998                                     struct snd_dma_buffer *dmab)
 999 {
1000         struct hdac_bus *bus = &codec->bus->core;
1001         struct azx *chip = bus_to_azx(bus);
1002         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1003         struct hdac_stream *hstr = azx_stream(azx_dev);
1004
1005         if (!dmab->area || !hstr->locked)
1006                 return;
1007
1008         snd_hdac_dsp_cleanup(hstr, dmab);
1009         spin_lock_irq(&bus->reg_lock);
1010         if (hstr->opened)
1011                 *azx_dev = chip->saved_azx_dev;
1012         hstr->locked = false;
1013         spin_unlock_irq(&bus->reg_lock);
1014 }
1015 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup);
1016 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1017
1018 /*
1019  * reset and start the controller registers
1020  */
1021 void azx_init_chip(struct azx *chip, bool full_reset)
1022 {
1023         if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {
1024                 /* correct RINTCNT for CXT */
1025                 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1026                         azx_writew(chip, RINTCNT, 0xc0);
1027         }
1028 }
1029 EXPORT_SYMBOL_GPL(azx_init_chip);
1030
1031 void azx_stop_all_streams(struct azx *chip)
1032 {
1033         struct hdac_bus *bus = azx_bus(chip);
1034
1035         snd_hdac_stop_streams(bus);
1036 }
1037 EXPORT_SYMBOL_GPL(azx_stop_all_streams);
1038
1039 void azx_stop_chip(struct azx *chip)
1040 {
1041         snd_hdac_bus_stop_chip(azx_bus(chip));
1042 }
1043 EXPORT_SYMBOL_GPL(azx_stop_chip);
1044
1045 /*
1046  * interrupt handler
1047  */
1048 static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
1049 {
1050         struct azx *chip = bus_to_azx(bus);
1051         struct azx_dev *azx_dev = stream_to_azx_dev(s);
1052
1053         /* check whether this IRQ is really acceptable */
1054         if (!chip->ops->position_check ||
1055             chip->ops->position_check(chip, azx_dev)) {
1056                 spin_unlock(&bus->reg_lock);
1057                 snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
1058                 spin_lock(&bus->reg_lock);
1059         }
1060 }
1061
1062 irqreturn_t azx_interrupt(int irq, void *dev_id)
1063 {
1064         struct azx *chip = dev_id;
1065         struct hdac_bus *bus = azx_bus(chip);
1066         u32 status;
1067         bool active, handled = false;
1068         int repeat = 0; /* count for avoiding endless loop */
1069
1070 #ifdef CONFIG_PM
1071         if (azx_has_pm_runtime(chip))
1072                 if (!pm_runtime_active(chip->card->dev))
1073                         return IRQ_NONE;
1074 #endif
1075
1076         spin_lock(&bus->reg_lock);
1077
1078         if (chip->disabled)
1079                 goto unlock;
1080
1081         do {
1082                 status = azx_readl(chip, INTSTS);
1083                 if (status == 0 || status == 0xffffffff)
1084                         break;
1085
1086                 handled = true;
1087                 active = false;
1088                 if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update))
1089                         active = true;
1090
1091                 status = azx_readb(chip, RIRBSTS);
1092                 if (status & RIRB_INT_MASK) {
1093                         /*
1094                          * Clearing the interrupt status here ensures that no
1095                          * interrupt gets masked after the RIRB wp is read in
1096                          * snd_hdac_bus_update_rirb. This avoids a possible
1097                          * race condition where codec response in RIRB may
1098                          * remain unserviced by IRQ, eventually falling back
1099                          * to polling mode in azx_rirb_get_response.
1100                          */
1101                         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1102                         active = true;
1103                         if (status & RIRB_INT_RESPONSE) {
1104                                 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1105                                         udelay(80);
1106                                 snd_hdac_bus_update_rirb(bus);
1107                         }
1108                 }
1109         } while (active && ++repeat < 10);
1110
1111  unlock:
1112         spin_unlock(&bus->reg_lock);
1113
1114         return IRQ_RETVAL(handled);
1115 }
1116 EXPORT_SYMBOL_GPL(azx_interrupt);
1117
1118 /*
1119  * Codec initerface
1120  */
1121
1122 /*
1123  * Probe the given codec address
1124  */
1125 static int probe_codec(struct azx *chip, int addr)
1126 {
1127         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1128                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1129         struct hdac_bus *bus = azx_bus(chip);
1130         int err;
1131         unsigned int res = -1;
1132
1133         mutex_lock(&bus->cmd_mutex);
1134         chip->probing = 1;
1135         azx_send_cmd(bus, cmd);
1136         err = azx_get_response(bus, addr, &res);
1137         chip->probing = 0;
1138         mutex_unlock(&bus->cmd_mutex);
1139         if (err < 0 || res == -1)
1140                 return -EIO;
1141         dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1142         return 0;
1143 }
1144
1145 void snd_hda_bus_reset(struct hda_bus *bus)
1146 {
1147         struct azx *chip = bus_to_azx(&bus->core);
1148
1149         bus->in_reset = 1;
1150         azx_stop_chip(chip);
1151         azx_init_chip(chip, true);
1152         if (bus->core.chip_init)
1153                 snd_hda_bus_reset_codecs(bus);
1154         bus->in_reset = 0;
1155 }
1156
1157 /* HD-audio bus initialization */
1158 int azx_bus_init(struct azx *chip, const char *model)
1159 {
1160         struct hda_bus *bus = &chip->bus;
1161         int err;
1162
1163         err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops);
1164         if (err < 0)
1165                 return err;
1166
1167         bus->card = chip->card;
1168         mutex_init(&bus->prepare_mutex);
1169         bus->pci = chip->pci;
1170         bus->modelname = model;
1171         bus->mixer_assigned = -1;
1172         bus->core.snoop = azx_snoop(chip);
1173         if (chip->get_position[0] != azx_get_pos_lpib ||
1174             chip->get_position[1] != azx_get_pos_lpib)
1175                 bus->core.use_posbuf = true;
1176         bus->core.bdl_pos_adj = chip->bdl_pos_adj;
1177         if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)
1178                 bus->core.corbrp_self_clear = true;
1179
1180         if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY)
1181                 bus->core.align_bdle_4k = true;
1182
1183         /* enable sync_write flag for stable communication as default */
1184         bus->core.sync_write = 1;
1185
1186         return 0;
1187 }
1188 EXPORT_SYMBOL_GPL(azx_bus_init);
1189
1190 /* Probe codecs */
1191 int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
1192 {
1193         struct hdac_bus *bus = azx_bus(chip);
1194         int c, codecs, err;
1195
1196         codecs = 0;
1197         if (!max_slots)
1198                 max_slots = AZX_DEFAULT_CODECS;
1199
1200         /* First try to probe all given codec slots */
1201         for (c = 0; c < max_slots; c++) {
1202                 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1203                         if (probe_codec(chip, c) < 0) {
1204                                 /* Some BIOSen give you wrong codec addresses
1205                                  * that don't exist
1206                                  */
1207                                 dev_warn(chip->card->dev,
1208                                          "Codec #%d probe error; disabling it...\n", c);
1209                                 bus->codec_mask &= ~(1 << c);
1210                                 /* More badly, accessing to a non-existing
1211                                  * codec often screws up the controller chip,
1212                                  * and disturbs the further communications.
1213                                  * Thus if an error occurs during probing,
1214                                  * better to reset the controller chip to
1215                                  * get back to the sanity state.
1216                                  */
1217                                 azx_stop_chip(chip);
1218                                 azx_init_chip(chip, true);
1219                         }
1220                 }
1221         }
1222
1223         /* Then create codec instances */
1224         for (c = 0; c < max_slots; c++) {
1225                 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1226                         struct hda_codec *codec;
1227                         err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec);
1228                         if (err < 0)
1229                                 continue;
1230                         codec->jackpoll_interval = chip->jackpoll_interval;
1231                         codec->beep_mode = chip->beep_mode;
1232                         codec->ctl_dev_id = chip->ctl_dev_id;
1233                         codecs++;
1234                 }
1235         }
1236         if (!codecs) {
1237                 dev_err(chip->card->dev, "no codecs initialized\n");
1238                 return -ENXIO;
1239         }
1240         return 0;
1241 }
1242 EXPORT_SYMBOL_GPL(azx_probe_codecs);
1243
1244 /* configure each codec instance */
1245 int azx_codec_configure(struct azx *chip)
1246 {
1247         struct hda_codec *codec, *next;
1248         int success = 0;
1249
1250         list_for_each_codec(codec, &chip->bus) {
1251                 if (!snd_hda_codec_configure(codec))
1252                         success++;
1253         }
1254
1255         if (success) {
1256                 /* unregister failed codecs if any codec has been probed */
1257                 list_for_each_codec_safe(codec, next, &chip->bus) {
1258                         if (!codec->configured) {
1259                                 codec_err(codec, "Unable to configure, disabling\n");
1260                                 snd_hdac_device_unregister(&codec->core);
1261                         }
1262                 }
1263         }
1264
1265         return success ? 0 : -ENODEV;
1266 }
1267 EXPORT_SYMBOL_GPL(azx_codec_configure);
1268
1269 static int stream_direction(struct azx *chip, unsigned char index)
1270 {
1271         if (index >= chip->capture_index_offset &&
1272             index < chip->capture_index_offset + chip->capture_streams)
1273                 return SNDRV_PCM_STREAM_CAPTURE;
1274         return SNDRV_PCM_STREAM_PLAYBACK;
1275 }
1276
1277 /* initialize SD streams */
1278 int azx_init_streams(struct azx *chip)
1279 {
1280         int i;
1281         int stream_tags[2] = { 0, 0 };
1282
1283         /* initialize each stream (aka device)
1284          * assign the starting bdl address to each stream (device)
1285          * and initialize
1286          */
1287         for (i = 0; i < chip->num_streams; i++) {
1288                 struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL);
1289                 int dir, tag;
1290
1291                 if (!azx_dev)
1292                         return -ENOMEM;
1293
1294                 dir = stream_direction(chip, i);
1295                 /* stream tag must be unique throughout
1296                  * the stream direction group,
1297                  * valid values 1...15
1298                  * use separate stream tag if the flag
1299                  * AZX_DCAPS_SEPARATE_STREAM_TAG is used
1300                  */
1301                 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
1302                         tag = ++stream_tags[dir];
1303                 else
1304                         tag = i + 1;
1305                 snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev),
1306                                      i, dir, tag);
1307         }
1308
1309         return 0;
1310 }
1311 EXPORT_SYMBOL_GPL(azx_init_streams);
1312
1313 void azx_free_streams(struct azx *chip)
1314 {
1315         struct hdac_bus *bus = azx_bus(chip);
1316         struct hdac_stream *s;
1317
1318         while (!list_empty(&bus->stream_list)) {
1319                 s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
1320                 list_del(&s->list);
1321                 kfree(stream_to_azx_dev(s));
1322         }
1323 }
1324 EXPORT_SYMBOL_GPL(azx_free_streams);