sound/pci/hda/hda_controller.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  Implementation of primary alsa driver code base for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  */
  11
  12 #include <linux/clocksource.h>
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/slab.h>
  19
  20 #ifdef CONFIG_X86
  21 /* for art-tsc conversion */
  22 #include <asm/tsc.h>
  23 #endif
  24
  25 #include <sound/core.h>
  26 #include <sound/initval.h>
  27 #include "hda_controller.h"
  28
  29 #define CREATE_TRACE_POINTS
  30 #include "hda_controller_trace.h"
  31
  32 /* DSP lock helpers */
  33 #define dsp_lock(dev)           snd_hdac_dsp_lock(azx_stream(dev))
  34 #define dsp_unlock(dev)         snd_hdac_dsp_unlock(azx_stream(dev))
  35 #define dsp_is_locked(dev)      snd_hdac_stream_is_locked(azx_stream(dev))
  36
  37 /* assign a stream for the PCM */
  38 static inline struct azx_dev *
  39 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
  40 {
  41         struct hdac_stream *s;
  42
  43         s = snd_hdac_stream_assign(azx_bus(chip), substream);
  44         if (!s)
  45                 return NULL;
  46         return stream_to_azx_dev(s);
  47 }
  48
  49 /* release the assigned stream */
  50 static inline void azx_release_device(struct azx_dev *azx_dev)
  51 {
  52         snd_hdac_stream_release(azx_stream(azx_dev));
  53 }
  54
  55 static inline struct hda_pcm_stream *
  56 to_hda_pcm_stream(struct snd_pcm_substream *substream)
  57 {
  58         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  59         return &apcm->info->stream[substream->stream];
  60 }
  61
  62 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
  63                                 u64 nsec)
  64 {
  65         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  66         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
  67         u64 codec_frames, codec_nsecs;
  68
  69         if (!hinfo->ops.get_delay)
  70                 return nsec;
  71
  72         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
  73         codec_nsecs = div_u64(codec_frames * 1000000000LL,
  74                               substream->runtime->rate);
  75
  76         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  77                 return nsec + codec_nsecs;
  78
  79         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
  80 }
  81
  82 /*
  83  * PCM ops
  84  */
  85
  86 static int azx_pcm_close(struct snd_pcm_substream *substream)
  87 {
  88         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  89         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
  90         struct azx *chip = apcm->chip;
  91         struct azx_dev *azx_dev = get_azx_dev(substream);
  92
  93         trace_azx_pcm_close(chip, azx_dev);
  94         mutex_lock(&chip->open_mutex);
  95         azx_release_device(azx_dev);
  96         if (hinfo->ops.close)
  97                 hinfo->ops.close(hinfo, apcm->codec, substream);
  98         snd_hda_power_down(apcm->codec);
  99         mutex_unlock(&chip->open_mutex);
 100         snd_hda_codec_pcm_put(apcm->info);
 101         return 0;
 102 }
 103
 104 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
 105                              struct snd_pcm_hw_params *hw_params)
 106 {
 107         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 108         struct azx *chip = apcm->chip;
 109         struct azx_dev *azx_dev = get_azx_dev(substream);
 110         int ret;
 111
 112         trace_azx_pcm_hw_params(chip, azx_dev);
 113         dsp_lock(azx_dev);
 114         if (dsp_is_locked(azx_dev)) {
 115                 ret = -EBUSY;
 116                 goto unlock;
 117         }
 118
 119         azx_dev->core.bufsize = 0;
 120         azx_dev->core.period_bytes = 0;
 121         azx_dev->core.format_val = 0;
 122         ret = snd_pcm_lib_malloc_pages(substream,
 123                                        params_buffer_bytes(hw_params));
 124
 125 unlock:
 126         dsp_unlock(azx_dev);
 127         return ret;
 128 }
 129
 130 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
 131 {
 132         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 133         struct azx_dev *azx_dev = get_azx_dev(substream);
 134         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 135         int err;
 136
 137         /* reset BDL address */
 138         dsp_lock(azx_dev);
 139         if (!dsp_is_locked(azx_dev))
 140                 snd_hdac_stream_cleanup(azx_stream(azx_dev));
 141
 142         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
 143
 144         err = snd_pcm_lib_free_pages(substream);
 145         azx_stream(azx_dev)->prepared = 0;
 146         dsp_unlock(azx_dev);
 147         return err;
 148 }
 149
 150 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
 151 {
 152         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 153         struct azx *chip = apcm->chip;
 154         struct azx_dev *azx_dev = get_azx_dev(substream);
 155         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 156         struct snd_pcm_runtime *runtime = substream->runtime;
 157         unsigned int format_val, stream_tag;
 158         int err;
 159         struct hda_spdif_out *spdif =
 160                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
 161         unsigned short ctls = spdif ? spdif->ctls : 0;
 162
 163         trace_azx_pcm_prepare(chip, azx_dev);
 164         dsp_lock(azx_dev);
 165         if (dsp_is_locked(azx_dev)) {
 166                 err = -EBUSY;
 167                 goto unlock;
 168         }
 169
 170         snd_hdac_stream_reset(azx_stream(azx_dev));
 171         format_val = snd_hdac_calc_stream_format(runtime->rate,
 172                                                 runtime->channels,
 173                                                 runtime->format,
 174                                                 hinfo->maxbps,
 175                                                 ctls);
 176         if (!format_val) {
 177                 dev_err(chip->card->dev,
 178                         "invalid format_val, rate=%d, ch=%d, format=%d\n",
 179                         runtime->rate, runtime->channels, runtime->format);
 180                 err = -EINVAL;
 181                 goto unlock;
 182         }
 183
 184         err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val);
 185         if (err < 0)
 186                 goto unlock;
 187
 188         snd_hdac_stream_setup(azx_stream(azx_dev));
 189
 190         stream_tag = azx_dev->core.stream_tag;
 191         /* CA-IBG chips need the playback stream starting from 1 */
 192         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
 193             stream_tag > chip->capture_streams)
 194                 stream_tag -= chip->capture_streams;
 195         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
 196                                      azx_dev->core.format_val, substream);
 197
 198  unlock:
 199         if (!err)
 200                 azx_stream(azx_dev)->prepared = 1;
 201         dsp_unlock(azx_dev);
 202         return err;
 203 }
 204
 205 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 206 {
 207         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 208         struct azx *chip = apcm->chip;
 209         struct hdac_bus *bus = azx_bus(chip);
 210         struct azx_dev *azx_dev;
 211         struct snd_pcm_substream *s;
 212         struct hdac_stream *hstr;
 213         bool start;
 214         int sbits = 0;
 215         int sync_reg;
 216
 217         azx_dev = get_azx_dev(substream);
 218         trace_azx_pcm_trigger(chip, azx_dev, cmd);
 219
 220         hstr = azx_stream(azx_dev);
 221         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
 222                 sync_reg = AZX_REG_OLD_SSYNC;
 223         else
 224                 sync_reg = AZX_REG_SSYNC;
 225
 226         if (dsp_is_locked(azx_dev) || !hstr->prepared)
 227                 return -EPIPE;
 228
 229         switch (cmd) {
 230         case SNDRV_PCM_TRIGGER_START:
 231         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 232         case SNDRV_PCM_TRIGGER_RESUME:
 233                 start = true;
 234                 break;
 235         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 236         case SNDRV_PCM_TRIGGER_SUSPEND:
 237         case SNDRV_PCM_TRIGGER_STOP:
 238                 start = false;
 239                 break;
 240         default:
 241                 return -EINVAL;
 242         }
 243
 244         snd_pcm_group_for_each_entry(s, substream) {
 245                 if (s->pcm->card != substream->pcm->card)
 246                         continue;
 247                 azx_dev = get_azx_dev(s);
 248                 sbits |= 1 << azx_dev->core.index;
 249                 snd_pcm_trigger_done(s, substream);
 250         }
 251
 252         spin_lock(&bus->reg_lock);
 253
 254         /* first, set SYNC bits of corresponding streams */
 255         snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
 256
 257         snd_pcm_group_for_each_entry(s, substream) {
 258                 if (s->pcm->card != substream->pcm->card)
 259                         continue;
 260                 azx_dev = get_azx_dev(s);
 261                 if (start) {
 262                         azx_dev->insufficient = 1;
 263                         snd_hdac_stream_start(azx_stream(azx_dev), true);
 264                 } else {
 265                         snd_hdac_stream_stop(azx_stream(azx_dev));
 266                 }
 267         }
 268         spin_unlock(&bus->reg_lock);
 269
 270         snd_hdac_stream_sync(hstr, start, sbits);
 271
 272         spin_lock(&bus->reg_lock);
 273         /* reset SYNC bits */
 274         snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
 275         if (start)
 276                 snd_hdac_stream_timecounter_init(hstr, sbits);
 277         spin_unlock(&bus->reg_lock);
 278         return 0;
 279 }
 280
 281 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
 282 {
 283         return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 284 }
 285 EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
 286
 287 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
 288 {
 289         return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev));
 290 }
 291 EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
 292
 293 unsigned int azx_get_position(struct azx *chip,
 294                               struct azx_dev *azx_dev)
 295 {
 296         struct snd_pcm_substream *substream = azx_dev->core.substream;
 297         unsigned int pos;
 298         int stream = substream->stream;
 299         int delay = 0;
 300
 301         if (chip->get_position[stream])
 302                 pos = chip->get_position[stream](chip, azx_dev);
 303         else /* use the position buffer as default */
 304                 pos = azx_get_pos_posbuf(chip, azx_dev);
 305
 306         if (pos >= azx_dev->core.bufsize)
 307                 pos = 0;
 308
 309         if (substream->runtime) {
 310                 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 311                 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 312
 313                 if (chip->get_delay[stream])
 314                         delay += chip->get_delay[stream](chip, azx_dev, pos);
 315                 if (hinfo->ops.get_delay)
 316                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
 317                                                       substream);
 318                 substream->runtime->delay = delay;
 319         }
 320
 321         trace_azx_get_position(chip, azx_dev, pos, delay);
 322         return pos;
 323 }
 324 EXPORT_SYMBOL_GPL(azx_get_position);
 325
 326 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
 327 {
 328         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 329         struct azx *chip = apcm->chip;
 330         struct azx_dev *azx_dev = get_azx_dev(substream);
 331         return bytes_to_frames(substream->runtime,
 332                                azx_get_position(chip, azx_dev));
 333 }
 334
 335 /*
 336  * azx_scale64: Scale base by mult/div while not overflowing sanely
 337  *
 338  * Derived from scale64_check_overflow in kernel/time/timekeeping.c
 339  *
 340  * The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which
 341  * is about 384307 ie ~4.5 days.
 342  *
 343  * This scales the calculation so that overflow will happen but after 2^64 /
 344  * 48000 secs, which is pretty large!
 345  *
 346  * In caln below:
 347  *      base may overflow, but since there isn’t any additional division
 348  *      performed on base it’s OK
 349  *      rem can’t overflow because both are 32-bit values
 350  */
 351
 352 #ifdef CONFIG_X86
 353 static u64 azx_scale64(u64 base, u32 num, u32 den)
 354 {
 355         u64 rem;
 356
 357         rem = do_div(base, den);
 358
 359         base *= num;
 360         rem *= num;
 361
 362         do_div(rem, den);
 363
 364         return base + rem;
 365 }
 366
 367 static int azx_get_sync_time(ktime_t *device,
 368                 struct system_counterval_t *system, void *ctx)
 369 {
 370         struct snd_pcm_substream *substream = ctx;
 371         struct azx_dev *azx_dev = get_azx_dev(substream);
 372         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 373         struct azx *chip = apcm->chip;
 374         struct snd_pcm_runtime *runtime;
 375         u64 ll_counter, ll_counter_l, ll_counter_h;
 376         u64 tsc_counter, tsc_counter_l, tsc_counter_h;
 377         u32 wallclk_ctr, wallclk_cycles;
 378         bool direction;
 379         u32 dma_select;
 380         u32 timeout = 200;
 381         u32 retry_count = 0;
 382
 383         runtime = substream->runtime;
 384
 385         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 386                 direction = 1;
 387         else
 388                 direction = 0;
 389
 390         /* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */
 391         do {
 392                 timeout = 100;
 393                 dma_select = (direction << GTSCC_CDMAS_DMA_DIR_SHIFT) |
 394                                         (azx_dev->core.stream_tag - 1);
 395                 snd_hdac_chip_writel(azx_bus(chip), GTSCC, dma_select);
 396
 397                 /* Enable the capture */
 398                 snd_hdac_chip_updatel(azx_bus(chip), GTSCC, 0, GTSCC_TSCCI_MASK);
 399
 400                 while (timeout) {
 401                         if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) &
 402                                                 GTSCC_TSCCD_MASK)
 403                                 break;
 404
 405                         timeout--;
 406                 }
 407
 408                 if (!timeout) {
 409                         dev_err(chip->card->dev, "GTSCC capture Timedout!\n");
 410                         return -EIO;
 411                 }
 412
 413                 /* Read wall clock counter */
 414                 wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC);
 415
 416                 /* Read TSC counter */
 417                 tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL);
 418                 tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU);
 419
 420                 /* Read Link counter */
 421                 ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL);
 422                 ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU);
 423
 424                 /* Ack: registers read done */
 425                 snd_hdac_chip_writel(azx_bus(chip), GTSCC, GTSCC_TSCCD_SHIFT);
 426
 427                 tsc_counter = (tsc_counter_h << TSCCU_CCU_SHIFT) |
 428                                                 tsc_counter_l;
 429
 430                 ll_counter = (ll_counter_h << LLPC_CCU_SHIFT) | ll_counter_l;
 431                 wallclk_cycles = wallclk_ctr & WALFCC_CIF_MASK;
 432
 433                 /*
 434                  * An error occurs near frame "rollover". The clocks in
 435                  * frame value indicates whether this error may have
 436                  * occurred. Here we use the value of 10 i.e.,
 437                  * HDA_MAX_CYCLE_OFFSET
 438                  */
 439                 if (wallclk_cycles < HDA_MAX_CYCLE_VALUE - HDA_MAX_CYCLE_OFFSET
 440                                         && wallclk_cycles > HDA_MAX_CYCLE_OFFSET)
 441                         break;
 442
 443                 /*
 444                  * Sleep before we read again, else we may again get
 445                  * value near to MAX_CYCLE. Try to sleep for different
 446                  * amount of time so we dont hit the same number again
 447                  */
 448                 udelay(retry_count++);
 449
 450         } while (retry_count != HDA_MAX_CYCLE_READ_RETRY);
 451
 452         if (retry_count == HDA_MAX_CYCLE_READ_RETRY) {
 453                 dev_err_ratelimited(chip->card->dev,
 454                         "Error in WALFCC cycle count\n");
 455                 return -EIO;
 456         }
 457
 458         *device = ns_to_ktime(azx_scale64(ll_counter,
 459                                 NSEC_PER_SEC, runtime->rate));
 460         *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) /
 461                                ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate));
 462
 463         *system = convert_art_to_tsc(tsc_counter);
 464
 465         return 0;
 466 }
 467
 468 #else
 469 static int azx_get_sync_time(ktime_t *device,
 470                 struct system_counterval_t *system, void *ctx)
 471 {
 472         return -ENXIO;
 473 }
 474 #endif
 475
 476 static int azx_get_crosststamp(struct snd_pcm_substream *substream,
 477                               struct system_device_crosststamp *xtstamp)
 478 {
 479         return get_device_system_crosststamp(azx_get_sync_time,
 480                                         substream, NULL, xtstamp);
 481 }
 482
 483 static inline bool is_link_time_supported(struct snd_pcm_runtime *runtime,
 484                                 struct snd_pcm_audio_tstamp_config *ts)
 485 {
 486         if (runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME)
 487                 if (ts->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED)
 488                         return true;
 489
 490         return false;
 491 }
 492
 493 static int azx_get_time_info(struct snd_pcm_substream *substream,
 494                         struct timespec *system_ts, struct timespec *audio_ts,
 495                         struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
 496                         struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
 497 {
 498         struct azx_dev *azx_dev = get_azx_dev(substream);
 499         struct snd_pcm_runtime *runtime = substream->runtime;
 500         struct system_device_crosststamp xtstamp;
 501         int ret;
 502         u64 nsec;
 503
 504         if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
 505                 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
 506
 507                 snd_pcm_gettime(substream->runtime, system_ts);
 508
 509                 nsec = timecounter_read(&azx_dev->core.tc);
 510                 nsec = div_u64(nsec, 3); /* can be optimized */
 511                 if (audio_tstamp_config->report_delay)
 512                         nsec = azx_adjust_codec_delay(substream, nsec);
 513
 514                 *audio_ts = ns_to_timespec(nsec);
 515
 516                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
 517                 audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
 518                 audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */
 519
 520         } else if (is_link_time_supported(runtime, audio_tstamp_config)) {
 521
 522                 ret = azx_get_crosststamp(substream, &xtstamp);
 523                 if (ret)
 524                         return ret;
 525
 526                 switch (runtime->tstamp_type) {
 527                 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC:
 528                         return -EINVAL;
 529
 530                 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW:
 531                         *system_ts = ktime_to_timespec(xtstamp.sys_monoraw);
 532                         break;
 533
 534                 default:
 535                         *system_ts = ktime_to_timespec(xtstamp.sys_realtime);
 536                         break;
 537
 538                 }
 539
 540                 *audio_ts = ktime_to_timespec(xtstamp.device);
 541
 542                 audio_tstamp_report->actual_type =
 543                         SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED;
 544                 audio_tstamp_report->accuracy_report = 1;
 545                 /* 24 MHz WallClock == 42ns resolution */
 546                 audio_tstamp_report->accuracy = 42;
 547
 548         } else {
 549                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
 550         }
 551
 552         return 0;
 553 }
 554
 555 static struct snd_pcm_hardware azx_pcm_hw = {
 556         .info =                 (SNDRV_PCM_INFO_MMAP |
 557                                  SNDRV_PCM_INFO_INTERLEAVED |
 558                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 559                                  SNDRV_PCM_INFO_MMAP_VALID |
 560                                  /* No full-resume yet implemented */
 561                                  /* SNDRV_PCM_INFO_RESUME |*/
 562                                  SNDRV_PCM_INFO_PAUSE |
 563                                  SNDRV_PCM_INFO_SYNC_START |
 564                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
 565                                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
 566                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
 567         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 568         .rates =                SNDRV_PCM_RATE_48000,
 569         .rate_min =             48000,
 570         .rate_max =             48000,
 571         .channels_min =         2,
 572         .channels_max =         2,
 573         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
 574         .period_bytes_min =     128,
 575         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
 576         .periods_min =          2,
 577         .periods_max =          AZX_MAX_FRAG,
 578         .fifo_size =            0,
 579 };
 580
 581 static int azx_pcm_open(struct snd_pcm_substream *substream)
 582 {
 583         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 584         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 585         struct azx *chip = apcm->chip;
 586         struct azx_dev *azx_dev;
 587         struct snd_pcm_runtime *runtime = substream->runtime;
 588         int err;
 589         int buff_step;
 590
 591         snd_hda_codec_pcm_get(apcm->info);
 592         mutex_lock(&chip->open_mutex);
 593         azx_dev = azx_assign_device(chip, substream);
 594         trace_azx_pcm_open(chip, azx_dev);
 595         if (azx_dev == NULL) {
 596                 err = -EBUSY;
 597                 goto unlock;
 598         }
 599         runtime->private_data = azx_dev;
 600
 601         runtime->hw = azx_pcm_hw;
 602         if (chip->gts_present)
 603                 runtime->hw.info |= SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME;
 604         runtime->hw.channels_min = hinfo->channels_min;
 605         runtime->hw.channels_max = hinfo->channels_max;
 606         runtime->hw.formats = hinfo->formats;
 607         runtime->hw.rates = hinfo->rates;
 608         snd_pcm_limit_hw_rates(runtime);
 609         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 610
 611         /* avoid wrap-around with wall-clock */
 612         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
 613                                      20,
 614                                      178000000);
 615
 616         if (chip->align_buffer_size)
 617                 /* constrain buffer sizes to be multiple of 128
 618                    bytes. This is more efficient in terms of memory
 619                    access but isn't required by the HDA spec and
 620                    prevents users from specifying exact period/buffer
 621                    sizes. For example for 44.1kHz, a period size set
 622                    to 20ms will be rounded to 19.59ms. */
 623                 buff_step = 128;
 624         else
 625                 /* Don't enforce steps on buffer sizes, still need to
 626                    be multiple of 4 bytes (HDA spec). Tested on Intel
 627                    HDA controllers, may not work on all devices where
 628                    option needs to be disabled */
 629                 buff_step = 4;
 630
 631         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 632                                    buff_step);
 633         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 634                                    buff_step);
 635         snd_hda_power_up(apcm->codec);
 636         if (hinfo->ops.open)
 637                 err = hinfo->ops.open(hinfo, apcm->codec, substream);
 638         else
 639                 err = -ENODEV;
 640         if (err < 0) {
 641                 azx_release_device(azx_dev);
 642                 goto powerdown;
 643         }
 644         snd_pcm_limit_hw_rates(runtime);
 645         /* sanity check */
 646         if (snd_BUG_ON(!runtime->hw.channels_min) ||
 647             snd_BUG_ON(!runtime->hw.channels_max) ||
 648             snd_BUG_ON(!runtime->hw.formats) ||
 649             snd_BUG_ON(!runtime->hw.rates)) {
 650                 azx_release_device(azx_dev);
 651                 if (hinfo->ops.close)
 652                         hinfo->ops.close(hinfo, apcm->codec, substream);
 653                 err = -EINVAL;
 654                 goto powerdown;
 655         }
 656
 657         /* disable LINK_ATIME timestamps for capture streams
 658            until we figure out how to handle digital inputs */
 659         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 660                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
 661                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
 662         }
 663
 664         snd_pcm_set_sync(substream);
 665         mutex_unlock(&chip->open_mutex);
 666         return 0;
 667
 668  powerdown:
 669         snd_hda_power_down(apcm->codec);
 670  unlock:
 671         mutex_unlock(&chip->open_mutex);
 672         snd_hda_codec_pcm_put(apcm->info);
 673         return err;
 674 }
 675
 676 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
 677                         struct vm_area_struct *area)
 678 {
 679         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 680         struct azx *chip = apcm->chip;
 681         if (chip->ops->pcm_mmap_prepare)
 682                 chip->ops->pcm_mmap_prepare(substream, area);
 683         return snd_pcm_lib_default_mmap(substream, area);
 684 }
 685
 686 static const struct snd_pcm_ops azx_pcm_ops = {
 687         .open = azx_pcm_open,
 688         .close = azx_pcm_close,
 689         .ioctl = snd_pcm_lib_ioctl,
 690         .hw_params = azx_pcm_hw_params,
 691         .hw_free = azx_pcm_hw_free,
 692         .prepare = azx_pcm_prepare,
 693         .trigger = azx_pcm_trigger,
 694         .pointer = azx_pcm_pointer,
 695         .get_time_info =  azx_get_time_info,
 696         .mmap = azx_pcm_mmap,
 697         .page = snd_pcm_sgbuf_ops_page,
 698 };
 699
 700 static void azx_pcm_free(struct snd_pcm *pcm)
 701 {
 702         struct azx_pcm *apcm = pcm->private_data;
 703         if (apcm) {
 704                 list_del(&apcm->list);
 705                 apcm->info->pcm = NULL;
 706                 kfree(apcm);
 707         }
 708 }
 709
 710 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
 711
 712 int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec,
 713                               struct hda_pcm *cpcm)
 714 {
 715         struct hdac_bus *bus = &_bus->core;
 716         struct azx *chip = bus_to_azx(bus);
 717         struct snd_pcm *pcm;
 718         struct azx_pcm *apcm;
 719         int pcm_dev = cpcm->device;
 720         unsigned int size;
 721         int s, err;
 722         int type = SNDRV_DMA_TYPE_DEV_SG;
 723
 724         list_for_each_entry(apcm, &chip->pcm_list, list) {
 725                 if (apcm->pcm->device == pcm_dev) {
 726                         dev_err(chip->card->dev, "PCM %d already exists\n",
 727                                 pcm_dev);
 728                         return -EBUSY;
 729                 }
 730         }
 731         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
 732                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
 733                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
 734                           &pcm);
 735         if (err < 0)
 736                 return err;
 737         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
 738         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
 739         if (apcm == NULL) {
 740                 snd_device_free(chip->card, pcm);
 741                 return -ENOMEM;
 742         }
 743         apcm->chip = chip;
 744         apcm->pcm = pcm;
 745         apcm->codec = codec;
 746         apcm->info = cpcm;
 747         pcm->private_data = apcm;
 748         pcm->private_free = azx_pcm_free;
 749         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
 750                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
 751         list_add_tail(&apcm->list, &chip->pcm_list);
 752         cpcm->pcm = pcm;
 753         for (s = 0; s < 2; s++) {
 754                 if (cpcm->stream[s].substreams)
 755                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
 756         }
 757         /* buffer pre-allocation */
 758         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
 759         if (size > MAX_PREALLOC_SIZE)
 760                 size = MAX_PREALLOC_SIZE;
 761         if (chip->uc_buffer)
 762                 type = SNDRV_DMA_TYPE_DEV_UC_SG;
 763         snd_pcm_lib_preallocate_pages_for_all(pcm, type,
 764                                               chip->card->dev,
 765                                               size, MAX_PREALLOC_SIZE);
 766         return 0;
 767 }
 768
 769 static unsigned int azx_command_addr(u32 cmd)
 770 {
 771         unsigned int addr = cmd >> 28;
 772
 773         if (addr >= AZX_MAX_CODECS) {
 774                 snd_BUG();
 775                 addr = 0;
 776         }
 777
 778         return addr;
 779 }
 780
 781 /* receive a response */
 782 static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
 783                                  unsigned int *res)
 784 {
 785         struct azx *chip = bus_to_azx(bus);
 786         struct hda_bus *hbus = &chip->bus;
 787         unsigned long timeout;
 788         unsigned long loopcounter;
 789         int do_poll = 0;
 790
 791  again:
 792         timeout = jiffies + msecs_to_jiffies(1000);
 793
 794         for (loopcounter = 0;; loopcounter++) {
 795                 spin_lock_irq(&bus->reg_lock);
 796                 if (bus->polling_mode || do_poll)
 797                         snd_hdac_bus_update_rirb(bus);
 798                 if (!bus->rirb.cmds[addr]) {
 799                         if (!do_poll)
 800                                 bus->poll_count = 0;
 801                         if (res)
 802                                 *res = bus->rirb.res[addr]; /* the last value */
 803                         spin_unlock_irq(&bus->reg_lock);
 804                         return 0;
 805                 }
 806                 spin_unlock_irq(&bus->reg_lock);
 807                 if (time_after(jiffies, timeout))
 808                         break;
 809                 if (hbus->needs_damn_long_delay || loopcounter > 3000)
 810                         msleep(2); /* temporary workaround */
 811                 else {
 812                         udelay(10);
 813                         cond_resched();
 814                 }
 815         }
 816
 817         if (hbus->no_response_fallback)
 818                 return -EIO;
 819
 820         if (!bus->polling_mode && bus->poll_count < 2) {
 821                 dev_dbg(chip->card->dev,
 822                         "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
 823                         bus->last_cmd[addr]);
 824                 do_poll = 1;
 825                 bus->poll_count++;
 826                 goto again;
 827         }
 828
 829
 830         if (!bus->polling_mode) {
 831                 dev_warn(chip->card->dev,
 832                          "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
 833                          bus->last_cmd[addr]);
 834                 bus->polling_mode = 1;
 835                 goto again;
 836         }
 837
 838         if (chip->msi) {
 839                 dev_warn(chip->card->dev,
 840                          "No response from codec, disabling MSI: last cmd=0x%08x\n",
 841                          bus->last_cmd[addr]);
 842                 if (chip->ops->disable_msi_reset_irq &&
 843                     chip->ops->disable_msi_reset_irq(chip) < 0)
 844                         return -EIO;
 845                 goto again;
 846         }
 847
 848         if (chip->probing) {
 849                 /* If this critical timeout happens during the codec probing
 850                  * phase, this is likely an access to a non-existing codec
 851                  * slot.  Better to return an error and reset the system.
 852                  */
 853                 return -EIO;
 854         }
 855
 856         /* no fallback mechanism? */
 857         if (!chip->fallback_to_single_cmd)
 858                 return -EIO;
 859
 860         /* a fatal communication error; need either to reset or to fallback
 861          * to the single_cmd mode
 862          */
 863         if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) {
 864                 hbus->response_reset = 1;
 865                 return -EAGAIN; /* give a chance to retry */
 866         }
 867
 868         dev_err(chip->card->dev,
 869                 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
 870                 bus->last_cmd[addr]);
 871         chip->single_cmd = 1;
 872         hbus->response_reset = 0;
 873         snd_hdac_bus_stop_cmd_io(bus);
 874         return -EIO;
 875 }
 876
 877 /*
 878  * Use the single immediate command instead of CORB/RIRB for simplicity
 879  *
 880  * Note: according to Intel, this is not preferred use.  The command was
 881  *       intended for the BIOS only, and may get confused with unsolicited
 882  *       responses.  So, we shouldn't use it for normal operation from the
 883  *       driver.
 884  *       I left the codes, however, for debugging/testing purposes.
 885  */
 886
 887 /* receive a response */
 888 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 889 {
 890         int timeout = 50;
 891
 892         while (timeout--) {
 893                 /* check IRV busy bit */
 894                 if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
 895                         /* reuse rirb.res as the response return value */
 896                         azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
 897                         return 0;
 898                 }
 899                 udelay(1);
 900         }
 901         if (printk_ratelimit())
 902                 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
 903                         azx_readw(chip, IRS));
 904         azx_bus(chip)->rirb.res[addr] = -1;
 905         return -EIO;
 906 }
 907
 908 /* send a command */
 909 static int azx_single_send_cmd(struct hdac_bus *bus, u32 val)
 910 {
 911         struct azx *chip = bus_to_azx(bus);
 912         unsigned int addr = azx_command_addr(val);
 913         int timeout = 50;
 914
 915         bus->last_cmd[azx_command_addr(val)] = val;
 916         while (timeout--) {
 917                 /* check ICB busy bit */
 918                 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
 919                         /* Clear IRV valid bit */
 920                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 921                                    AZX_IRS_VALID);
 922                         azx_writel(chip, IC, val);
 923                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 924                                    AZX_IRS_BUSY);
 925                         return azx_single_wait_for_response(chip, addr);
 926                 }
 927                 udelay(1);
 928         }
 929         if (printk_ratelimit())
 930                 dev_dbg(chip->card->dev,
 931                         "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 932                         azx_readw(chip, IRS), val);
 933         return -EIO;
 934 }
 935
 936 /* receive a response */
 937 static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr,
 938                                    unsigned int *res)
 939 {
 940         if (res)
 941                 *res = bus->rirb.res[addr];
 942         return 0;
 943 }
 944
 945 /*
 946  * The below are the main callbacks from hda_codec.
 947  *
 948  * They are just the skeleton to call sub-callbacks according to the
 949  * current setting of chip->single_cmd.
 950  */
 951
 952 /* send a command */
 953 static int azx_send_cmd(struct hdac_bus *bus, unsigned int val)
 954 {
 955         struct azx *chip = bus_to_azx(bus);
 956
 957         if (chip->disabled)
 958                 return 0;
 959         if (chip->single_cmd)
 960                 return azx_single_send_cmd(bus, val);
 961         else
 962                 return snd_hdac_bus_send_cmd(bus, val);
 963 }
 964
 965 /* get a response */
 966 static int azx_get_response(struct hdac_bus *bus, unsigned int addr,
 967                             unsigned int *res)
 968 {
 969         struct azx *chip = bus_to_azx(bus);
 970
 971         if (chip->disabled)
 972                 return 0;
 973         if (chip->single_cmd)
 974                 return azx_single_get_response(bus, addr, res);
 975         else
 976                 return azx_rirb_get_response(bus, addr, res);
 977 }
 978
 979 static const struct hdac_bus_ops bus_core_ops = {
 980         .command = azx_send_cmd,
 981         .get_response = azx_get_response,
 982 };
 983
 984 #ifdef CONFIG_SND_HDA_DSP_LOADER
 985 /*
 986  * DSP loading code (e.g. for CA0132)
 987  */
 988
 989 /* use the first stream for loading DSP */
 990 static struct azx_dev *
 991 azx_get_dsp_loader_dev(struct azx *chip)
 992 {
 993         struct hdac_bus *bus = azx_bus(chip);
 994         struct hdac_stream *s;
 995
 996         list_for_each_entry(s, &bus->stream_list, list)
 997                 if (s->index == chip->playback_index_offset)
 998                         return stream_to_azx_dev(s);
 999
1000         return NULL;
1001 }
1002
1003 int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
1004                                    unsigned int byte_size,
1005                                    struct snd_dma_buffer *bufp)
1006 {
1007         struct hdac_bus *bus = &codec->bus->core;
1008         struct azx *chip = bus_to_azx(bus);
1009         struct azx_dev *azx_dev;
1010         struct hdac_stream *hstr;
1011         bool saved = false;
1012         int err;
1013
1014         azx_dev = azx_get_dsp_loader_dev(chip);
1015         hstr = azx_stream(azx_dev);
1016         spin_lock_irq(&bus->reg_lock);
1017         if (hstr->opened) {
1018                 chip->saved_azx_dev = *azx_dev;
1019                 saved = true;
1020         }
1021         spin_unlock_irq(&bus->reg_lock);
1022
1023         err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
1024         if (err < 0) {
1025                 spin_lock_irq(&bus->reg_lock);
1026                 if (saved)
1027                         *azx_dev = chip->saved_azx_dev;
1028                 spin_unlock_irq(&bus->reg_lock);
1029                 return err;
1030         }
1031
1032         hstr->prepared = 0;
1033         return err;
1034 }
1035 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare);
1036
1037 void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start)
1038 {
1039         struct hdac_bus *bus = &codec->bus->core;
1040         struct azx *chip = bus_to_azx(bus);
1041         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1042
1043         snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
1044 }
1045 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger);
1046
1047 void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
1048                                     struct snd_dma_buffer *dmab)
1049 {
1050         struct hdac_bus *bus = &codec->bus->core;
1051         struct azx *chip = bus_to_azx(bus);
1052         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1053         struct hdac_stream *hstr = azx_stream(azx_dev);
1054
1055         if (!dmab->area || !hstr->locked)
1056                 return;
1057
1058         snd_hdac_dsp_cleanup(hstr, dmab);
1059         spin_lock_irq(&bus->reg_lock);
1060         if (hstr->opened)
1061                 *azx_dev = chip->saved_azx_dev;
1062         hstr->locked = false;
1063         spin_unlock_irq(&bus->reg_lock);
1064 }
1065 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup);
1066 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1067
1068 /*
1069  * reset and start the controller registers
1070  */
1071 void azx_init_chip(struct azx *chip, bool full_reset)
1072 {
1073         if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {
1074                 /* correct RINTCNT for CXT */
1075                 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1076                         azx_writew(chip, RINTCNT, 0xc0);
1077         }
1078 }
1079 EXPORT_SYMBOL_GPL(azx_init_chip);
1080
1081 void azx_stop_all_streams(struct azx *chip)
1082 {
1083         struct hdac_bus *bus = azx_bus(chip);
1084         struct hdac_stream *s;
1085
1086         list_for_each_entry(s, &bus->stream_list, list)
1087                 snd_hdac_stream_stop(s);
1088 }
1089 EXPORT_SYMBOL_GPL(azx_stop_all_streams);
1090
1091 void azx_stop_chip(struct azx *chip)
1092 {
1093         snd_hdac_bus_stop_chip(azx_bus(chip));
1094 }
1095 EXPORT_SYMBOL_GPL(azx_stop_chip);
1096
1097 /*
1098  * interrupt handler
1099  */
1100 static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
1101 {
1102         struct azx *chip = bus_to_azx(bus);
1103         struct azx_dev *azx_dev = stream_to_azx_dev(s);
1104
1105         /* check whether this IRQ is really acceptable */
1106         if (!chip->ops->position_check ||
1107             chip->ops->position_check(chip, azx_dev)) {
1108                 spin_unlock(&bus->reg_lock);
1109                 snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
1110                 spin_lock(&bus->reg_lock);
1111         }
1112 }
1113
1114 irqreturn_t azx_interrupt(int irq, void *dev_id)
1115 {
1116         struct azx *chip = dev_id;
1117         struct hdac_bus *bus = azx_bus(chip);
1118         u32 status;
1119         bool active, handled = false;
1120         int repeat = 0; /* count for avoiding endless loop */
1121
1122 #ifdef CONFIG_PM
1123         if (azx_has_pm_runtime(chip))
1124                 if (!pm_runtime_active(chip->card->dev))
1125                         return IRQ_NONE;
1126 #endif
1127
1128         spin_lock(&bus->reg_lock);
1129
1130         if (chip->disabled)
1131                 goto unlock;
1132
1133         do {
1134                 status = azx_readl(chip, INTSTS);
1135                 if (status == 0 || status == 0xffffffff)
1136                         break;
1137
1138                 handled = true;
1139                 active = false;
1140                 if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update))
1141                         active = true;
1142
1143                 /* clear rirb int */
1144                 status = azx_readb(chip, RIRBSTS);
1145                 if (status & RIRB_INT_MASK) {
1146                         active = true;
1147                         if (status & RIRB_INT_RESPONSE) {
1148                                 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1149                                         udelay(80);
1150                                 snd_hdac_bus_update_rirb(bus);
1151                         }
1152                         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1153                 }
1154         } while (active && ++repeat < 10);
1155
1156  unlock:
1157         spin_unlock(&bus->reg_lock);
1158
1159         return IRQ_RETVAL(handled);
1160 }
1161 EXPORT_SYMBOL_GPL(azx_interrupt);
1162
1163 /*
1164  * Codec initerface
1165  */
1166
1167 /*
1168  * Probe the given codec address
1169  */
1170 static int probe_codec(struct azx *chip, int addr)
1171 {
1172         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1173                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1174         struct hdac_bus *bus = azx_bus(chip);
1175         int err;
1176         unsigned int res = -1;
1177
1178         mutex_lock(&bus->cmd_mutex);
1179         chip->probing = 1;
1180         azx_send_cmd(bus, cmd);
1181         err = azx_get_response(bus, addr, &res);
1182         chip->probing = 0;
1183         mutex_unlock(&bus->cmd_mutex);
1184         if (err < 0 || res == -1)
1185                 return -EIO;
1186         dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1187         return 0;
1188 }
1189
1190 void snd_hda_bus_reset(struct hda_bus *bus)
1191 {
1192         struct azx *chip = bus_to_azx(&bus->core);
1193
1194         bus->in_reset = 1;
1195         azx_stop_chip(chip);
1196         azx_init_chip(chip, true);
1197         if (bus->core.chip_init)
1198                 snd_hda_bus_reset_codecs(bus);
1199         bus->in_reset = 0;
1200 }
1201
1202 /* HD-audio bus initialization */
1203 int azx_bus_init(struct azx *chip, const char *model,
1204                  const struct hdac_io_ops *io_ops)
1205 {
1206         struct hda_bus *bus = &chip->bus;
1207         int err;
1208
1209         err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops,
1210                                 io_ops);
1211         if (err < 0)
1212                 return err;
1213
1214         bus->card = chip->card;
1215         mutex_init(&bus->prepare_mutex);
1216         bus->pci = chip->pci;
1217         bus->modelname = model;
1218         bus->mixer_assigned = -1;
1219         bus->core.snoop = azx_snoop(chip);
1220         if (chip->get_position[0] != azx_get_pos_lpib ||
1221             chip->get_position[1] != azx_get_pos_lpib)
1222                 bus->core.use_posbuf = true;
1223         bus->core.bdl_pos_adj = chip->bdl_pos_adj;
1224         if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)
1225                 bus->core.corbrp_self_clear = true;
1226
1227         if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY)
1228                 bus->core.align_bdle_4k = true;
1229
1230         /* AMD chipsets often cause the communication stalls upon certain
1231          * sequence like the pin-detection.  It seems that forcing the synced
1232          * access works around the stall.  Grrr...
1233          */
1234         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1235                 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1236                 bus->core.sync_write = 1;
1237                 bus->allow_bus_reset = 1;
1238         }
1239
1240         return 0;
1241 }
1242 EXPORT_SYMBOL_GPL(azx_bus_init);
1243
1244 /* Probe codecs */
1245 int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
1246 {
1247         struct hdac_bus *bus = azx_bus(chip);
1248         int c, codecs, err;
1249
1250         codecs = 0;
1251         if (!max_slots)
1252                 max_slots = AZX_DEFAULT_CODECS;
1253
1254         /* First try to probe all given codec slots */
1255         for (c = 0; c < max_slots; c++) {
1256                 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1257                         if (probe_codec(chip, c) < 0) {
1258                                 /* Some BIOSen give you wrong codec addresses
1259                                  * that don't exist
1260                                  */
1261                                 dev_warn(chip->card->dev,
1262                                          "Codec #%d probe error; disabling it...\n", c);
1263                                 bus->codec_mask &= ~(1 << c);
1264                                 /* More badly, accessing to a non-existing
1265                                  * codec often screws up the controller chip,
1266                                  * and disturbs the further communications.
1267                                  * Thus if an error occurs during probing,
1268                                  * better to reset the controller chip to
1269                                  * get back to the sanity state.
1270                                  */
1271                                 azx_stop_chip(chip);
1272                                 azx_init_chip(chip, true);
1273                         }
1274                 }
1275         }
1276
1277         /* Then create codec instances */
1278         for (c = 0; c < max_slots; c++) {
1279                 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1280                         struct hda_codec *codec;
1281                         err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec);
1282                         if (err < 0)
1283                                 continue;
1284                         codec->jackpoll_interval = chip->jackpoll_interval;
1285                         codec->beep_mode = chip->beep_mode;
1286                         codecs++;
1287                 }
1288         }
1289         if (!codecs) {
1290                 dev_err(chip->card->dev, "no codecs initialized\n");
1291                 return -ENXIO;
1292         }
1293         return 0;
1294 }
1295 EXPORT_SYMBOL_GPL(azx_probe_codecs);
1296
1297 /* configure each codec instance */
1298 int azx_codec_configure(struct azx *chip)
1299 {
1300         struct hda_codec *codec, *next;
1301
1302         /* use _safe version here since snd_hda_codec_configure() deregisters
1303          * the device upon error and deletes itself from the bus list.
1304          */
1305         list_for_each_codec_safe(codec, next, &chip->bus) {
1306                 snd_hda_codec_configure(codec);
1307         }
1308
1309         if (!azx_bus(chip)->num_codecs)
1310                 return -ENODEV;
1311         return 0;
1312 }
1313 EXPORT_SYMBOL_GPL(azx_codec_configure);
1314
1315 static int stream_direction(struct azx *chip, unsigned char index)
1316 {
1317         if (index >= chip->capture_index_offset &&
1318             index < chip->capture_index_offset + chip->capture_streams)
1319                 return SNDRV_PCM_STREAM_CAPTURE;
1320         return SNDRV_PCM_STREAM_PLAYBACK;
1321 }
1322
1323 /* initialize SD streams */
1324 int azx_init_streams(struct azx *chip)
1325 {
1326         int i;
1327         int stream_tags[2] = { 0, 0 };
1328
1329         /* initialize each stream (aka device)
1330          * assign the starting bdl address to each stream (device)
1331          * and initialize
1332          */
1333         for (i = 0; i < chip->num_streams; i++) {
1334                 struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL);
1335                 int dir, tag;
1336
1337                 if (!azx_dev)
1338                         return -ENOMEM;
1339
1340                 dir = stream_direction(chip, i);
1341                 /* stream tag must be unique throughout
1342                  * the stream direction group,
1343                  * valid values 1...15
1344                  * use separate stream tag if the flag
1345                  * AZX_DCAPS_SEPARATE_STREAM_TAG is used
1346                  */
1347                 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
1348                         tag = ++stream_tags[dir];
1349                 else
1350                         tag = i + 1;
1351                 snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev),
1352                                      i, dir, tag);
1353         }
1354
1355         return 0;
1356 }
1357 EXPORT_SYMBOL_GPL(azx_init_streams);
1358
1359 void azx_free_streams(struct azx *chip)
1360 {
1361         struct hdac_bus *bus = azx_bus(chip);
1362         struct hdac_stream *s;
1363
1364         while (!list_empty(&bus->stream_list)) {
1365                 s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
1366                 list_del(&s->list);
1367                 kfree(stream_to_azx_dev(s));
1368         }
1369 }
1370 EXPORT_SYMBOL_GPL(azx_free_streams);