sound/pci/hda/hda_controller.c

   1 /*
   2  *
   3  *  Implementation of primary alsa driver code base for Intel HD Audio.
   4  *
   5  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   6  *
   7  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   8  *                     PeiSen Hou <pshou@realtek.com.tw>
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License as published by the Free
  12  *  Software Foundation; either version 2 of the License, or (at your option)
  13  *  any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  *  more details.
  19  *
  20  *
  21  */
  22
  23 #include <linux/clocksource.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/slab.h>
  30 #include <linux/reboot.h>
  31 #include <sound/core.h>
  32 #include <sound/initval.h>
  33 #include "hda_controller.h"
  34
  35 #define CREATE_TRACE_POINTS
  36 #include "hda_intel_trace.h"
  37
  38 /* DSP lock helpers */
  39 #ifdef CONFIG_SND_HDA_DSP_LOADER
  40 #define dsp_lock_init(dev)      mutex_init(&(dev)->dsp_mutex)
  41 #define dsp_lock(dev)           mutex_lock(&(dev)->dsp_mutex)
  42 #define dsp_unlock(dev)         mutex_unlock(&(dev)->dsp_mutex)
  43 #define dsp_is_locked(dev)      ((dev)->locked)
  44 #else
  45 #define dsp_lock_init(dev)      do {} while (0)
  46 #define dsp_lock(dev)           do {} while (0)
  47 #define dsp_unlock(dev)         do {} while (0)
  48 #define dsp_is_locked(dev)      0
  49 #endif
  50
  51 /*
  52  * AZX stream operations.
  53  */
  54
  55 /* start a stream */
  56 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
  57 {
  58         /*
  59          * Before stream start, initialize parameter
  60          */
  61         azx_dev->insufficient = 1;
  62
  63         /* enable SIE */
  64         azx_writel(chip, INTCTL,
  65                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
  66         /* set DMA start and interrupt mask */
  67         azx_sd_writeb(chip, azx_dev, SD_CTL,
  68                       azx_sd_readb(chip, azx_dev, SD_CTL) |
  69                       SD_CTL_DMA_START | SD_INT_MASK);
  70 }
  71
  72 /* stop DMA */
  73 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
  74 {
  75         azx_sd_writeb(chip, azx_dev, SD_CTL,
  76                       azx_sd_readb(chip, azx_dev, SD_CTL) &
  77                       ~(SD_CTL_DMA_START | SD_INT_MASK));
  78         azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
  79 }
  80
  81 /* stop a stream */
  82 void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
  83 {
  84         azx_stream_clear(chip, azx_dev);
  85         /* disable SIE */
  86         azx_writel(chip, INTCTL,
  87                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
  88 }
  89 EXPORT_SYMBOL_GPL(azx_stream_stop);
  90
  91 /* reset stream */
  92 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
  93 {
  94         unsigned char val;
  95         int timeout;
  96
  97         azx_stream_clear(chip, azx_dev);
  98
  99         azx_sd_writeb(chip, azx_dev, SD_CTL,
 100                       azx_sd_readb(chip, azx_dev, SD_CTL) |
 101                       SD_CTL_STREAM_RESET);
 102         udelay(3);
 103         timeout = 300;
 104         while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
 105                  SD_CTL_STREAM_RESET) && --timeout)
 106                 ;
 107         val &= ~SD_CTL_STREAM_RESET;
 108         azx_sd_writeb(chip, azx_dev, SD_CTL, val);
 109         udelay(3);
 110
 111         timeout = 300;
 112         /* waiting for hardware to report that the stream is out of reset */
 113         while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
 114                 SD_CTL_STREAM_RESET) && --timeout)
 115                 ;
 116
 117         /* reset first position - may not be synced with hw at this time */
 118         *azx_dev->posbuf = 0;
 119 }
 120
 121 /*
 122  * set up the SD for streaming
 123  */
 124 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
 125 {
 126         unsigned int val;
 127         /* make sure the run bit is zero for SD */
 128         azx_stream_clear(chip, azx_dev);
 129         /* program the stream_tag */
 130         val = azx_sd_readl(chip, azx_dev, SD_CTL);
 131         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
 132                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
 133         if (!azx_snoop(chip))
 134                 val |= SD_CTL_TRAFFIC_PRIO;
 135         azx_sd_writel(chip, azx_dev, SD_CTL, val);
 136
 137         /* program the length of samples in cyclic buffer */
 138         azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize);
 139
 140         /* program the stream format */
 141         /* this value needs to be the same as the one programmed */
 142         azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val);
 143
 144         /* program the stream LVI (last valid index) of the BDL */
 145         azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1);
 146
 147         /* program the BDL address */
 148         /* lower BDL address */
 149         azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
 150         /* upper BDL address */
 151         azx_sd_writel(chip, azx_dev, SD_BDLPU,
 152                       upper_32_bits(azx_dev->bdl.addr));
 153
 154         /* enable the position buffer */
 155         if (chip->get_position[0] != azx_get_pos_lpib ||
 156             chip->get_position[1] != azx_get_pos_lpib) {
 157                 if (!(azx_readl(chip, DPLBASE) & AZX_DPLBASE_ENABLE))
 158                         azx_writel(chip, DPLBASE,
 159                                 (u32)chip->posbuf.addr | AZX_DPLBASE_ENABLE);
 160         }
 161
 162         /* set the interrupt enable bits in the descriptor control register */
 163         azx_sd_writel(chip, azx_dev, SD_CTL,
 164                       azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK);
 165
 166         return 0;
 167 }
 168
 169 /* assign a stream for the PCM */
 170 static inline struct azx_dev *
 171 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
 172 {
 173         int dev, i, nums;
 174         struct azx_dev *res = NULL;
 175         /* make a non-zero unique key for the substream */
 176         int key = (substream->pcm->device << 16) | (substream->number << 2) |
 177                 (substream->stream + 1);
 178
 179         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 180                 dev = chip->playback_index_offset;
 181                 nums = chip->playback_streams;
 182         } else {
 183                 dev = chip->capture_index_offset;
 184                 nums = chip->capture_streams;
 185         }
 186         for (i = 0; i < nums; i++, dev++) {
 187                 struct azx_dev *azx_dev = &chip->azx_dev[dev];
 188                 dsp_lock(azx_dev);
 189                 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
 190                         if (azx_dev->assigned_key == key) {
 191                                 azx_dev->opened = 1;
 192                                 azx_dev->assigned_key = key;
 193                                 dsp_unlock(azx_dev);
 194                                 return azx_dev;
 195                         }
 196                         if (!res ||
 197                             (chip->driver_caps & AZX_DCAPS_REVERSE_ASSIGN))
 198                                 res = azx_dev;
 199                 }
 200                 dsp_unlock(azx_dev);
 201         }
 202         if (res) {
 203                 dsp_lock(res);
 204                 res->opened = 1;
 205                 res->assigned_key = key;
 206                 dsp_unlock(res);
 207         }
 208         return res;
 209 }
 210
 211 /* release the assigned stream */
 212 static inline void azx_release_device(struct azx_dev *azx_dev)
 213 {
 214         azx_dev->opened = 0;
 215 }
 216
 217 static cycle_t azx_cc_read(const struct cyclecounter *cc)
 218 {
 219         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
 220         struct snd_pcm_substream *substream = azx_dev->substream;
 221         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 222         struct azx *chip = apcm->chip;
 223
 224         return azx_readl(chip, WALLCLK);
 225 }
 226
 227 static void azx_timecounter_init(struct snd_pcm_substream *substream,
 228                                 bool force, cycle_t last)
 229 {
 230         struct azx_dev *azx_dev = get_azx_dev(substream);
 231         struct timecounter *tc = &azx_dev->azx_tc;
 232         struct cyclecounter *cc = &azx_dev->azx_cc;
 233         u64 nsec;
 234
 235         cc->read = azx_cc_read;
 236         cc->mask = CLOCKSOURCE_MASK(32);
 237
 238         /*
 239          * Converting from 24 MHz to ns means applying a 125/3 factor.
 240          * To avoid any saturation issues in intermediate operations,
 241          * the 125 factor is applied first. The division is applied
 242          * last after reading the timecounter value.
 243          * Applying the 1/3 factor as part of the multiplication
 244          * requires at least 20 bits for a decent precision, however
 245          * overflows occur after about 4 hours or less, not a option.
 246          */
 247
 248         cc->mult = 125; /* saturation after 195 years */
 249         cc->shift = 0;
 250
 251         nsec = 0; /* audio time is elapsed time since trigger */
 252         timecounter_init(tc, cc, nsec);
 253         if (force)
 254                 /*
 255                  * force timecounter to use predefined value,
 256                  * used for synchronized starts
 257                  */
 258                 tc->cycle_last = last;
 259 }
 260
 261 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
 262                                 u64 nsec)
 263 {
 264         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 265         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 266         u64 codec_frames, codec_nsecs;
 267
 268         if (!hinfo->ops.get_delay)
 269                 return nsec;
 270
 271         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
 272         codec_nsecs = div_u64(codec_frames * 1000000000LL,
 273                               substream->runtime->rate);
 274
 275         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 276                 return nsec + codec_nsecs;
 277
 278         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
 279 }
 280
 281 /*
 282  * set up a BDL entry
 283  */
 284 static int setup_bdle(struct azx *chip,
 285                       struct snd_dma_buffer *dmab,
 286                       struct azx_dev *azx_dev, u32 **bdlp,
 287                       int ofs, int size, int with_ioc)
 288 {
 289         u32 *bdl = *bdlp;
 290
 291         while (size > 0) {
 292                 dma_addr_t addr;
 293                 int chunk;
 294
 295                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
 296                         return -EINVAL;
 297
 298                 addr = snd_sgbuf_get_addr(dmab, ofs);
 299                 /* program the address field of the BDL entry */
 300                 bdl[0] = cpu_to_le32((u32)addr);
 301                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
 302                 /* program the size field of the BDL entry */
 303                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
 304                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
 305                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
 306                         u32 remain = 0x1000 - (ofs & 0xfff);
 307                         if (chunk > remain)
 308                                 chunk = remain;
 309                 }
 310                 bdl[2] = cpu_to_le32(chunk);
 311                 /* program the IOC to enable interrupt
 312                  * only when the whole fragment is processed
 313                  */
 314                 size -= chunk;
 315                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
 316                 bdl += 4;
 317                 azx_dev->frags++;
 318                 ofs += chunk;
 319         }
 320         *bdlp = bdl;
 321         return ofs;
 322 }
 323
 324 /*
 325  * set up BDL entries
 326  */
 327 static int azx_setup_periods(struct azx *chip,
 328                              struct snd_pcm_substream *substream,
 329                              struct azx_dev *azx_dev)
 330 {
 331         u32 *bdl;
 332         int i, ofs, periods, period_bytes;
 333         int pos_adj = 0;
 334
 335         /* reset BDL address */
 336         azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
 337         azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
 338
 339         period_bytes = azx_dev->period_bytes;
 340         periods = azx_dev->bufsize / period_bytes;
 341
 342         /* program the initial BDL entries */
 343         bdl = (u32 *)azx_dev->bdl.area;
 344         ofs = 0;
 345         azx_dev->frags = 0;
 346
 347         if (chip->bdl_pos_adj)
 348                 pos_adj = chip->bdl_pos_adj[chip->dev_index];
 349         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
 350                 struct snd_pcm_runtime *runtime = substream->runtime;
 351                 int pos_align = pos_adj;
 352                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
 353                 if (!pos_adj)
 354                         pos_adj = pos_align;
 355                 else
 356                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
 357                                 pos_align;
 358                 pos_adj = frames_to_bytes(runtime, pos_adj);
 359                 if (pos_adj >= period_bytes) {
 360                         dev_warn(chip->card->dev,"Too big adjustment %d\n",
 361                                  pos_adj);
 362                         pos_adj = 0;
 363                 } else {
 364                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
 365                                          azx_dev,
 366                                          &bdl, ofs, pos_adj, true);
 367                         if (ofs < 0)
 368                                 goto error;
 369                 }
 370         } else
 371                 pos_adj = 0;
 372
 373         for (i = 0; i < periods; i++) {
 374                 if (i == periods - 1 && pos_adj)
 375                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
 376                                          azx_dev, &bdl, ofs,
 377                                          period_bytes - pos_adj, 0);
 378                 else
 379                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
 380                                          azx_dev, &bdl, ofs,
 381                                          period_bytes,
 382                                          !azx_dev->no_period_wakeup);
 383                 if (ofs < 0)
 384                         goto error;
 385         }
 386         return 0;
 387
 388  error:
 389         dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n",
 390                 azx_dev->bufsize, period_bytes);
 391         return -EINVAL;
 392 }
 393
 394 /*
 395  * PCM ops
 396  */
 397
 398 static int azx_pcm_close(struct snd_pcm_substream *substream)
 399 {
 400         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 401         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 402         struct azx *chip = apcm->chip;
 403         struct azx_dev *azx_dev = get_azx_dev(substream);
 404         unsigned long flags;
 405
 406         mutex_lock(&chip->open_mutex);
 407         spin_lock_irqsave(&chip->reg_lock, flags);
 408         azx_dev->substream = NULL;
 409         azx_dev->running = 0;
 410         spin_unlock_irqrestore(&chip->reg_lock, flags);
 411         azx_release_device(azx_dev);
 412         hinfo->ops.close(hinfo, apcm->codec, substream);
 413         snd_hda_power_down(apcm->codec);
 414         mutex_unlock(&chip->open_mutex);
 415         return 0;
 416 }
 417
 418 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
 419                              struct snd_pcm_hw_params *hw_params)
 420 {
 421         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 422         struct azx *chip = apcm->chip;
 423         int ret;
 424
 425         dsp_lock(get_azx_dev(substream));
 426         if (dsp_is_locked(get_azx_dev(substream))) {
 427                 ret = -EBUSY;
 428                 goto unlock;
 429         }
 430
 431         ret = chip->ops->substream_alloc_pages(chip, substream,
 432                                           params_buffer_bytes(hw_params));
 433 unlock:
 434         dsp_unlock(get_azx_dev(substream));
 435         return ret;
 436 }
 437
 438 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
 439 {
 440         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 441         struct azx_dev *azx_dev = get_azx_dev(substream);
 442         struct azx *chip = apcm->chip;
 443         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 444         int err;
 445
 446         /* reset BDL address */
 447         dsp_lock(azx_dev);
 448         if (!dsp_is_locked(azx_dev)) {
 449                 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
 450                 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
 451                 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
 452                 azx_dev->bufsize = 0;
 453                 azx_dev->period_bytes = 0;
 454                 azx_dev->format_val = 0;
 455         }
 456
 457         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
 458
 459         err = chip->ops->substream_free_pages(chip, substream);
 460         azx_dev->prepared = 0;
 461         dsp_unlock(azx_dev);
 462         return err;
 463 }
 464
 465 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
 466 {
 467         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 468         struct azx *chip = apcm->chip;
 469         struct azx_dev *azx_dev = get_azx_dev(substream);
 470         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 471         struct snd_pcm_runtime *runtime = substream->runtime;
 472         unsigned int bufsize, period_bytes, format_val, stream_tag;
 473         int err;
 474         struct hda_spdif_out *spdif =
 475                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
 476         unsigned short ctls = spdif ? spdif->ctls : 0;
 477
 478         dsp_lock(azx_dev);
 479         if (dsp_is_locked(azx_dev)) {
 480                 err = -EBUSY;
 481                 goto unlock;
 482         }
 483
 484         azx_stream_reset(chip, azx_dev);
 485         format_val = snd_hda_calc_stream_format(apcm->codec,
 486                                                 runtime->rate,
 487                                                 runtime->channels,
 488                                                 runtime->format,
 489                                                 hinfo->maxbps,
 490                                                 ctls);
 491         if (!format_val) {
 492                 dev_err(chip->card->dev,
 493                         "invalid format_val, rate=%d, ch=%d, format=%d\n",
 494                         runtime->rate, runtime->channels, runtime->format);
 495                 err = -EINVAL;
 496                 goto unlock;
 497         }
 498
 499         bufsize = snd_pcm_lib_buffer_bytes(substream);
 500         period_bytes = snd_pcm_lib_period_bytes(substream);
 501
 502         dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
 503                 bufsize, format_val);
 504
 505         if (bufsize != azx_dev->bufsize ||
 506             period_bytes != azx_dev->period_bytes ||
 507             format_val != azx_dev->format_val ||
 508             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
 509                 azx_dev->bufsize = bufsize;
 510                 azx_dev->period_bytes = period_bytes;
 511                 azx_dev->format_val = format_val;
 512                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
 513                 err = azx_setup_periods(chip, substream, azx_dev);
 514                 if (err < 0)
 515                         goto unlock;
 516         }
 517
 518         /* when LPIB delay correction gives a small negative value,
 519          * we ignore it; currently set the threshold statically to
 520          * 64 frames
 521          */
 522         if (runtime->period_size > 64)
 523                 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
 524         else
 525                 azx_dev->delay_negative_threshold = 0;
 526
 527         /* wallclk has 24Mhz clock source */
 528         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
 529                                                 runtime->rate) * 1000);
 530         azx_setup_controller(chip, azx_dev);
 531         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 532                 azx_dev->fifo_size =
 533                         azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1;
 534         else
 535                 azx_dev->fifo_size = 0;
 536
 537         stream_tag = azx_dev->stream_tag;
 538         /* CA-IBG chips need the playback stream starting from 1 */
 539         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
 540             stream_tag > chip->capture_streams)
 541                 stream_tag -= chip->capture_streams;
 542         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
 543                                      azx_dev->format_val, substream);
 544
 545  unlock:
 546         if (!err)
 547                 azx_dev->prepared = 1;
 548         dsp_unlock(azx_dev);
 549         return err;
 550 }
 551
 552 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 553 {
 554         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 555         struct azx *chip = apcm->chip;
 556         struct azx_dev *azx_dev;
 557         struct snd_pcm_substream *s;
 558         int rstart = 0, start, nsync = 0, sbits = 0;
 559         int nwait, timeout;
 560
 561         azx_dev = get_azx_dev(substream);
 562         trace_azx_pcm_trigger(chip, azx_dev, cmd);
 563
 564         if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
 565                 return -EPIPE;
 566
 567         switch (cmd) {
 568         case SNDRV_PCM_TRIGGER_START:
 569                 rstart = 1;
 570         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 571         case SNDRV_PCM_TRIGGER_RESUME:
 572                 start = 1;
 573                 break;
 574         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 575         case SNDRV_PCM_TRIGGER_SUSPEND:
 576         case SNDRV_PCM_TRIGGER_STOP:
 577                 start = 0;
 578                 break;
 579         default:
 580                 return -EINVAL;
 581         }
 582
 583         snd_pcm_group_for_each_entry(s, substream) {
 584                 if (s->pcm->card != substream->pcm->card)
 585                         continue;
 586                 azx_dev = get_azx_dev(s);
 587                 sbits |= 1 << azx_dev->index;
 588                 nsync++;
 589                 snd_pcm_trigger_done(s, substream);
 590         }
 591
 592         spin_lock(&chip->reg_lock);
 593
 594         /* first, set SYNC bits of corresponding streams */
 595         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
 596                 azx_writel(chip, OLD_SSYNC,
 597                         azx_readl(chip, OLD_SSYNC) | sbits);
 598         else
 599                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
 600
 601         snd_pcm_group_for_each_entry(s, substream) {
 602                 if (s->pcm->card != substream->pcm->card)
 603                         continue;
 604                 azx_dev = get_azx_dev(s);
 605                 if (start) {
 606                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
 607                         if (!rstart)
 608                                 azx_dev->start_wallclk -=
 609                                                 azx_dev->period_wallclk;
 610                         azx_stream_start(chip, azx_dev);
 611                 } else {
 612                         azx_stream_stop(chip, azx_dev);
 613                 }
 614                 azx_dev->running = start;
 615         }
 616         spin_unlock(&chip->reg_lock);
 617         if (start) {
 618                 /* wait until all FIFOs get ready */
 619                 for (timeout = 5000; timeout; timeout--) {
 620                         nwait = 0;
 621                         snd_pcm_group_for_each_entry(s, substream) {
 622                                 if (s->pcm->card != substream->pcm->card)
 623                                         continue;
 624                                 azx_dev = get_azx_dev(s);
 625                                 if (!(azx_sd_readb(chip, azx_dev, SD_STS) &
 626                                       SD_STS_FIFO_READY))
 627                                         nwait++;
 628                         }
 629                         if (!nwait)
 630                                 break;
 631                         cpu_relax();
 632                 }
 633         } else {
 634                 /* wait until all RUN bits are cleared */
 635                 for (timeout = 5000; timeout; timeout--) {
 636                         nwait = 0;
 637                         snd_pcm_group_for_each_entry(s, substream) {
 638                                 if (s->pcm->card != substream->pcm->card)
 639                                         continue;
 640                                 azx_dev = get_azx_dev(s);
 641                                 if (azx_sd_readb(chip, azx_dev, SD_CTL) &
 642                                     SD_CTL_DMA_START)
 643                                         nwait++;
 644                         }
 645                         if (!nwait)
 646                                 break;
 647                         cpu_relax();
 648                 }
 649         }
 650         spin_lock(&chip->reg_lock);
 651         /* reset SYNC bits */
 652         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
 653                 azx_writel(chip, OLD_SSYNC,
 654                         azx_readl(chip, OLD_SSYNC) & ~sbits);
 655         else
 656                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
 657         if (start) {
 658                 azx_timecounter_init(substream, 0, 0);
 659                 snd_pcm_gettime(substream->runtime, &substream->runtime->trigger_tstamp);
 660                 substream->runtime->trigger_tstamp_latched = true;
 661
 662                 if (nsync > 1) {
 663                         cycle_t cycle_last;
 664
 665                         /* same start cycle for master and group */
 666                         azx_dev = get_azx_dev(substream);
 667                         cycle_last = azx_dev->azx_tc.cycle_last;
 668
 669                         snd_pcm_group_for_each_entry(s, substream) {
 670                                 if (s->pcm->card != substream->pcm->card)
 671                                         continue;
 672                                 azx_timecounter_init(s, 1, cycle_last);
 673                         }
 674                 }
 675         }
 676         spin_unlock(&chip->reg_lock);
 677         return 0;
 678 }
 679
 680 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
 681 {
 682         return azx_sd_readl(chip, azx_dev, SD_LPIB);
 683 }
 684 EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
 685
 686 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
 687 {
 688         return le32_to_cpu(*azx_dev->posbuf);
 689 }
 690 EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
 691
 692 unsigned int azx_get_position(struct azx *chip,
 693                               struct azx_dev *azx_dev)
 694 {
 695         struct snd_pcm_substream *substream = azx_dev->substream;
 696         unsigned int pos;
 697         int stream = substream->stream;
 698         int delay = 0;
 699
 700         if (chip->get_position[stream])
 701                 pos = chip->get_position[stream](chip, azx_dev);
 702         else /* use the position buffer as default */
 703                 pos = azx_get_pos_posbuf(chip, azx_dev);
 704
 705         if (pos >= azx_dev->bufsize)
 706                 pos = 0;
 707
 708         if (substream->runtime) {
 709                 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 710                 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
 711
 712                 if (chip->get_delay[stream])
 713                         delay += chip->get_delay[stream](chip, azx_dev, pos);
 714                 if (hinfo->ops.get_delay)
 715                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
 716                                                       substream);
 717                 substream->runtime->delay = delay;
 718         }
 719
 720         trace_azx_get_position(chip, azx_dev, pos, delay);
 721         return pos;
 722 }
 723 EXPORT_SYMBOL_GPL(azx_get_position);
 724
 725 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
 726 {
 727         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 728         struct azx *chip = apcm->chip;
 729         struct azx_dev *azx_dev = get_azx_dev(substream);
 730         return bytes_to_frames(substream->runtime,
 731                                azx_get_position(chip, azx_dev));
 732 }
 733
 734 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
 735                                 struct timespec *ts)
 736 {
 737         struct azx_dev *azx_dev = get_azx_dev(substream);
 738         u64 nsec;
 739
 740         nsec = timecounter_read(&azx_dev->azx_tc);
 741         nsec = div_u64(nsec, 3); /* can be optimized */
 742         nsec = azx_adjust_codec_delay(substream, nsec);
 743
 744         *ts = ns_to_timespec(nsec);
 745
 746         return 0;
 747 }
 748
 749 static struct snd_pcm_hardware azx_pcm_hw = {
 750         .info =                 (SNDRV_PCM_INFO_MMAP |
 751                                  SNDRV_PCM_INFO_INTERLEAVED |
 752                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 753                                  SNDRV_PCM_INFO_MMAP_VALID |
 754                                  /* No full-resume yet implemented */
 755                                  /* SNDRV_PCM_INFO_RESUME |*/
 756                                  SNDRV_PCM_INFO_PAUSE |
 757                                  SNDRV_PCM_INFO_SYNC_START |
 758                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
 759                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
 760         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 761         .rates =                SNDRV_PCM_RATE_48000,
 762         .rate_min =             48000,
 763         .rate_max =             48000,
 764         .channels_min =         2,
 765         .channels_max =         2,
 766         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
 767         .period_bytes_min =     128,
 768         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
 769         .periods_min =          2,
 770         .periods_max =          AZX_MAX_FRAG,
 771         .fifo_size =            0,
 772 };
 773
 774 static int azx_pcm_open(struct snd_pcm_substream *substream)
 775 {
 776         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 777         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 778         struct azx *chip = apcm->chip;
 779         struct azx_dev *azx_dev;
 780         struct snd_pcm_runtime *runtime = substream->runtime;
 781         unsigned long flags;
 782         int err;
 783         int buff_step;
 784
 785         mutex_lock(&chip->open_mutex);
 786         azx_dev = azx_assign_device(chip, substream);
 787         if (azx_dev == NULL) {
 788                 mutex_unlock(&chip->open_mutex);
 789                 return -EBUSY;
 790         }
 791         runtime->hw = azx_pcm_hw;
 792         runtime->hw.channels_min = hinfo->channels_min;
 793         runtime->hw.channels_max = hinfo->channels_max;
 794         runtime->hw.formats = hinfo->formats;
 795         runtime->hw.rates = hinfo->rates;
 796         snd_pcm_limit_hw_rates(runtime);
 797         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 798
 799         /* avoid wrap-around with wall-clock */
 800         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
 801                                      20,
 802                                      178000000);
 803
 804         if (chip->align_buffer_size)
 805                 /* constrain buffer sizes to be multiple of 128
 806                    bytes. This is more efficient in terms of memory
 807                    access but isn't required by the HDA spec and
 808                    prevents users from specifying exact period/buffer
 809                    sizes. For example for 44.1kHz, a period size set
 810                    to 20ms will be rounded to 19.59ms. */
 811                 buff_step = 128;
 812         else
 813                 /* Don't enforce steps on buffer sizes, still need to
 814                    be multiple of 4 bytes (HDA spec). Tested on Intel
 815                    HDA controllers, may not work on all devices where
 816                    option needs to be disabled */
 817                 buff_step = 4;
 818
 819         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 820                                    buff_step);
 821         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 822                                    buff_step);
 823         snd_hda_power_up_d3wait(apcm->codec);
 824         err = hinfo->ops.open(hinfo, apcm->codec, substream);
 825         if (err < 0) {
 826                 azx_release_device(azx_dev);
 827                 snd_hda_power_down(apcm->codec);
 828                 mutex_unlock(&chip->open_mutex);
 829                 return err;
 830         }
 831         snd_pcm_limit_hw_rates(runtime);
 832         /* sanity check */
 833         if (snd_BUG_ON(!runtime->hw.channels_min) ||
 834             snd_BUG_ON(!runtime->hw.channels_max) ||
 835             snd_BUG_ON(!runtime->hw.formats) ||
 836             snd_BUG_ON(!runtime->hw.rates)) {
 837                 azx_release_device(azx_dev);
 838                 hinfo->ops.close(hinfo, apcm->codec, substream);
 839                 snd_hda_power_down(apcm->codec);
 840                 mutex_unlock(&chip->open_mutex);
 841                 return -EINVAL;
 842         }
 843
 844         /* disable WALLCLOCK timestamps for capture streams
 845            until we figure out how to handle digital inputs */
 846         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 847                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
 848
 849         spin_lock_irqsave(&chip->reg_lock, flags);
 850         azx_dev->substream = substream;
 851         azx_dev->running = 0;
 852         spin_unlock_irqrestore(&chip->reg_lock, flags);
 853
 854         runtime->private_data = azx_dev;
 855         snd_pcm_set_sync(substream);
 856         mutex_unlock(&chip->open_mutex);
 857         return 0;
 858 }
 859
 860 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
 861                         struct vm_area_struct *area)
 862 {
 863         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 864         struct azx *chip = apcm->chip;
 865         if (chip->ops->pcm_mmap_prepare)
 866                 chip->ops->pcm_mmap_prepare(substream, area);
 867         return snd_pcm_lib_default_mmap(substream, area);
 868 }
 869
 870 static struct snd_pcm_ops azx_pcm_ops = {
 871         .open = azx_pcm_open,
 872         .close = azx_pcm_close,
 873         .ioctl = snd_pcm_lib_ioctl,
 874         .hw_params = azx_pcm_hw_params,
 875         .hw_free = azx_pcm_hw_free,
 876         .prepare = azx_pcm_prepare,
 877         .trigger = azx_pcm_trigger,
 878         .pointer = azx_pcm_pointer,
 879         .wall_clock =  azx_get_wallclock_tstamp,
 880         .mmap = azx_pcm_mmap,
 881         .page = snd_pcm_sgbuf_ops_page,
 882 };
 883
 884 static void azx_pcm_free(struct snd_pcm *pcm)
 885 {
 886         struct azx_pcm *apcm = pcm->private_data;
 887         if (apcm) {
 888                 list_del(&apcm->list);
 889                 kfree(apcm);
 890         }
 891 }
 892
 893 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
 894
 895 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
 896                                  struct hda_pcm *cpcm)
 897 {
 898         struct azx *chip = bus->private_data;
 899         struct snd_pcm *pcm;
 900         struct azx_pcm *apcm;
 901         int pcm_dev = cpcm->device;
 902         unsigned int size;
 903         int s, err;
 904
 905         list_for_each_entry(apcm, &chip->pcm_list, list) {
 906                 if (apcm->pcm->device == pcm_dev) {
 907                         dev_err(chip->card->dev, "PCM %d already exists\n",
 908                                 pcm_dev);
 909                         return -EBUSY;
 910                 }
 911         }
 912         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
 913                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
 914                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
 915                           &pcm);
 916         if (err < 0)
 917                 return err;
 918         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
 919         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
 920         if (apcm == NULL)
 921                 return -ENOMEM;
 922         apcm->chip = chip;
 923         apcm->pcm = pcm;
 924         apcm->codec = codec;
 925         pcm->private_data = apcm;
 926         pcm->private_free = azx_pcm_free;
 927         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
 928                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
 929         list_add_tail(&apcm->list, &chip->pcm_list);
 930         cpcm->pcm = pcm;
 931         for (s = 0; s < 2; s++) {
 932                 apcm->hinfo[s] = &cpcm->stream[s];
 933                 if (cpcm->stream[s].substreams)
 934                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
 935         }
 936         /* buffer pre-allocation */
 937         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
 938         if (size > MAX_PREALLOC_SIZE)
 939                 size = MAX_PREALLOC_SIZE;
 940         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
 941                                               chip->card->dev,
 942                                               size, MAX_PREALLOC_SIZE);
 943         /* link to codec */
 944         for (s = 0; s < 2; s++)
 945                 pcm->streams[s].dev.parent = &codec->dev;
 946         return 0;
 947 }
 948
 949 /*
 950  * CORB / RIRB interface
 951  */
 952 static int azx_alloc_cmd_io(struct azx *chip)
 953 {
 954         int err;
 955
 956         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 957         err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
 958                                          PAGE_SIZE, &chip->rb);
 959         if (err < 0)
 960                 dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n");
 961         return err;
 962 }
 963 EXPORT_SYMBOL_GPL(azx_alloc_cmd_io);
 964
 965 static void azx_init_cmd_io(struct azx *chip)
 966 {
 967         int timeout;
 968
 969         spin_lock_irq(&chip->reg_lock);
 970         /* CORB set up */
 971         chip->corb.addr = chip->rb.addr;
 972         chip->corb.buf = (u32 *)chip->rb.area;
 973         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 974         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 975
 976         /* set the corb size to 256 entries (ULI requires explicitly) */
 977         azx_writeb(chip, CORBSIZE, 0x02);
 978         /* set the corb write pointer to 0 */
 979         azx_writew(chip, CORBWP, 0);
 980
 981         /* reset the corb hw read pointer */
 982         azx_writew(chip, CORBRP, AZX_CORBRP_RST);
 983         if (!(chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)) {
 984                 for (timeout = 1000; timeout > 0; timeout--) {
 985                         if ((azx_readw(chip, CORBRP) & AZX_CORBRP_RST) == AZX_CORBRP_RST)
 986                                 break;
 987                         udelay(1);
 988                 }
 989                 if (timeout <= 0)
 990                         dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n",
 991                                 azx_readw(chip, CORBRP));
 992
 993                 azx_writew(chip, CORBRP, 0);
 994                 for (timeout = 1000; timeout > 0; timeout--) {
 995                         if (azx_readw(chip, CORBRP) == 0)
 996                                 break;
 997                         udelay(1);
 998                 }
 999                 if (timeout <= 0)
1000                         dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n",
1001                                 azx_readw(chip, CORBRP));
1002         }
1003
1004         /* enable corb dma */
1005         azx_writeb(chip, CORBCTL, AZX_CORBCTL_RUN);
1006
1007         /* RIRB set up */
1008         chip->rirb.addr = chip->rb.addr + 2048;
1009         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
1010         chip->rirb.wp = chip->rirb.rp = 0;
1011         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1012         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
1013         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1014
1015         /* set the rirb size to 256 entries (ULI requires explicitly) */
1016         azx_writeb(chip, RIRBSIZE, 0x02);
1017         /* reset the rirb hw write pointer */
1018         azx_writew(chip, RIRBWP, AZX_RIRBWP_RST);
1019         /* set N=1, get RIRB response interrupt for new entry */
1020         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1021                 azx_writew(chip, RINTCNT, 0xc0);
1022         else
1023                 azx_writew(chip, RINTCNT, 1);
1024         /* enable rirb dma and response irq */
1025         azx_writeb(chip, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
1026         spin_unlock_irq(&chip->reg_lock);
1027 }
1028 EXPORT_SYMBOL_GPL(azx_init_cmd_io);
1029
1030 static void azx_free_cmd_io(struct azx *chip)
1031 {
1032         spin_lock_irq(&chip->reg_lock);
1033         /* disable ringbuffer DMAs */
1034         azx_writeb(chip, RIRBCTL, 0);
1035         azx_writeb(chip, CORBCTL, 0);
1036         spin_unlock_irq(&chip->reg_lock);
1037 }
1038 EXPORT_SYMBOL_GPL(azx_free_cmd_io);
1039
1040 static unsigned int azx_command_addr(u32 cmd)
1041 {
1042         unsigned int addr = cmd >> 28;
1043
1044         if (addr >= AZX_MAX_CODECS) {
1045                 snd_BUG();
1046                 addr = 0;
1047         }
1048
1049         return addr;
1050 }
1051
1052 /* send a command */
1053 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1054 {
1055         struct azx *chip = bus->private_data;
1056         unsigned int addr = azx_command_addr(val);
1057         unsigned int wp, rp;
1058
1059         spin_lock_irq(&chip->reg_lock);
1060
1061         /* add command to corb */
1062         wp = azx_readw(chip, CORBWP);
1063         if (wp == 0xffff) {
1064                 /* something wrong, controller likely turned to D3 */
1065                 spin_unlock_irq(&chip->reg_lock);
1066                 return -EIO;
1067         }
1068         wp++;
1069         wp %= AZX_MAX_CORB_ENTRIES;
1070
1071         rp = azx_readw(chip, CORBRP);
1072         if (wp == rp) {
1073                 /* oops, it's full */
1074                 spin_unlock_irq(&chip->reg_lock);
1075                 return -EAGAIN;
1076         }
1077
1078         chip->rirb.cmds[addr]++;
1079         chip->corb.buf[wp] = cpu_to_le32(val);
1080         azx_writew(chip, CORBWP, wp);
1081
1082         spin_unlock_irq(&chip->reg_lock);
1083
1084         return 0;
1085 }
1086
1087 #define AZX_RIRB_EX_UNSOL_EV    (1<<4)
1088
1089 /* retrieve RIRB entry - called from interrupt handler */
1090 static void azx_update_rirb(struct azx *chip)
1091 {
1092         unsigned int rp, wp;
1093         unsigned int addr;
1094         u32 res, res_ex;
1095
1096         wp = azx_readw(chip, RIRBWP);
1097         if (wp == 0xffff) {
1098                 /* something wrong, controller likely turned to D3 */
1099                 return;
1100         }
1101
1102         if (wp == chip->rirb.wp)
1103                 return;
1104         chip->rirb.wp = wp;
1105
1106         while (chip->rirb.rp != wp) {
1107                 chip->rirb.rp++;
1108                 chip->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
1109
1110                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
1111                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
1112                 res = le32_to_cpu(chip->rirb.buf[rp]);
1113                 addr = res_ex & 0xf;
1114                 if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
1115                         dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d",
1116                                 res, res_ex,
1117                                 chip->rirb.rp, wp);
1118                         snd_BUG();
1119                 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
1120                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
1121                 else if (chip->rirb.cmds[addr]) {
1122                         chip->rirb.res[addr] = res;
1123                         smp_wmb();
1124                         chip->rirb.cmds[addr]--;
1125                 } else if (printk_ratelimit()) {
1126                         dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n",
1127                                 res, res_ex,
1128                                 chip->last_cmd[addr]);
1129                 }
1130         }
1131 }
1132
1133 /* receive a response */
1134 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
1135                                           unsigned int addr)
1136 {
1137         struct azx *chip = bus->private_data;
1138         unsigned long timeout;
1139         unsigned long loopcounter;
1140         int do_poll = 0;
1141
1142  again:
1143         timeout = jiffies + msecs_to_jiffies(1000);
1144
1145         for (loopcounter = 0;; loopcounter++) {
1146                 if (chip->polling_mode || do_poll) {
1147                         spin_lock_irq(&chip->reg_lock);
1148                         azx_update_rirb(chip);
1149                         spin_unlock_irq(&chip->reg_lock);
1150                 }
1151                 if (!chip->rirb.cmds[addr]) {
1152                         smp_rmb();
1153                         bus->rirb_error = 0;
1154
1155                         if (!do_poll)
1156                                 chip->poll_count = 0;
1157                         return chip->rirb.res[addr]; /* the last value */
1158                 }
1159                 if (time_after(jiffies, timeout))
1160                         break;
1161                 if (bus->needs_damn_long_delay || loopcounter > 3000)
1162                         msleep(2); /* temporary workaround */
1163                 else {
1164                         udelay(10);
1165                         cond_resched();
1166                 }
1167         }
1168
1169         if (!bus->no_response_fallback)
1170                 return -1;
1171
1172         if (!chip->polling_mode && chip->poll_count < 2) {
1173                 dev_dbg(chip->card->dev,
1174                         "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
1175                         chip->last_cmd[addr]);
1176                 do_poll = 1;
1177                 chip->poll_count++;
1178                 goto again;
1179         }
1180
1181
1182         if (!chip->polling_mode) {
1183                 dev_warn(chip->card->dev,
1184                          "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
1185                          chip->last_cmd[addr]);
1186                 chip->polling_mode = 1;
1187                 goto again;
1188         }
1189
1190         if (chip->msi) {
1191                 dev_warn(chip->card->dev,
1192                          "No response from codec, disabling MSI: last cmd=0x%08x\n",
1193                          chip->last_cmd[addr]);
1194                 if (chip->ops->disable_msi_reset_irq(chip) &&
1195                     chip->ops->disable_msi_reset_irq(chip) < 0) {
1196                         bus->rirb_error = 1;
1197                         return -1;
1198                 }
1199                 goto again;
1200         }
1201
1202         if (chip->probing) {
1203                 /* If this critical timeout happens during the codec probing
1204                  * phase, this is likely an access to a non-existing codec
1205                  * slot.  Better to return an error and reset the system.
1206                  */
1207                 return -1;
1208         }
1209
1210         /* a fatal communication error; need either to reset or to fallback
1211          * to the single_cmd mode
1212          */
1213         bus->rirb_error = 1;
1214         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
1215                 bus->response_reset = 1;
1216                 return -1; /* give a chance to retry */
1217         }
1218
1219         dev_err(chip->card->dev,
1220                 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
1221                 chip->last_cmd[addr]);
1222         chip->single_cmd = 1;
1223         bus->response_reset = 0;
1224         /* release CORB/RIRB */
1225         azx_free_cmd_io(chip);
1226         /* disable unsolicited responses */
1227         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_UNSOL);
1228         return -1;
1229 }
1230
1231 /*
1232  * Use the single immediate command instead of CORB/RIRB for simplicity
1233  *
1234  * Note: according to Intel, this is not preferred use.  The command was
1235  *       intended for the BIOS only, and may get confused with unsolicited
1236  *       responses.  So, we shouldn't use it for normal operation from the
1237  *       driver.
1238  *       I left the codes, however, for debugging/testing purposes.
1239  */
1240
1241 /* receive a response */
1242 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1243 {
1244         int timeout = 50;
1245
1246         while (timeout--) {
1247                 /* check IRV busy bit */
1248                 if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
1249                         /* reuse rirb.res as the response return value */
1250                         chip->rirb.res[addr] = azx_readl(chip, IR);
1251                         return 0;
1252                 }
1253                 udelay(1);
1254         }
1255         if (printk_ratelimit())
1256                 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
1257                         azx_readw(chip, IRS));
1258         chip->rirb.res[addr] = -1;
1259         return -EIO;
1260 }
1261
1262 /* send a command */
1263 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1264 {
1265         struct azx *chip = bus->private_data;
1266         unsigned int addr = azx_command_addr(val);
1267         int timeout = 50;
1268
1269         bus->rirb_error = 0;
1270         while (timeout--) {
1271                 /* check ICB busy bit */
1272                 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
1273                         /* Clear IRV valid bit */
1274                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1275                                    AZX_IRS_VALID);
1276                         azx_writel(chip, IC, val);
1277                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1278                                    AZX_IRS_BUSY);
1279                         return azx_single_wait_for_response(chip, addr);
1280                 }
1281                 udelay(1);
1282         }
1283         if (printk_ratelimit())
1284                 dev_dbg(chip->card->dev,
1285                         "send_cmd timeout: IRS=0x%x, val=0x%x\n",
1286                         azx_readw(chip, IRS), val);
1287         return -EIO;
1288 }
1289
1290 /* receive a response */
1291 static unsigned int azx_single_get_response(struct hda_bus *bus,
1292                                             unsigned int addr)
1293 {
1294         struct azx *chip = bus->private_data;
1295         return chip->rirb.res[addr];
1296 }
1297
1298 /*
1299  * The below are the main callbacks from hda_codec.
1300  *
1301  * They are just the skeleton to call sub-callbacks according to the
1302  * current setting of chip->single_cmd.
1303  */
1304
1305 /* send a command */
1306 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1307 {
1308         struct azx *chip = bus->private_data;
1309
1310         if (chip->disabled)
1311                 return 0;
1312         chip->last_cmd[azx_command_addr(val)] = val;
1313         if (chip->single_cmd)
1314                 return azx_single_send_cmd(bus, val);
1315         else
1316                 return azx_corb_send_cmd(bus, val);
1317 }
1318 EXPORT_SYMBOL_GPL(azx_send_cmd);
1319
1320 /* get a response */
1321 static unsigned int azx_get_response(struct hda_bus *bus,
1322                                      unsigned int addr)
1323 {
1324         struct azx *chip = bus->private_data;
1325         if (chip->disabled)
1326                 return 0;
1327         if (chip->single_cmd)
1328                 return azx_single_get_response(bus, addr);
1329         else
1330                 return azx_rirb_get_response(bus, addr);
1331 }
1332 EXPORT_SYMBOL_GPL(azx_get_response);
1333
1334 #ifdef CONFIG_SND_HDA_DSP_LOADER
1335 /*
1336  * DSP loading code (e.g. for CA0132)
1337  */
1338
1339 /* use the first stream for loading DSP */
1340 static struct azx_dev *
1341 azx_get_dsp_loader_dev(struct azx *chip)
1342 {
1343         return &chip->azx_dev[chip->playback_index_offset];
1344 }
1345
1346 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1347                                 unsigned int byte_size,
1348                                 struct snd_dma_buffer *bufp)
1349 {
1350         u32 *bdl;
1351         struct azx *chip = bus->private_data;
1352         struct azx_dev *azx_dev;
1353         int err;
1354
1355         azx_dev = azx_get_dsp_loader_dev(chip);
1356
1357         dsp_lock(azx_dev);
1358         spin_lock_irq(&chip->reg_lock);
1359         if (azx_dev->running || azx_dev->locked) {
1360                 spin_unlock_irq(&chip->reg_lock);
1361                 err = -EBUSY;
1362                 goto unlock;
1363         }
1364         azx_dev->prepared = 0;
1365         chip->saved_azx_dev = *azx_dev;
1366         azx_dev->locked = 1;
1367         spin_unlock_irq(&chip->reg_lock);
1368
1369         err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV_SG,
1370                                          byte_size, bufp);
1371         if (err < 0)
1372                 goto err_alloc;
1373
1374         azx_dev->bufsize = byte_size;
1375         azx_dev->period_bytes = byte_size;
1376         azx_dev->format_val = format;
1377
1378         azx_stream_reset(chip, azx_dev);
1379
1380         /* reset BDL address */
1381         azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1382         azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1383
1384         azx_dev->frags = 0;
1385         bdl = (u32 *)azx_dev->bdl.area;
1386         err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
1387         if (err < 0)
1388                 goto error;
1389
1390         azx_setup_controller(chip, azx_dev);
1391         dsp_unlock(azx_dev);
1392         return azx_dev->stream_tag;
1393
1394  error:
1395         chip->ops->dma_free_pages(chip, bufp);
1396  err_alloc:
1397         spin_lock_irq(&chip->reg_lock);
1398         if (azx_dev->opened)
1399                 *azx_dev = chip->saved_azx_dev;
1400         azx_dev->locked = 0;
1401         spin_unlock_irq(&chip->reg_lock);
1402  unlock:
1403         dsp_unlock(azx_dev);
1404         return err;
1405 }
1406
1407 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
1408 {
1409         struct azx *chip = bus->private_data;
1410         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1411
1412         if (start)
1413                 azx_stream_start(chip, azx_dev);
1414         else
1415                 azx_stream_stop(chip, azx_dev);
1416         azx_dev->running = start;
1417 }
1418
1419 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1420                                  struct snd_dma_buffer *dmab)
1421 {
1422         struct azx *chip = bus->private_data;
1423         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1424
1425         if (!dmab->area || !azx_dev->locked)
1426                 return;
1427
1428         dsp_lock(azx_dev);
1429         /* reset BDL address */
1430         azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1431         azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1432         azx_sd_writel(chip, azx_dev, SD_CTL, 0);
1433         azx_dev->bufsize = 0;
1434         azx_dev->period_bytes = 0;
1435         azx_dev->format_val = 0;
1436
1437         chip->ops->dma_free_pages(chip, dmab);
1438         dmab->area = NULL;
1439
1440         spin_lock_irq(&chip->reg_lock);
1441         if (azx_dev->opened)
1442                 *azx_dev = chip->saved_azx_dev;
1443         azx_dev->locked = 0;
1444         spin_unlock_irq(&chip->reg_lock);
1445         dsp_unlock(azx_dev);
1446 }
1447 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1448
1449 int azx_alloc_stream_pages(struct azx *chip)
1450 {
1451         int i, err;
1452         struct snd_card *card = chip->card;
1453
1454         for (i = 0; i < chip->num_streams; i++) {
1455                 dsp_lock_init(&chip->azx_dev[i]);
1456                 /* allocate memory for the BDL for each stream */
1457                 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
1458                                                  BDL_SIZE,
1459                                                  &chip->azx_dev[i].bdl);
1460                 if (err < 0) {
1461                         dev_err(card->dev, "cannot allocate BDL\n");
1462                         return -ENOMEM;
1463                 }
1464         }
1465         /* allocate memory for the position buffer */
1466         err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
1467                                          chip->num_streams * 8, &chip->posbuf);
1468         if (err < 0) {
1469                 dev_err(card->dev, "cannot allocate posbuf\n");
1470                 return -ENOMEM;
1471         }
1472
1473         /* allocate CORB/RIRB */
1474         err = azx_alloc_cmd_io(chip);
1475         if (err < 0)
1476                 return err;
1477         return 0;
1478 }
1479 EXPORT_SYMBOL_GPL(azx_alloc_stream_pages);
1480
1481 void azx_free_stream_pages(struct azx *chip)
1482 {
1483         int i;
1484         if (chip->azx_dev) {
1485                 for (i = 0; i < chip->num_streams; i++)
1486                         if (chip->azx_dev[i].bdl.area)
1487                                 chip->ops->dma_free_pages(
1488                                         chip, &chip->azx_dev[i].bdl);
1489         }
1490         if (chip->rb.area)
1491                 chip->ops->dma_free_pages(chip, &chip->rb);
1492         if (chip->posbuf.area)
1493                 chip->ops->dma_free_pages(chip, &chip->posbuf);
1494 }
1495 EXPORT_SYMBOL_GPL(azx_free_stream_pages);
1496
1497 /*
1498  * Lowlevel interface
1499  */
1500
1501 /* enter link reset */
1502 void azx_enter_link_reset(struct azx *chip)
1503 {
1504         unsigned long timeout;
1505
1506         /* reset controller */
1507         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_RESET);
1508
1509         timeout = jiffies + msecs_to_jiffies(100);
1510         while ((azx_readb(chip, GCTL) & AZX_GCTL_RESET) &&
1511                         time_before(jiffies, timeout))
1512                 usleep_range(500, 1000);
1513 }
1514 EXPORT_SYMBOL_GPL(azx_enter_link_reset);
1515
1516 /* exit link reset */
1517 static void azx_exit_link_reset(struct azx *chip)
1518 {
1519         unsigned long timeout;
1520
1521         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | AZX_GCTL_RESET);
1522
1523         timeout = jiffies + msecs_to_jiffies(100);
1524         while (!azx_readb(chip, GCTL) &&
1525                         time_before(jiffies, timeout))
1526                 usleep_range(500, 1000);
1527 }
1528
1529 /* reset codec link */
1530 static int azx_reset(struct azx *chip, bool full_reset)
1531 {
1532         if (!full_reset)
1533                 goto __skip;
1534
1535         /* clear STATESTS */
1536         azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1537
1538         /* reset controller */
1539         azx_enter_link_reset(chip);
1540
1541         /* delay for >= 100us for codec PLL to settle per spec
1542          * Rev 0.9 section 5.5.1
1543          */
1544         usleep_range(500, 1000);
1545
1546         /* Bring controller out of reset */
1547         azx_exit_link_reset(chip);
1548
1549         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1550         usleep_range(1000, 1200);
1551
1552       __skip:
1553         /* check to see if controller is ready */
1554         if (!azx_readb(chip, GCTL)) {
1555                 dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n");
1556                 return -EBUSY;
1557         }
1558
1559         /* Accept unsolicited responses */
1560         if (!chip->single_cmd)
1561                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1562                            AZX_GCTL_UNSOL);
1563
1564         /* detect codecs */
1565         if (!chip->codec_mask) {
1566                 chip->codec_mask = azx_readw(chip, STATESTS);
1567                 dev_dbg(chip->card->dev, "codec_mask = 0x%x\n",
1568                         chip->codec_mask);
1569         }
1570
1571         return 0;
1572 }
1573
1574 /* enable interrupts */
1575 static void azx_int_enable(struct azx *chip)
1576 {
1577         /* enable controller CIE and GIE */
1578         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1579                    AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
1580 }
1581
1582 /* disable interrupts */
1583 static void azx_int_disable(struct azx *chip)
1584 {
1585         int i;
1586
1587         /* disable interrupts in stream descriptor */
1588         for (i = 0; i < chip->num_streams; i++) {
1589                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1590                 azx_sd_writeb(chip, azx_dev, SD_CTL,
1591                               azx_sd_readb(chip, azx_dev, SD_CTL) &
1592                                         ~SD_INT_MASK);
1593         }
1594
1595         /* disable SIE for all streams */
1596         azx_writeb(chip, INTCTL, 0);
1597
1598         /* disable controller CIE and GIE */
1599         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1600                    ~(AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN));
1601 }
1602
1603 /* clear interrupts */
1604 static void azx_int_clear(struct azx *chip)
1605 {
1606         int i;
1607
1608         /* clear stream status */
1609         for (i = 0; i < chip->num_streams; i++) {
1610                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1611                 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
1612         }
1613
1614         /* clear STATESTS */
1615         azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1616
1617         /* clear rirb status */
1618         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1619
1620         /* clear int status */
1621         azx_writel(chip, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
1622 }
1623
1624 /*
1625  * reset and start the controller registers
1626  */
1627 void azx_init_chip(struct azx *chip, bool full_reset)
1628 {
1629         if (chip->initialized)
1630                 return;
1631
1632         /* reset controller */
1633         azx_reset(chip, full_reset);
1634
1635         /* initialize interrupts */
1636         azx_int_clear(chip);
1637         azx_int_enable(chip);
1638
1639         /* initialize the codec command I/O */
1640         if (!chip->single_cmd)
1641                 azx_init_cmd_io(chip);
1642
1643         /* program the position buffer */
1644         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1645         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1646
1647         chip->initialized = 1;
1648 }
1649 EXPORT_SYMBOL_GPL(azx_init_chip);
1650
1651 void azx_stop_chip(struct azx *chip)
1652 {
1653         if (!chip->initialized)
1654                 return;
1655
1656         /* disable interrupts */
1657         azx_int_disable(chip);
1658         azx_int_clear(chip);
1659
1660         /* disable CORB/RIRB */
1661         azx_free_cmd_io(chip);
1662
1663         /* disable position buffer */
1664         azx_writel(chip, DPLBASE, 0);
1665         azx_writel(chip, DPUBASE, 0);
1666
1667         chip->initialized = 0;
1668 }
1669 EXPORT_SYMBOL_GPL(azx_stop_chip);
1670
1671 /*
1672  * interrupt handler
1673  */
1674 irqreturn_t azx_interrupt(int irq, void *dev_id)
1675 {
1676         struct azx *chip = dev_id;
1677         struct azx_dev *azx_dev;
1678         u32 status;
1679         u8 sd_status;
1680         int i;
1681
1682 #ifdef CONFIG_PM
1683         if (azx_has_pm_runtime(chip))
1684                 if (!pm_runtime_active(chip->card->dev))
1685                         return IRQ_NONE;
1686 #endif
1687
1688         spin_lock(&chip->reg_lock);
1689
1690         if (chip->disabled) {
1691                 spin_unlock(&chip->reg_lock);
1692                 return IRQ_NONE;
1693         }
1694
1695         status = azx_readl(chip, INTSTS);
1696         if (status == 0 || status == 0xffffffff) {
1697                 spin_unlock(&chip->reg_lock);
1698                 return IRQ_NONE;
1699         }
1700
1701         for (i = 0; i < chip->num_streams; i++) {
1702                 azx_dev = &chip->azx_dev[i];
1703                 if (status & azx_dev->sd_int_sta_mask) {
1704                         sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
1705                         azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
1706                         if (!azx_dev->substream || !azx_dev->running ||
1707                             !(sd_status & SD_INT_COMPLETE))
1708                                 continue;
1709                         /* check whether this IRQ is really acceptable */
1710                         if (!chip->ops->position_check ||
1711                             chip->ops->position_check(chip, azx_dev)) {
1712                                 spin_unlock(&chip->reg_lock);
1713                                 snd_pcm_period_elapsed(azx_dev->substream);
1714                                 spin_lock(&chip->reg_lock);
1715                         }
1716                 }
1717         }
1718
1719         /* clear rirb int */
1720         status = azx_readb(chip, RIRBSTS);
1721         if (status & RIRB_INT_MASK) {
1722                 if (status & RIRB_INT_RESPONSE) {
1723                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1724                                 udelay(80);
1725                         azx_update_rirb(chip);
1726                 }
1727                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1728         }
1729
1730         spin_unlock(&chip->reg_lock);
1731
1732         return IRQ_HANDLED;
1733 }
1734 EXPORT_SYMBOL_GPL(azx_interrupt);
1735
1736 /*
1737  * Codec initerface
1738  */
1739
1740 /*
1741  * Probe the given codec address
1742  */
1743 static int probe_codec(struct azx *chip, int addr)
1744 {
1745         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1746                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1747         unsigned int res;
1748
1749         mutex_lock(&chip->bus->cmd_mutex);
1750         chip->probing = 1;
1751         azx_send_cmd(chip->bus, cmd);
1752         res = azx_get_response(chip->bus, addr);
1753         chip->probing = 0;
1754         mutex_unlock(&chip->bus->cmd_mutex);
1755         if (res == -1)
1756                 return -EIO;
1757         dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1758         return 0;
1759 }
1760
1761 static void azx_bus_reset(struct hda_bus *bus)
1762 {
1763         struct azx *chip = bus->private_data;
1764
1765         bus->in_reset = 1;
1766         azx_stop_chip(chip);
1767         azx_init_chip(chip, true);
1768 #ifdef CONFIG_PM
1769         if (chip->initialized) {
1770                 struct azx_pcm *p;
1771                 list_for_each_entry(p, &chip->pcm_list, list)
1772                         snd_pcm_suspend_all(p->pcm);
1773                 snd_hda_suspend(chip->bus);
1774                 snd_hda_resume(chip->bus);
1775         }
1776 #endif
1777         bus->in_reset = 0;
1778 }
1779
1780 #ifdef CONFIG_PM
1781 /* power-up/down the controller */
1782 static void azx_power_notify(struct hda_bus *bus, bool power_up)
1783 {
1784         struct azx *chip = bus->private_data;
1785
1786         if (!azx_has_pm_runtime(chip))
1787                 return;
1788
1789         if (power_up)
1790                 pm_runtime_get_sync(chip->card->dev);
1791         else
1792                 pm_runtime_put_sync(chip->card->dev);
1793 }
1794 #endif
1795
1796 static int get_jackpoll_interval(struct azx *chip)
1797 {
1798         int i;
1799         unsigned int j;
1800
1801         if (!chip->jackpoll_ms)
1802                 return 0;
1803
1804         i = chip->jackpoll_ms[chip->dev_index];
1805         if (i == 0)
1806                 return 0;
1807         if (i < 50 || i > 60000)
1808                 j = 0;
1809         else
1810                 j = msecs_to_jiffies(i);
1811         if (j == 0)
1812                 dev_warn(chip->card->dev,
1813                          "jackpoll_ms value out of range: %d\n", i);
1814         return j;
1815 }
1816
1817 static struct hda_bus_ops bus_ops = {
1818         .command = azx_send_cmd,
1819         .get_response = azx_get_response,
1820         .attach_pcm = azx_attach_pcm_stream,
1821         .bus_reset = azx_bus_reset,
1822 #ifdef CONFIG_PM
1823         .pm_notify = azx_power_notify,
1824 #endif
1825 #ifdef CONFIG_SND_HDA_DSP_LOADER
1826         .load_dsp_prepare = azx_load_dsp_prepare,
1827         .load_dsp_trigger = azx_load_dsp_trigger,
1828         .load_dsp_cleanup = azx_load_dsp_cleanup,
1829 #endif
1830 };
1831
1832 /* HD-audio bus initialization */
1833 int azx_bus_create(struct azx *chip, const char *model, int *power_save_to)
1834 {
1835         struct hda_bus *bus;
1836         int err;
1837
1838         err = snd_hda_bus_new(chip->card, &bus);
1839         if (err < 0)
1840                 return err;
1841
1842         chip->bus = bus;
1843         bus->private_data = chip;
1844         bus->pci = chip->pci;
1845         bus->modelname = model;
1846         bus->ops = bus_ops;
1847 #ifdef CONFIG_PM
1848         bus->power_save = power_save_to;
1849 #endif
1850
1851         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1852                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1853                 bus->needs_damn_long_delay = 1;
1854         }
1855
1856         /* AMD chipsets often cause the communication stalls upon certain
1857          * sequence like the pin-detection.  It seems that forcing the synced
1858          * access works around the stall.  Grrr...
1859          */
1860         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1861                 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1862                 bus->sync_write = 1;
1863                 bus->allow_bus_reset = 1;
1864         }
1865
1866         return 0;
1867 }
1868 EXPORT_SYMBOL_GPL(azx_bus_create);
1869
1870 /* Probe codecs */
1871 int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
1872 {
1873         struct hda_bus *bus = chip->bus;
1874         int c, codecs, err;
1875
1876         codecs = 0;
1877         if (!max_slots)
1878                 max_slots = AZX_DEFAULT_CODECS;
1879
1880         /* First try to probe all given codec slots */
1881         for (c = 0; c < max_slots; c++) {
1882                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1883                         if (probe_codec(chip, c) < 0) {
1884                                 /* Some BIOSen give you wrong codec addresses
1885                                  * that don't exist
1886                                  */
1887                                 dev_warn(chip->card->dev,
1888                                          "Codec #%d probe error; disabling it...\n", c);
1889                                 chip->codec_mask &= ~(1 << c);
1890                                 /* More badly, accessing to a non-existing
1891                                  * codec often screws up the controller chip,
1892                                  * and disturbs the further communications.
1893                                  * Thus if an error occurs during probing,
1894                                  * better to reset the controller chip to
1895                                  * get back to the sanity state.
1896                                  */
1897                                 azx_stop_chip(chip);
1898                                 azx_init_chip(chip, true);
1899                         }
1900                 }
1901         }
1902
1903         /* Then create codec instances */
1904         for (c = 0; c < max_slots; c++) {
1905                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1906                         struct hda_codec *codec;
1907                         err = snd_hda_codec_new(bus, c, &codec);
1908                         if (err < 0)
1909                                 continue;
1910                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1911                         codec->beep_mode = chip->beep_mode;
1912                         codecs++;
1913                 }
1914         }
1915         if (!codecs) {
1916                 dev_err(chip->card->dev, "no codecs initialized\n");
1917                 return -ENXIO;
1918         }
1919         return 0;
1920 }
1921 EXPORT_SYMBOL_GPL(azx_probe_codecs);
1922
1923 /* configure each codec instance */
1924 int azx_codec_configure(struct azx *chip)
1925 {
1926         struct hda_codec *codec;
1927         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1928                 snd_hda_codec_configure(codec);
1929         }
1930         return 0;
1931 }
1932 EXPORT_SYMBOL_GPL(azx_codec_configure);
1933
1934
1935 static bool is_input_stream(struct azx *chip, unsigned char index)
1936 {
1937         return (index >= chip->capture_index_offset &&
1938                 index < chip->capture_index_offset + chip->capture_streams);
1939 }
1940
1941 /* initialize SD streams */
1942 int azx_init_stream(struct azx *chip)
1943 {
1944         int i;
1945         int in_stream_tag = 0;
1946         int out_stream_tag = 0;
1947
1948         /* initialize each stream (aka device)
1949          * assign the starting bdl address to each stream (device)
1950          * and initialize
1951          */
1952         for (i = 0; i < chip->num_streams; i++) {
1953                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1954                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1955                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1956                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1957                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1958                 azx_dev->sd_int_sta_mask = 1 << i;
1959                 azx_dev->index = i;
1960
1961                 /* stream tag must be unique throughout
1962                  * the stream direction group,
1963                  * valid values 1...15
1964                  * use separate stream tag if the flag
1965                  * AZX_DCAPS_SEPARATE_STREAM_TAG is used
1966                  */
1967                 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
1968                         azx_dev->stream_tag =
1969                                 is_input_stream(chip, i) ?
1970                                 ++in_stream_tag :
1971                                 ++out_stream_tag;
1972                 else
1973                         azx_dev->stream_tag = i + 1;
1974         }
1975
1976         return 0;
1977 }
1978 EXPORT_SYMBOL_GPL(azx_init_stream);
1979
1980 /*
1981  * reboot notifier for hang-up problem at power-down
1982  */
1983 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
1984 {
1985         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
1986         snd_hda_bus_reboot_notify(chip->bus);
1987         azx_stop_chip(chip);
1988         return NOTIFY_OK;
1989 }
1990
1991 void azx_notifier_register(struct azx *chip)
1992 {
1993         chip->reboot_notifier.notifier_call = azx_halt;
1994         register_reboot_notifier(&chip->reboot_notifier);
1995 }
1996 EXPORT_SYMBOL_GPL(azx_notifier_register);
1997
1998 void azx_notifier_unregister(struct azx *chip)
1999 {
2000         if (chip->reboot_notifier.notifier_call)
2001                 unregister_reboot_notifier(&chip->reboot_notifier);
2002 }
2003 EXPORT_SYMBOL_GPL(azx_notifier_unregister);
2004
2005 MODULE_LICENSE("GPL");
2006 MODULE_DESCRIPTION("Common HDA driver functions");