1 /******************************************************************************
3 AudioScience HPI driver
4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of version 2 of the GNU General Public License as
8 published by the Free Software Foundation;
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 Hardware Programming Interface (HPI) for AudioScience ASI6200 series adapters.
20 These PCI bus adapters are based on the TI C6711 DSP.
23 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
26 HIDE_PCI_ASSERTS to show the PCI asserts
27 PROFILE_DSP2 get profile data from DSP2 if present (instead of DSP 1)
29 (C) Copyright AudioScience Inc. 1998-2003
30 *******************************************************************************/
31 #define SOURCEFILE_NAME "hpi6000.c"
33 #include "hpi_internal.h"
34 #include "hpimsginit.h"
40 #define HPI_HIF_BASE (0x00000200) /* start of C67xx internal RAM */
41 #define HPI_HIF_ADDR(member) \
42 (HPI_HIF_BASE + offsetof(struct hpi_hif_6000, member))
43 #define HPI_HIF_ERROR_MASK 0x4000
45 /* HPI6000 specific error codes */
47 #define HPI6000_ERROR_BASE 900
48 #define HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT 901
49 #define HPI6000_ERROR_MSG_RESP_SEND_MSG_ACK 902
50 #define HPI6000_ERROR_MSG_RESP_GET_RESP_ACK 903
51 #define HPI6000_ERROR_MSG_GET_ADR 904
52 #define HPI6000_ERROR_RESP_GET_ADR 905
53 #define HPI6000_ERROR_MSG_RESP_BLOCKWRITE32 906
54 #define HPI6000_ERROR_MSG_RESP_BLOCKREAD32 907
55 #define HPI6000_ERROR_MSG_INVALID_DSP_INDEX 908
56 #define HPI6000_ERROR_CONTROL_CACHE_PARAMS 909
58 #define HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT 911
59 #define HPI6000_ERROR_SEND_DATA_ACK 912
60 #define HPI6000_ERROR_SEND_DATA_ADR 913
61 #define HPI6000_ERROR_SEND_DATA_TIMEOUT 914
62 #define HPI6000_ERROR_SEND_DATA_CMD 915
63 #define HPI6000_ERROR_SEND_DATA_WRITE 916
64 #define HPI6000_ERROR_SEND_DATA_IDLECMD 917
65 #define HPI6000_ERROR_SEND_DATA_VERIFY 918
67 #define HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT 921
68 #define HPI6000_ERROR_GET_DATA_ACK 922
69 #define HPI6000_ERROR_GET_DATA_CMD 923
70 #define HPI6000_ERROR_GET_DATA_READ 924
71 #define HPI6000_ERROR_GET_DATA_IDLECMD 925
73 #define HPI6000_ERROR_CONTROL_CACHE_ADDRLEN 951
74 #define HPI6000_ERROR_CONTROL_CACHE_READ 952
75 #define HPI6000_ERROR_CONTROL_CACHE_FLUSH 953
77 #define HPI6000_ERROR_MSG_RESP_GETRESPCMD 961
78 #define HPI6000_ERROR_MSG_RESP_IDLECMD 962
79 #define HPI6000_ERROR_MSG_RESP_BLOCKVERIFY32 963
81 /* adapter init errors */
82 #define HPI6000_ERROR_UNHANDLED_SUBSYS_ID 930
84 /* can't access PCI2040 */
85 #define HPI6000_ERROR_INIT_PCI2040 931
86 /* can't access DSP HPI i/f */
87 #define HPI6000_ERROR_INIT_DSPHPI 932
88 /* can't access internal DSP memory */
89 #define HPI6000_ERROR_INIT_DSPINTMEM 933
90 /* can't access SDRAM - test#1 */
91 #define HPI6000_ERROR_INIT_SDRAM1 934
92 /* can't access SDRAM - test#2 */
93 #define HPI6000_ERROR_INIT_SDRAM2 935
95 #define HPI6000_ERROR_INIT_VERIFY 938
97 #define HPI6000_ERROR_INIT_NOACK 939
99 #define HPI6000_ERROR_INIT_PLDTEST1 941
100 #define HPI6000_ERROR_INIT_PLDTEST2 942
104 #define HIDE_PCI_ASSERTS
107 /* for PCI2040 i/f chip */
108 /* HPI CSR registers */
109 /* word offsets from CSR base */
110 /* use when io addresses defined as u32 * */
112 #define INTERRUPT_EVENT_SET 0
113 #define INTERRUPT_EVENT_CLEAR 1
114 #define INTERRUPT_MASK_SET 2
115 #define INTERRUPT_MASK_CLEAR 3
116 #define HPI_ERROR_REPORT 4
118 #define HPI_DATA_WIDTH 6
121 /* HPI registers, spaced 8K bytes = 2K words apart */
122 #define DSP_SPACING 0x800
124 #define CONTROL 0x0000
125 #define ADDRESS 0x0200
126 #define DATA_AUTOINC 0x0400
129 #define TIMEOUT 500000
132 __iomem u32 *prHPI_control;
133 __iomem u32 *prHPI_address;
134 __iomem u32 *prHPI_data;
135 __iomem u32 *prHPI_data_auto_inc;
136 char c_dsp_rev; /*A, B */
137 u32 control_cache_address_on_dsp;
138 u32 control_cache_length_on_dsp;
139 struct hpi_adapter_obj *pa_parent_adapter;
143 __iomem u32 *dw2040_HPICSR;
144 __iomem u32 *dw2040_HPIDSP;
147 struct dsp_obj ado[MAX_DSPS];
149 u32 message_buffer_address_on_dsp;
150 u32 response_buffer_address_on_dsp;
151 u32 pCI2040HPI_error_count;
153 struct hpi_control_cache_single control_cache[HPI_NMIXER_CONTROLS];
154 struct hpi_control_cache *p_cache;
157 static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
158 u16 dsp_index, u32 hpi_address, u32 *source, u32 count);
159 static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
160 u16 dsp_index, u32 hpi_address, u32 *dest, u32 count);
162 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
163 u32 *pos_error_code);
164 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
169 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
170 struct hpi_message *phm);
171 static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
172 u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr);
174 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
175 struct hpi_response *phr);
177 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
180 static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
181 u16 dsp_index, u32 host_cmd);
183 static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo);
185 static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
186 struct hpi_message *phm, struct hpi_response *phr);
188 static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
189 struct hpi_message *phm, struct hpi_response *phr);
191 static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data);
193 static u32 hpi_read_word(struct dsp_obj *pdo, u32 address);
195 static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
198 static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
201 static void subsys_create_adapter(struct hpi_message *phm,
202 struct hpi_response *phr);
204 static void subsys_delete_adapter(struct hpi_message *phm,
205 struct hpi_response *phr);
207 static void adapter_get_asserts(struct hpi_adapter_obj *pao,
208 struct hpi_message *phm, struct hpi_response *phr);
210 static short create_adapter_obj(struct hpi_adapter_obj *pao,
211 u32 *pos_error_code);
215 static u16 gw_pci_read_asserts; /* used to count PCI2040 errors */
216 static u16 gw_pci_write_asserts; /* used to count PCI2040 errors */
218 static void subsys_message(struct hpi_message *phm, struct hpi_response *phr)
221 switch (phm->function) {
222 case HPI_SUBSYS_OPEN:
223 case HPI_SUBSYS_CLOSE:
224 case HPI_SUBSYS_GET_INFO:
225 case HPI_SUBSYS_DRIVER_UNLOAD:
226 case HPI_SUBSYS_DRIVER_LOAD:
227 case HPI_SUBSYS_FIND_ADAPTERS:
228 /* messages that should not get here */
229 phr->error = HPI_ERROR_UNIMPLEMENTED;
231 case HPI_SUBSYS_CREATE_ADAPTER:
232 subsys_create_adapter(phm, phr);
234 case HPI_SUBSYS_DELETE_ADAPTER:
235 subsys_delete_adapter(phm, phr);
238 phr->error = HPI_ERROR_INVALID_FUNC;
243 static void control_message(struct hpi_adapter_obj *pao,
244 struct hpi_message *phm, struct hpi_response *phr)
247 switch (phm->function) {
248 case HPI_CONTROL_GET_STATE:
249 if (pao->has_control_cache) {
251 err = hpi6000_update_control_cache(pao, phm);
258 if (hpi_check_control_cache(((struct hpi_hw_obj *)
259 pao->priv)->p_cache, phm,
263 hw_message(pao, phm, phr);
265 case HPI_CONTROL_GET_INFO:
266 hw_message(pao, phm, phr);
268 case HPI_CONTROL_SET_STATE:
269 hw_message(pao, phm, phr);
270 hpi_sync_control_cache(((struct hpi_hw_obj *)pao->priv)->
274 phr->error = HPI_ERROR_INVALID_FUNC;
279 static void adapter_message(struct hpi_adapter_obj *pao,
280 struct hpi_message *phm, struct hpi_response *phr)
282 switch (phm->function) {
283 case HPI_ADAPTER_GET_INFO:
284 hw_message(pao, phm, phr);
286 case HPI_ADAPTER_GET_ASSERT:
287 adapter_get_asserts(pao, phm, phr);
289 case HPI_ADAPTER_OPEN:
290 case HPI_ADAPTER_CLOSE:
291 case HPI_ADAPTER_TEST_ASSERT:
292 case HPI_ADAPTER_SELFTEST:
293 case HPI_ADAPTER_GET_MODE:
294 case HPI_ADAPTER_SET_MODE:
295 case HPI_ADAPTER_FIND_OBJECT:
296 case HPI_ADAPTER_GET_PROPERTY:
297 case HPI_ADAPTER_SET_PROPERTY:
298 case HPI_ADAPTER_ENUM_PROPERTY:
299 hw_message(pao, phm, phr);
302 phr->error = HPI_ERROR_INVALID_FUNC;
307 static void outstream_message(struct hpi_adapter_obj *pao,
308 struct hpi_message *phm, struct hpi_response *phr)
310 switch (phm->function) {
311 case HPI_OSTREAM_HOSTBUFFER_ALLOC:
312 case HPI_OSTREAM_HOSTBUFFER_FREE:
313 /* Don't let these messages go to the HW function because
314 * they're called without allocating the spinlock.
315 * For the HPI6000 adapters the HW would return
316 * HPI_ERROR_INVALID_FUNC anyway.
318 phr->error = HPI_ERROR_INVALID_FUNC;
321 hw_message(pao, phm, phr);
326 static void instream_message(struct hpi_adapter_obj *pao,
327 struct hpi_message *phm, struct hpi_response *phr)
330 switch (phm->function) {
331 case HPI_ISTREAM_HOSTBUFFER_ALLOC:
332 case HPI_ISTREAM_HOSTBUFFER_FREE:
333 /* Don't let these messages go to the HW function because
334 * they're called without allocating the spinlock.
335 * For the HPI6000 adapters the HW would return
336 * HPI_ERROR_INVALID_FUNC anyway.
338 phr->error = HPI_ERROR_INVALID_FUNC;
341 hw_message(pao, phm, phr);
346 /************************************************************************/
348 * Entry point from HPIMAN
349 * All calls to the HPI start here
351 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
353 struct hpi_adapter_obj *pao = NULL;
355 /* subsytem messages get executed by every HPI. */
356 /* All other messages are ignored unless the adapter index matches */
357 /* an adapter in the HPI */
358 HPI_DEBUG_LOG(DEBUG, "O %d,F %x\n", phm->object, phm->function);
360 /* if Dsp has crashed then do not communicate with it any more */
361 if (phm->object != HPI_OBJ_SUBSYSTEM) {
362 pao = hpi_find_adapter(phm->adapter_index);
365 " %d,%d refused, for another HPI?\n",
366 phm->object, phm->function);
370 if (pao->dsp_crashed >= 10) {
371 hpi_init_response(phr, phm->object, phm->function,
372 HPI_ERROR_DSP_HARDWARE);
373 HPI_DEBUG_LOG(DEBUG, " %d,%d dsp crashed.\n",
374 phm->object, phm->function);
378 /* Init default response including the size field */
379 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
380 hpi_init_response(phr, phm->object, phm->function,
381 HPI_ERROR_PROCESSING_MESSAGE);
384 case HPI_TYPE_MESSAGE:
385 switch (phm->object) {
386 case HPI_OBJ_SUBSYSTEM:
387 subsys_message(phm, phr);
390 case HPI_OBJ_ADAPTER:
392 sizeof(struct hpi_response_header) +
393 sizeof(struct hpi_adapter_res);
394 adapter_message(pao, phm, phr);
397 case HPI_OBJ_CONTROL:
398 control_message(pao, phm, phr);
401 case HPI_OBJ_OSTREAM:
402 outstream_message(pao, phm, phr);
405 case HPI_OBJ_ISTREAM:
406 instream_message(pao, phm, phr);
410 hw_message(pao, phm, phr);
416 phr->error = HPI_ERROR_INVALID_TYPE;
421 /************************************************************************/
424 /* create an adapter object and initialise it based on resource information
425 * passed in in the message
426 * NOTE - you cannot use this function AND the FindAdapters function at the
427 * same time, the application must use only one of them to get the adapters
429 static void subsys_create_adapter(struct hpi_message *phm,
430 struct hpi_response *phr)
432 /* create temp adapter obj, because we don't know what index yet */
433 struct hpi_adapter_obj ao;
434 struct hpi_adapter_obj *pao;
439 HPI_DEBUG_LOG(VERBOSE, "subsys_create_adapter\n");
441 memset(&ao, 0, sizeof(ao));
443 /* this HPI only creates adapters for TI/PCI2040 based devices */
444 if (phm->u.s.resource.bus_type != HPI_BUS_PCI)
446 if (phm->u.s.resource.r.pci->vendor_id != HPI_PCI_VENDOR_ID_TI)
448 if (phm->u.s.resource.r.pci->device_id != HPI_PCI_DEV_ID_PCI2040)
451 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
453 HPI_DEBUG_LOG(ERROR, "cant get mem for adapter object\n");
454 phr->error = HPI_ERROR_MEMORY_ALLOC;
458 /* create the adapter object based on the resource information */
459 /*? memcpy(&ao.Pci,&phm->u.s.Resource.r.Pci,sizeof(ao.Pci)); */
460 ao.pci = *phm->u.s.resource.r.pci;
462 error = create_adapter_obj(&ao, &os_error_code);
464 error = hpi_add_adapter(&ao);
466 phr->u.s.data = os_error_code;
471 /* need to update paParentAdapter */
472 pao = hpi_find_adapter(ao.index);
474 /* We just added this adapter, why can't we find it!? */
475 HPI_DEBUG_LOG(ERROR, "lost adapter after boot\n");
480 for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
481 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
482 phw->ado[dsp_index].pa_parent_adapter = pao;
485 phr->u.s.aw_adapter_list[ao.index] = ao.adapter_type;
486 phr->u.s.adapter_index = ao.index;
487 phr->u.s.num_adapters++;
491 static void subsys_delete_adapter(struct hpi_message *phm,
492 struct hpi_response *phr)
494 struct hpi_adapter_obj *pao = NULL;
495 struct hpi_hw_obj *phw;
497 pao = hpi_find_adapter(phm->adapter_index);
501 phw = (struct hpi_hw_obj *)pao->priv;
503 if (pao->has_control_cache)
504 hpi_free_control_cache(phw->p_cache);
506 hpi_delete_adapter(pao);
512 /* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */
513 static short create_adapter_obj(struct hpi_adapter_obj *pao,
516 short boot_error = 0;
518 u32 control_cache_size = 0;
519 u32 control_cache_count = 0;
520 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
522 /* init error reporting */
523 pao->dsp_crashed = 0;
525 /* The PCI2040 has the following address map */
526 /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */
527 /* BAR1 - 32K = HPI registers on DSP */
528 phw->dw2040_HPICSR = pao->pci.ap_mem_base[0];
529 phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1];
530 HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR,
533 /* set addresses for the possible DSP HPI interfaces */
534 for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
535 phw->ado[dsp_index].prHPI_control =
536 phw->dw2040_HPIDSP + (CONTROL +
537 DSP_SPACING * dsp_index);
539 phw->ado[dsp_index].prHPI_address =
540 phw->dw2040_HPIDSP + (ADDRESS +
541 DSP_SPACING * dsp_index);
542 phw->ado[dsp_index].prHPI_data =
543 phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index);
545 phw->ado[dsp_index].prHPI_data_auto_inc =
546 phw->dw2040_HPIDSP + (DATA_AUTOINC +
547 DSP_SPACING * dsp_index);
549 HPI_DEBUG_LOG(VERBOSE, "ctl %p, adr %p, dat %p, dat++ %p\n",
550 phw->ado[dsp_index].prHPI_control,
551 phw->ado[dsp_index].prHPI_address,
552 phw->ado[dsp_index].prHPI_data,
553 phw->ado[dsp_index].prHPI_data_auto_inc);
555 phw->ado[dsp_index].pa_parent_adapter = pao;
558 phw->pCI2040HPI_error_count = 0;
559 pao->has_control_cache = 0;
561 /* Set the default number of DSPs on this card */
562 /* This is (conditionally) adjusted after bootloading */
563 /* of the first DSP in the bootload section. */
566 boot_error = hpi6000_adapter_boot_load_dsp(pao, pos_error_code);
570 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
572 phw->message_buffer_address_on_dsp = 0L;
573 phw->response_buffer_address_on_dsp = 0L;
575 /* get info about the adapter by asking the adapter */
576 /* send a HPI_ADAPTER_GET_INFO message */
578 struct hpi_message hM;
579 struct hpi_response hR0; /* response from DSP 0 */
580 struct hpi_response hR1; /* response from DSP 1 */
583 HPI_DEBUG_LOG(VERBOSE, "send ADAPTER_GET_INFO\n");
584 memset(&hM, 0, sizeof(hM));
585 hM.type = HPI_TYPE_MESSAGE;
586 hM.size = sizeof(struct hpi_message);
587 hM.object = HPI_OBJ_ADAPTER;
588 hM.function = HPI_ADAPTER_GET_INFO;
589 hM.adapter_index = 0;
590 memset(&hR0, 0, sizeof(hR0));
591 memset(&hR1, 0, sizeof(hR1));
592 hR0.size = sizeof(hR0);
593 hR1.size = sizeof(hR1);
595 error = hpi6000_message_response_sequence(pao, 0, &hM, &hR0);
597 HPI_DEBUG_LOG(DEBUG, "message error %d\n", hR0.error);
600 if (phw->num_dsp == 2) {
601 error = hpi6000_message_response_sequence(pao, 1, &hM,
606 pao->adapter_type = hR0.u.a.adapter_type;
607 pao->index = hR0.u.a.adapter_index;
610 memset(&phw->control_cache[0], 0,
611 sizeof(struct hpi_control_cache_single) *
612 HPI_NMIXER_CONTROLS);
613 /* Read the control cache length to figure out if it is turned on */
615 hpi_read_word(&phw->ado[0],
616 HPI_HIF_ADDR(control_cache_size_in_bytes));
617 if (control_cache_size) {
618 control_cache_count =
619 hpi_read_word(&phw->ado[0],
620 HPI_HIF_ADDR(control_cache_count));
621 pao->has_control_cache = 1;
624 hpi_alloc_control_cache(control_cache_count,
625 control_cache_size, (struct hpi_control_cache_info *)
626 &phw->control_cache[0]
629 pao->has_control_cache = 0;
631 HPI_DEBUG_LOG(DEBUG, "get adapter info ASI%04X index %d\n",
632 pao->adapter_type, pao->index);
633 pao->open = 0; /* upon creation the adapter is closed */
637 /************************************************************************/
640 static void adapter_get_asserts(struct hpi_adapter_obj *pao,
641 struct hpi_message *phm, struct hpi_response *phr)
643 #ifndef HIDE_PCI_ASSERTS
644 /* if we have PCI2040 asserts then collect them */
645 if ((gw_pci_read_asserts > 0) || (gw_pci_write_asserts > 0)) {
646 phr->u.a.serial_number =
647 gw_pci_read_asserts * 100 + gw_pci_write_asserts;
648 phr->u.a.adapter_index = 1; /* assert count */
649 phr->u.a.adapter_type = -1; /* "dsp index" */
650 strcpy(phr->u.a.sz_adapter_assert, "PCI2040 error");
651 gw_pci_read_asserts = 0;
652 gw_pci_write_asserts = 0;
656 hw_message(pao, phm, phr); /*get DSP asserts */
661 /************************************************************************/
664 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
667 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
674 u32 test_addr = 0x80000000;
675 u32 test_data = 0x00000001;
676 u32 dw2040_reset = 0;
679 u32 adapter_info = 0;
682 struct dsp_code dsp_code;
683 u16 boot_load_family = 0;
685 /* NOTE don't use wAdapterType in this routine. It is not setup yet */
687 switch (pao->pci.subsys_device_id) {
689 case 0x5110: /* ASI5100 revB or higher with C6711D */
690 case 0x5200: /* ASI5200 PC_ie version of ASI5100 */
693 boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x6200);
696 return HPI6000_ERROR_UNHANDLED_SUBSYS_ID;
699 /* reset all DSPs, indicate two DSPs are present
700 * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode
703 dw2040_reset = 0x0003000F;
704 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
706 /* read back register to make sure PCI2040 chip is functioning
707 * note that bits 4..15 are read-only and so should always return zero,
708 * even though we wrote 1 to them
710 for (i = 0; i < 1000; i++)
711 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
712 if (delay != dw2040_reset) {
713 HPI_DEBUG_LOG(ERROR, "INIT_PCI2040 %x %x\n", dw2040_reset,
715 return HPI6000_ERROR_INIT_PCI2040;
718 /* Indicate that DSP#0,1 is a C6X */
719 iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH);
720 /* set Bit30 and 29 - which will prevent Target aborts from being
721 * issued upon HPI or GP error
723 iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET);
725 /* isolate DSP HAD8 line from PCI2040 so that
726 * Little endian can be set by pullup
728 dw2040_reset = dw2040_reset & (~(endian << 3));
729 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
731 phw->ado[0].c_dsp_rev = 'B'; /* revB */
732 phw->ado[1].c_dsp_rev = 'B'; /* revB */
734 /*Take both DSPs out of reset, setting HAD8 to the correct Endian */
735 dw2040_reset = dw2040_reset & (~0x00000001); /* start DSP 0 */
736 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
737 dw2040_reset = dw2040_reset & (~0x00000002); /* start DSP 1 */
738 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
740 /* set HAD8 back to PCI2040, now that DSP set to little endian mode */
741 dw2040_reset = dw2040_reset & (~0x00000008);
742 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
743 /*delay to allow DSP to get going */
744 for (i = 0; i < 100; i++)
745 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
747 /* loop through all DSPs, downloading DSP code */
748 for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) {
749 struct dsp_obj *pdo = &phw->ado[dsp_index];
751 /* configure DSP so that we download code into the SRAM */
752 /* set control reg for little endian, HWOB=1 */
753 iowrite32(0x00010001, pdo->prHPI_control);
755 /* test access to the HPI address register (HPIA) */
756 test_data = 0x00000001;
757 for (j = 0; j < 32; j++) {
758 iowrite32(test_data, pdo->prHPI_address);
759 data = ioread32(pdo->prHPI_address);
760 if (data != test_data) {
761 HPI_DEBUG_LOG(ERROR, "INIT_DSPHPI %x %x %x\n",
762 test_data, data, dsp_index);
763 return HPI6000_ERROR_INIT_DSPHPI;
765 test_data = test_data << 1;
768 /* if C6713 the setup PLL to generate 225MHz from 25MHz.
769 * Since the PLLDIV1 read is sometimes wrong, even on a C6713,
770 * we're going to do this unconditionally
772 /* PLLDIV1 should have a value of 8000 after reset */
774 if (HpiReadWord(pdo,0x01B7C118) == 0x8000)
777 /* C6713 datasheet says we cannot program PLL from HPI,
778 * and indeed if we try to set the PLL multiply from the
779 * HPI, the PLL does not seem to lock,
780 * so we enable the PLL and use the default of x 7
783 hpi_write_word(pdo, 0x01B7C100, 0x0000);
784 for (i = 0; i < 100; i++)
785 delay = ioread32(phw->dw2040_HPICSR +
788 /* ** use default of PLL x7 ** */
789 /* EMIF = 225/3=75MHz */
790 hpi_write_word(pdo, 0x01B7C120, 0x8002);
792 hpi_write_word(pdo, 0x01B7C11C, 0x8001);
794 hpi_write_word(pdo, 0x01B7C118, 0x8000);
796 for (i = 0; i < 2000; i++)
797 delay = ioread32(phw->dw2040_HPICSR +
799 /* PLL not bypassed */
800 hpi_write_word(pdo, 0x01B7C100, 0x0001);
802 for (i = 0; i < 2000; i++)
803 delay = ioread32(phw->dw2040_HPICSR +
807 /* test r/w to internal DSP memory
808 * C6711 has L2 cache mapped to 0x0 when reset
810 * revB - because of bug 3.0.1 last HPI read
811 * (before HPI address issued) must be non-autoinc
813 /* test each bit in the 32bit word */
814 for (i = 0; i < 100; i++) {
815 test_addr = 0x00000000;
816 test_data = 0x00000001;
817 for (j = 0; j < 32; j++) {
818 hpi_write_word(pdo, test_addr + i, test_data);
819 data = hpi_read_word(pdo, test_addr + i);
820 if (data != test_data) {
822 "DSP mem %x %x %x %x\n",
823 test_addr + i, test_data,
826 return HPI6000_ERROR_INIT_DSPINTMEM;
828 test_data = test_data << 1;
832 /* memory map of ASI6200
833 00000000-0000FFFF 16Kx32 internal program
834 01800000-019FFFFF Internal peripheral
835 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz
836 90000000-9000FFFF CE1 Async peripherals:
844 3 CLK2EN = 1 CLKOUT2 enabled
845 4 CLK1EN = 0 CLKOUT1 disabled
846 5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT
848 7 NOHOLD = 1 external HOLD disabled
849 8 HOLDA = 0 HOLDA output is low
850 9 HOLD = 0 HOLD input is low
851 10 ARDY = 1 ARDY input is high
852 11 BUSREQ = 0 BUSREQ output is low
855 hpi_write_word(pdo, 0x01800000, 0x34A8);
857 /* EMIF CE0 setup - 2Mx32 Sync DRAM
864 7..4 MTYPE 0011 Sync DRAM 32bits
868 hpi_write_word(pdo, 0x01800008, 0x00000030);
870 /* EMIF SDRAM Extension
880 6-5 TWR = 2-1 = 01b (tWR = 10ns)
881 4 TRRD = 0b = 2 ECLK (tRRD = 14ns)
882 3-1 TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK)
883 1 CAS latency = 3 ECLK
884 (for Micron 2M32-7 operating at 100Mhz)
887 /* need to use this else DSP code crashes */
888 hpi_write_word(pdo, 0x01800020, 0x001BDF29);
890 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
893 29..28 SDRSZ 00 11 row address pins
894 27..26 SDCSZ 01 8 column address pins
895 25 RFEN 1 refersh enabled
902 /* need to use this else DSP code crashes */
903 hpi_write_word(pdo, 0x01800018, 0x47117000);
905 /* EMIF SDRAM Refresh Timing */
906 hpi_write_word(pdo, 0x0180001C, 0x00000410);
908 /*MIF CE1 setup - Async peripherals
909 @100MHz bus speed, each cycle is 10ns,
911 27..22 Wr strobe = 3 30ns
915 13..8 Rd strobe = 3 30ns
916 7..4 MTYPE 0010 Async 32bits
922 (1L << 28) | (3L << 22) | (1L << 20) | (1L <<
923 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L;
924 hpi_write_word(pdo, 0x01800004, cE1);
927 /* delay a little to allow SDRAM and DSP to "get going" */
929 for (i = 0; i < 1000; i++)
930 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
932 /* test access to SDRAM */
934 test_addr = 0x80000000;
935 test_data = 0x00000001;
936 /* test each bit in the 32bit word */
937 for (j = 0; j < 32; j++) {
938 hpi_write_word(pdo, test_addr, test_data);
939 data = hpi_read_word(pdo, test_addr);
940 if (data != test_data) {
942 "DSP dram %x %x %x %x\n",
943 test_addr, test_data, data,
946 return HPI6000_ERROR_INIT_SDRAM1;
948 test_data = test_data << 1;
950 /* test every Nth address in the DRAM */
951 #define DRAM_SIZE_WORDS 0x200000 /*2_mx32 */
952 #define DRAM_INC 1024
953 test_addr = 0x80000000;
955 for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
956 hpi_write_word(pdo, test_addr + i, test_data);
959 test_addr = 0x80000000;
961 for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
962 data = hpi_read_word(pdo, test_addr + i);
963 if (data != test_data) {
965 "DSP dram %x %x %x %x\n",
966 test_addr + i, test_data,
968 return HPI6000_ERROR_INIT_SDRAM2;
975 /* write the DSP code down into the DSPs memory */
976 /*HpiDspCode_Open(nBootLoadFamily,&DspCode,pdwOsErrorCode); */
977 dsp_code.ps_dev = pao->pci.p_os_data;
979 error = hpi_dsp_code_open(boot_load_family, &dsp_code,
991 error = hpi_dsp_code_read_word(&dsp_code, &length);
994 if (length == 0xFFFFFFFF)
995 break; /* end of code */
997 error = hpi_dsp_code_read_word(&dsp_code, &address);
1000 error = hpi_dsp_code_read_word(&dsp_code, &type);
1003 error = hpi_dsp_code_read_block(length, &dsp_code,
1007 error = hpi6000_dsp_block_write32(pao, (u16)dsp_index,
1008 address, pcode, length);
1014 hpi_dsp_code_close(&dsp_code);
1017 /* verify that code was written correctly */
1018 /* this time through, assume no errors in DSP code file/array */
1019 hpi_dsp_code_rewind(&dsp_code);
1026 hpi_dsp_code_read_word(&dsp_code, &length);
1027 if (length == 0xFFFFFFFF)
1028 break; /* end of code */
1030 hpi_dsp_code_read_word(&dsp_code, &address);
1031 hpi_dsp_code_read_word(&dsp_code, &type);
1032 hpi_dsp_code_read_block(length, &dsp_code, &pcode);
1034 for (i = 0; i < length; i++) {
1035 data = hpi_read_word(pdo, address);
1036 if (data != *pcode) {
1037 error = HPI6000_ERROR_INIT_VERIFY;
1038 HPI_DEBUG_LOG(ERROR,
1039 "DSP verify %x %x %x %x\n",
1040 address, *pcode, data,
1050 hpi_dsp_code_close(&dsp_code);
1054 /* zero out the hostmailbox */
1056 u32 address = HPI_HIF_ADDR(host_cmd);
1057 for (i = 0; i < 4; i++) {
1058 hpi_write_word(pdo, address, 0);
1062 /* write the DSP number into the hostmailbox */
1063 /* structure before starting the DSP */
1064 hpi_write_word(pdo, HPI_HIF_ADDR(dsp_number), dsp_index);
1066 /* write the DSP adapter Info into the */
1067 /* hostmailbox before starting the DSP */
1069 hpi_write_word(pdo, HPI_HIF_ADDR(adapter_info),
1072 /* step 3. Start code by sending interrupt */
1073 iowrite32(0x00030003, pdo->prHPI_control);
1074 for (i = 0; i < 10000; i++)
1075 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
1077 /* wait for a non-zero value in hostcmd -
1078 * indicating initialization is complete
1080 * Init could take a while if DSP checks SDRAM memory
1081 * Was 200000. Increased to 2000000 for ASI8801 so we
1082 * don't get 938 errors.
1087 read = hpi_read_word(pdo,
1088 HPI_HIF_ADDR(host_cmd));
1090 && hpi6000_check_PCI2040_error_flag(pao,
1095 /* The following is a workaround for bug #94:
1096 * Bluescreen on install and subsequent boots on a
1097 * DELL PowerEdge 600SC PC with 1.8GHz P4 and
1098 * ServerWorks chipset. Without this delay the system
1099 * locks up with a bluescreen (NOT GPF or pagefault).
1102 hpios_delay_micro_seconds(1000);
1105 return HPI6000_ERROR_INIT_NOACK;
1107 /* read the DSP adapter Info from the */
1108 /* hostmailbox structure after starting the DSP */
1109 if (dsp_index == 0) {
1110 /*u32 dwTestData=0; */
1115 HPI_HIF_ADDR(adapter_info));
1116 if (HPI_ADAPTER_FAMILY_ASI
1117 (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER
1119 HPI_ADAPTER_FAMILY_ASI(0x6200))
1120 /* all 6200 cards have this many DSPs */
1123 /* test that the PLD is programmed */
1124 /* and we can read/write 24bits */
1125 #define PLD_BASE_ADDRESS 0x90000000L /*for ASI6100/6200/8800 */
1127 switch (boot_load_family) {
1128 case HPI_ADAPTER_FAMILY_ASI(0x6200):
1129 /* ASI6100/6200 has 24bit path to FPGA */
1131 /* ASI5100 uses AX6 code, */
1132 /* but has no PLD r/w register to test */
1133 if (HPI_ADAPTER_FAMILY_ASI(pao->pci.
1134 subsys_device_id) ==
1135 HPI_ADAPTER_FAMILY_ASI(0x5100))
1137 /* ASI5200 uses AX6 code, */
1138 /* but has no PLD r/w register to test */
1139 if (HPI_ADAPTER_FAMILY_ASI(pao->pci.
1140 subsys_device_id) ==
1141 HPI_ADAPTER_FAMILY_ASI(0x5200))
1144 case HPI_ADAPTER_FAMILY_ASI(0x8800):
1145 /* ASI8800 has 16bit path to FPGA */
1149 test_data = 0xAAAAAA00L & mask;
1150 /* write to 24 bit Debug register (D31-D8) */
1151 hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
1152 read = hpi_read_word(pdo,
1153 PLD_BASE_ADDRESS + 4L) & mask;
1154 if (read != test_data) {
1155 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
1157 return HPI6000_ERROR_INIT_PLDTEST1;
1159 test_data = 0x55555500L & mask;
1160 hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
1161 read = hpi_read_word(pdo,
1162 PLD_BASE_ADDRESS + 4L) & mask;
1163 if (read != test_data) {
1164 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
1166 return HPI6000_ERROR_INIT_PLDTEST2;
1173 #define PCI_TIMEOUT 100
1175 static int hpi_set_address(struct dsp_obj *pdo, u32 address)
1177 u32 timeout = PCI_TIMEOUT;
1180 iowrite32(address, pdo->prHPI_address);
1181 } while (hpi6000_check_PCI2040_error_flag(pdo->pa_parent_adapter,
1191 /* write one word to the HPI port */
1192 static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data)
1194 if (hpi_set_address(pdo, address))
1196 iowrite32(data, pdo->prHPI_data);
1199 /* read one word from the HPI port */
1200 static u32 hpi_read_word(struct dsp_obj *pdo, u32 address)
1204 if (hpi_set_address(pdo, address))
1205 return 0; /*? no way to return error */
1207 /* take care of errata in revB DSP (2.0.1) */
1208 data = ioread32(pdo->prHPI_data);
1212 /* write a block of 32bit words to the DSP HPI port using auto-inc mode */
1213 static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
1216 u16 length16 = length - 1;
1221 if (hpi_set_address(pdo, address))
1224 iowrite32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
1226 /* take care of errata in revB DSP (2.0.1) */
1227 /* must end with non auto-inc */
1228 iowrite32(*(pdata + length - 1), pdo->prHPI_data);
1231 /** read a block of 32bit words from the DSP HPI port using auto-inc mode
1233 static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
1236 u16 length16 = length - 1;
1241 if (hpi_set_address(pdo, address))
1244 ioread32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
1246 /* take care of errata in revB DSP (2.0.1) */
1247 /* must end with non auto-inc */
1248 *(pdata + length - 1) = ioread32(pdo->prHPI_data);
1251 static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
1252 u16 dsp_index, u32 hpi_address, u32 *source, u32 count)
1254 struct dsp_obj *pdo =
1255 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1256 u32 time_out = PCI_TIMEOUT;
1257 int c6711_burst_size = 128;
1258 u32 local_hpi_address = hpi_address;
1259 int local_count = count;
1261 u32 *pdata = source;
1263 while (local_count) {
1264 if (local_count > c6711_burst_size)
1265 xfer_size = c6711_burst_size;
1267 xfer_size = local_count;
1269 time_out = PCI_TIMEOUT;
1271 hpi_write_block(pdo, local_hpi_address, pdata,
1273 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
1279 local_hpi_address += sizeof(u32) * xfer_size;
1280 local_count -= xfer_size;
1289 static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
1290 u16 dsp_index, u32 hpi_address, u32 *dest, u32 count)
1292 struct dsp_obj *pdo =
1293 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1294 u32 time_out = PCI_TIMEOUT;
1295 int c6711_burst_size = 16;
1296 u32 local_hpi_address = hpi_address;
1297 int local_count = count;
1302 while (local_count) {
1303 if (local_count > c6711_burst_size)
1304 xfer_size = c6711_burst_size;
1306 xfer_size = local_count;
1308 time_out = PCI_TIMEOUT;
1310 hpi_read_block(pdo, local_hpi_address, pdata,
1312 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1318 local_hpi_address += sizeof(u32) * xfer_size;
1319 local_count -= xfer_size;
1329 static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
1330 u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr)
1332 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1333 struct dsp_obj *pdo = &phw->ado[dsp_index];
1341 /* does the DSP we are referencing exist? */
1342 if (dsp_index >= phw->num_dsp)
1343 return HPI6000_ERROR_MSG_INVALID_DSP_INDEX;
1345 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1346 if (ack & HPI_HIF_ERROR_MASK) {
1348 return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT;
1350 pao->dsp_crashed = 0;
1352 /* send the message */
1354 /* get the address and size */
1355 if (phw->message_buffer_address_on_dsp == 0) {
1360 HPI_HIF_ADDR(message_buffer_address));
1361 phw->message_buffer_address_on_dsp = address;
1362 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1365 return HPI6000_ERROR_MSG_GET_ADR;
1367 address = phw->message_buffer_address_on_dsp;
1369 /* dwLength = sizeof(struct hpi_message); */
1373 p_data = (u32 *)phm;
1374 if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data,
1376 return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32;
1378 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_RESP))
1379 return HPI6000_ERROR_MSG_RESP_GETRESPCMD;
1380 hpi6000_send_dsp_interrupt(pdo);
1382 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_RESP);
1383 if (ack & HPI_HIF_ERROR_MASK)
1384 return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK;
1386 /* get the address and size */
1387 if (phw->response_buffer_address_on_dsp == 0) {
1392 HPI_HIF_ADDR(response_buffer_address));
1393 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1395 phw->response_buffer_address_on_dsp = address;
1398 return HPI6000_ERROR_RESP_GET_ADR;
1400 address = phw->response_buffer_address_on_dsp;
1402 /* read the length of the response back from the DSP */
1405 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1406 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
1408 length = sizeof(struct hpi_response);
1411 p_data = (u32 *)phr;
1412 if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data,
1414 return HPI6000_ERROR_MSG_RESP_BLOCKREAD32;
1416 /* set i/f back to idle */
1417 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1418 return HPI6000_ERROR_MSG_RESP_IDLECMD;
1419 hpi6000_send_dsp_interrupt(pdo);
1421 error = hpi_validate_response(phm, phr);
1425 /* have to set up the below defines to match stuff in the MAP file */
1427 #define MSG_ADDRESS (HPI_HIF_BASE+0x18)
1428 #define MSG_LENGTH 11
1429 #define RESP_ADDRESS (HPI_HIF_BASE+0x44)
1430 #define RESP_LENGTH 16
1431 #define QUEUE_START (HPI_HIF_BASE+0x88)
1432 #define QUEUE_SIZE 0x8000
1434 static short hpi6000_send_data_check_adr(u32 address, u32 length_in_dwords)
1436 /*#define CHECKING // comment this line in to enable checking */
1438 if (address < (u32)MSG_ADDRESS)
1440 if (address > (u32)(QUEUE_START + QUEUE_SIZE))
1442 if ((address + (length_in_dwords << 2)) >
1443 (u32)(QUEUE_START + QUEUE_SIZE))
1447 (void)length_in_dwords;
1452 static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
1453 struct hpi_message *phm, struct hpi_response *phr)
1455 struct dsp_obj *pdo =
1456 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1459 u32 length, address;
1460 u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
1465 /* round dwDataSize down to nearest 4 bytes */
1466 while ((data_sent < (phm->u.d.u.data.data_size & ~3L))
1468 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1469 if (ack & HPI_HIF_ERROR_MASK)
1470 return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT;
1472 if (hpi6000_send_host_command(pao, dsp_index,
1474 return HPI6000_ERROR_SEND_DATA_CMD;
1476 hpi6000_send_dsp_interrupt(pdo);
1478 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_SEND_DATA);
1480 if (ack & HPI_HIF_ERROR_MASK)
1481 return HPI6000_ERROR_SEND_DATA_ACK;
1484 /* get the address and size */
1485 address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
1486 /* DSP returns number of DWORDS */
1487 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1488 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
1490 if (!hpi6000_send_data_check_adr(address, length))
1491 return HPI6000_ERROR_SEND_DATA_ADR;
1493 /* send the data. break data into 512 DWORD blocks (2K bytes)
1494 * and send using block write. 2Kbytes is the max as this is the
1495 * memory window given to the HPI data register by the PCI2040
1504 if (hpi6000_dsp_block_write32(pao, dsp_index,
1505 address, p_data, blk_len))
1506 return HPI6000_ERROR_SEND_DATA_WRITE;
1507 address += blk_len * 4;
1513 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1514 return HPI6000_ERROR_SEND_DATA_IDLECMD;
1516 hpi6000_send_dsp_interrupt(pdo);
1518 data_sent += length * 4;
1521 return HPI6000_ERROR_SEND_DATA_TIMEOUT;
1525 static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
1526 struct hpi_message *phm, struct hpi_response *phr)
1528 struct dsp_obj *pdo =
1529 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1532 u32 length, address;
1533 u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
1535 (void)phr; /* this parameter not used! */
1537 /* round dwDataSize down to nearest 4 bytes */
1538 while (data_got < (phm->u.d.u.data.data_size & ~3L)) {
1539 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1540 if (ack & HPI_HIF_ERROR_MASK)
1541 return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT;
1543 if (hpi6000_send_host_command(pao, dsp_index,
1545 return HPI6000_ERROR_GET_DATA_CMD;
1546 hpi6000_send_dsp_interrupt(pdo);
1548 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_DATA);
1550 if (ack & HPI_HIF_ERROR_MASK)
1551 return HPI6000_ERROR_GET_DATA_ACK;
1553 /* get the address and size */
1555 address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
1556 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1557 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
1566 if (hpi6000_dsp_block_read32(pao, dsp_index,
1567 address, p_data, blk_len))
1568 return HPI6000_ERROR_GET_DATA_READ;
1569 address += blk_len * 4;
1575 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1576 return HPI6000_ERROR_GET_DATA_IDLECMD;
1577 hpi6000_send_dsp_interrupt(pdo);
1579 data_got += length * 4;
1584 static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo)
1586 iowrite32(0x00030003, pdo->prHPI_control); /* DSPINT */
1589 static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
1590 u16 dsp_index, u32 host_cmd)
1592 struct dsp_obj *pdo =
1593 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1594 u32 timeout = TIMEOUT;
1598 hpi_write_word(pdo, HPI_HIF_ADDR(host_cmd), host_cmd);
1599 /* flush the FIFO */
1600 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
1601 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout);
1603 /* reset the interrupt bit */
1604 iowrite32(0x00040004, pdo->prHPI_control);
1612 /* if the PCI2040 has recorded an HPI timeout, reset the error and return 1 */
1613 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
1618 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1620 /* read the error bits from the PCI2040 */
1621 hPI_error = ioread32(phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1623 /* reset the error flag */
1624 iowrite32(0L, phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1625 phw->pCI2040HPI_error_count++;
1626 if (read_or_write == 1)
1627 gw_pci_read_asserts++; /************* inc global */
1629 gw_pci_write_asserts++;
1635 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
1638 struct dsp_obj *pdo =
1639 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1644 /* wait for host interrupt to signal ack is ready */
1647 hPIC = ioread32(pdo->prHPI_control);
1648 if (hPIC & 0x04) /* 0x04 = HINT from DSP */
1652 return HPI_HIF_ERROR_MASK;
1654 /* wait for dwAckValue */
1657 /* read the ack mailbox */
1658 ack = hpi_read_word(pdo, HPI_HIF_ADDR(dsp_ack));
1659 if (ack == ack_value)
1661 if ((ack & HPI_HIF_ERROR_MASK)
1662 && !hpi6000_check_PCI2040_error_flag(pao, H6READ))
1664 /*for (i=0;i<1000;i++) */
1667 if (ack & HPI_HIF_ERROR_MASK)
1668 /* indicates bad read from DSP -
1669 typically 0xffffff is read for some reason */
1670 ack = HPI_HIF_ERROR_MASK;
1673 ack = HPI_HIF_ERROR_MASK;
1677 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
1678 struct hpi_message *phm)
1680 const u16 dsp_index = 0;
1681 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1682 struct dsp_obj *pdo = &phw->ado[dsp_index];
1684 u32 cache_dirty_flag;
1687 hpios_dsplock_lock(pao);
1692 hpi_read_word((struct dsp_obj *)pdo,
1693 HPI_HIF_ADDR(control_cache_is_dirty));
1694 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
1696 err = HPI6000_ERROR_CONTROL_CACHE_PARAMS;
1700 if (cache_dirty_flag) {
1701 /* read the cached controls */
1706 if (pdo->control_cache_address_on_dsp == 0) {
1709 hpi_read_word((struct dsp_obj *)pdo,
1710 HPI_HIF_ADDR(control_cache_address));
1712 length = hpi_read_word((struct dsp_obj *)pdo,
1714 (control_cache_size_in_bytes));
1715 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1718 err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN;
1721 pdo->control_cache_address_on_dsp = address;
1722 pdo->control_cache_length_on_dsp = length;
1724 address = pdo->control_cache_address_on_dsp;
1725 length = pdo->control_cache_length_on_dsp;
1728 if (hpi6000_dsp_block_read32(pao, dsp_index, address,
1729 (u32 *)&phw->control_cache[0],
1730 length / sizeof(u32))) {
1731 err = HPI6000_ERROR_CONTROL_CACHE_READ;
1735 hpi_write_word((struct dsp_obj *)pdo,
1736 HPI_HIF_ADDR(control_cache_is_dirty), 0);
1737 /* flush the FIFO */
1738 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
1739 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
1742 err = HPI6000_ERROR_CONTROL_CACHE_FLUSH;
1750 hpios_dsplock_unlock(pao);
1754 /** Get dsp index for multi DSP adapters only */
1755 static u16 get_dsp_index(struct hpi_adapter_obj *pao, struct hpi_message *phm)
1758 switch (phm->object) {
1759 case HPI_OBJ_ISTREAM:
1760 if (phm->obj_index < 2)
1763 case HPI_OBJ_PROFILE:
1764 ret = phm->obj_index;
1772 /** Complete transaction with DSP
1774 Send message, get response, send or get stream data if any.
1776 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
1777 struct hpi_response *phr)
1781 u16 num_dsp = ((struct hpi_hw_obj *)pao->priv)->num_dsp;
1786 dsp_index = get_dsp_index(pao, phm);
1788 /* is this checked on the DSP anyway? */
1789 if ((phm->function == HPI_ISTREAM_GROUP_ADD)
1790 || (phm->function == HPI_OSTREAM_GROUP_ADD)) {
1791 struct hpi_message hm;
1793 hm.obj_index = phm->u.d.u.stream.stream_index;
1794 hm.object = phm->u.d.u.stream.object_type;
1795 add_index = get_dsp_index(pao, &hm);
1796 if (add_index != dsp_index) {
1797 phr->error = HPI_ERROR_NO_INTERDSP_GROUPS;
1803 hpios_dsplock_lock(pao);
1804 error = hpi6000_message_response_sequence(pao, dsp_index, phm, phr);
1806 /* maybe an error response */
1808 /* something failed in the HPI/DSP interface */
1810 /* just the header of the response is valid */
1811 phr->size = sizeof(struct hpi_response_header);
1815 if (phr->error != 0) /* something failed in the DSP */
1818 switch (phm->function) {
1819 case HPI_OSTREAM_WRITE:
1820 case HPI_ISTREAM_ANC_WRITE:
1821 error = hpi6000_send_data(pao, dsp_index, phm, phr);
1823 case HPI_ISTREAM_READ:
1824 case HPI_OSTREAM_ANC_READ:
1825 error = hpi6000_get_data(pao, dsp_index, phm, phr);
1827 case HPI_ADAPTER_GET_ASSERT:
1828 phr->u.a.adapter_index = 0; /* dsp 0 default */
1830 if (!phr->u.a.adapter_type) {
1831 /* no assert from dsp 0, check dsp 1 */
1832 error = hpi6000_message_response_sequence(pao,
1834 phr->u.a.adapter_index = 1;
1843 hpios_dsplock_unlock(pao);