2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
3 * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
6 * - sometimes record brokes playback with WSS portion of
8 * - CS4231 (GUS MAX) - still trouble with occasional noises
9 * - broken initialization?
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #include <linux/delay.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/slab.h>
32 #include <linux/ioport.h>
33 #include <sound/core.h>
34 #include <sound/wss.h>
35 #include <sound/pcm_params.h>
36 #include <sound/tlv.h>
42 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
43 MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
44 MODULE_LICENSE("GPL");
47 #define SNDRV_DEBUG_MCE
54 static unsigned char freq_bits[14] = {
55 /* 5510 */ 0x00 | CS4231_XTAL2,
56 /* 6620 */ 0x0E | CS4231_XTAL2,
57 /* 8000 */ 0x00 | CS4231_XTAL1,
58 /* 9600 */ 0x0E | CS4231_XTAL1,
59 /* 11025 */ 0x02 | CS4231_XTAL2,
60 /* 16000 */ 0x02 | CS4231_XTAL1,
61 /* 18900 */ 0x04 | CS4231_XTAL2,
62 /* 22050 */ 0x06 | CS4231_XTAL2,
63 /* 27042 */ 0x04 | CS4231_XTAL1,
64 /* 32000 */ 0x06 | CS4231_XTAL1,
65 /* 33075 */ 0x0C | CS4231_XTAL2,
66 /* 37800 */ 0x08 | CS4231_XTAL2,
67 /* 44100 */ 0x0A | CS4231_XTAL2,
68 /* 48000 */ 0x0C | CS4231_XTAL1
71 static unsigned int rates[14] = {
72 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
73 27042, 32000, 33075, 37800, 44100, 48000
76 static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
77 .count = ARRAY_SIZE(rates),
82 static int snd_wss_xrate(struct snd_pcm_runtime *runtime)
84 return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
85 &hw_constraints_rates);
88 static unsigned char snd_wss_original_image[32] =
90 0x00, /* 00/00 - lic */
91 0x00, /* 01/01 - ric */
92 0x9f, /* 02/02 - la1ic */
93 0x9f, /* 03/03 - ra1ic */
94 0x9f, /* 04/04 - la2ic */
95 0x9f, /* 05/05 - ra2ic */
96 0xbf, /* 06/06 - loc */
97 0xbf, /* 07/07 - roc */
98 0x20, /* 08/08 - pdfr */
99 CS4231_AUTOCALIB, /* 09/09 - ic */
100 0x00, /* 0a/10 - pc */
101 0x00, /* 0b/11 - ti */
102 CS4231_MODE2, /* 0c/12 - mi */
103 0xfc, /* 0d/13 - lbc */
104 0x00, /* 0e/14 - pbru */
105 0x00, /* 0f/15 - pbrl */
106 0x80, /* 10/16 - afei */
107 0x01, /* 11/17 - afeii */
108 0x9f, /* 12/18 - llic */
109 0x9f, /* 13/19 - rlic */
110 0x00, /* 14/20 - tlb */
111 0x00, /* 15/21 - thb */
112 0x00, /* 16/22 - la3mic/reserved */
113 0x00, /* 17/23 - ra3mic/reserved */
114 0x00, /* 18/24 - afs */
115 0x00, /* 19/25 - lamoc/version */
116 0xcf, /* 1a/26 - mioc */
117 0x00, /* 1b/27 - ramoc/reserved */
118 0x20, /* 1c/28 - cdfr */
119 0x00, /* 1d/29 - res4 */
120 0x00, /* 1e/30 - cbru */
121 0x00, /* 1f/31 - cbrl */
124 static unsigned char snd_opti93x_original_image[32] =
126 0x00, /* 00/00 - l_mixout_outctrl */
127 0x00, /* 01/01 - r_mixout_outctrl */
128 0x88, /* 02/02 - l_cd_inctrl */
129 0x88, /* 03/03 - r_cd_inctrl */
130 0x88, /* 04/04 - l_a1/fm_inctrl */
131 0x88, /* 05/05 - r_a1/fm_inctrl */
132 0x80, /* 06/06 - l_dac_inctrl */
133 0x80, /* 07/07 - r_dac_inctrl */
134 0x00, /* 08/08 - ply_dataform_reg */
135 0x00, /* 09/09 - if_conf */
136 0x00, /* 0a/10 - pin_ctrl */
137 0x00, /* 0b/11 - err_init_reg */
138 0x0a, /* 0c/12 - id_reg */
139 0x00, /* 0d/13 - reserved */
140 0x00, /* 0e/14 - ply_upcount_reg */
141 0x00, /* 0f/15 - ply_lowcount_reg */
142 0x88, /* 10/16 - reserved/l_a1_inctrl */
143 0x88, /* 11/17 - reserved/r_a1_inctrl */
144 0x88, /* 12/18 - l_line_inctrl */
145 0x88, /* 13/19 - r_line_inctrl */
146 0x88, /* 14/20 - l_mic_inctrl */
147 0x88, /* 15/21 - r_mic_inctrl */
148 0x80, /* 16/22 - l_out_outctrl */
149 0x80, /* 17/23 - r_out_outctrl */
150 0x00, /* 18/24 - reserved */
151 0x00, /* 19/25 - reserved */
152 0x00, /* 1a/26 - reserved */
153 0x00, /* 1b/27 - reserved */
154 0x00, /* 1c/28 - cap_dataform_reg */
155 0x00, /* 1d/29 - reserved */
156 0x00, /* 1e/30 - cap_upcount_reg */
157 0x00 /* 1f/31 - cap_lowcount_reg */
161 * Basic I/O functions
164 static inline void wss_outb(struct snd_wss *chip, u8 offset, u8 val)
166 outb(val, chip->port + offset);
169 static inline u8 wss_inb(struct snd_wss *chip, u8 offset)
171 return inb(chip->port + offset);
174 static void snd_wss_wait(struct snd_wss *chip)
179 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
184 static void snd_wss_outm(struct snd_wss *chip, unsigned char reg,
185 unsigned char mask, unsigned char value)
187 unsigned char tmp = (chip->image[reg] & mask) | value;
190 #ifdef CONFIG_SND_DEBUG
191 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
192 snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
194 chip->image[reg] = tmp;
195 if (!chip->calibrate_mute) {
196 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
198 wss_outb(chip, CS4231P(REG), tmp);
203 static void snd_wss_dout(struct snd_wss *chip, unsigned char reg,
209 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
212 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
213 wss_outb(chip, CS4231P(REG), value);
217 void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char value)
220 #ifdef CONFIG_SND_DEBUG
221 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
222 snd_printk(KERN_DEBUG "out: auto calibration time out "
223 "- reg = 0x%x, value = 0x%x\n", reg, value);
225 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
226 wss_outb(chip, CS4231P(REG), value);
227 chip->image[reg] = value;
229 snd_printdd("codec out - reg 0x%x = 0x%x\n",
230 chip->mce_bit | reg, value);
232 EXPORT_SYMBOL(snd_wss_out);
234 unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg)
237 #ifdef CONFIG_SND_DEBUG
238 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
239 snd_printk(KERN_DEBUG "in: auto calibration time out "
240 "- reg = 0x%x\n", reg);
242 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
244 return wss_inb(chip, CS4231P(REG));
246 EXPORT_SYMBOL(snd_wss_in);
248 void snd_cs4236_ext_out(struct snd_wss *chip, unsigned char reg,
251 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
252 wss_outb(chip, CS4231P(REG),
253 reg | (chip->image[CS4236_EXT_REG] & 0x01));
254 wss_outb(chip, CS4231P(REG), val);
255 chip->eimage[CS4236_REG(reg)] = val;
257 printk(KERN_DEBUG "ext out : reg = 0x%x, val = 0x%x\n", reg, val);
260 EXPORT_SYMBOL(snd_cs4236_ext_out);
262 unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg)
264 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
265 wss_outb(chip, CS4231P(REG),
266 reg | (chip->image[CS4236_EXT_REG] & 0x01));
268 return wss_inb(chip, CS4231P(REG));
272 res = wss_inb(chip, CS4231P(REG));
273 printk(KERN_DEBUG "ext in : reg = 0x%x, val = 0x%x\n",
279 EXPORT_SYMBOL(snd_cs4236_ext_in);
283 static void snd_wss_debug(struct snd_wss *chip)
286 "CS4231 REGS: INDEX = 0x%02x "
287 " STATUS = 0x%02x\n",
288 wss_inb(chip, CS4231P(REGSEL)),
289 wss_inb(chip, CS4231P(STATUS)));
291 " 0x00: left input = 0x%02x "
292 " 0x10: alt 1 (CFIG 2) = 0x%02x\n",
293 snd_wss_in(chip, 0x00),
294 snd_wss_in(chip, 0x10));
296 " 0x01: right input = 0x%02x "
297 " 0x11: alt 2 (CFIG 3) = 0x%02x\n",
298 snd_wss_in(chip, 0x01),
299 snd_wss_in(chip, 0x11));
301 " 0x02: GF1 left input = 0x%02x "
302 " 0x12: left line in = 0x%02x\n",
303 snd_wss_in(chip, 0x02),
304 snd_wss_in(chip, 0x12));
306 " 0x03: GF1 right input = 0x%02x "
307 " 0x13: right line in = 0x%02x\n",
308 snd_wss_in(chip, 0x03),
309 snd_wss_in(chip, 0x13));
311 " 0x04: CD left input = 0x%02x "
312 " 0x14: timer low = 0x%02x\n",
313 snd_wss_in(chip, 0x04),
314 snd_wss_in(chip, 0x14));
316 " 0x05: CD right input = 0x%02x "
317 " 0x15: timer high = 0x%02x\n",
318 snd_wss_in(chip, 0x05),
319 snd_wss_in(chip, 0x15));
321 " 0x06: left output = 0x%02x "
322 " 0x16: left MIC (PnP) = 0x%02x\n",
323 snd_wss_in(chip, 0x06),
324 snd_wss_in(chip, 0x16));
326 " 0x07: right output = 0x%02x "
327 " 0x17: right MIC (PnP) = 0x%02x\n",
328 snd_wss_in(chip, 0x07),
329 snd_wss_in(chip, 0x17));
331 " 0x08: playback format = 0x%02x "
332 " 0x18: IRQ status = 0x%02x\n",
333 snd_wss_in(chip, 0x08),
334 snd_wss_in(chip, 0x18));
336 " 0x09: iface (CFIG 1) = 0x%02x "
337 " 0x19: left line out = 0x%02x\n",
338 snd_wss_in(chip, 0x09),
339 snd_wss_in(chip, 0x19));
341 " 0x0a: pin control = 0x%02x "
342 " 0x1a: mono control = 0x%02x\n",
343 snd_wss_in(chip, 0x0a),
344 snd_wss_in(chip, 0x1a));
346 " 0x0b: init & status = 0x%02x "
347 " 0x1b: right line out = 0x%02x\n",
348 snd_wss_in(chip, 0x0b),
349 snd_wss_in(chip, 0x1b));
351 " 0x0c: revision & mode = 0x%02x "
352 " 0x1c: record format = 0x%02x\n",
353 snd_wss_in(chip, 0x0c),
354 snd_wss_in(chip, 0x1c));
356 " 0x0d: loopback = 0x%02x "
357 " 0x1d: var freq (PnP) = 0x%02x\n",
358 snd_wss_in(chip, 0x0d),
359 snd_wss_in(chip, 0x1d));
361 " 0x0e: ply upr count = 0x%02x "
362 " 0x1e: ply lwr count = 0x%02x\n",
363 snd_wss_in(chip, 0x0e),
364 snd_wss_in(chip, 0x1e));
366 " 0x0f: rec upr count = 0x%02x "
367 " 0x1f: rec lwr count = 0x%02x\n",
368 snd_wss_in(chip, 0x0f),
369 snd_wss_in(chip, 0x1f));
375 * CS4231 detection / MCE routines
378 static void snd_wss_busy_wait(struct snd_wss *chip)
382 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
383 for (timeout = 5; timeout > 0; timeout--)
384 wss_inb(chip, CS4231P(REGSEL));
385 /* end of cleanup sequence */
386 for (timeout = 25000;
387 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
392 void snd_wss_mce_up(struct snd_wss *chip)
398 #ifdef CONFIG_SND_DEBUG
399 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
400 snd_printk(KERN_DEBUG
401 "mce_up - auto calibration time out (0)\n");
403 spin_lock_irqsave(&chip->reg_lock, flags);
404 chip->mce_bit |= CS4231_MCE;
405 timeout = wss_inb(chip, CS4231P(REGSEL));
407 snd_printk(KERN_DEBUG "mce_up [0x%lx]: "
408 "serious init problem - codec still busy\n",
410 if (!(timeout & CS4231_MCE))
411 wss_outb(chip, CS4231P(REGSEL),
412 chip->mce_bit | (timeout & 0x1f));
413 spin_unlock_irqrestore(&chip->reg_lock, flags);
415 EXPORT_SYMBOL(snd_wss_mce_up);
417 void snd_wss_mce_down(struct snd_wss *chip)
420 unsigned long end_time;
422 int hw_mask = WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK | WSS_HW_AD1848;
424 snd_wss_busy_wait(chip);
426 #ifdef CONFIG_SND_DEBUG
427 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
428 snd_printk(KERN_DEBUG "mce_down [0x%lx] - "
429 "auto calibration time out (0)\n",
430 (long)CS4231P(REGSEL));
432 spin_lock_irqsave(&chip->reg_lock, flags);
433 chip->mce_bit &= ~CS4231_MCE;
434 timeout = wss_inb(chip, CS4231P(REGSEL));
435 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
436 spin_unlock_irqrestore(&chip->reg_lock, flags);
438 snd_printk(KERN_DEBUG "mce_down [0x%lx]: "
439 "serious init problem - codec still busy\n",
441 if ((timeout & CS4231_MCE) == 0 || !(chip->hardware & hw_mask))
445 * Wait for (possible -- during init auto-calibration may not be set)
446 * calibration process to start. Needs upto 5 sample periods on AD1848
447 * which at the slowest possible rate of 5.5125 kHz means 907 us.
451 snd_printdd("(1) jiffies = %lu\n", jiffies);
453 /* check condition up to 250 ms */
454 end_time = jiffies + msecs_to_jiffies(250);
455 while (snd_wss_in(chip, CS4231_TEST_INIT) &
456 CS4231_CALIB_IN_PROGRESS) {
458 if (time_after(jiffies, end_time)) {
459 snd_printk(KERN_ERR "mce_down - "
460 "auto calibration time out (2)\n");
466 snd_printdd("(2) jiffies = %lu\n", jiffies);
468 /* check condition up to 100 ms */
469 end_time = jiffies + msecs_to_jiffies(100);
470 while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
471 if (time_after(jiffies, end_time)) {
472 snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
478 snd_printdd("(3) jiffies = %lu\n", jiffies);
479 snd_printd("mce_down - exit = 0x%x\n", wss_inb(chip, CS4231P(REGSEL)));
481 EXPORT_SYMBOL(snd_wss_mce_down);
483 static unsigned int snd_wss_get_count(unsigned char format, unsigned int size)
485 switch (format & 0xe0) {
486 case CS4231_LINEAR_16:
487 case CS4231_LINEAR_16_BIG:
490 case CS4231_ADPCM_16:
493 if (format & CS4231_STEREO)
498 static int snd_wss_trigger(struct snd_pcm_substream *substream,
501 struct snd_wss *chip = snd_pcm_substream_chip(substream);
504 struct snd_pcm_substream *s;
508 case SNDRV_PCM_TRIGGER_START:
509 case SNDRV_PCM_TRIGGER_RESUME:
511 case SNDRV_PCM_TRIGGER_STOP:
512 case SNDRV_PCM_TRIGGER_SUSPEND:
519 snd_pcm_group_for_each_entry(s, substream) {
520 if (s == chip->playback_substream) {
521 what |= CS4231_PLAYBACK_ENABLE;
522 snd_pcm_trigger_done(s, substream);
523 } else if (s == chip->capture_substream) {
524 what |= CS4231_RECORD_ENABLE;
525 snd_pcm_trigger_done(s, substream);
528 spin_lock(&chip->reg_lock);
530 chip->image[CS4231_IFACE_CTRL] |= what;
532 chip->trigger(chip, what, 1);
534 chip->image[CS4231_IFACE_CTRL] &= ~what;
536 chip->trigger(chip, what, 0);
538 snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
539 spin_unlock(&chip->reg_lock);
550 static unsigned char snd_wss_get_rate(unsigned int rate)
554 for (i = 0; i < ARRAY_SIZE(rates); i++)
555 if (rate == rates[i])
558 return freq_bits[ARRAY_SIZE(rates) - 1];
561 static unsigned char snd_wss_get_format(struct snd_wss *chip,
565 unsigned char rformat;
567 rformat = CS4231_LINEAR_8;
569 case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
570 case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
571 case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
572 case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
573 case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
576 rformat |= CS4231_STEREO;
578 snd_printk(KERN_DEBUG "get_format: 0x%x (mode=0x%x)\n", format, mode);
583 static void snd_wss_calibrate_mute(struct snd_wss *chip, int mute)
587 mute = mute ? 0x80 : 0;
588 spin_lock_irqsave(&chip->reg_lock, flags);
589 if (chip->calibrate_mute == mute) {
590 spin_unlock_irqrestore(&chip->reg_lock, flags);
594 snd_wss_dout(chip, CS4231_LEFT_INPUT,
595 chip->image[CS4231_LEFT_INPUT]);
596 snd_wss_dout(chip, CS4231_RIGHT_INPUT,
597 chip->image[CS4231_RIGHT_INPUT]);
598 snd_wss_dout(chip, CS4231_LOOPBACK,
599 chip->image[CS4231_LOOPBACK]);
601 snd_wss_dout(chip, CS4231_AUX1_LEFT_INPUT,
602 mute | chip->image[CS4231_AUX1_LEFT_INPUT]);
603 snd_wss_dout(chip, CS4231_AUX1_RIGHT_INPUT,
604 mute | chip->image[CS4231_AUX1_RIGHT_INPUT]);
605 snd_wss_dout(chip, CS4231_AUX2_LEFT_INPUT,
606 mute | chip->image[CS4231_AUX2_LEFT_INPUT]);
607 snd_wss_dout(chip, CS4231_AUX2_RIGHT_INPUT,
608 mute | chip->image[CS4231_AUX2_RIGHT_INPUT]);
609 snd_wss_dout(chip, CS4231_LEFT_OUTPUT,
610 mute | chip->image[CS4231_LEFT_OUTPUT]);
611 snd_wss_dout(chip, CS4231_RIGHT_OUTPUT,
612 mute | chip->image[CS4231_RIGHT_OUTPUT]);
613 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
614 snd_wss_dout(chip, CS4231_LEFT_LINE_IN,
615 mute | chip->image[CS4231_LEFT_LINE_IN]);
616 snd_wss_dout(chip, CS4231_RIGHT_LINE_IN,
617 mute | chip->image[CS4231_RIGHT_LINE_IN]);
618 snd_wss_dout(chip, CS4231_MONO_CTRL,
619 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
621 if (chip->hardware == WSS_HW_INTERWAVE) {
622 snd_wss_dout(chip, CS4231_LEFT_MIC_INPUT,
623 mute | chip->image[CS4231_LEFT_MIC_INPUT]);
624 snd_wss_dout(chip, CS4231_RIGHT_MIC_INPUT,
625 mute | chip->image[CS4231_RIGHT_MIC_INPUT]);
626 snd_wss_dout(chip, CS4231_LINE_LEFT_OUTPUT,
627 mute | chip->image[CS4231_LINE_LEFT_OUTPUT]);
628 snd_wss_dout(chip, CS4231_LINE_RIGHT_OUTPUT,
629 mute | chip->image[CS4231_LINE_RIGHT_OUTPUT]);
631 chip->calibrate_mute = mute;
632 spin_unlock_irqrestore(&chip->reg_lock, flags);
635 static void snd_wss_playback_format(struct snd_wss *chip,
636 struct snd_pcm_hw_params *params,
642 mutex_lock(&chip->mce_mutex);
643 snd_wss_calibrate_mute(chip, 1);
644 if (chip->hardware == WSS_HW_CS4231A ||
645 (chip->hardware & WSS_HW_CS4232_MASK)) {
646 spin_lock_irqsave(&chip->reg_lock, flags);
647 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */
648 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
649 chip->image[CS4231_ALT_FEATURE_1] | 0x10);
650 chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
651 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
652 chip->image[CS4231_PLAYBK_FORMAT]);
653 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
654 chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
655 udelay(100); /* Fixes audible clicks at least on GUS MAX */
658 spin_unlock_irqrestore(&chip->reg_lock, flags);
661 snd_wss_mce_up(chip);
662 spin_lock_irqsave(&chip->reg_lock, flags);
663 if (chip->hardware != WSS_HW_INTERWAVE && !chip->single_dma) {
664 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)
665 pdfr = (pdfr & 0xf0) |
666 (chip->image[CS4231_REC_FORMAT] & 0x0f);
668 chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
670 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, pdfr);
671 spin_unlock_irqrestore(&chip->reg_lock, flags);
672 if (chip->hardware == WSS_HW_OPL3SA2)
673 udelay(100); /* this seems to help */
674 snd_wss_mce_down(chip);
676 snd_wss_calibrate_mute(chip, 0);
677 mutex_unlock(&chip->mce_mutex);
680 static void snd_wss_capture_format(struct snd_wss *chip,
681 struct snd_pcm_hw_params *params,
687 mutex_lock(&chip->mce_mutex);
688 snd_wss_calibrate_mute(chip, 1);
689 if (chip->hardware == WSS_HW_CS4231A ||
690 (chip->hardware & WSS_HW_CS4232_MASK)) {
691 spin_lock_irqsave(&chip->reg_lock, flags);
692 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */
693 (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
694 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
695 chip->image[CS4231_ALT_FEATURE_1] | 0x20);
696 snd_wss_out(chip, CS4231_REC_FORMAT,
697 chip->image[CS4231_REC_FORMAT] = cdfr);
698 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
699 chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
702 spin_unlock_irqrestore(&chip->reg_lock, flags);
705 snd_wss_mce_up(chip);
706 spin_lock_irqsave(&chip->reg_lock, flags);
707 if (chip->hardware != WSS_HW_INTERWAVE &&
708 !(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
709 if (chip->single_dma)
710 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
712 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
713 (chip->image[CS4231_PLAYBK_FORMAT] & 0xf0) |
715 spin_unlock_irqrestore(&chip->reg_lock, flags);
716 snd_wss_mce_down(chip);
717 snd_wss_mce_up(chip);
718 spin_lock_irqsave(&chip->reg_lock, flags);
720 if (chip->hardware & WSS_HW_AD1848_MASK)
721 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
723 snd_wss_out(chip, CS4231_REC_FORMAT, cdfr);
724 spin_unlock_irqrestore(&chip->reg_lock, flags);
725 snd_wss_mce_down(chip);
727 snd_wss_calibrate_mute(chip, 0);
728 mutex_unlock(&chip->mce_mutex);
735 static unsigned long snd_wss_timer_resolution(struct snd_timer *timer)
737 struct snd_wss *chip = snd_timer_chip(timer);
738 if (chip->hardware & WSS_HW_CS4236B_MASK)
741 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
744 static int snd_wss_timer_start(struct snd_timer *timer)
748 struct snd_wss *chip = snd_timer_chip(timer);
749 spin_lock_irqsave(&chip->reg_lock, flags);
750 ticks = timer->sticks;
751 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
752 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
753 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
754 chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8);
755 snd_wss_out(chip, CS4231_TIMER_HIGH,
756 chip->image[CS4231_TIMER_HIGH]);
757 chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks;
758 snd_wss_out(chip, CS4231_TIMER_LOW,
759 chip->image[CS4231_TIMER_LOW]);
760 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
761 chip->image[CS4231_ALT_FEATURE_1] |
762 CS4231_TIMER_ENABLE);
764 spin_unlock_irqrestore(&chip->reg_lock, flags);
768 static int snd_wss_timer_stop(struct snd_timer *timer)
771 struct snd_wss *chip = snd_timer_chip(timer);
772 spin_lock_irqsave(&chip->reg_lock, flags);
773 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
774 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
775 chip->image[CS4231_ALT_FEATURE_1]);
776 spin_unlock_irqrestore(&chip->reg_lock, flags);
780 static void snd_wss_init(struct snd_wss *chip)
784 snd_wss_mce_down(chip);
786 #ifdef SNDRV_DEBUG_MCE
787 snd_printk(KERN_DEBUG "init: (1)\n");
789 snd_wss_mce_up(chip);
790 spin_lock_irqsave(&chip->reg_lock, flags);
791 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
792 CS4231_PLAYBACK_PIO |
793 CS4231_RECORD_ENABLE |
796 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
797 snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
798 spin_unlock_irqrestore(&chip->reg_lock, flags);
799 snd_wss_mce_down(chip);
801 #ifdef SNDRV_DEBUG_MCE
802 snd_printk(KERN_DEBUG "init: (2)\n");
805 snd_wss_mce_up(chip);
806 spin_lock_irqsave(&chip->reg_lock, flags);
808 CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
809 spin_unlock_irqrestore(&chip->reg_lock, flags);
810 snd_wss_mce_down(chip);
812 #ifdef SNDRV_DEBUG_MCE
813 snd_printk(KERN_DEBUG "init: (3) - afei = 0x%x\n",
814 chip->image[CS4231_ALT_FEATURE_1]);
817 spin_lock_irqsave(&chip->reg_lock, flags);
818 snd_wss_out(chip, CS4231_ALT_FEATURE_2,
819 chip->image[CS4231_ALT_FEATURE_2]);
820 spin_unlock_irqrestore(&chip->reg_lock, flags);
822 snd_wss_mce_up(chip);
823 spin_lock_irqsave(&chip->reg_lock, flags);
824 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
825 chip->image[CS4231_PLAYBK_FORMAT]);
826 spin_unlock_irqrestore(&chip->reg_lock, flags);
827 snd_wss_mce_down(chip);
829 #ifdef SNDRV_DEBUG_MCE
830 snd_printk(KERN_DEBUG "init: (4)\n");
833 snd_wss_mce_up(chip);
834 spin_lock_irqsave(&chip->reg_lock, flags);
835 if (!(chip->hardware & WSS_HW_AD1848_MASK))
836 snd_wss_out(chip, CS4231_REC_FORMAT,
837 chip->image[CS4231_REC_FORMAT]);
838 spin_unlock_irqrestore(&chip->reg_lock, flags);
839 snd_wss_mce_down(chip);
841 #ifdef SNDRV_DEBUG_MCE
842 snd_printk(KERN_DEBUG "init: (5)\n");
846 static int snd_wss_open(struct snd_wss *chip, unsigned int mode)
850 mutex_lock(&chip->open_mutex);
851 if ((chip->mode & mode) ||
852 ((chip->mode & WSS_MODE_OPEN) && chip->single_dma)) {
853 mutex_unlock(&chip->open_mutex);
856 if (chip->mode & WSS_MODE_OPEN) {
858 mutex_unlock(&chip->open_mutex);
861 /* ok. now enable and ack CODEC IRQ */
862 spin_lock_irqsave(&chip->reg_lock, flags);
863 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
864 snd_wss_out(chip, CS4231_IRQ_STATUS,
865 CS4231_PLAYBACK_IRQ |
868 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
870 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
871 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
872 chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
873 snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
874 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
875 snd_wss_out(chip, CS4231_IRQ_STATUS,
876 CS4231_PLAYBACK_IRQ |
879 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
881 spin_unlock_irqrestore(&chip->reg_lock, flags);
884 mutex_unlock(&chip->open_mutex);
888 static void snd_wss_close(struct snd_wss *chip, unsigned int mode)
892 mutex_lock(&chip->open_mutex);
894 if (chip->mode & WSS_MODE_OPEN) {
895 mutex_unlock(&chip->open_mutex);
898 snd_wss_calibrate_mute(chip, 1);
901 spin_lock_irqsave(&chip->reg_lock, flags);
902 if (!(chip->hardware & WSS_HW_AD1848_MASK))
903 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
904 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
905 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
906 chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
907 snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
909 /* now disable record & playback */
911 if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
912 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
913 spin_unlock_irqrestore(&chip->reg_lock, flags);
914 snd_wss_mce_up(chip);
915 spin_lock_irqsave(&chip->reg_lock, flags);
916 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
917 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
918 snd_wss_out(chip, CS4231_IFACE_CTRL,
919 chip->image[CS4231_IFACE_CTRL]);
920 spin_unlock_irqrestore(&chip->reg_lock, flags);
921 snd_wss_mce_down(chip);
922 spin_lock_irqsave(&chip->reg_lock, flags);
925 /* clear IRQ again */
926 if (!(chip->hardware & WSS_HW_AD1848_MASK))
927 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
928 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
929 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
930 spin_unlock_irqrestore(&chip->reg_lock, flags);
932 snd_wss_calibrate_mute(chip, 0);
935 mutex_unlock(&chip->open_mutex);
942 static int snd_wss_timer_open(struct snd_timer *timer)
944 struct snd_wss *chip = snd_timer_chip(timer);
945 snd_wss_open(chip, WSS_MODE_TIMER);
949 static int snd_wss_timer_close(struct snd_timer *timer)
951 struct snd_wss *chip = snd_timer_chip(timer);
952 snd_wss_close(chip, WSS_MODE_TIMER);
956 static struct snd_timer_hardware snd_wss_timer_table =
958 .flags = SNDRV_TIMER_HW_AUTO,
961 .open = snd_wss_timer_open,
962 .close = snd_wss_timer_close,
963 .c_resolution = snd_wss_timer_resolution,
964 .start = snd_wss_timer_start,
965 .stop = snd_wss_timer_stop,
969 * ok.. exported functions..
972 static int snd_wss_playback_hw_params(struct snd_pcm_substream *substream,
973 struct snd_pcm_hw_params *hw_params)
975 struct snd_wss *chip = snd_pcm_substream_chip(substream);
976 unsigned char new_pdfr;
979 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
981 new_pdfr = snd_wss_get_format(chip, params_format(hw_params),
982 params_channels(hw_params)) |
983 snd_wss_get_rate(params_rate(hw_params));
984 chip->set_playback_format(chip, hw_params, new_pdfr);
988 static int snd_wss_playback_hw_free(struct snd_pcm_substream *substream)
990 return snd_pcm_lib_free_pages(substream);
993 static int snd_wss_playback_prepare(struct snd_pcm_substream *substream)
995 struct snd_wss *chip = snd_pcm_substream_chip(substream);
996 struct snd_pcm_runtime *runtime = substream->runtime;
998 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
999 unsigned int count = snd_pcm_lib_period_bytes(substream);
1001 spin_lock_irqsave(&chip->reg_lock, flags);
1002 chip->p_dma_size = size;
1003 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
1004 snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
1005 count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
1006 snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
1007 snd_wss_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
1008 spin_unlock_irqrestore(&chip->reg_lock, flags);
1010 snd_wss_debug(chip);
1015 static int snd_wss_capture_hw_params(struct snd_pcm_substream *substream,
1016 struct snd_pcm_hw_params *hw_params)
1018 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1019 unsigned char new_cdfr;
1022 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1024 new_cdfr = snd_wss_get_format(chip, params_format(hw_params),
1025 params_channels(hw_params)) |
1026 snd_wss_get_rate(params_rate(hw_params));
1027 chip->set_capture_format(chip, hw_params, new_cdfr);
1031 static int snd_wss_capture_hw_free(struct snd_pcm_substream *substream)
1033 return snd_pcm_lib_free_pages(substream);
1036 static int snd_wss_capture_prepare(struct snd_pcm_substream *substream)
1038 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1039 struct snd_pcm_runtime *runtime = substream->runtime;
1040 unsigned long flags;
1041 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
1042 unsigned int count = snd_pcm_lib_period_bytes(substream);
1044 spin_lock_irqsave(&chip->reg_lock, flags);
1045 chip->c_dma_size = size;
1046 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
1047 snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
1048 if (chip->hardware & WSS_HW_AD1848_MASK)
1049 count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT],
1052 count = snd_wss_get_count(chip->image[CS4231_REC_FORMAT],
1055 if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
1056 snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
1057 snd_wss_out(chip, CS4231_PLY_UPR_CNT,
1058 (unsigned char) (count >> 8));
1060 snd_wss_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
1061 snd_wss_out(chip, CS4231_REC_UPR_CNT,
1062 (unsigned char) (count >> 8));
1064 spin_unlock_irqrestore(&chip->reg_lock, flags);
1068 void snd_wss_overrange(struct snd_wss *chip)
1070 unsigned long flags;
1073 spin_lock_irqsave(&chip->reg_lock, flags);
1074 res = snd_wss_in(chip, CS4231_TEST_INIT);
1075 spin_unlock_irqrestore(&chip->reg_lock, flags);
1076 if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
1077 chip->capture_substream->runtime->overrange++;
1079 EXPORT_SYMBOL(snd_wss_overrange);
1081 irqreturn_t snd_wss_interrupt(int irq, void *dev_id)
1083 struct snd_wss *chip = dev_id;
1084 unsigned char status;
1086 if (chip->hardware & WSS_HW_AD1848_MASK)
1087 /* pretend it was the only possible irq for AD1848 */
1088 status = CS4231_PLAYBACK_IRQ;
1090 status = snd_wss_in(chip, CS4231_IRQ_STATUS);
1091 if (status & CS4231_TIMER_IRQ) {
1093 snd_timer_interrupt(chip->timer, chip->timer->sticks);
1095 if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
1096 if (status & CS4231_PLAYBACK_IRQ) {
1097 if (chip->mode & WSS_MODE_PLAY) {
1098 if (chip->playback_substream)
1099 snd_pcm_period_elapsed(chip->playback_substream);
1101 if (chip->mode & WSS_MODE_RECORD) {
1102 if (chip->capture_substream) {
1103 snd_wss_overrange(chip);
1104 snd_pcm_period_elapsed(chip->capture_substream);
1109 if (status & CS4231_PLAYBACK_IRQ) {
1110 if (chip->playback_substream)
1111 snd_pcm_period_elapsed(chip->playback_substream);
1113 if (status & CS4231_RECORD_IRQ) {
1114 if (chip->capture_substream) {
1115 snd_wss_overrange(chip);
1116 snd_pcm_period_elapsed(chip->capture_substream);
1121 spin_lock(&chip->reg_lock);
1122 status = ~CS4231_ALL_IRQS | ~status;
1123 if (chip->hardware & WSS_HW_AD1848_MASK)
1124 wss_outb(chip, CS4231P(STATUS), 0);
1126 snd_wss_outm(chip, CS4231_IRQ_STATUS, status, 0);
1127 spin_unlock(&chip->reg_lock);
1130 EXPORT_SYMBOL(snd_wss_interrupt);
1132 static snd_pcm_uframes_t snd_wss_playback_pointer(struct snd_pcm_substream *substream)
1134 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1137 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
1139 ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
1140 return bytes_to_frames(substream->runtime, ptr);
1143 static snd_pcm_uframes_t snd_wss_capture_pointer(struct snd_pcm_substream *substream)
1145 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1148 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
1150 ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
1151 return bytes_to_frames(substream->runtime, ptr);
1158 static int snd_ad1848_probe(struct snd_wss *chip)
1160 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1161 unsigned long flags;
1163 unsigned short hardware = 0;
1167 while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
1168 if (time_after(jiffies, timeout))
1172 spin_lock_irqsave(&chip->reg_lock, flags);
1174 /* set CS423x MODE 1 */
1175 snd_wss_dout(chip, CS4231_MISC_INFO, 0);
1177 snd_wss_dout(chip, CS4231_RIGHT_INPUT, 0x45); /* 0x55 & ~0x10 */
1178 r = snd_wss_in(chip, CS4231_RIGHT_INPUT);
1180 /* RMGE always high on AD1847 */
1181 if ((r & ~CS4231_ENABLE_MIC_GAIN) != 0x45) {
1185 hardware = WSS_HW_AD1847;
1187 snd_wss_dout(chip, CS4231_LEFT_INPUT, 0xaa);
1188 r = snd_wss_in(chip, CS4231_LEFT_INPUT);
1189 /* L/RMGE always low on AT2320 */
1190 if ((r | CS4231_ENABLE_MIC_GAIN) != 0xaa) {
1196 /* clear pending IRQ */
1197 wss_inb(chip, CS4231P(STATUS));
1198 wss_outb(chip, CS4231P(STATUS), 0);
1201 if ((chip->hardware & WSS_HW_TYPE_MASK) != WSS_HW_DETECT)
1205 chip->hardware = hardware;
1209 r = snd_wss_in(chip, CS4231_MISC_INFO);
1211 /* set CS423x MODE 2 */
1212 snd_wss_dout(chip, CS4231_MISC_INFO, CS4231_MODE2);
1213 for (i = 0; i < 16; i++) {
1214 if (snd_wss_in(chip, i) != snd_wss_in(chip, 16 + i)) {
1215 /* we have more than 16 registers: check ID */
1216 if ((r & 0xf) != 0xa)
1219 * on CMI8330, CS4231_VERSION is volume control and
1222 snd_wss_dout(chip, CS4231_VERSION, 0);
1223 r = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
1225 chip->hardware = WSS_HW_CMI8330;
1230 chip->hardware = WSS_HW_CS4248;
1232 chip->hardware = WSS_HW_AD1848;
1234 snd_wss_dout(chip, CS4231_MISC_INFO, 0);
1236 spin_unlock_irqrestore(&chip->reg_lock, flags);
1240 static int snd_wss_probe(struct snd_wss *chip)
1242 unsigned long flags;
1243 int i, id, rev, regnum;
1247 id = snd_ad1848_probe(chip);
1251 hw = chip->hardware;
1252 if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
1253 for (i = 0; i < 50; i++) {
1255 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
1258 spin_lock_irqsave(&chip->reg_lock, flags);
1259 snd_wss_out(chip, CS4231_MISC_INFO,
1261 id = snd_wss_in(chip, CS4231_MISC_INFO) & 0x0f;
1262 spin_unlock_irqrestore(&chip->reg_lock, flags);
1264 break; /* this is valid value */
1267 snd_printdd("wss: port = 0x%lx, id = 0x%x\n", chip->port, id);
1269 return -ENODEV; /* no valid device found */
1271 rev = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
1272 snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
1274 unsigned char tmp = snd_wss_in(chip, 23);
1275 snd_wss_out(chip, 23, ~tmp);
1276 if (snd_wss_in(chip, 23) != tmp)
1277 chip->hardware = WSS_HW_AD1845;
1279 chip->hardware = WSS_HW_CS4231;
1280 } else if (rev == 0xa0) {
1281 chip->hardware = WSS_HW_CS4231A;
1282 } else if (rev == 0xa2) {
1283 chip->hardware = WSS_HW_CS4232;
1284 } else if (rev == 0xb2) {
1285 chip->hardware = WSS_HW_CS4232A;
1286 } else if (rev == 0x83) {
1287 chip->hardware = WSS_HW_CS4236;
1288 } else if (rev == 0x03) {
1289 chip->hardware = WSS_HW_CS4236B;
1292 "unknown CS chip with version 0x%x\n", rev);
1293 return -ENODEV; /* unknown CS4231 chip? */
1296 spin_lock_irqsave(&chip->reg_lock, flags);
1297 wss_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */
1298 wss_outb(chip, CS4231P(STATUS), 0);
1300 spin_unlock_irqrestore(&chip->reg_lock, flags);
1302 if (!(chip->hardware & WSS_HW_AD1848_MASK))
1303 chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1304 switch (chip->hardware) {
1305 case WSS_HW_INTERWAVE:
1306 chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
1309 case WSS_HW_CS4236B:
1310 case WSS_HW_CS4237B:
1311 case WSS_HW_CS4238B:
1313 if (hw == WSS_HW_DETECT3)
1314 chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
1316 chip->hardware = WSS_HW_CS4236;
1320 chip->image[CS4231_IFACE_CTRL] =
1321 (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
1322 (chip->single_dma ? CS4231_SINGLE_DMA : 0);
1323 if (chip->hardware != WSS_HW_OPTI93X) {
1324 chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1325 chip->image[CS4231_ALT_FEATURE_2] =
1326 chip->hardware == WSS_HW_INTERWAVE ? 0xc2 : 0x01;
1328 ptr = (unsigned char *) &chip->image;
1329 regnum = (chip->hardware & WSS_HW_AD1848_MASK) ? 16 : 32;
1330 snd_wss_mce_down(chip);
1331 spin_lock_irqsave(&chip->reg_lock, flags);
1332 for (i = 0; i < regnum; i++) /* ok.. fill all registers */
1333 snd_wss_out(chip, i, *ptr++);
1334 spin_unlock_irqrestore(&chip->reg_lock, flags);
1335 snd_wss_mce_up(chip);
1336 snd_wss_mce_down(chip);
1340 /* ok.. try check hardware version for CS4236+ chips */
1341 if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
1342 if (chip->hardware == WSS_HW_CS4236B) {
1343 rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
1344 snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
1345 id = snd_cs4236_ext_in(chip, CS4236_VERSION);
1346 snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
1347 snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
1348 if ((id & 0x1f) == 0x1d) { /* CS4235 */
1349 chip->hardware = WSS_HW_CS4235;
1356 snd_printk(KERN_WARNING
1357 "unknown CS4235 chip "
1358 "(enhanced version = 0x%x)\n",
1361 } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */
1367 chip->hardware = WSS_HW_CS4236B;
1370 snd_printk(KERN_WARNING
1371 "unknown CS4236 chip "
1372 "(enhanced version = 0x%x)\n",
1375 } else if ((id & 0x1f) == 0x08) { /* CS4237B */
1376 chip->hardware = WSS_HW_CS4237B;
1384 snd_printk(KERN_WARNING
1385 "unknown CS4237B chip "
1386 "(enhanced version = 0x%x)\n",
1389 } else if ((id & 0x1f) == 0x09) { /* CS4238B */
1390 chip->hardware = WSS_HW_CS4238B;
1397 snd_printk(KERN_WARNING
1398 "unknown CS4238B chip "
1399 "(enhanced version = 0x%x)\n",
1402 } else if ((id & 0x1f) == 0x1e) { /* CS4239 */
1403 chip->hardware = WSS_HW_CS4239;
1410 snd_printk(KERN_WARNING
1411 "unknown CS4239 chip "
1412 "(enhanced version = 0x%x)\n",
1416 snd_printk(KERN_WARNING
1417 "unknown CS4236/CS423xB chip "
1418 "(enhanced version = 0x%x)\n", id);
1422 return 0; /* all things are ok.. */
1429 static struct snd_pcm_hardware snd_wss_playback =
1431 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1432 SNDRV_PCM_INFO_MMAP_VALID |
1433 SNDRV_PCM_INFO_RESUME |
1434 SNDRV_PCM_INFO_SYNC_START),
1435 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
1436 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
1437 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1442 .buffer_bytes_max = (128*1024),
1443 .period_bytes_min = 64,
1444 .period_bytes_max = (128*1024),
1446 .periods_max = 1024,
1450 static struct snd_pcm_hardware snd_wss_capture =
1452 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1453 SNDRV_PCM_INFO_MMAP_VALID |
1454 SNDRV_PCM_INFO_RESUME |
1455 SNDRV_PCM_INFO_SYNC_START),
1456 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
1457 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
1458 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1463 .buffer_bytes_max = (128*1024),
1464 .period_bytes_min = 64,
1465 .period_bytes_max = (128*1024),
1467 .periods_max = 1024,
1475 static int snd_wss_playback_open(struct snd_pcm_substream *substream)
1477 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1478 struct snd_pcm_runtime *runtime = substream->runtime;
1481 runtime->hw = snd_wss_playback;
1483 /* hardware limitation of older chipsets */
1484 if (chip->hardware & WSS_HW_AD1848_MASK)
1485 runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
1486 SNDRV_PCM_FMTBIT_S16_BE);
1488 /* hardware bug in InterWave chipset */
1489 if (chip->hardware == WSS_HW_INTERWAVE && chip->dma1 > 3)
1490 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;
1492 /* hardware limitation of cheap chips */
1493 if (chip->hardware == WSS_HW_CS4235 ||
1494 chip->hardware == WSS_HW_CS4239)
1495 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
1497 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
1498 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
1500 if (chip->claim_dma) {
1501 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
1505 err = snd_wss_open(chip, WSS_MODE_PLAY);
1507 if (chip->release_dma)
1508 chip->release_dma(chip, chip->dma_private_data, chip->dma1);
1509 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1512 chip->playback_substream = substream;
1513 snd_pcm_set_sync(substream);
1514 chip->rate_constraint(runtime);
1518 static int snd_wss_capture_open(struct snd_pcm_substream *substream)
1520 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1521 struct snd_pcm_runtime *runtime = substream->runtime;
1524 runtime->hw = snd_wss_capture;
1526 /* hardware limitation of older chipsets */
1527 if (chip->hardware & WSS_HW_AD1848_MASK)
1528 runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
1529 SNDRV_PCM_FMTBIT_S16_BE);
1531 /* hardware limitation of cheap chips */
1532 if (chip->hardware == WSS_HW_CS4235 ||
1533 chip->hardware == WSS_HW_CS4239 ||
1534 chip->hardware == WSS_HW_OPTI93X)
1535 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 |
1536 SNDRV_PCM_FMTBIT_S16_LE;
1538 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
1539 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
1541 if (chip->claim_dma) {
1542 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
1546 err = snd_wss_open(chip, WSS_MODE_RECORD);
1548 if (chip->release_dma)
1549 chip->release_dma(chip, chip->dma_private_data, chip->dma2);
1550 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1553 chip->capture_substream = substream;
1554 snd_pcm_set_sync(substream);
1555 chip->rate_constraint(runtime);
1559 static int snd_wss_playback_close(struct snd_pcm_substream *substream)
1561 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1563 chip->playback_substream = NULL;
1564 snd_wss_close(chip, WSS_MODE_PLAY);
1568 static int snd_wss_capture_close(struct snd_pcm_substream *substream)
1570 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1572 chip->capture_substream = NULL;
1573 snd_wss_close(chip, WSS_MODE_RECORD);
1577 static void snd_wss_thinkpad_twiddle(struct snd_wss *chip, int on)
1581 if (!chip->thinkpad_flag)
1584 outb(0x1c, AD1848_THINKPAD_CTL_PORT1);
1585 tmp = inb(AD1848_THINKPAD_CTL_PORT2);
1589 tmp |= AD1848_THINKPAD_CS4248_ENABLE_BIT;
1592 tmp &= ~AD1848_THINKPAD_CS4248_ENABLE_BIT;
1594 outb(tmp, AD1848_THINKPAD_CTL_PORT2);
1599 /* lowlevel suspend callback for CS4231 */
1600 static void snd_wss_suspend(struct snd_wss *chip)
1603 unsigned long flags;
1605 snd_pcm_suspend_all(chip->pcm);
1606 spin_lock_irqsave(&chip->reg_lock, flags);
1607 for (reg = 0; reg < 32; reg++)
1608 chip->image[reg] = snd_wss_in(chip, reg);
1609 spin_unlock_irqrestore(&chip->reg_lock, flags);
1610 if (chip->thinkpad_flag)
1611 snd_wss_thinkpad_twiddle(chip, 0);
1614 /* lowlevel resume callback for CS4231 */
1615 static void snd_wss_resume(struct snd_wss *chip)
1618 unsigned long flags;
1621 if (chip->thinkpad_flag)
1622 snd_wss_thinkpad_twiddle(chip, 1);
1623 snd_wss_mce_up(chip);
1624 spin_lock_irqsave(&chip->reg_lock, flags);
1625 for (reg = 0; reg < 32; reg++) {
1627 case CS4231_VERSION:
1630 snd_wss_out(chip, reg, chip->image[reg]);
1634 spin_unlock_irqrestore(&chip->reg_lock, flags);
1636 snd_wss_mce_down(chip);
1638 /* The following is a workaround to avoid freeze after resume on TP600E.
1639 This is the first half of copy of snd_wss_mce_down(), but doesn't
1640 include rescheduling. -- iwai
1642 snd_wss_busy_wait(chip);
1643 spin_lock_irqsave(&chip->reg_lock, flags);
1644 chip->mce_bit &= ~CS4231_MCE;
1645 timeout = wss_inb(chip, CS4231P(REGSEL));
1646 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
1647 spin_unlock_irqrestore(&chip->reg_lock, flags);
1648 if (timeout == 0x80)
1649 snd_printk(KERN_ERR "down [0x%lx]: serious init problem "
1650 "- codec still busy\n", chip->port);
1651 if ((timeout & CS4231_MCE) == 0 ||
1652 !(chip->hardware & (WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK))) {
1655 snd_wss_busy_wait(chip);
1658 #endif /* CONFIG_PM */
1660 int snd_wss_free(struct snd_wss *chip)
1662 release_and_free_resource(chip->res_port);
1663 release_and_free_resource(chip->res_cport);
1664 if (chip->irq >= 0) {
1665 disable_irq(chip->irq);
1666 if (!(chip->hwshare & WSS_HWSHARE_IRQ))
1667 free_irq(chip->irq, (void *) chip);
1669 if (!(chip->hwshare & WSS_HWSHARE_DMA1) && chip->dma1 >= 0) {
1670 snd_dma_disable(chip->dma1);
1671 free_dma(chip->dma1);
1673 if (!(chip->hwshare & WSS_HWSHARE_DMA2) &&
1674 chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
1675 snd_dma_disable(chip->dma2);
1676 free_dma(chip->dma2);
1679 snd_device_free(chip->card, chip->timer);
1683 EXPORT_SYMBOL(snd_wss_free);
1685 static int snd_wss_dev_free(struct snd_device *device)
1687 struct snd_wss *chip = device->device_data;
1688 return snd_wss_free(chip);
1691 const char *snd_wss_chip_id(struct snd_wss *chip)
1693 switch (chip->hardware) {
1696 case WSS_HW_CS4231A:
1700 case WSS_HW_CS4232A:
1706 case WSS_HW_CS4236B:
1708 case WSS_HW_CS4237B:
1710 case WSS_HW_CS4238B:
1714 case WSS_HW_INTERWAVE:
1715 return "AMD InterWave";
1716 case WSS_HW_OPL3SA2:
1717 return chip->card->shortname;
1720 case WSS_HW_OPTI93X:
1728 case WSS_HW_CMI8330:
1729 return "CMI8330/C3D";
1734 EXPORT_SYMBOL(snd_wss_chip_id);
1736 static int snd_wss_new(struct snd_card *card,
1737 unsigned short hardware,
1738 unsigned short hwshare,
1739 struct snd_wss **rchip)
1741 struct snd_wss *chip;
1744 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1747 chip->hardware = hardware;
1748 chip->hwshare = hwshare;
1750 spin_lock_init(&chip->reg_lock);
1751 mutex_init(&chip->mce_mutex);
1752 mutex_init(&chip->open_mutex);
1754 chip->rate_constraint = snd_wss_xrate;
1755 chip->set_playback_format = snd_wss_playback_format;
1756 chip->set_capture_format = snd_wss_capture_format;
1757 if (chip->hardware == WSS_HW_OPTI93X)
1758 memcpy(&chip->image, &snd_opti93x_original_image,
1759 sizeof(snd_opti93x_original_image));
1761 memcpy(&chip->image, &snd_wss_original_image,
1762 sizeof(snd_wss_original_image));
1763 if (chip->hardware & WSS_HW_AD1848_MASK) {
1764 chip->image[CS4231_PIN_CTRL] = 0;
1765 chip->image[CS4231_TEST_INIT] = 0;
1772 int snd_wss_create(struct snd_card *card,
1774 unsigned long cport,
1775 int irq, int dma1, int dma2,
1776 unsigned short hardware,
1777 unsigned short hwshare,
1778 struct snd_wss **rchip)
1780 static struct snd_device_ops ops = {
1781 .dev_free = snd_wss_dev_free,
1783 struct snd_wss *chip;
1786 err = snd_wss_new(card, hardware, hwshare, &chip);
1794 chip->res_port = request_region(port, 4, "WSS");
1795 if (!chip->res_port) {
1796 snd_printk(KERN_ERR "wss: can't grab port 0x%lx\n", port);
1801 if ((long)cport >= 0) {
1802 chip->res_cport = request_region(cport, 8, "CS4232 Control");
1803 if (!chip->res_cport) {
1805 "wss: can't grab control port 0x%lx\n", cport);
1810 chip->cport = cport;
1811 if (!(hwshare & WSS_HWSHARE_IRQ))
1812 if (request_irq(irq, snd_wss_interrupt, IRQF_DISABLED,
1813 "WSS", (void *) chip)) {
1814 snd_printk(KERN_ERR "wss: can't grab IRQ %d\n", irq);
1819 if (!(hwshare & WSS_HWSHARE_DMA1) && request_dma(dma1, "WSS - 1")) {
1820 snd_printk(KERN_ERR "wss: can't grab DMA1 %d\n", dma1);
1825 if (!(hwshare & WSS_HWSHARE_DMA2) && dma1 != dma2 &&
1826 dma2 >= 0 && request_dma(dma2, "WSS - 2")) {
1827 snd_printk(KERN_ERR "wss: can't grab DMA2 %d\n", dma2);
1831 if (dma1 == dma2 || dma2 < 0) {
1832 chip->single_dma = 1;
1833 chip->dma2 = chip->dma1;
1837 if (hardware == WSS_HW_THINKPAD) {
1838 chip->thinkpad_flag = 1;
1839 chip->hardware = WSS_HW_DETECT; /* reset */
1840 snd_wss_thinkpad_twiddle(chip, 1);
1844 if (snd_wss_probe(chip) < 0) {
1851 if (chip->hardware & WSS_HW_CS4232_MASK) {
1852 if (chip->res_cport == NULL)
1853 snd_printk(KERN_ERR "CS4232 control port features are "
1854 "not accessible\n");
1858 /* Register device */
1859 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1866 /* Power Management */
1867 chip->suspend = snd_wss_suspend;
1868 chip->resume = snd_wss_resume;
1874 EXPORT_SYMBOL(snd_wss_create);
1876 static struct snd_pcm_ops snd_wss_playback_ops = {
1877 .open = snd_wss_playback_open,
1878 .close = snd_wss_playback_close,
1879 .ioctl = snd_pcm_lib_ioctl,
1880 .hw_params = snd_wss_playback_hw_params,
1881 .hw_free = snd_wss_playback_hw_free,
1882 .prepare = snd_wss_playback_prepare,
1883 .trigger = snd_wss_trigger,
1884 .pointer = snd_wss_playback_pointer,
1887 static struct snd_pcm_ops snd_wss_capture_ops = {
1888 .open = snd_wss_capture_open,
1889 .close = snd_wss_capture_close,
1890 .ioctl = snd_pcm_lib_ioctl,
1891 .hw_params = snd_wss_capture_hw_params,
1892 .hw_free = snd_wss_capture_hw_free,
1893 .prepare = snd_wss_capture_prepare,
1894 .trigger = snd_wss_trigger,
1895 .pointer = snd_wss_capture_pointer,
1898 int snd_wss_pcm(struct snd_wss *chip, int device, struct snd_pcm **rpcm)
1900 struct snd_pcm *pcm;
1903 err = snd_pcm_new(chip->card, "WSS", device, 1, 1, &pcm);
1907 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_wss_playback_ops);
1908 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_wss_capture_ops);
1911 pcm->private_data = chip;
1912 pcm->info_flags = 0;
1913 if (chip->single_dma)
1914 pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;
1915 if (chip->hardware != WSS_HW_INTERWAVE)
1916 pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;
1917 strcpy(pcm->name, snd_wss_chip_id(chip));
1919 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1921 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
1928 EXPORT_SYMBOL(snd_wss_pcm);
1930 static void snd_wss_timer_free(struct snd_timer *timer)
1932 struct snd_wss *chip = timer->private_data;
1936 int snd_wss_timer(struct snd_wss *chip, int device, struct snd_timer **rtimer)
1938 struct snd_timer *timer;
1939 struct snd_timer_id tid;
1942 /* Timer initialization */
1943 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1944 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
1945 tid.card = chip->card->number;
1946 tid.device = device;
1948 if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
1950 strcpy(timer->name, snd_wss_chip_id(chip));
1951 timer->private_data = chip;
1952 timer->private_free = snd_wss_timer_free;
1953 timer->hw = snd_wss_timer_table;
1954 chip->timer = timer;
1959 EXPORT_SYMBOL(snd_wss_timer);
1965 static int snd_wss_info_mux(struct snd_kcontrol *kcontrol,
1966 struct snd_ctl_elem_info *uinfo)
1968 static char *texts[4] = {
1969 "Line", "Aux", "Mic", "Mix"
1971 static char *opl3sa_texts[4] = {
1972 "Line", "CD", "Mic", "Mix"
1974 static char *gusmax_texts[4] = {
1975 "Line", "Synth", "Mic", "Mix"
1977 char **ptexts = texts;
1978 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
1980 if (snd_BUG_ON(!chip->card))
1982 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1984 uinfo->value.enumerated.items = 4;
1985 if (uinfo->value.enumerated.item > 3)
1986 uinfo->value.enumerated.item = 3;
1987 if (!strcmp(chip->card->driver, "GUS MAX"))
1988 ptexts = gusmax_texts;
1989 switch (chip->hardware) {
1990 case WSS_HW_INTERWAVE:
1991 ptexts = gusmax_texts;
1993 case WSS_HW_OPL3SA2:
1994 ptexts = opl3sa_texts;
1997 strcpy(uinfo->value.enumerated.name, ptexts[uinfo->value.enumerated.item]);
2001 static int snd_wss_get_mux(struct snd_kcontrol *kcontrol,
2002 struct snd_ctl_elem_value *ucontrol)
2004 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2005 unsigned long flags;
2007 spin_lock_irqsave(&chip->reg_lock, flags);
2008 ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
2009 ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
2010 spin_unlock_irqrestore(&chip->reg_lock, flags);
2014 static int snd_wss_put_mux(struct snd_kcontrol *kcontrol,
2015 struct snd_ctl_elem_value *ucontrol)
2017 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2018 unsigned long flags;
2019 unsigned short left, right;
2022 if (ucontrol->value.enumerated.item[0] > 3 ||
2023 ucontrol->value.enumerated.item[1] > 3)
2025 left = ucontrol->value.enumerated.item[0] << 6;
2026 right = ucontrol->value.enumerated.item[1] << 6;
2027 spin_lock_irqsave(&chip->reg_lock, flags);
2028 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
2029 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
2030 change = left != chip->image[CS4231_LEFT_INPUT] ||
2031 right != chip->image[CS4231_RIGHT_INPUT];
2032 snd_wss_out(chip, CS4231_LEFT_INPUT, left);
2033 snd_wss_out(chip, CS4231_RIGHT_INPUT, right);
2034 spin_unlock_irqrestore(&chip->reg_lock, flags);
2038 int snd_wss_info_single(struct snd_kcontrol *kcontrol,
2039 struct snd_ctl_elem_info *uinfo)
2041 int mask = (kcontrol->private_value >> 16) & 0xff;
2043 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2045 uinfo->value.integer.min = 0;
2046 uinfo->value.integer.max = mask;
2049 EXPORT_SYMBOL(snd_wss_info_single);
2051 int snd_wss_get_single(struct snd_kcontrol *kcontrol,
2052 struct snd_ctl_elem_value *ucontrol)
2054 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2055 unsigned long flags;
2056 int reg = kcontrol->private_value & 0xff;
2057 int shift = (kcontrol->private_value >> 8) & 0xff;
2058 int mask = (kcontrol->private_value >> 16) & 0xff;
2059 int invert = (kcontrol->private_value >> 24) & 0xff;
2061 spin_lock_irqsave(&chip->reg_lock, flags);
2062 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
2063 spin_unlock_irqrestore(&chip->reg_lock, flags);
2065 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
2068 EXPORT_SYMBOL(snd_wss_get_single);
2070 int snd_wss_put_single(struct snd_kcontrol *kcontrol,
2071 struct snd_ctl_elem_value *ucontrol)
2073 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2074 unsigned long flags;
2075 int reg = kcontrol->private_value & 0xff;
2076 int shift = (kcontrol->private_value >> 8) & 0xff;
2077 int mask = (kcontrol->private_value >> 16) & 0xff;
2078 int invert = (kcontrol->private_value >> 24) & 0xff;
2082 val = (ucontrol->value.integer.value[0] & mask);
2086 spin_lock_irqsave(&chip->reg_lock, flags);
2087 val = (chip->image[reg] & ~(mask << shift)) | val;
2088 change = val != chip->image[reg];
2089 snd_wss_out(chip, reg, val);
2090 spin_unlock_irqrestore(&chip->reg_lock, flags);
2093 EXPORT_SYMBOL(snd_wss_put_single);
2095 int snd_wss_info_double(struct snd_kcontrol *kcontrol,
2096 struct snd_ctl_elem_info *uinfo)
2098 int mask = (kcontrol->private_value >> 24) & 0xff;
2100 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2102 uinfo->value.integer.min = 0;
2103 uinfo->value.integer.max = mask;
2106 EXPORT_SYMBOL(snd_wss_info_double);
2108 int snd_wss_get_double(struct snd_kcontrol *kcontrol,
2109 struct snd_ctl_elem_value *ucontrol)
2111 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2112 unsigned long flags;
2113 int left_reg = kcontrol->private_value & 0xff;
2114 int right_reg = (kcontrol->private_value >> 8) & 0xff;
2115 int shift_left = (kcontrol->private_value >> 16) & 0x07;
2116 int shift_right = (kcontrol->private_value >> 19) & 0x07;
2117 int mask = (kcontrol->private_value >> 24) & 0xff;
2118 int invert = (kcontrol->private_value >> 22) & 1;
2120 spin_lock_irqsave(&chip->reg_lock, flags);
2121 ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
2122 ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
2123 spin_unlock_irqrestore(&chip->reg_lock, flags);
2125 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
2126 ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
2130 EXPORT_SYMBOL(snd_wss_get_double);
2132 int snd_wss_put_double(struct snd_kcontrol *kcontrol,
2133 struct snd_ctl_elem_value *ucontrol)
2135 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2136 unsigned long flags;
2137 int left_reg = kcontrol->private_value & 0xff;
2138 int right_reg = (kcontrol->private_value >> 8) & 0xff;
2139 int shift_left = (kcontrol->private_value >> 16) & 0x07;
2140 int shift_right = (kcontrol->private_value >> 19) & 0x07;
2141 int mask = (kcontrol->private_value >> 24) & 0xff;
2142 int invert = (kcontrol->private_value >> 22) & 1;
2144 unsigned short val1, val2;
2146 val1 = ucontrol->value.integer.value[0] & mask;
2147 val2 = ucontrol->value.integer.value[1] & mask;
2152 val1 <<= shift_left;
2153 val2 <<= shift_right;
2154 spin_lock_irqsave(&chip->reg_lock, flags);
2155 if (left_reg != right_reg) {
2156 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
2157 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
2158 change = val1 != chip->image[left_reg] ||
2159 val2 != chip->image[right_reg];
2160 snd_wss_out(chip, left_reg, val1);
2161 snd_wss_out(chip, right_reg, val2);
2163 mask = (mask << shift_left) | (mask << shift_right);
2164 val1 = (chip->image[left_reg] & ~mask) | val1 | val2;
2165 change = val1 != chip->image[left_reg];
2166 snd_wss_out(chip, left_reg, val1);
2168 spin_unlock_irqrestore(&chip->reg_lock, flags);
2171 EXPORT_SYMBOL(snd_wss_put_double);
2173 static const DECLARE_TLV_DB_SCALE(db_scale_6bit, -9450, 150, 0);
2174 static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0);
2175 static const DECLARE_TLV_DB_SCALE(db_scale_rec_gain, 0, 150, 0);
2177 static struct snd_kcontrol_new snd_ad1848_controls[] = {
2178 WSS_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT,
2180 WSS_DOUBLE_TLV("PCM Playback Volume", 0,
2181 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1,
2183 WSS_DOUBLE("Aux Playback Switch", 0,
2184 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2185 WSS_DOUBLE_TLV("Aux Playback Volume", 0,
2186 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1,
2187 db_scale_5bit_12db_max),
2188 WSS_DOUBLE("Aux Playback Switch", 1,
2189 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2190 WSS_DOUBLE_TLV("Aux Playback Volume", 1,
2191 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1,
2192 db_scale_5bit_12db_max),
2193 WSS_DOUBLE_TLV("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT,
2194 0, 0, 15, 0, db_scale_rec_gain),
2196 .name = "Capture Source",
2197 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2198 .info = snd_wss_info_mux,
2199 .get = snd_wss_get_mux,
2200 .put = snd_wss_put_mux,
2202 WSS_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
2203 WSS_SINGLE_TLV("Loopback Capture Volume", 0, CS4231_LOOPBACK, 1, 63, 0,
2207 static struct snd_kcontrol_new snd_wss_controls[] = {
2208 WSS_DOUBLE("PCM Playback Switch", 0,
2209 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
2210 WSS_DOUBLE("PCM Playback Volume", 0,
2211 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
2212 WSS_DOUBLE("Line Playback Switch", 0,
2213 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
2214 WSS_DOUBLE("Line Playback Volume", 0,
2215 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
2216 WSS_DOUBLE("Aux Playback Switch", 0,
2217 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2218 WSS_DOUBLE("Aux Playback Volume", 0,
2219 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
2220 WSS_DOUBLE("Aux Playback Switch", 1,
2221 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2222 WSS_DOUBLE("Aux Playback Volume", 1,
2223 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
2224 WSS_SINGLE("Mono Playback Switch", 0,
2225 CS4231_MONO_CTRL, 7, 1, 1),
2226 WSS_SINGLE("Mono Playback Volume", 0,
2227 CS4231_MONO_CTRL, 0, 15, 1),
2228 WSS_SINGLE("Mono Output Playback Switch", 0,
2229 CS4231_MONO_CTRL, 6, 1, 1),
2230 WSS_SINGLE("Mono Output Playback Bypass", 0,
2231 CS4231_MONO_CTRL, 5, 1, 0),
2232 WSS_DOUBLE("Capture Volume", 0,
2233 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
2235 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2236 .name = "Capture Source",
2237 .info = snd_wss_info_mux,
2238 .get = snd_wss_get_mux,
2239 .put = snd_wss_put_mux,
2241 WSS_DOUBLE("Mic Boost", 0,
2242 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
2243 WSS_SINGLE("Loopback Capture Switch", 0,
2244 CS4231_LOOPBACK, 0, 1, 0),
2245 WSS_SINGLE("Loopback Capture Volume", 0,
2246 CS4231_LOOPBACK, 2, 63, 1)
2249 static struct snd_kcontrol_new snd_opti93x_controls[] = {
2250 WSS_DOUBLE("Master Playback Switch", 0,
2251 OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 7, 7, 1, 1),
2252 WSS_DOUBLE("Master Playback Volume", 0,
2253 OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 1, 1, 31, 1),
2254 WSS_DOUBLE("PCM Playback Switch", 0,
2255 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
2256 WSS_DOUBLE("PCM Playback Volume", 0,
2257 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 31, 1),
2258 WSS_DOUBLE("FM Playback Switch", 0,
2259 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2260 WSS_DOUBLE("FM Playback Volume", 0,
2261 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 1, 1, 15, 1),
2262 WSS_DOUBLE("Line Playback Switch", 0,
2263 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
2264 WSS_DOUBLE("Line Playback Volume", 0,
2265 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 15, 1),
2266 WSS_DOUBLE("Mic Playback Switch", 0,
2267 OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 7, 7, 1, 1),
2268 WSS_DOUBLE("Mic Playback Volume", 0,
2269 OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 1, 1, 15, 1),
2270 WSS_DOUBLE("Mic Boost", 0,
2271 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
2272 WSS_DOUBLE("CD Playback Switch", 0,
2273 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2274 WSS_DOUBLE("CD Playback Volume", 0,
2275 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 1, 1, 15, 1),
2276 WSS_DOUBLE("Aux Playback Switch", 0,
2277 OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 7, 7, 1, 1),
2278 WSS_DOUBLE("Aux Playback Volume", 0,
2279 OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 1, 1, 15, 1),
2280 WSS_DOUBLE("Capture Volume", 0,
2281 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
2283 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2284 .name = "Capture Source",
2285 .info = snd_wss_info_mux,
2286 .get = snd_wss_get_mux,
2287 .put = snd_wss_put_mux,
2291 int snd_wss_mixer(struct snd_wss *chip)
2293 struct snd_card *card;
2297 if (snd_BUG_ON(!chip || !chip->pcm))
2302 strcpy(card->mixername, chip->pcm->name);
2304 if (chip->hardware == WSS_HW_OPTI93X)
2305 for (idx = 0; idx < ARRAY_SIZE(snd_opti93x_controls); idx++) {
2306 err = snd_ctl_add(card,
2307 snd_ctl_new1(&snd_opti93x_controls[idx],
2312 else if (chip->hardware & WSS_HW_AD1848_MASK)
2313 for (idx = 0; idx < ARRAY_SIZE(snd_ad1848_controls); idx++) {
2314 err = snd_ctl_add(card,
2315 snd_ctl_new1(&snd_ad1848_controls[idx],
2321 for (idx = 0; idx < ARRAY_SIZE(snd_wss_controls); idx++) {
2322 err = snd_ctl_add(card,
2323 snd_ctl_new1(&snd_wss_controls[idx],
2330 EXPORT_SYMBOL(snd_wss_mixer);
2332 const struct snd_pcm_ops *snd_wss_get_pcm_ops(int direction)
2334 return direction == SNDRV_PCM_STREAM_PLAYBACK ?
2335 &snd_wss_playback_ops : &snd_wss_capture_ops;
2337 EXPORT_SYMBOL(snd_wss_get_pcm_ops);
2343 static int __init alsa_wss_init(void)
2348 static void __exit alsa_wss_exit(void)
2352 module_init(alsa_wss_init);
2353 module_exit(alsa_wss_exit);