1 // SPDX-License-Identifier: GPL-2.0-only
3 * HD-audio controller helpers
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/export.h>
9 #include <sound/core.h>
10 #include <sound/hdaudio.h>
11 #include <sound/hda_register.h>
13 /* clear CORB read pointer properly */
14 static void azx_clear_corbrp(struct hdac_bus *bus)
18 for (timeout = 1000; timeout > 0; timeout--) {
19 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
24 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
25 snd_hdac_chip_readw(bus, CORBRP));
27 snd_hdac_chip_writew(bus, CORBRP, 0);
28 for (timeout = 1000; timeout > 0; timeout--) {
29 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
34 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
35 snd_hdac_chip_readw(bus, CORBRP));
39 * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
40 * @bus: HD-audio core bus
42 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
44 WARN_ON_ONCE(!bus->rb.area);
46 spin_lock_irq(&bus->reg_lock);
48 bus->corb.addr = bus->rb.addr;
49 bus->corb.buf = (__le32 *)bus->rb.area;
50 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
51 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
53 /* set the corb size to 256 entries (ULI requires explicitly) */
54 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
55 /* set the corb write pointer to 0 */
56 snd_hdac_chip_writew(bus, CORBWP, 0);
58 /* reset the corb hw read pointer */
59 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
60 if (!bus->corbrp_self_clear)
61 azx_clear_corbrp(bus);
64 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
67 bus->rirb.addr = bus->rb.addr + 2048;
68 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
69 bus->rirb.wp = bus->rirb.rp = 0;
70 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
71 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
72 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
74 /* set the rirb size to 256 entries (ULI requires explicitly) */
75 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
76 /* reset the rirb hw write pointer */
77 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
78 /* set N=1, get RIRB response interrupt for new entry */
79 snd_hdac_chip_writew(bus, RINTCNT, 1);
80 /* enable rirb dma and response irq */
81 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
82 spin_unlock_irq(&bus->reg_lock);
84 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
86 /* wait for cmd dmas till they are stopped */
87 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
89 unsigned long timeout;
91 timeout = jiffies + msecs_to_jiffies(100);
92 while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
93 && time_before(jiffies, timeout))
96 timeout = jiffies + msecs_to_jiffies(100);
97 while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
98 && time_before(jiffies, timeout))
103 * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
104 * @bus: HD-audio core bus
106 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
108 spin_lock_irq(&bus->reg_lock);
109 /* disable ringbuffer DMAs */
110 snd_hdac_chip_writeb(bus, RIRBCTL, 0);
111 snd_hdac_chip_writeb(bus, CORBCTL, 0);
112 spin_unlock_irq(&bus->reg_lock);
114 hdac_wait_for_cmd_dmas(bus);
116 spin_lock_irq(&bus->reg_lock);
117 /* disable unsolicited responses */
118 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
119 spin_unlock_irq(&bus->reg_lock);
121 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
123 static unsigned int azx_command_addr(u32 cmd)
125 unsigned int addr = cmd >> 28;
127 if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
133 * snd_hdac_bus_send_cmd - send a command verb via CORB
134 * @bus: HD-audio core bus
135 * @val: encoded verb value to send
137 * Returns zero for success or a negative error code.
139 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
141 unsigned int addr = azx_command_addr(val);
144 spin_lock_irq(&bus->reg_lock);
146 bus->last_cmd[azx_command_addr(val)] = val;
148 /* add command to corb */
149 wp = snd_hdac_chip_readw(bus, CORBWP);
151 /* something wrong, controller likely turned to D3 */
152 spin_unlock_irq(&bus->reg_lock);
156 wp %= AZX_MAX_CORB_ENTRIES;
158 rp = snd_hdac_chip_readw(bus, CORBRP);
160 /* oops, it's full */
161 spin_unlock_irq(&bus->reg_lock);
165 bus->rirb.cmds[addr]++;
166 bus->corb.buf[wp] = cpu_to_le32(val);
167 snd_hdac_chip_writew(bus, CORBWP, wp);
169 spin_unlock_irq(&bus->reg_lock);
173 EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
175 #define AZX_RIRB_EX_UNSOL_EV (1<<4)
178 * snd_hdac_bus_update_rirb - retrieve RIRB entries
179 * @bus: HD-audio core bus
181 * Usually called from interrupt handler.
183 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
189 wp = snd_hdac_chip_readw(bus, RIRBWP);
191 /* something wrong, controller likely turned to D3 */
195 if (wp == bus->rirb.wp)
199 while (bus->rirb.rp != wp) {
201 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
203 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
204 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
205 res = le32_to_cpu(bus->rirb.buf[rp]);
207 if (addr >= HDA_MAX_CODECS) {
209 "spurious response %#x:%#x, rp = %d, wp = %d",
210 res, res_ex, bus->rirb.rp, wp);
212 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
213 snd_hdac_bus_queue_event(bus, res, res_ex);
214 else if (bus->rirb.cmds[addr]) {
215 bus->rirb.res[addr] = res;
216 bus->rirb.cmds[addr]--;
218 dev_err_ratelimited(bus->dev,
219 "spurious response %#x:%#x, last cmd=%#08x\n",
220 res, res_ex, bus->last_cmd[addr]);
224 EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
227 * snd_hdac_bus_get_response - receive a response via RIRB
228 * @bus: HD-audio core bus
229 * @addr: codec address
230 * @res: pointer to store the value, NULL when not needed
232 * Returns zero if a value is read, or a negative error code.
234 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
237 unsigned long timeout;
238 unsigned long loopcounter;
240 timeout = jiffies + msecs_to_jiffies(1000);
242 for (loopcounter = 0;; loopcounter++) {
243 spin_lock_irq(&bus->reg_lock);
244 if (!bus->rirb.cmds[addr]) {
246 *res = bus->rirb.res[addr]; /* the last value */
247 spin_unlock_irq(&bus->reg_lock);
250 spin_unlock_irq(&bus->reg_lock);
251 if (time_after(jiffies, timeout))
253 if (loopcounter > 3000)
254 msleep(2); /* temporary workaround */
263 EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
265 #define HDAC_MAX_CAPS 10
267 * snd_hdac_bus_parse_capabilities - parse capability structure
268 * @bus: the pointer to bus object
270 * Returns 0 if successful, or a negative error code.
272 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
274 unsigned int cur_cap;
276 unsigned int counter = 0;
278 offset = snd_hdac_chip_readw(bus, LLCH);
280 /* Lets walk the linked capabilities list */
282 cur_cap = _snd_hdac_chip_readl(bus, offset);
284 dev_dbg(bus->dev, "Capability version: 0x%x\n",
285 (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF);
287 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
288 (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF);
291 dev_dbg(bus->dev, "Invalid capability reg read\n");
295 switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) {
297 dev_dbg(bus->dev, "Found ML capability\n");
298 bus->mlcap = bus->remap_addr + offset;
302 dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
303 bus->gtscap = bus->remap_addr + offset;
307 /* PP capability found, the Audio DSP is present */
308 dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
309 bus->ppcap = bus->remap_addr + offset;
313 /* SPIB capability found, handler function */
314 dev_dbg(bus->dev, "Found SPB capability\n");
315 bus->spbcap = bus->remap_addr + offset;
318 case AZX_DRSM_CAP_ID:
319 /* DMA resume capability found, handler function */
320 dev_dbg(bus->dev, "Found DRSM capability\n");
321 bus->drsmcap = bus->remap_addr + offset;
325 dev_err(bus->dev, "Unknown capability %d\n", cur_cap);
332 if (counter > HDAC_MAX_CAPS) {
333 dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
337 /* read the offset of next capability */
338 offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK;
344 EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities);
351 * snd_hdac_bus_enter_link_reset - enter link reset
352 * @bus: HD-audio core bus
354 * Enter to the link reset state.
356 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
358 unsigned long timeout;
360 /* reset controller */
361 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
363 timeout = jiffies + msecs_to_jiffies(100);
364 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
365 time_before(jiffies, timeout))
366 usleep_range(500, 1000);
368 EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
371 * snd_hdac_bus_exit_link_reset - exit link reset
372 * @bus: HD-audio core bus
374 * Exit from the link reset state.
376 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
378 unsigned long timeout;
380 snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET);
382 timeout = jiffies + msecs_to_jiffies(100);
383 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
384 usleep_range(500, 1000);
386 EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
388 /* reset codec link */
389 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset)
395 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
397 /* reset controller */
398 snd_hdac_bus_enter_link_reset(bus);
400 /* delay for >= 100us for codec PLL to settle per spec
401 * Rev 0.9 section 5.5.1
403 usleep_range(500, 1000);
405 /* Bring controller out of reset */
406 snd_hdac_bus_exit_link_reset(bus);
408 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
409 usleep_range(1000, 1200);
412 /* check to see if controller is ready */
413 if (!snd_hdac_chip_readb(bus, GCTL)) {
414 dev_dbg(bus->dev, "controller not ready!\n");
418 /* Accept unsolicited responses */
419 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
422 if (!bus->codec_mask) {
423 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
424 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
429 EXPORT_SYMBOL_GPL(snd_hdac_bus_reset_link);
431 /* enable interrupts */
432 static void azx_int_enable(struct hdac_bus *bus)
434 /* enable controller CIE and GIE */
435 snd_hdac_chip_updatel(bus, INTCTL,
436 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN,
437 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
440 /* disable interrupts */
441 static void azx_int_disable(struct hdac_bus *bus)
443 struct hdac_stream *azx_dev;
445 /* disable interrupts in stream descriptor */
446 list_for_each_entry(azx_dev, &bus->stream_list, list)
447 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
449 /* disable SIE for all streams */
450 snd_hdac_chip_writeb(bus, INTCTL, 0);
452 /* disable controller CIE and GIE */
453 snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0);
456 /* clear interrupts */
457 static void azx_int_clear(struct hdac_bus *bus)
459 struct hdac_stream *azx_dev;
461 /* clear stream status */
462 list_for_each_entry(azx_dev, &bus->stream_list, list)
463 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
466 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
468 /* clear rirb status */
469 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
471 /* clear int status */
472 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
476 * snd_hdac_bus_init_chip - reset and start the controller registers
477 * @bus: HD-audio core bus
478 * @full_reset: Do full reset
480 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
485 /* reset controller */
486 snd_hdac_bus_reset_link(bus, full_reset);
488 /* clear interrupts */
491 /* initialize the codec command I/O */
492 snd_hdac_bus_init_cmd_io(bus);
494 /* enable interrupts after CORB/RIRB buffers are initialized above */
497 /* program the position buffer */
498 if (bus->use_posbuf && bus->posbuf.addr) {
499 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
500 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
503 bus->chip_init = true;
506 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
509 * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
510 * @bus: HD-audio core bus
512 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
517 /* disable interrupts */
518 azx_int_disable(bus);
521 /* disable CORB/RIRB */
522 snd_hdac_bus_stop_cmd_io(bus);
524 /* disable position buffer */
525 if (bus->posbuf.addr) {
526 snd_hdac_chip_writel(bus, DPLBASE, 0);
527 snd_hdac_chip_writel(bus, DPUBASE, 0);
530 bus->chip_init = false;
532 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
535 * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
536 * @bus: HD-audio core bus
537 * @status: INTSTS register value
538 * @ask: callback to be called for woken streams
540 * Returns the bits of handled streams, or zero if no stream is handled.
542 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
543 void (*ack)(struct hdac_bus *,
544 struct hdac_stream *))
546 struct hdac_stream *azx_dev;
550 list_for_each_entry(azx_dev, &bus->stream_list, list) {
551 if (status & azx_dev->sd_int_sta_mask) {
552 sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
553 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
554 handled |= 1 << azx_dev->index;
555 if (!azx_dev->substream || !azx_dev->running ||
556 !(sd_status & SD_INT_COMPLETE))
564 EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
567 * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
568 * @bus: HD-audio core bus
570 * Call this after assigning the all streams.
571 * Returns zero for success, or a negative error code.
573 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
575 struct hdac_stream *s;
579 list_for_each_entry(s, &bus->stream_list, list) {
580 /* allocate memory for the BDL for each stream */
581 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
588 if (WARN_ON(!num_streams))
590 /* allocate memory for the position buffer */
591 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
592 num_streams * 8, &bus->posbuf);
595 list_for_each_entry(s, &bus->stream_list, list)
596 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
598 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
599 return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
600 PAGE_SIZE, &bus->rb);
602 EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
605 * snd_hdac_bus_free_stream_pages - release BDL and other buffers
606 * @bus: HD-audio core bus
608 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
610 struct hdac_stream *s;
612 list_for_each_entry(s, &bus->stream_list, list) {
614 bus->io_ops->dma_free_pages(bus, &s->bdl);
618 bus->io_ops->dma_free_pages(bus, &bus->rb);
619 if (bus->posbuf.area)
620 bus->io_ops->dma_free_pages(bus, &bus->posbuf);
622 EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);