1 // SPDX-License-Identifier: GPL-2.0-only
3 * dice_stream.c - a part of driver for DICE based devices
5 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
6 * Copyright (c) 2014 Takashi Sakamoto <o-takashi@sakamocchi.jp>
11 #define CALLBACK_TIMEOUT 200
12 #define NOTIFICATION_TIMEOUT_MS (2 * MSEC_PER_SEC)
19 const unsigned int snd_dice_rates[SND_DICE_RATES_COUNT] = {
32 int snd_dice_stream_get_rate_mode(struct snd_dice *dice, unsigned int rate,
33 enum snd_dice_rate_mode *mode)
35 /* Corresponding to each entry in snd_dice_rates. */
36 static const enum snd_dice_rate_mode modes[] = {
37 [0] = SND_DICE_RATE_MODE_LOW,
38 [1] = SND_DICE_RATE_MODE_LOW,
39 [2] = SND_DICE_RATE_MODE_LOW,
40 [3] = SND_DICE_RATE_MODE_MIDDLE,
41 [4] = SND_DICE_RATE_MODE_MIDDLE,
42 [5] = SND_DICE_RATE_MODE_HIGH,
43 [6] = SND_DICE_RATE_MODE_HIGH,
47 for (i = 0; i < ARRAY_SIZE(snd_dice_rates); i++) {
48 if (!(dice->clock_caps & BIT(i)))
50 if (snd_dice_rates[i] != rate)
61 * This operation has an effect to synchronize GLOBAL_STATUS/GLOBAL_SAMPLE_RATE
62 * to GLOBAL_STATUS. Especially, just after powering on, these are different.
64 static int ensure_phase_lock(struct snd_dice *dice, unsigned int rate)
71 err = snd_dice_transaction_read_global(dice, GLOBAL_CLOCK_SELECT,
76 data = be32_to_cpu(reg);
78 data &= ~CLOCK_RATE_MASK;
79 for (i = 0; i < ARRAY_SIZE(snd_dice_rates); ++i) {
80 if (snd_dice_rates[i] == rate)
83 if (i == ARRAY_SIZE(snd_dice_rates))
85 data |= i << CLOCK_RATE_SHIFT;
87 if (completion_done(&dice->clock_accepted))
88 reinit_completion(&dice->clock_accepted);
90 reg = cpu_to_be32(data);
91 err = snd_dice_transaction_write_global(dice, GLOBAL_CLOCK_SELECT,
96 if (wait_for_completion_timeout(&dice->clock_accepted,
97 msecs_to_jiffies(NOTIFICATION_TIMEOUT_MS)) == 0) {
99 * Old versions of Dice firmware transfer no notification when
100 * the same clock status as current one is set. In this case,
101 * just check current clock status.
103 err = snd_dice_transaction_read_global(dice, GLOBAL_STATUS,
104 &nominal, sizeof(nominal));
107 if (!(be32_to_cpu(nominal) & STATUS_SOURCE_LOCKED))
114 static int get_register_params(struct snd_dice *dice,
115 struct reg_params *tx_params,
116 struct reg_params *rx_params)
121 err = snd_dice_transaction_read_tx(dice, TX_NUMBER, reg, sizeof(reg));
125 min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS);
126 tx_params->size = be32_to_cpu(reg[1]) * 4;
128 err = snd_dice_transaction_read_rx(dice, RX_NUMBER, reg, sizeof(reg));
132 min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS);
133 rx_params->size = be32_to_cpu(reg[1]) * 4;
138 static void release_resources(struct snd_dice *dice)
142 for (i = 0; i < MAX_STREAMS; ++i) {
143 fw_iso_resources_free(&dice->tx_resources[i]);
144 fw_iso_resources_free(&dice->rx_resources[i]);
148 static void stop_streams(struct snd_dice *dice, enum amdtp_stream_direction dir,
149 struct reg_params *params)
154 for (i = 0; i < params->count; i++) {
155 reg = cpu_to_be32((u32)-1);
156 if (dir == AMDTP_IN_STREAM) {
157 amdtp_stream_stop(&dice->tx_stream[i]);
159 snd_dice_transaction_write_tx(dice,
160 params->size * i + TX_ISOCHRONOUS,
163 amdtp_stream_stop(&dice->rx_stream[i]);
165 snd_dice_transaction_write_rx(dice,
166 params->size * i + RX_ISOCHRONOUS,
172 static int keep_resources(struct snd_dice *dice, struct amdtp_stream *stream,
173 struct fw_iso_resources *resources, unsigned int rate,
174 unsigned int pcm_chs, unsigned int midi_ports)
176 bool double_pcm_frames;
180 // At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in
181 // one data block of AMDTP packet. Thus sampling transfer frequency is
182 // a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are
183 // transferred on AMDTP packets at 96 kHz. Two successive samples of a
184 // channel are stored consecutively in the packet. This quirk is called
186 // For this quirk, blocking mode is required and PCM buffer size should
187 // be aligned to SYT_INTERVAL.
188 double_pcm_frames = rate > 96000;
189 if (double_pcm_frames) {
194 err = amdtp_am824_set_parameters(stream, rate, pcm_chs, midi_ports,
199 if (double_pcm_frames) {
202 for (i = 0; i < pcm_chs; i++) {
203 amdtp_am824_set_pcm_position(stream, i, i * 2);
204 amdtp_am824_set_pcm_position(stream, i + pcm_chs,
209 return fw_iso_resources_allocate(resources,
210 amdtp_stream_get_max_payload(stream),
211 fw_parent_device(dice->unit)->max_speed);
214 static int keep_dual_resources(struct snd_dice *dice, unsigned int rate,
215 enum amdtp_stream_direction dir,
216 struct reg_params *params)
218 enum snd_dice_rate_mode mode;
222 err = snd_dice_stream_get_rate_mode(dice, rate, &mode);
226 for (i = 0; i < params->count; ++i) {
228 struct amdtp_stream *stream;
229 struct fw_iso_resources *resources;
230 unsigned int pcm_cache;
231 unsigned int midi_cache;
232 unsigned int pcm_chs;
233 unsigned int midi_ports;
235 if (dir == AMDTP_IN_STREAM) {
236 stream = &dice->tx_stream[i];
237 resources = &dice->tx_resources[i];
239 pcm_cache = dice->tx_pcm_chs[i][mode];
240 midi_cache = dice->tx_midi_ports[i];
241 err = snd_dice_transaction_read_tx(dice,
242 params->size * i + TX_NUMBER_AUDIO,
245 stream = &dice->rx_stream[i];
246 resources = &dice->rx_resources[i];
248 pcm_cache = dice->rx_pcm_chs[i][mode];
249 midi_cache = dice->rx_midi_ports[i];
250 err = snd_dice_transaction_read_rx(dice,
251 params->size * i + RX_NUMBER_AUDIO,
256 pcm_chs = be32_to_cpu(reg[0]);
257 midi_ports = be32_to_cpu(reg[1]);
259 // These are important for developer of this driver.
260 if (pcm_chs != pcm_cache || midi_ports != midi_cache) {
261 dev_info(&dice->unit->device,
262 "cache mismatch: pcm: %u:%u, midi: %u:%u\n",
263 pcm_chs, pcm_cache, midi_ports, midi_cache);
267 err = keep_resources(dice, stream, resources, rate, pcm_chs,
276 static void finish_session(struct snd_dice *dice, struct reg_params *tx_params,
277 struct reg_params *rx_params)
279 stop_streams(dice, AMDTP_IN_STREAM, tx_params);
280 stop_streams(dice, AMDTP_OUT_STREAM, rx_params);
282 snd_dice_transaction_clear_enable(dice);
285 int snd_dice_stream_reserve_duplex(struct snd_dice *dice, unsigned int rate)
287 unsigned int curr_rate;
290 // Check sampling transmission frequency.
291 err = snd_dice_transaction_get_rate(dice, &curr_rate);
297 if (dice->substreams_counter == 0 || curr_rate != rate) {
298 struct reg_params tx_params, rx_params;
300 err = get_register_params(dice, &tx_params, &rx_params);
304 finish_session(dice, &tx_params, &rx_params);
306 release_resources(dice);
308 // Just after owning the unit (GLOBAL_OWNER), the unit can
309 // return invalid stream formats. Selecting clock parameters
310 // have an effect for the unit to refine it.
311 err = ensure_phase_lock(dice, rate);
315 // After changing sampling transfer frequency, the value of
316 // register can be changed.
317 err = get_register_params(dice, &tx_params, &rx_params);
321 err = keep_dual_resources(dice, rate, AMDTP_IN_STREAM,
326 err = keep_dual_resources(dice, rate, AMDTP_OUT_STREAM,
334 release_resources(dice);
338 static int start_streams(struct snd_dice *dice, enum amdtp_stream_direction dir,
339 unsigned int rate, struct reg_params *params)
341 unsigned int max_speed = fw_parent_device(dice->unit)->max_speed;
345 for (i = 0; i < params->count; i++) {
346 struct amdtp_stream *stream;
347 struct fw_iso_resources *resources;
350 if (dir == AMDTP_IN_STREAM) {
351 stream = dice->tx_stream + i;
352 resources = dice->tx_resources + i;
354 stream = dice->rx_stream + i;
355 resources = dice->rx_resources + i;
358 reg = cpu_to_be32(resources->channel);
359 if (dir == AMDTP_IN_STREAM) {
360 err = snd_dice_transaction_write_tx(dice,
361 params->size * i + TX_ISOCHRONOUS,
364 err = snd_dice_transaction_write_rx(dice,
365 params->size * i + RX_ISOCHRONOUS,
371 if (dir == AMDTP_IN_STREAM) {
372 reg = cpu_to_be32(max_speed);
373 err = snd_dice_transaction_write_tx(dice,
374 params->size * i + TX_SPEED,
380 err = amdtp_stream_start(stream, resources->channel, max_speed);
389 * MEMO: After this function, there're two states of streams:
390 * - None streams are running.
391 * - All streams are running.
393 int snd_dice_stream_start_duplex(struct snd_dice *dice)
395 unsigned int generation = dice->rx_resources[0].generation;
396 struct reg_params tx_params, rx_params;
399 enum snd_dice_rate_mode mode;
402 if (dice->substreams_counter == 0)
405 err = get_register_params(dice, &tx_params, &rx_params);
409 // Check error of packet streaming.
410 for (i = 0; i < MAX_STREAMS; ++i) {
411 if (amdtp_streaming_error(&dice->tx_stream[i]) ||
412 amdtp_streaming_error(&dice->rx_stream[i])) {
413 finish_session(dice, &tx_params, &rx_params);
418 if (generation != fw_parent_device(dice->unit)->card->generation) {
419 for (i = 0; i < MAX_STREAMS; ++i) {
420 if (i < tx_params.count)
421 fw_iso_resources_update(dice->tx_resources + i);
422 if (i < rx_params.count)
423 fw_iso_resources_update(dice->rx_resources + i);
427 // Check required streams are running or not.
428 err = snd_dice_transaction_get_rate(dice, &rate);
431 err = snd_dice_stream_get_rate_mode(dice, rate, &mode);
434 for (i = 0; i < MAX_STREAMS; ++i) {
435 if (dice->tx_pcm_chs[i][mode] > 0 &&
436 !amdtp_stream_running(&dice->tx_stream[i]))
438 if (dice->rx_pcm_chs[i][mode] > 0 &&
439 !amdtp_stream_running(&dice->rx_stream[i]))
442 if (i < MAX_STREAMS) {
443 // Start both streams.
444 err = start_streams(dice, AMDTP_IN_STREAM, rate, &tx_params);
448 err = start_streams(dice, AMDTP_OUT_STREAM, rate, &rx_params);
452 err = snd_dice_transaction_set_enable(dice);
454 dev_err(&dice->unit->device,
455 "fail to enable interface\n");
459 for (i = 0; i < MAX_STREAMS; i++) {
460 if ((i < tx_params.count &&
461 !amdtp_stream_wait_callback(&dice->tx_stream[i],
462 CALLBACK_TIMEOUT)) ||
463 (i < rx_params.count &&
464 !amdtp_stream_wait_callback(&dice->rx_stream[i],
465 CALLBACK_TIMEOUT))) {
474 finish_session(dice, &tx_params, &rx_params);
479 * MEMO: After this function, there're two states of streams:
480 * - None streams are running.
481 * - All streams are running.
483 void snd_dice_stream_stop_duplex(struct snd_dice *dice)
485 struct reg_params tx_params, rx_params;
487 if (dice->substreams_counter == 0) {
488 if (get_register_params(dice, &tx_params, &rx_params) >= 0)
489 finish_session(dice, &tx_params, &rx_params);
491 release_resources(dice);
495 static int init_stream(struct snd_dice *dice, enum amdtp_stream_direction dir,
498 struct amdtp_stream *stream;
499 struct fw_iso_resources *resources;
502 if (dir == AMDTP_IN_STREAM) {
503 stream = &dice->tx_stream[index];
504 resources = &dice->tx_resources[index];
506 stream = &dice->rx_stream[index];
507 resources = &dice->rx_resources[index];
510 err = fw_iso_resources_init(resources, dice->unit);
513 resources->channels_mask = 0x00000000ffffffffuLL;
515 err = amdtp_am824_init(stream, dice->unit, dir, CIP_BLOCKING);
517 amdtp_stream_destroy(stream);
518 fw_iso_resources_destroy(resources);
525 * This function should be called before starting streams or after stopping
528 static void destroy_stream(struct snd_dice *dice,
529 enum amdtp_stream_direction dir,
532 struct amdtp_stream *stream;
533 struct fw_iso_resources *resources;
535 if (dir == AMDTP_IN_STREAM) {
536 stream = &dice->tx_stream[index];
537 resources = &dice->tx_resources[index];
539 stream = &dice->rx_stream[index];
540 resources = &dice->rx_resources[index];
543 amdtp_stream_destroy(stream);
544 fw_iso_resources_destroy(resources);
547 int snd_dice_stream_init_duplex(struct snd_dice *dice)
551 for (i = 0; i < MAX_STREAMS; i++) {
552 err = init_stream(dice, AMDTP_IN_STREAM, i);
555 destroy_stream(dice, AMDTP_IN_STREAM, i);
560 for (i = 0; i < MAX_STREAMS; i++) {
561 err = init_stream(dice, AMDTP_OUT_STREAM, i);
564 destroy_stream(dice, AMDTP_OUT_STREAM, i);
565 for (i = 0; i < MAX_STREAMS; i++)
566 destroy_stream(dice, AMDTP_IN_STREAM, i);
574 void snd_dice_stream_destroy_duplex(struct snd_dice *dice)
578 for (i = 0; i < MAX_STREAMS; i++) {
579 destroy_stream(dice, AMDTP_IN_STREAM, i);
580 destroy_stream(dice, AMDTP_OUT_STREAM, i);
584 void snd_dice_stream_update_duplex(struct snd_dice *dice)
586 struct reg_params tx_params, rx_params;
589 * On a bus reset, the DICE firmware disables streaming and then goes
590 * off contemplating its own navel for hundreds of milliseconds before
591 * it can react to any of our attempts to reenable streaming. This
592 * means that we lose synchronization anyway, so we force our streams
593 * to stop so that the application can restart them in an orderly
596 dice->global_enabled = false;
598 if (get_register_params(dice, &tx_params, &rx_params) == 0) {
599 stop_streams(dice, AMDTP_IN_STREAM, &tx_params);
600 stop_streams(dice, AMDTP_OUT_STREAM, &rx_params);
604 int snd_dice_stream_detect_current_formats(struct snd_dice *dice)
607 enum snd_dice_rate_mode mode;
609 struct reg_params tx_params, rx_params;
613 /* If extended protocol is available, detect detail spec. */
614 err = snd_dice_detect_extension_formats(dice);
619 * Available stream format is restricted at current mode of sampling
622 err = snd_dice_transaction_get_rate(dice, &rate);
626 err = snd_dice_stream_get_rate_mode(dice, rate, &mode);
631 * Just after owning the unit (GLOBAL_OWNER), the unit can return
632 * invalid stream formats. Selecting clock parameters have an effect
633 * for the unit to refine it.
635 err = ensure_phase_lock(dice, rate);
639 err = get_register_params(dice, &tx_params, &rx_params);
643 for (i = 0; i < tx_params.count; ++i) {
644 err = snd_dice_transaction_read_tx(dice,
645 tx_params.size * i + TX_NUMBER_AUDIO,
649 dice->tx_pcm_chs[i][mode] = be32_to_cpu(reg[0]);
650 dice->tx_midi_ports[i] = max_t(unsigned int,
651 be32_to_cpu(reg[1]), dice->tx_midi_ports[i]);
653 for (i = 0; i < rx_params.count; ++i) {
654 err = snd_dice_transaction_read_rx(dice,
655 rx_params.size * i + RX_NUMBER_AUDIO,
659 dice->rx_pcm_chs[i][mode] = be32_to_cpu(reg[0]);
660 dice->rx_midi_ports[i] = max_t(unsigned int,
661 be32_to_cpu(reg[1]), dice->rx_midi_ports[i]);
667 static void dice_lock_changed(struct snd_dice *dice)
669 dice->dev_lock_changed = true;
670 wake_up(&dice->hwdep_wait);
673 int snd_dice_stream_lock_try(struct snd_dice *dice)
677 spin_lock_irq(&dice->lock);
679 if (dice->dev_lock_count < 0) {
684 if (dice->dev_lock_count++ == 0)
685 dice_lock_changed(dice);
688 spin_unlock_irq(&dice->lock);
692 void snd_dice_stream_lock_release(struct snd_dice *dice)
694 spin_lock_irq(&dice->lock);
696 if (WARN_ON(dice->dev_lock_count <= 0))
699 if (--dice->dev_lock_count == 0)
700 dice_lock_changed(dice);
702 spin_unlock_irq(&dice->lock);