1 // SPDX-License-Identifier: GPL-2.0-only
3 * Audio and Music Data Transmission Protocol (IEC 61883-6) streams
4 * with Common Isochronous Packet (IEC 61883-1) headers
6 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/firewire.h>
12 #include <linux/module.h>
13 #include <linux/slab.h>
14 #include <sound/pcm.h>
15 #include <sound/pcm_params.h>
16 #include "amdtp-stream.h"
18 #define TICKS_PER_CYCLE 3072
19 #define CYCLES_PER_SECOND 8000
20 #define TICKS_PER_SECOND (TICKS_PER_CYCLE * CYCLES_PER_SECOND)
22 /* Always support Linux tracing subsystem. */
23 #define CREATE_TRACE_POINTS
24 #include "amdtp-stream-trace.h"
26 #define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 microseconds */
28 /* isochronous header parameters */
29 #define ISO_DATA_LENGTH_SHIFT 16
30 #define TAG_NO_CIP_HEADER 0
33 /* common isochronous packet header parameters */
34 #define CIP_EOH_SHIFT 31
35 #define CIP_EOH (1u << CIP_EOH_SHIFT)
36 #define CIP_EOH_MASK 0x80000000
37 #define CIP_SID_SHIFT 24
38 #define CIP_SID_MASK 0x3f000000
39 #define CIP_DBS_MASK 0x00ff0000
40 #define CIP_DBS_SHIFT 16
41 #define CIP_SPH_MASK 0x00000400
42 #define CIP_SPH_SHIFT 10
43 #define CIP_DBC_MASK 0x000000ff
44 #define CIP_FMT_SHIFT 24
45 #define CIP_FMT_MASK 0x3f000000
46 #define CIP_FDF_MASK 0x00ff0000
47 #define CIP_FDF_SHIFT 16
48 #define CIP_SYT_MASK 0x0000ffff
49 #define CIP_SYT_NO_INFO 0xffff
51 /* Audio and Music transfer protocol specific parameters */
52 #define CIP_FMT_AM 0x10
53 #define AMDTP_FDF_NO_DATA 0xff
55 // For iso header, tstamp and 2 CIP header.
56 #define IR_CTX_HEADER_SIZE_CIP 16
57 // For iso header and tstamp.
58 #define IR_CTX_HEADER_SIZE_NO_CIP 8
59 #define HEADER_TSTAMP_MASK 0x0000ffff
61 #define IT_PKT_HEADER_SIZE_CIP 8 // For 2 CIP header.
62 #define IT_PKT_HEADER_SIZE_NO_CIP 0 // Nothing.
64 static void pcm_period_tasklet(unsigned long data);
67 * amdtp_stream_init - initialize an AMDTP stream structure
68 * @s: the AMDTP stream to initialize
69 * @unit: the target of the stream
70 * @dir: the direction of stream
71 * @flags: the packet transmission method to use
72 * @fmt: the value of fmt field in CIP header
73 * @process_ctx_payloads: callback handler to process payloads of isoc context
74 * @protocol_size: the size to allocate newly for protocol
76 int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit,
77 enum amdtp_stream_direction dir, enum cip_flags flags,
79 amdtp_stream_process_ctx_payloads_t process_ctx_payloads,
80 unsigned int protocol_size)
82 if (process_ctx_payloads == NULL)
85 s->protocol = kzalloc(protocol_size, GFP_KERNEL);
92 s->context = ERR_PTR(-1);
93 mutex_init(&s->mutex);
94 tasklet_init(&s->period_tasklet, pcm_period_tasklet, (unsigned long)s);
97 init_waitqueue_head(&s->callback_wait);
98 s->callbacked = false;
101 s->process_ctx_payloads = process_ctx_payloads;
103 if (dir == AMDTP_OUT_STREAM)
104 s->ctx_data.rx.syt_override = -1;
108 EXPORT_SYMBOL(amdtp_stream_init);
111 * amdtp_stream_destroy - free stream resources
112 * @s: the AMDTP stream to destroy
114 void amdtp_stream_destroy(struct amdtp_stream *s)
116 /* Not initialized. */
117 if (s->protocol == NULL)
120 WARN_ON(amdtp_stream_running(s));
122 mutex_destroy(&s->mutex);
124 EXPORT_SYMBOL(amdtp_stream_destroy);
126 const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = {
130 [CIP_SFC_88200] = 16,
131 [CIP_SFC_96000] = 16,
132 [CIP_SFC_176400] = 32,
133 [CIP_SFC_192000] = 32,
135 EXPORT_SYMBOL(amdtp_syt_intervals);
137 const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = {
138 [CIP_SFC_32000] = 32000,
139 [CIP_SFC_44100] = 44100,
140 [CIP_SFC_48000] = 48000,
141 [CIP_SFC_88200] = 88200,
142 [CIP_SFC_96000] = 96000,
143 [CIP_SFC_176400] = 176400,
144 [CIP_SFC_192000] = 192000,
146 EXPORT_SYMBOL(amdtp_rate_table);
148 static int apply_constraint_to_size(struct snd_pcm_hw_params *params,
149 struct snd_pcm_hw_rule *rule)
151 struct snd_interval *s = hw_param_interval(params, rule->var);
152 const struct snd_interval *r =
153 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
154 struct snd_interval t = {0};
155 unsigned int step = 0;
158 for (i = 0; i < CIP_SFC_COUNT; ++i) {
159 if (snd_interval_test(r, amdtp_rate_table[i]))
160 step = max(step, amdtp_syt_intervals[i]);
163 t.min = roundup(s->min, step);
164 t.max = rounddown(s->max, step);
167 return snd_interval_refine(s, &t);
171 * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream
172 * @s: the AMDTP stream, which must be initialized.
173 * @runtime: the PCM substream runtime
175 int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s,
176 struct snd_pcm_runtime *runtime)
178 struct snd_pcm_hardware *hw = &runtime->hw;
179 unsigned int ctx_header_size;
180 unsigned int maximum_usec_per_period;
183 hw->info = SNDRV_PCM_INFO_BATCH |
184 SNDRV_PCM_INFO_BLOCK_TRANSFER |
185 SNDRV_PCM_INFO_INTERLEAVED |
186 SNDRV_PCM_INFO_JOINT_DUPLEX |
187 SNDRV_PCM_INFO_MMAP |
188 SNDRV_PCM_INFO_MMAP_VALID;
190 /* SNDRV_PCM_INFO_BATCH */
192 hw->periods_max = UINT_MAX;
194 /* bytes for a frame */
195 hw->period_bytes_min = 4 * hw->channels_max;
197 /* Just to prevent from allocating much pages. */
198 hw->period_bytes_max = hw->period_bytes_min * 2048;
199 hw->buffer_bytes_max = hw->period_bytes_max * hw->periods_min;
201 // Linux driver for 1394 OHCI controller voluntarily flushes isoc
202 // context when total size of accumulated context header reaches
203 // PAGE_SIZE. This kicks tasklet for the isoc context and brings
204 // callback in the middle of scheduled interrupts.
205 // Although AMDTP streams in the same domain use the same events per
206 // IRQ, use the largest size of context header between IT/IR contexts.
207 // Here, use the value of context header in IR context is for both
209 if (!(s->flags & CIP_NO_HEADER))
210 ctx_header_size = IR_CTX_HEADER_SIZE_CIP;
212 ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP;
213 maximum_usec_per_period = USEC_PER_SEC * PAGE_SIZE /
214 CYCLES_PER_SECOND / ctx_header_size;
216 err = snd_pcm_hw_constraint_minmax(runtime,
217 SNDRV_PCM_HW_PARAM_PERIOD_TIME,
218 5000, maximum_usec_per_period);
222 /* Non-Blocking stream has no more constraints */
223 if (!(s->flags & CIP_BLOCKING))
227 * One AMDTP packet can include some frames. In blocking mode, the
228 * number equals to SYT_INTERVAL. So the number is 8, 16 or 32,
229 * depending on its sampling rate. For accurate period interrupt, it's
230 * preferrable to align period/buffer sizes to current SYT_INTERVAL.
232 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
233 apply_constraint_to_size, NULL,
234 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
235 SNDRV_PCM_HW_PARAM_RATE, -1);
238 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
239 apply_constraint_to_size, NULL,
240 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
241 SNDRV_PCM_HW_PARAM_RATE, -1);
247 EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints);
250 * amdtp_stream_set_parameters - set stream parameters
251 * @s: the AMDTP stream to configure
252 * @rate: the sample rate
253 * @data_block_quadlets: the size of a data block in quadlet unit
255 * The parameters must be set before the stream is started, and must not be
256 * changed while the stream is running.
258 int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate,
259 unsigned int data_block_quadlets)
263 for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) {
264 if (amdtp_rate_table[sfc] == rate)
267 if (sfc == ARRAY_SIZE(amdtp_rate_table))
271 s->data_block_quadlets = data_block_quadlets;
272 s->syt_interval = amdtp_syt_intervals[sfc];
274 // default buffering in the device.
275 if (s->direction == AMDTP_OUT_STREAM) {
276 s->ctx_data.rx.transfer_delay =
277 TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE;
279 if (s->flags & CIP_BLOCKING) {
280 // additional buffering needed to adjust for no-data
282 s->ctx_data.rx.transfer_delay +=
283 TICKS_PER_SECOND * s->syt_interval / rate;
289 EXPORT_SYMBOL(amdtp_stream_set_parameters);
292 * amdtp_stream_get_max_payload - get the stream's packet size
293 * @s: the AMDTP stream
295 * This function must not be called before the stream has been configured
296 * with amdtp_stream_set_parameters().
298 unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s)
300 unsigned int multiplier = 1;
301 unsigned int cip_header_size = 0;
303 if (s->flags & CIP_JUMBO_PAYLOAD)
305 if (!(s->flags & CIP_NO_HEADER))
306 cip_header_size = sizeof(__be32) * 2;
308 return cip_header_size +
309 s->syt_interval * s->data_block_quadlets * sizeof(__be32) * multiplier;
311 EXPORT_SYMBOL(amdtp_stream_get_max_payload);
314 * amdtp_stream_pcm_prepare - prepare PCM device for running
315 * @s: the AMDTP stream
317 * This function should be called from the PCM device's .prepare callback.
319 void amdtp_stream_pcm_prepare(struct amdtp_stream *s)
321 tasklet_kill(&s->period_tasklet);
322 s->pcm_buffer_pointer = 0;
323 s->pcm_period_pointer = 0;
325 EXPORT_SYMBOL(amdtp_stream_pcm_prepare);
327 static unsigned int calculate_data_blocks(struct amdtp_stream *s,
330 unsigned int phase, data_blocks;
333 if (s->flags & CIP_BLOCKING) {
334 /* This module generate empty packet for 'no data'. */
335 if (syt == CIP_SYT_NO_INFO)
338 data_blocks = s->syt_interval;
339 /* Non-blocking mode. */
341 if (!cip_sfc_is_base_44100(s->sfc)) {
342 // Sample_rate / 8000 is an integer, and precomputed.
343 data_blocks = s->ctx_data.rx.data_block_state;
345 phase = s->ctx_data.rx.data_block_state;
348 * This calculates the number of data blocks per packet so that
349 * 1) the overall rate is correct and exactly synchronized to
351 * 2) packets with a rounded-up number of blocks occur as early
352 * as possible in the sequence (to prevent underruns of the
355 if (s->sfc == CIP_SFC_44100)
356 /* 6 6 5 6 5 6 5 ... */
357 data_blocks = 5 + ((phase & 1) ^
358 (phase == 0 || phase >= 40));
360 /* 12 11 11 11 11 ... or 23 22 22 22 22 ... */
361 data_blocks = 11 * (s->sfc >> 1) + (phase == 0);
362 if (++phase >= (80 >> (s->sfc >> 1)))
364 s->ctx_data.rx.data_block_state = phase;
371 static unsigned int calculate_syt(struct amdtp_stream *s,
374 unsigned int syt_offset, phase, index, syt;
376 if (s->ctx_data.rx.last_syt_offset < TICKS_PER_CYCLE) {
377 if (!cip_sfc_is_base_44100(s->sfc))
378 syt_offset = s->ctx_data.rx.last_syt_offset +
379 s->ctx_data.rx.syt_offset_state;
382 * The time, in ticks, of the n'th SYT_INTERVAL sample is:
383 * n * SYT_INTERVAL * 24576000 / sample_rate
384 * Modulo TICKS_PER_CYCLE, the difference between successive
385 * elements is about 1386.23. Rounding the results of this
386 * formula to the SYT precision results in a sequence of
387 * differences that begins with:
388 * 1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ...
389 * This code generates _exactly_ the same sequence.
391 phase = s->ctx_data.rx.syt_offset_state;
393 syt_offset = s->ctx_data.rx.last_syt_offset;
394 syt_offset += 1386 + ((index && !(index & 3)) ||
398 s->ctx_data.rx.syt_offset_state = phase;
401 syt_offset = s->ctx_data.rx.last_syt_offset - TICKS_PER_CYCLE;
402 s->ctx_data.rx.last_syt_offset = syt_offset;
404 if (syt_offset < TICKS_PER_CYCLE) {
405 syt_offset += s->ctx_data.rx.transfer_delay;
406 syt = (cycle + syt_offset / TICKS_PER_CYCLE) << 12;
407 syt += syt_offset % TICKS_PER_CYCLE;
409 return syt & CIP_SYT_MASK;
411 return CIP_SYT_NO_INFO;
415 static void update_pcm_pointers(struct amdtp_stream *s,
416 struct snd_pcm_substream *pcm,
421 ptr = s->pcm_buffer_pointer + frames;
422 if (ptr >= pcm->runtime->buffer_size)
423 ptr -= pcm->runtime->buffer_size;
424 WRITE_ONCE(s->pcm_buffer_pointer, ptr);
426 s->pcm_period_pointer += frames;
427 if (s->pcm_period_pointer >= pcm->runtime->period_size) {
428 s->pcm_period_pointer -= pcm->runtime->period_size;
429 tasklet_hi_schedule(&s->period_tasklet);
433 static void pcm_period_tasklet(unsigned long data)
435 struct amdtp_stream *s = (void *)data;
436 struct snd_pcm_substream *pcm = READ_ONCE(s->pcm);
439 snd_pcm_period_elapsed(pcm);
442 static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params,
447 params->interrupt = sched_irq;
448 params->tag = s->tag;
451 err = fw_iso_context_queue(s->context, params, &s->buffer.iso_buffer,
452 s->buffer.packets[s->packet_index].offset);
454 dev_err(&s->unit->device, "queueing error: %d\n", err);
458 if (++s->packet_index >= s->queue_size)
464 static inline int queue_out_packet(struct amdtp_stream *s,
465 struct fw_iso_packet *params, bool sched_irq)
468 !!(params->header_length == 0 && params->payload_length == 0);
469 return queue_packet(s, params, sched_irq);
472 static inline int queue_in_packet(struct amdtp_stream *s,
473 struct fw_iso_packet *params, bool sched_irq)
475 // Queue one packet for IR context.
476 params->header_length = s->ctx_data.tx.ctx_header_size;
477 params->payload_length = s->ctx_data.tx.max_ctx_payload_length;
478 params->skip = false;
479 return queue_packet(s, params, sched_irq);
482 static void generate_cip_header(struct amdtp_stream *s, __be32 cip_header[2],
483 unsigned int data_block_counter, unsigned int syt)
485 cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) |
486 (s->data_block_quadlets << CIP_DBS_SHIFT) |
487 ((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) |
489 cip_header[1] = cpu_to_be32(CIP_EOH |
490 ((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) |
491 ((s->ctx_data.rx.fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) |
492 (syt & CIP_SYT_MASK));
495 static void build_it_pkt_header(struct amdtp_stream *s, unsigned int cycle,
496 struct fw_iso_packet *params,
497 unsigned int data_blocks,
498 unsigned int data_block_counter,
499 unsigned int syt, unsigned int index)
501 unsigned int payload_length;
504 payload_length = data_blocks * sizeof(__be32) * s->data_block_quadlets;
505 params->payload_length = payload_length;
507 if (!(s->flags & CIP_NO_HEADER)) {
508 cip_header = (__be32 *)params->header;
509 generate_cip_header(s, cip_header, data_block_counter, syt);
510 params->header_length = 2 * sizeof(__be32);
511 payload_length += params->header_length;
516 trace_amdtp_packet(s, cycle, cip_header, payload_length, data_blocks,
517 data_block_counter, index);
520 static int check_cip_header(struct amdtp_stream *s, const __be32 *buf,
521 unsigned int payload_length,
522 unsigned int *data_blocks,
523 unsigned int *data_block_counter, unsigned int *syt)
532 cip_header[0] = be32_to_cpu(buf[0]);
533 cip_header[1] = be32_to_cpu(buf[1]);
536 * This module supports 'Two-quadlet CIP header with SYT field'.
537 * For convenience, also check FMT field is AM824 or not.
539 if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) ||
540 ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) &&
541 (!(s->flags & CIP_HEADER_WITHOUT_EOH))) {
542 dev_info_ratelimited(&s->unit->device,
543 "Invalid CIP header for AMDTP: %08X:%08X\n",
544 cip_header[0], cip_header[1]);
548 /* Check valid protocol or not. */
549 sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT;
550 fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT;
551 if (sph != s->sph || fmt != s->fmt) {
552 dev_info_ratelimited(&s->unit->device,
553 "Detect unexpected protocol: %08x %08x\n",
554 cip_header[0], cip_header[1]);
558 /* Calculate data blocks */
559 fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT;
560 if (payload_length < sizeof(__be32) * 2 ||
561 (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) {
564 unsigned int data_block_quadlets =
565 (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT;
566 /* avoid division by zero */
567 if (data_block_quadlets == 0) {
568 dev_err(&s->unit->device,
569 "Detect invalid value in dbs field: %08X\n",
573 if (s->flags & CIP_WRONG_DBS)
574 data_block_quadlets = s->data_block_quadlets;
576 *data_blocks = (payload_length / sizeof(__be32) - 2) /
580 /* Check data block counter continuity */
581 dbc = cip_header[0] & CIP_DBC_MASK;
582 if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) &&
583 *data_block_counter != UINT_MAX)
584 dbc = *data_block_counter;
586 if ((dbc == 0x00 && (s->flags & CIP_SKIP_DBC_ZERO_CHECK)) ||
587 *data_block_counter == UINT_MAX) {
589 } else if (!(s->flags & CIP_DBC_IS_END_EVENT)) {
590 lost = dbc != *data_block_counter;
592 unsigned int dbc_interval;
594 if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0)
595 dbc_interval = s->ctx_data.tx.dbc_interval;
597 dbc_interval = *data_blocks;
599 lost = dbc != ((*data_block_counter + dbc_interval) & 0xff);
603 dev_err(&s->unit->device,
604 "Detect discontinuity of CIP: %02X %02X\n",
605 *data_block_counter, dbc);
609 *data_block_counter = dbc;
611 *syt = cip_header[1] & CIP_SYT_MASK;
616 static int parse_ir_ctx_header(struct amdtp_stream *s, unsigned int cycle,
617 const __be32 *ctx_header,
618 unsigned int *payload_length,
619 unsigned int *data_blocks,
620 unsigned int *data_block_counter,
621 unsigned int *syt, unsigned int index)
623 const __be32 *cip_header;
626 *payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT;
627 if (*payload_length > s->ctx_data.tx.ctx_header_size +
628 s->ctx_data.tx.max_ctx_payload_length) {
629 dev_err(&s->unit->device,
630 "Detect jumbo payload: %04x %04x\n",
631 *payload_length, s->ctx_data.tx.max_ctx_payload_length);
635 if (!(s->flags & CIP_NO_HEADER)) {
636 cip_header = ctx_header + 2;
637 err = check_cip_header(s, cip_header, *payload_length,
638 data_blocks, data_block_counter, syt);
644 *data_blocks = *payload_length / sizeof(__be32) /
645 s->data_block_quadlets;
648 if (*data_block_counter == UINT_MAX)
649 *data_block_counter = 0;
652 trace_amdtp_packet(s, cycle, cip_header, *payload_length, *data_blocks,
653 *data_block_counter, index);
658 // In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On
659 // the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent
660 // it. Thus, via Linux firewire subsystem, we can get the 3 bits for second.
661 static inline u32 compute_cycle_count(__be32 ctx_header_tstamp)
663 u32 tstamp = be32_to_cpu(ctx_header_tstamp) & HEADER_TSTAMP_MASK;
664 return (((tstamp >> 13) & 0x07) * 8000) + (tstamp & 0x1fff);
667 static inline u32 increment_cycle_count(u32 cycle, unsigned int addend)
670 if (cycle >= 8 * CYCLES_PER_SECOND)
671 cycle -= 8 * CYCLES_PER_SECOND;
675 // Align to actual cycle count for the packet which is going to be scheduled.
676 // This module queued the same number of isochronous cycle as the size of queue
677 // to kip isochronous cycle, therefore it's OK to just increment the cycle by
678 // the size of queue for scheduled cycle.
679 static inline u32 compute_it_cycle(const __be32 ctx_header_tstamp,
680 unsigned int queue_size)
682 u32 cycle = compute_cycle_count(ctx_header_tstamp);
683 return increment_cycle_count(cycle, queue_size);
686 static int generate_device_pkt_descs(struct amdtp_stream *s,
687 struct pkt_desc *descs,
688 const __be32 *ctx_header,
689 unsigned int packets)
691 unsigned int dbc = s->data_block_counter;
695 for (i = 0; i < packets; ++i) {
696 struct pkt_desc *desc = descs + i;
697 unsigned int index = (s->packet_index + i) % s->queue_size;
699 unsigned int payload_length;
700 unsigned int data_blocks;
703 cycle = compute_cycle_count(ctx_header[1]);
705 err = parse_ir_ctx_header(s, cycle, ctx_header, &payload_length,
706 &data_blocks, &dbc, &syt, i);
712 desc->data_blocks = data_blocks;
713 desc->data_block_counter = dbc;
714 desc->ctx_payload = s->buffer.packets[index].buffer;
716 if (!(s->flags & CIP_DBC_IS_END_EVENT))
717 dbc = (dbc + desc->data_blocks) & 0xff;
720 s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header);
723 s->data_block_counter = dbc;
728 static void generate_ideal_pkt_descs(struct amdtp_stream *s,
729 struct pkt_desc *descs,
730 const __be32 *ctx_header,
731 unsigned int packets)
733 unsigned int dbc = s->data_block_counter;
736 for (i = 0; i < packets; ++i) {
737 struct pkt_desc *desc = descs + i;
738 unsigned int index = (s->packet_index + i) % s->queue_size;
740 desc->cycle = compute_it_cycle(*ctx_header, s->queue_size);
741 desc->syt = calculate_syt(s, desc->cycle);
742 desc->data_blocks = calculate_data_blocks(s, desc->syt);
744 if (s->flags & CIP_DBC_IS_END_EVENT)
745 dbc = (dbc + desc->data_blocks) & 0xff;
747 desc->data_block_counter = dbc;
749 if (!(s->flags & CIP_DBC_IS_END_EVENT))
750 dbc = (dbc + desc->data_blocks) & 0xff;
752 desc->ctx_payload = s->buffer.packets[index].buffer;
757 s->data_block_counter = dbc;
760 static inline void cancel_stream(struct amdtp_stream *s)
762 s->packet_index = -1;
764 amdtp_stream_pcm_abort(s);
765 WRITE_ONCE(s->pcm_buffer_pointer, SNDRV_PCM_POS_XRUN);
768 static void process_ctx_payloads(struct amdtp_stream *s,
769 const struct pkt_desc *descs,
770 unsigned int packets)
772 struct snd_pcm_substream *pcm;
773 unsigned int pcm_frames;
775 pcm = READ_ONCE(s->pcm);
776 pcm_frames = s->process_ctx_payloads(s, descs, packets, pcm);
778 update_pcm_pointers(s, pcm, pcm_frames);
781 static void out_stream_callback(struct fw_iso_context *context, u32 tstamp,
782 size_t header_length, void *header,
785 struct amdtp_stream *s = private_data;
786 const __be32 *ctx_header = header;
787 unsigned int events_per_period = s->events_per_period;
788 unsigned int event_count = s->event_count;
789 unsigned int packets;
792 if (s->packet_index < 0)
795 // Calculate the number of packets in buffer and check XRUN.
796 packets = header_length / sizeof(*ctx_header);
798 generate_ideal_pkt_descs(s, s->pkt_descs, ctx_header, packets);
800 process_ctx_payloads(s, s->pkt_descs, packets);
802 for (i = 0; i < packets; ++i) {
803 const struct pkt_desc *desc = s->pkt_descs + i;
806 struct fw_iso_packet params;
807 __be32 header[IT_PKT_HEADER_SIZE_CIP / sizeof(__be32)];
808 } template = { {0}, {0} };
809 bool sched_irq = false;
811 if (s->ctx_data.rx.syt_override < 0)
814 syt = s->ctx_data.rx.syt_override;
816 build_it_pkt_header(s, desc->cycle, &template.params,
817 desc->data_blocks, desc->data_block_counter,
820 event_count += desc->data_blocks;
821 if (event_count >= events_per_period) {
822 event_count -= events_per_period;
826 if (queue_out_packet(s, &template.params, sched_irq) < 0) {
832 s->event_count = event_count;
834 fw_iso_context_queue_flush(s->context);
837 static void in_stream_callback(struct fw_iso_context *context, u32 tstamp,
838 size_t header_length, void *header,
841 struct amdtp_stream *s = private_data;
842 __be32 *ctx_header = header;
843 unsigned int events_per_period = s->events_per_period;
844 unsigned int event_count = s->event_count;
845 unsigned int packets;
849 if (s->packet_index < 0)
852 // Calculate the number of packets in buffer and check XRUN.
853 packets = header_length / s->ctx_data.tx.ctx_header_size;
855 err = generate_device_pkt_descs(s, s->pkt_descs, ctx_header, packets);
857 if (err != -EAGAIN) {
862 process_ctx_payloads(s, s->pkt_descs, packets);
865 for (i = 0; i < packets; ++i) {
866 const struct pkt_desc *desc = s->pkt_descs + i;
867 struct fw_iso_packet params = {0};
868 bool sched_irq = false;
871 event_count += desc->data_blocks;
872 if (event_count >= events_per_period) {
873 event_count -= events_per_period;
878 !((s->packet_index + 1) % s->idle_irq_interval);
881 if (queue_in_packet(s, ¶ms, sched_irq) < 0) {
887 s->event_count = event_count;
889 fw_iso_context_queue_flush(s->context);
892 /* this is executed one time */
893 static void amdtp_stream_first_callback(struct fw_iso_context *context,
894 u32 tstamp, size_t header_length,
895 void *header, void *private_data)
897 struct amdtp_stream *s = private_data;
898 const __be32 *ctx_header = header;
902 * For in-stream, first packet has come.
903 * For out-stream, prepared to transmit first packet
905 s->callbacked = true;
906 wake_up(&s->callback_wait);
908 if (s->direction == AMDTP_IN_STREAM) {
909 cycle = compute_cycle_count(ctx_header[1]);
911 context->callback.sc = in_stream_callback;
913 cycle = compute_it_cycle(*ctx_header, s->queue_size);
915 context->callback.sc = out_stream_callback;
918 s->start_cycle = cycle;
920 context->callback.sc(context, tstamp, header_length, header, s);
924 * amdtp_stream_start - start transferring packets
925 * @s: the AMDTP stream to start
926 * @channel: the isochronous channel on the bus
927 * @speed: firewire speed code
929 * The stream cannot be started until it has been configured with
930 * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI
931 * device can be started.
933 static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed,
934 struct amdtp_domain *d)
936 static const struct {
937 unsigned int data_block;
938 unsigned int syt_offset;
939 } *entry, initial_state[] = {
940 [CIP_SFC_32000] = { 4, 3072 },
941 [CIP_SFC_48000] = { 6, 1024 },
942 [CIP_SFC_96000] = { 12, 1024 },
943 [CIP_SFC_192000] = { 24, 1024 },
944 [CIP_SFC_44100] = { 0, 67 },
945 [CIP_SFC_88200] = { 0, 67 },
946 [CIP_SFC_176400] = { 0, 67 },
948 unsigned int events_per_buffer = d->events_per_buffer;
949 unsigned int events_per_period = d->events_per_period;
950 unsigned int ctx_header_size;
951 unsigned int max_ctx_payload_size;
952 enum dma_data_direction dir;
955 mutex_lock(&s->mutex);
957 if (WARN_ON(amdtp_stream_running(s) ||
958 (s->data_block_quadlets < 1))) {
963 if (s->direction == AMDTP_IN_STREAM) {
964 s->data_block_counter = UINT_MAX;
966 entry = &initial_state[s->sfc];
968 s->data_block_counter = 0;
969 s->ctx_data.rx.data_block_state = entry->data_block;
970 s->ctx_data.rx.syt_offset_state = entry->syt_offset;
971 s->ctx_data.rx.last_syt_offset = TICKS_PER_CYCLE;
974 /* initialize packet buffer */
975 if (s->direction == AMDTP_IN_STREAM) {
976 dir = DMA_FROM_DEVICE;
977 type = FW_ISO_CONTEXT_RECEIVE;
978 if (!(s->flags & CIP_NO_HEADER))
979 ctx_header_size = IR_CTX_HEADER_SIZE_CIP;
981 ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP;
983 max_ctx_payload_size = amdtp_stream_get_max_payload(s) -
987 type = FW_ISO_CONTEXT_TRANSMIT;
988 ctx_header_size = 0; // No effect for IT context.
990 max_ctx_payload_size = amdtp_stream_get_max_payload(s);
991 if (!(s->flags & CIP_NO_HEADER))
992 max_ctx_payload_size -= IT_PKT_HEADER_SIZE_CIP;
995 // This is a case that AMDTP streams in domain run just for MIDI
996 // substream. Use the number of events equivalent to 10 msec as
997 // interval of hardware IRQ.
998 if (events_per_period == 0)
999 events_per_period = amdtp_rate_table[s->sfc] / 100;
1000 if (events_per_buffer == 0)
1001 events_per_buffer = events_per_period * 3;
1003 s->idle_irq_interval =
1004 DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_period,
1005 amdtp_rate_table[s->sfc]);
1006 s->queue_size = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_buffer,
1007 amdtp_rate_table[s->sfc]);
1008 s->events_per_period = events_per_period;
1011 err = iso_packets_buffer_init(&s->buffer, s->unit, s->queue_size,
1012 max_ctx_payload_size, dir);
1016 s->context = fw_iso_context_create(fw_parent_device(s->unit)->card,
1017 type, channel, speed, ctx_header_size,
1018 amdtp_stream_first_callback, s);
1019 if (IS_ERR(s->context)) {
1020 err = PTR_ERR(s->context);
1022 dev_err(&s->unit->device,
1023 "no free stream on this controller\n");
1027 amdtp_stream_update(s);
1029 if (s->direction == AMDTP_IN_STREAM) {
1030 s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size;
1031 s->ctx_data.tx.ctx_header_size = ctx_header_size;
1034 if (s->flags & CIP_NO_HEADER)
1035 s->tag = TAG_NO_CIP_HEADER;
1039 s->pkt_descs = kcalloc(s->queue_size, sizeof(*s->pkt_descs),
1041 if (!s->pkt_descs) {
1046 s->packet_index = 0;
1048 struct fw_iso_packet params;
1051 sched_irq = !((s->packet_index + 1) % s->idle_irq_interval);
1052 if (s->direction == AMDTP_IN_STREAM) {
1053 err = queue_in_packet(s, ¶ms, sched_irq);
1055 params.header_length = 0;
1056 params.payload_length = 0;
1057 err = queue_out_packet(s, ¶ms, sched_irq);
1061 } while (s->packet_index > 0);
1063 /* NOTE: TAG1 matches CIP. This just affects in stream. */
1064 tag = FW_ISO_CONTEXT_MATCH_TAG1;
1065 if ((s->flags & CIP_EMPTY_WITH_TAG0) || (s->flags & CIP_NO_HEADER))
1066 tag |= FW_ISO_CONTEXT_MATCH_TAG0;
1068 s->callbacked = false;
1069 err = fw_iso_context_start(s->context, -1, 0, tag);
1073 mutex_unlock(&s->mutex);
1077 kfree(s->pkt_descs);
1079 fw_iso_context_destroy(s->context);
1080 s->context = ERR_PTR(-1);
1082 iso_packets_buffer_destroy(&s->buffer, s->unit);
1084 mutex_unlock(&s->mutex);
1090 * amdtp_stream_pcm_pointer - get the PCM buffer position
1091 * @s: the AMDTP stream that transports the PCM data
1093 * Returns the current buffer position, in frames.
1095 unsigned long amdtp_stream_pcm_pointer(struct amdtp_stream *s)
1098 * This function is called in software IRQ context of period_tasklet or
1101 * When the software IRQ context was scheduled by software IRQ context
1102 * of IR/IT contexts, queued packets were already handled. Therefore,
1103 * no need to flush the queue in buffer anymore.
1105 * When the process context reach here, some packets will be already
1106 * queued in the buffer. These packets should be handled immediately
1107 * to keep better granularity of PCM pointer.
1109 * Later, the process context will sometimes schedules software IRQ
1110 * context of the period_tasklet. Then, no need to flush the queue by
1111 * the same reason as described for IR/IT contexts.
1113 if (!in_interrupt() && amdtp_stream_running(s))
1114 fw_iso_context_flush_completions(s->context);
1116 return READ_ONCE(s->pcm_buffer_pointer);
1118 EXPORT_SYMBOL(amdtp_stream_pcm_pointer);
1121 * amdtp_stream_pcm_ack - acknowledge queued PCM frames
1122 * @s: the AMDTP stream that transfers the PCM frames
1124 * Returns zero always.
1126 int amdtp_stream_pcm_ack(struct amdtp_stream *s)
1129 * Process isochronous packets for recent isochronous cycle to handle
1130 * queued PCM frames.
1132 if (amdtp_stream_running(s))
1133 fw_iso_context_flush_completions(s->context);
1137 EXPORT_SYMBOL(amdtp_stream_pcm_ack);
1140 * amdtp_stream_update - update the stream after a bus reset
1141 * @s: the AMDTP stream
1143 void amdtp_stream_update(struct amdtp_stream *s)
1146 WRITE_ONCE(s->source_node_id_field,
1147 (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & CIP_SID_MASK);
1149 EXPORT_SYMBOL(amdtp_stream_update);
1152 * amdtp_stream_stop - stop sending packets
1153 * @s: the AMDTP stream to stop
1155 * All PCM and MIDI devices of the stream must be stopped before the stream
1156 * itself can be stopped.
1158 static void amdtp_stream_stop(struct amdtp_stream *s)
1160 mutex_lock(&s->mutex);
1162 if (!amdtp_stream_running(s)) {
1163 mutex_unlock(&s->mutex);
1167 tasklet_kill(&s->period_tasklet);
1168 fw_iso_context_stop(s->context);
1169 fw_iso_context_destroy(s->context);
1170 s->context = ERR_PTR(-1);
1171 iso_packets_buffer_destroy(&s->buffer, s->unit);
1172 kfree(s->pkt_descs);
1174 s->callbacked = false;
1176 mutex_unlock(&s->mutex);
1180 * amdtp_stream_pcm_abort - abort the running PCM device
1181 * @s: the AMDTP stream about to be stopped
1183 * If the isochronous stream needs to be stopped asynchronously, call this
1184 * function first to stop the PCM device.
1186 void amdtp_stream_pcm_abort(struct amdtp_stream *s)
1188 struct snd_pcm_substream *pcm;
1190 pcm = READ_ONCE(s->pcm);
1192 snd_pcm_stop_xrun(pcm);
1194 EXPORT_SYMBOL(amdtp_stream_pcm_abort);
1197 * amdtp_domain_init - initialize an AMDTP domain structure
1198 * @d: the AMDTP domain to initialize.
1200 int amdtp_domain_init(struct amdtp_domain *d)
1202 INIT_LIST_HEAD(&d->streams);
1204 d->events_per_period = 0;
1208 EXPORT_SYMBOL_GPL(amdtp_domain_init);
1211 * amdtp_domain_destroy - destroy an AMDTP domain structure
1212 * @d: the AMDTP domain to destroy.
1214 void amdtp_domain_destroy(struct amdtp_domain *d)
1216 // At present nothing to do.
1219 EXPORT_SYMBOL_GPL(amdtp_domain_destroy);
1222 * amdtp_domain_add_stream - register isoc context into the domain.
1223 * @d: the AMDTP domain.
1224 * @s: the AMDTP stream.
1225 * @channel: the isochronous channel on the bus.
1226 * @speed: firewire speed code.
1228 int amdtp_domain_add_stream(struct amdtp_domain *d, struct amdtp_stream *s,
1229 int channel, int speed)
1231 struct amdtp_stream *tmp;
1233 list_for_each_entry(tmp, &d->streams, list) {
1238 list_add(&s->list, &d->streams);
1240 s->channel = channel;
1245 EXPORT_SYMBOL_GPL(amdtp_domain_add_stream);
1248 * amdtp_domain_start - start sending packets for isoc context in the domain.
1249 * @d: the AMDTP domain.
1251 int amdtp_domain_start(struct amdtp_domain *d)
1253 struct amdtp_stream *s;
1256 list_for_each_entry(s, &d->streams, list) {
1257 err = amdtp_stream_start(s, s->channel, s->speed, d);
1263 list_for_each_entry(s, &d->streams, list)
1264 amdtp_stream_stop(s);
1269 EXPORT_SYMBOL_GPL(amdtp_domain_start);
1272 * amdtp_domain_stop - stop sending packets for isoc context in the same domain.
1273 * @d: the AMDTP domain to which the isoc contexts belong.
1275 void amdtp_domain_stop(struct amdtp_domain *d)
1277 struct amdtp_stream *s, *next;
1279 list_for_each_entry_safe(s, next, &d->streams, list) {
1282 amdtp_stream_stop(s);
1285 d->events_per_period = 0;
1287 EXPORT_SYMBOL_GPL(amdtp_domain_stop);