2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __OMAP_OMAPDSS_H
19 #define __OMAP_OMAPDSS_H
21 #include <linux/list.h>
22 #include <linux/kobject.h>
23 #include <linux/device.h>
25 #define DISPC_IRQ_FRAMEDONE (1 << 0)
26 #define DISPC_IRQ_VSYNC (1 << 1)
27 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
28 #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
29 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
30 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
31 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
32 #define DISPC_IRQ_GFX_END_WIN (1 << 7)
33 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
34 #define DISPC_IRQ_OCP_ERR (1 << 9)
35 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
36 #define DISPC_IRQ_VID1_END_WIN (1 << 11)
37 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
38 #define DISPC_IRQ_VID2_END_WIN (1 << 13)
39 #define DISPC_IRQ_SYNC_LOST (1 << 14)
40 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
41 #define DISPC_IRQ_WAKEUP (1 << 16)
42 #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
43 #define DISPC_IRQ_VSYNC2 (1 << 18)
44 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
45 #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
47 struct omap_dss_device;
48 struct omap_overlay_manager;
50 enum omap_display_type {
51 OMAP_DISPLAY_TYPE_NONE = 0,
52 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
53 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
54 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
55 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
56 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
57 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
67 OMAP_DSS_CHANNEL_LCD = 0,
68 OMAP_DSS_CHANNEL_DIGIT = 1,
69 OMAP_DSS_CHANNEL_LCD2 = 2,
72 enum omap_color_mode {
73 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
74 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
75 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
76 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
77 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
78 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
79 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
80 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
81 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
82 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
83 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
84 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
85 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
86 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
87 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
88 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
89 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
90 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
91 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
94 enum omap_lcd_display_type {
95 OMAP_DSS_LCD_DISPLAY_STN,
96 OMAP_DSS_LCD_DISPLAY_TFT,
99 enum omap_dss_load_mode {
100 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
101 OMAP_DSS_LOAD_CLUT_ONLY = 1,
102 OMAP_DSS_LOAD_FRAME_ONLY = 2,
103 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
106 enum omap_dss_trans_key_type {
107 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
108 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
111 enum omap_rfbi_te_mode {
112 OMAP_DSS_RFBI_TE_MODE_1 = 1,
113 OMAP_DSS_RFBI_TE_MODE_2 = 2,
116 enum omap_panel_config {
117 OMAP_DSS_LCD_IVS = 1<<0,
118 OMAP_DSS_LCD_IHS = 1<<1,
119 OMAP_DSS_LCD_IPC = 1<<2,
120 OMAP_DSS_LCD_IEO = 1<<3,
121 OMAP_DSS_LCD_RF = 1<<4,
122 OMAP_DSS_LCD_ONOFF = 1<<5,
124 OMAP_DSS_LCD_TFT = 1<<20,
127 enum omap_dss_venc_type {
128 OMAP_DSS_VENC_TYPE_COMPOSITE,
129 OMAP_DSS_VENC_TYPE_SVIDEO,
132 enum omap_dss_dsi_pixel_format {
133 OMAP_DSS_DSI_FMT_RGB888,
134 OMAP_DSS_DSI_FMT_RGB666,
135 OMAP_DSS_DSI_FMT_RGB666_PACKED,
136 OMAP_DSS_DSI_FMT_RGB565,
139 enum omap_dss_dsi_mode {
140 OMAP_DSS_DSI_CMD_MODE = 0,
141 OMAP_DSS_DSI_VIDEO_MODE,
144 enum omap_display_caps {
145 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
146 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
149 enum omap_dss_display_state {
150 OMAP_DSS_DISPLAY_DISABLED = 0,
151 OMAP_DSS_DISPLAY_ACTIVE,
152 OMAP_DSS_DISPLAY_SUSPENDED,
155 /* XXX perhaps this should be removed */
156 enum omap_dss_overlay_managers {
157 OMAP_DSS_OVL_MGR_LCD,
159 OMAP_DSS_OVL_MGR_LCD2,
162 enum omap_dss_rotation_type {
163 OMAP_DSS_ROT_DMA = 0,
164 OMAP_DSS_ROT_VRFB = 1,
167 /* clockwise rotation angle */
168 enum omap_dss_rotation_angle {
171 OMAP_DSS_ROT_180 = 2,
172 OMAP_DSS_ROT_270 = 3,
175 enum omap_overlay_caps {
176 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
177 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
178 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
181 enum omap_overlay_manager_caps {
182 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
185 enum omap_dss_clk_source {
186 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
188 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
189 * OMAP4: PLL1_CLK1 */
190 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
191 * OMAP4: PLL1_CLK2 */
192 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
193 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
198 struct rfbi_timings {
212 u32 tim[5]; /* set by rfbi_convert_timings() */
217 void omap_rfbi_write_command(const void *buf, u32 len);
218 void omap_rfbi_read_data(void *buf, u32 len);
219 void omap_rfbi_write_data(const void *buf, u32 len);
220 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
223 int omap_rfbi_enable_te(bool enable, unsigned line);
224 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
225 unsigned hs_pulse_time, unsigned vs_pulse_time,
226 int hs_pol_inv, int vs_pol_inv, int extif_div);
227 void rfbi_bus_lock(void);
228 void rfbi_bus_unlock(void);
231 void dsi_bus_lock(struct omap_dss_device *dssdev);
232 void dsi_bus_unlock(struct omap_dss_device *dssdev);
233 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
235 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
237 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
238 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
239 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
241 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
243 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
244 u8 param1, u8 param2);
245 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
247 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
249 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
250 u8 *buf, int buflen);
251 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
253 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
254 u8 *buf, int buflen);
255 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
256 u8 param1, u8 param2, u8 *buf, int buflen);
257 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
259 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
260 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
262 /* Board specific data */
263 struct omap_dss_board_info {
264 int (*get_context_loss_count)(struct device *dev);
266 struct omap_dss_device **devices;
267 struct omap_dss_device *default_device;
268 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
269 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
272 #if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
273 /* Init with the board info */
274 extern int omap_display_init(struct omap_dss_board_info *board_data);
276 static inline int omap_display_init(struct omap_dss_board_info *board_data)
282 struct omap_display_platform_data {
283 struct omap_dss_board_info *board_data;
284 /* TODO: Additional members to be added when PM is considered */
287 struct omap_video_timings {
294 /* Unit: pixel clocks */
295 u16 hsw; /* Horizontal synchronization pulse width */
296 /* Unit: pixel clocks */
297 u16 hfp; /* Horizontal front porch */
298 /* Unit: pixel clocks */
299 u16 hbp; /* Horizontal back porch */
300 /* Unit: line clocks */
301 u16 vsw; /* Vertical synchronization pulse width */
302 /* Unit: line clocks */
303 u16 vfp; /* Vertical front porch */
304 /* Unit: line clocks */
305 u16 vbp; /* Vertical back porch */
308 #ifdef CONFIG_OMAP2_DSS_VENC
309 /* Hardcoded timings for tv modes. Venc only uses these to
310 * identify the mode, and does not actually use the configs
311 * itself. However, the configs should be something that
312 * a normal monitor can also show */
313 extern const struct omap_video_timings omap_dss_pal_timings;
314 extern const struct omap_video_timings omap_dss_ntsc_timings;
317 struct omap_dss_cpr_coefs {
323 struct omap_overlay_info {
328 u32 p_uv_addr; /* for NV12 format */
332 enum omap_color_mode color_mode;
334 enum omap_dss_rotation_type rotation_type;
339 u16 out_width; /* if 0, out_width == width */
340 u16 out_height; /* if 0, out_height == height */
345 struct omap_overlay {
347 struct list_head list;
352 enum omap_color_mode supported_modes;
353 enum omap_overlay_caps caps;
356 struct omap_overlay_manager *manager;
357 struct omap_overlay_info info;
359 bool manager_changed;
360 /* if true, info has been changed, but not applied() yet */
363 int (*set_manager)(struct omap_overlay *ovl,
364 struct omap_overlay_manager *mgr);
365 int (*unset_manager)(struct omap_overlay *ovl);
367 int (*set_overlay_info)(struct omap_overlay *ovl,
368 struct omap_overlay_info *info);
369 void (*get_overlay_info)(struct omap_overlay *ovl,
370 struct omap_overlay_info *info);
372 int (*wait_for_go)(struct omap_overlay *ovl);
375 struct omap_overlay_manager_info {
378 enum omap_dss_trans_key_type trans_key_type;
385 struct omap_dss_cpr_coefs cpr_coefs;
388 struct omap_overlay_manager {
390 struct list_head list;
394 enum omap_channel id;
395 enum omap_overlay_manager_caps caps;
397 struct omap_overlay **overlays;
398 enum omap_display_type supported_displays;
401 struct omap_dss_device *device;
402 struct omap_overlay_manager_info info;
405 /* if true, info has been changed but not applied() yet */
408 int (*set_device)(struct omap_overlay_manager *mgr,
409 struct omap_dss_device *dssdev);
410 int (*unset_device)(struct omap_overlay_manager *mgr);
412 int (*set_manager_info)(struct omap_overlay_manager *mgr,
413 struct omap_overlay_manager_info *info);
414 void (*get_manager_info)(struct omap_overlay_manager *mgr,
415 struct omap_overlay_manager_info *info);
417 int (*apply)(struct omap_overlay_manager *mgr);
418 int (*wait_for_go)(struct omap_overlay_manager *mgr);
419 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
421 int (*enable)(struct omap_overlay_manager *mgr);
422 int (*disable)(struct omap_overlay_manager *mgr);
425 struct omap_dss_device {
428 enum omap_display_type type;
430 enum omap_channel channel;
465 enum omap_dss_venc_type type;
466 bool invert_polarity;
475 enum omap_dss_clk_source lcd_clk_src;
478 enum omap_dss_clk_source dispc_fclk_src;
488 enum omap_dss_clk_source dsi_fclk_src;
498 struct omap_video_timings timings;
500 int acbi; /* ac-bias pin transitions per interrupt */
501 /* Unit: line clocks */
502 int acb; /* ac-bias pin frequency */
504 enum omap_panel_config config;
506 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
507 enum omap_dss_dsi_mode dsi_mode;
512 struct rfbi_timings rfbi_timings;
517 int max_backlight_level;
521 /* used to match device to driver */
522 const char *driver_name;
526 struct omap_dss_driver *driver;
528 /* helper variable for driver suspend/resume */
529 bool activate_after_resume;
531 enum omap_display_caps caps;
533 struct omap_overlay_manager *manager;
535 enum omap_dss_display_state state;
537 /* platform specific */
538 int (*platform_enable)(struct omap_dss_device *dssdev);
539 void (*platform_disable)(struct omap_dss_device *dssdev);
540 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
541 int (*get_backlight)(struct omap_dss_device *dssdev);
544 struct omap_dss_driver {
545 struct device_driver driver;
547 int (*probe)(struct omap_dss_device *);
548 void (*remove)(struct omap_dss_device *);
550 int (*enable)(struct omap_dss_device *display);
551 void (*disable)(struct omap_dss_device *display);
552 int (*suspend)(struct omap_dss_device *display);
553 int (*resume)(struct omap_dss_device *display);
554 int (*run_test)(struct omap_dss_device *display, int test);
556 int (*update)(struct omap_dss_device *dssdev,
557 u16 x, u16 y, u16 w, u16 h);
558 int (*sync)(struct omap_dss_device *dssdev);
560 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
561 int (*get_te)(struct omap_dss_device *dssdev);
563 u8 (*get_rotate)(struct omap_dss_device *dssdev);
564 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
566 bool (*get_mirror)(struct omap_dss_device *dssdev);
567 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
569 int (*memory_read)(struct omap_dss_device *dssdev,
570 void *buf, size_t size,
571 u16 x, u16 y, u16 w, u16 h);
573 void (*get_resolution)(struct omap_dss_device *dssdev,
574 u16 *xres, u16 *yres);
575 void (*get_dimensions)(struct omap_dss_device *dssdev,
576 u32 *width, u32 *height);
577 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
579 int (*check_timings)(struct omap_dss_device *dssdev,
580 struct omap_video_timings *timings);
581 void (*set_timings)(struct omap_dss_device *dssdev,
582 struct omap_video_timings *timings);
583 void (*get_timings)(struct omap_dss_device *dssdev,
584 struct omap_video_timings *timings);
586 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
587 u32 (*get_wss)(struct omap_dss_device *dssdev);
590 int omap_dss_register_driver(struct omap_dss_driver *);
591 void omap_dss_unregister_driver(struct omap_dss_driver *);
593 void omap_dss_get_device(struct omap_dss_device *dssdev);
594 void omap_dss_put_device(struct omap_dss_device *dssdev);
595 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
596 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
597 struct omap_dss_device *omap_dss_find_device(void *data,
598 int (*match)(struct omap_dss_device *dssdev, void *data));
600 int omap_dss_start_device(struct omap_dss_device *dssdev);
601 void omap_dss_stop_device(struct omap_dss_device *dssdev);
603 int omap_dss_get_num_overlay_managers(void);
604 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
606 int omap_dss_get_num_overlays(void);
607 struct omap_overlay *omap_dss_get_overlay(int num);
609 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
610 u16 *xres, u16 *yres);
611 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
613 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
614 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
615 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
617 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
618 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
619 unsigned long timeout);
621 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
622 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
624 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
626 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
628 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
629 u16 *x, u16 *y, u16 *w, u16 *h,
630 bool enlarge_update_area);
631 int omap_dsi_update(struct omap_dss_device *dssdev,
633 u16 x, u16 y, u16 w, u16 h,
634 void (*callback)(int, void *), void *data);
635 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
636 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
637 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
639 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
640 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
641 bool disconnect_lanes, bool enter_ulps);
643 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
644 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
645 void dpi_set_timings(struct omap_dss_device *dssdev,
646 struct omap_video_timings *timings);
647 int dpi_check_timings(struct omap_dss_device *dssdev,
648 struct omap_video_timings *timings);
650 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
651 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
653 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
654 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
655 int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
656 u16 *x, u16 *y, u16 *w, u16 *h);
657 int omap_rfbi_update(struct omap_dss_device *dssdev,
658 u16 x, u16 y, u16 w, u16 h,
659 void (*callback)(void *), void *data);
660 int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,