2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __OMAP_OMAPDSS_H
19 #define __OMAP_OMAPDSS_H
21 #include <linux/list.h>
22 #include <linux/kobject.h>
23 #include <linux/device.h>
24 #include <linux/interrupt.h>
26 #define DISPC_IRQ_FRAMEDONE (1 << 0)
27 #define DISPC_IRQ_VSYNC (1 << 1)
28 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
29 #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
30 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
31 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
32 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
33 #define DISPC_IRQ_GFX_END_WIN (1 << 7)
34 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
35 #define DISPC_IRQ_OCP_ERR (1 << 9)
36 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
37 #define DISPC_IRQ_VID1_END_WIN (1 << 11)
38 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
39 #define DISPC_IRQ_VID2_END_WIN (1 << 13)
40 #define DISPC_IRQ_SYNC_LOST (1 << 14)
41 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
42 #define DISPC_IRQ_WAKEUP (1 << 16)
43 #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
44 #define DISPC_IRQ_VSYNC2 (1 << 18)
45 #define DISPC_IRQ_VID3_END_WIN (1 << 19)
46 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
47 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
48 #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
49 #define DISPC_IRQ_FRAMEDONEWB (1 << 23)
50 #define DISPC_IRQ_FRAMEDONETV (1 << 24)
51 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
52 #define DISPC_IRQ_SYNC_LOST3 (1 << 27)
53 #define DISPC_IRQ_VSYNC3 (1 << 28)
54 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
55 #define DISPC_IRQ_FRAMEDONE3 (1 << 30)
57 struct omap_dss_device;
58 struct omap_overlay_manager;
59 struct dss_lcd_mgr_config;
60 struct snd_aes_iec958;
61 struct snd_cea_861_aud_if;
63 enum omap_display_type {
64 OMAP_DISPLAY_TYPE_NONE = 0,
65 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
66 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
67 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
68 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
69 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
70 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
82 OMAP_DSS_CHANNEL_LCD = 0,
83 OMAP_DSS_CHANNEL_DIGIT = 1,
84 OMAP_DSS_CHANNEL_LCD2 = 2,
85 OMAP_DSS_CHANNEL_LCD3 = 3,
88 enum omap_color_mode {
89 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
90 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
91 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
92 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
93 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
94 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
95 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
96 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
97 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
98 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
99 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
100 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
101 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
102 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
103 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
104 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
105 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
106 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
107 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
110 enum omap_dss_load_mode {
111 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
112 OMAP_DSS_LOAD_CLUT_ONLY = 1,
113 OMAP_DSS_LOAD_FRAME_ONLY = 2,
114 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
117 enum omap_dss_trans_key_type {
118 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
119 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
122 enum omap_rfbi_te_mode {
123 OMAP_DSS_RFBI_TE_MODE_1 = 1,
124 OMAP_DSS_RFBI_TE_MODE_2 = 2,
127 enum omap_dss_signal_level {
128 OMAPDSS_SIG_ACTIVE_HIGH = 0,
129 OMAPDSS_SIG_ACTIVE_LOW = 1,
132 enum omap_dss_signal_edge {
133 OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
134 OMAPDSS_DRIVE_SIG_RISING_EDGE,
135 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
138 enum omap_dss_venc_type {
139 OMAP_DSS_VENC_TYPE_COMPOSITE,
140 OMAP_DSS_VENC_TYPE_SVIDEO,
143 enum omap_dss_dsi_pixel_format {
144 OMAP_DSS_DSI_FMT_RGB888,
145 OMAP_DSS_DSI_FMT_RGB666,
146 OMAP_DSS_DSI_FMT_RGB666_PACKED,
147 OMAP_DSS_DSI_FMT_RGB565,
150 enum omap_dss_dsi_mode {
151 OMAP_DSS_DSI_CMD_MODE = 0,
152 OMAP_DSS_DSI_VIDEO_MODE,
155 enum omap_display_caps {
156 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
157 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
160 enum omap_dss_display_state {
161 OMAP_DSS_DISPLAY_DISABLED = 0,
162 OMAP_DSS_DISPLAY_ACTIVE,
165 enum omap_dss_audio_state {
166 OMAP_DSS_AUDIO_DISABLED = 0,
167 OMAP_DSS_AUDIO_ENABLED,
168 OMAP_DSS_AUDIO_CONFIGURED,
169 OMAP_DSS_AUDIO_PLAYING,
172 enum omap_dss_rotation_type {
173 OMAP_DSS_ROT_DMA = 1 << 0,
174 OMAP_DSS_ROT_VRFB = 1 << 1,
175 OMAP_DSS_ROT_TILER = 1 << 2,
178 /* clockwise rotation angle */
179 enum omap_dss_rotation_angle {
182 OMAP_DSS_ROT_180 = 2,
183 OMAP_DSS_ROT_270 = 3,
186 enum omap_overlay_caps {
187 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
188 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
189 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
190 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
191 OMAP_DSS_OVL_CAP_POS = 1 << 4,
192 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
195 enum omap_overlay_manager_caps {
196 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
199 enum omap_dss_clk_source {
200 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
202 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
203 * OMAP4: PLL1_CLK1 */
204 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
205 * OMAP4: PLL1_CLK2 */
206 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
207 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
210 enum omap_hdmi_flags {
211 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
214 enum omap_dss_output_id {
215 OMAP_DSS_OUTPUT_DPI = 1 << 0,
216 OMAP_DSS_OUTPUT_DBI = 1 << 1,
217 OMAP_DSS_OUTPUT_SDI = 1 << 2,
218 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
219 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
220 OMAP_DSS_OUTPUT_VENC = 1 << 5,
221 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
226 struct rfbi_timings {
240 u32 tim[5]; /* set by rfbi_convert_timings() */
245 void omap_rfbi_write_command(const void *buf, u32 len);
246 void omap_rfbi_read_data(void *buf, u32 len);
247 void omap_rfbi_write_data(const void *buf, u32 len);
248 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
251 int omap_rfbi_enable_te(bool enable, unsigned line);
252 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
253 unsigned hs_pulse_time, unsigned vs_pulse_time,
254 int hs_pol_inv, int vs_pol_inv, int extif_div);
255 void rfbi_bus_lock(void);
256 void rfbi_bus_unlock(void);
260 struct omap_dss_dsi_videomode_timings {
261 /* DSI video mode blanking data */
262 /* Unit: byte clock cycles */
266 /* Unit: line clocks */
271 /* DSI blanking modes */
273 int hsa_blanking_mode;
274 int hbp_blanking_mode;
275 int hfp_blanking_mode;
277 /* Video port sync events */
281 bool ddr_clk_always_on;
285 struct omap_dss_dsi_config {
286 enum omap_dss_dsi_mode mode;
287 enum omap_dss_dsi_pixel_format pixel_format;
288 const struct omap_video_timings *timings;
289 const struct omap_dss_dsi_videomode_timings *vm_timings;
291 unsigned long hs_clk;
292 unsigned long lp_clk;
295 void dsi_bus_lock(struct omap_dss_device *dssdev);
296 void dsi_bus_unlock(struct omap_dss_device *dssdev);
297 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
299 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
301 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
302 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
303 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
305 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
307 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
308 u8 param1, u8 param2);
309 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
311 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
313 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
314 u8 *buf, int buflen);
315 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
317 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
318 u8 *buf, int buflen);
319 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
320 u8 param1, u8 param2, u8 *buf, int buflen);
321 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
323 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
324 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
325 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
326 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
328 enum omapdss_version {
329 OMAPDSS_VER_UNKNOWN = 0,
330 OMAPDSS_VER_OMAP24xx,
331 OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */
332 OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */
333 OMAPDSS_VER_OMAP3630,
335 OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */
336 OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
337 OMAPDSS_VER_OMAP4, /* All other OMAP4s */
341 /* Board specific data */
342 struct omap_dss_board_info {
343 int (*get_context_loss_count)(struct device *dev);
345 struct omap_dss_device **devices;
346 struct omap_dss_device *default_device;
347 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
348 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
349 int (*set_min_bus_tput)(struct device *dev, unsigned long r);
350 enum omapdss_version version;
353 /* Init with the board info */
354 extern int omap_display_init(struct omap_dss_board_info *board_data);
356 extern int omap_hdmi_init(enum omap_hdmi_flags flags);
358 struct omap_video_timings {
365 /* Unit: pixel clocks */
366 u16 hsw; /* Horizontal synchronization pulse width */
367 /* Unit: pixel clocks */
368 u16 hfp; /* Horizontal front porch */
369 /* Unit: pixel clocks */
370 u16 hbp; /* Horizontal back porch */
371 /* Unit: line clocks */
372 u16 vsw; /* Vertical synchronization pulse width */
373 /* Unit: line clocks */
374 u16 vfp; /* Vertical front porch */
375 /* Unit: line clocks */
376 u16 vbp; /* Vertical back porch */
378 /* Vsync logic level */
379 enum omap_dss_signal_level vsync_level;
380 /* Hsync logic level */
381 enum omap_dss_signal_level hsync_level;
382 /* Interlaced or Progressive timings */
384 /* Pixel clock edge to drive LCD data */
385 enum omap_dss_signal_edge data_pclk_edge;
386 /* Data enable logic level */
387 enum omap_dss_signal_level de_level;
388 /* Pixel clock edges to drive HSYNC and VSYNC signals */
389 enum omap_dss_signal_edge sync_pclk_edge;
392 #ifdef CONFIG_OMAP2_DSS_VENC
393 /* Hardcoded timings for tv modes. Venc only uses these to
394 * identify the mode, and does not actually use the configs
395 * itself. However, the configs should be something that
396 * a normal monitor can also show */
397 extern const struct omap_video_timings omap_dss_pal_timings;
398 extern const struct omap_video_timings omap_dss_ntsc_timings;
401 struct omap_dss_cpr_coefs {
407 struct omap_overlay_info {
409 u32 p_uv_addr; /* for NV12 format */
413 enum omap_color_mode color_mode;
415 enum omap_dss_rotation_type rotation_type;
420 u16 out_width; /* if 0, out_width == width */
421 u16 out_height; /* if 0, out_height == height */
427 struct omap_overlay {
429 struct list_head list;
434 enum omap_color_mode supported_modes;
435 enum omap_overlay_caps caps;
438 struct omap_overlay_manager *manager;
441 * The following functions do not block:
447 * The rest of the functions may block and cannot be called from
451 int (*enable)(struct omap_overlay *ovl);
452 int (*disable)(struct omap_overlay *ovl);
453 bool (*is_enabled)(struct omap_overlay *ovl);
455 int (*set_manager)(struct omap_overlay *ovl,
456 struct omap_overlay_manager *mgr);
457 int (*unset_manager)(struct omap_overlay *ovl);
459 int (*set_overlay_info)(struct omap_overlay *ovl,
460 struct omap_overlay_info *info);
461 void (*get_overlay_info)(struct omap_overlay *ovl,
462 struct omap_overlay_info *info);
464 int (*wait_for_go)(struct omap_overlay *ovl);
466 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
469 struct omap_overlay_manager_info {
472 enum omap_dss_trans_key_type trans_key_type;
476 bool partial_alpha_enabled;
479 struct omap_dss_cpr_coefs cpr_coefs;
482 struct omap_overlay_manager {
487 enum omap_channel id;
488 enum omap_overlay_manager_caps caps;
489 struct list_head overlays;
490 enum omap_display_type supported_displays;
491 enum omap_dss_output_id supported_outputs;
494 struct omap_dss_output *output;
497 * The following functions do not block:
503 * The rest of the functions may block and cannot be called from
507 int (*set_output)(struct omap_overlay_manager *mgr,
508 struct omap_dss_output *output);
509 int (*unset_output)(struct omap_overlay_manager *mgr);
511 int (*set_manager_info)(struct omap_overlay_manager *mgr,
512 struct omap_overlay_manager_info *info);
513 void (*get_manager_info)(struct omap_overlay_manager *mgr,
514 struct omap_overlay_manager_info *info);
516 int (*apply)(struct omap_overlay_manager *mgr);
517 int (*wait_for_go)(struct omap_overlay_manager *mgr);
518 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
520 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
523 /* 22 pins means 1 clk lane and 10 data lanes */
524 #define OMAP_DSS_MAX_DSI_PINS 22
526 struct omap_dsi_pin_config {
529 * pin numbers in the following order:
535 int pins[OMAP_DSS_MAX_DSI_PINS];
538 struct omap_dss_writeback_info {
544 enum omap_color_mode color_mode;
546 enum omap_dss_rotation_type rotation_type;
551 struct omap_dss_output {
552 struct list_head list;
556 /* display type supported by the output */
557 enum omap_display_type type;
559 /* DISPC channel for this output */
560 enum omap_channel dispc_channel;
562 /* output instance */
563 enum omap_dss_output_id id;
565 /* output's platform device pointer */
566 struct platform_device *pdev;
569 struct omap_overlay_manager *manager;
571 struct omap_dss_device *device;
574 struct omap_dss_device {
577 enum omap_display_type type;
579 /* obsolete, to be removed */
580 enum omap_channel channel;
604 enum omap_dss_venc_type type;
605 bool invert_polarity;
610 struct omap_video_timings timings;
612 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
613 enum omap_dss_dsi_mode dsi_mode;
614 struct omap_dss_dsi_videomode_timings dsi_vm_timings;
619 struct rfbi_timings rfbi_timings;
624 int max_backlight_level;
628 /* used to match device to driver */
629 const char *driver_name;
633 struct omap_dss_driver *driver;
635 /* helper variable for driver suspend/resume */
636 bool activate_after_resume;
638 enum omap_display_caps caps;
640 struct omap_dss_output *output;
642 enum omap_dss_display_state state;
644 enum omap_dss_audio_state audio_state;
646 /* platform specific */
647 int (*platform_enable)(struct omap_dss_device *dssdev);
648 void (*platform_disable)(struct omap_dss_device *dssdev);
649 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
650 int (*get_backlight)(struct omap_dss_device *dssdev);
653 struct omap_dss_hdmi_data
660 struct omap_dss_audio {
661 struct snd_aes_iec958 *iec;
662 struct snd_cea_861_aud_if *cea;
665 struct omap_dss_driver {
666 struct device_driver driver;
668 int (*probe)(struct omap_dss_device *);
669 void (*remove)(struct omap_dss_device *);
671 int (*enable)(struct omap_dss_device *display);
672 void (*disable)(struct omap_dss_device *display);
673 int (*run_test)(struct omap_dss_device *display, int test);
675 int (*update)(struct omap_dss_device *dssdev,
676 u16 x, u16 y, u16 w, u16 h);
677 int (*sync)(struct omap_dss_device *dssdev);
679 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
680 int (*get_te)(struct omap_dss_device *dssdev);
682 u8 (*get_rotate)(struct omap_dss_device *dssdev);
683 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
685 bool (*get_mirror)(struct omap_dss_device *dssdev);
686 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
688 int (*memory_read)(struct omap_dss_device *dssdev,
689 void *buf, size_t size,
690 u16 x, u16 y, u16 w, u16 h);
692 void (*get_resolution)(struct omap_dss_device *dssdev,
693 u16 *xres, u16 *yres);
694 void (*get_dimensions)(struct omap_dss_device *dssdev,
695 u32 *width, u32 *height);
696 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
698 int (*check_timings)(struct omap_dss_device *dssdev,
699 struct omap_video_timings *timings);
700 void (*set_timings)(struct omap_dss_device *dssdev,
701 struct omap_video_timings *timings);
702 void (*get_timings)(struct omap_dss_device *dssdev,
703 struct omap_video_timings *timings);
705 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
706 u32 (*get_wss)(struct omap_dss_device *dssdev);
708 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
709 bool (*detect)(struct omap_dss_device *dssdev);
712 * For display drivers that support audio. This encompasses
713 * HDMI and DisplayPort at the moment.
716 * Note: These functions might sleep. Do not call while
717 * holding a spinlock/readlock.
719 int (*audio_enable)(struct omap_dss_device *dssdev);
720 void (*audio_disable)(struct omap_dss_device *dssdev);
721 bool (*audio_supported)(struct omap_dss_device *dssdev);
722 int (*audio_config)(struct omap_dss_device *dssdev,
723 struct omap_dss_audio *audio);
724 /* Note: These functions may not sleep */
725 int (*audio_start)(struct omap_dss_device *dssdev);
726 void (*audio_stop)(struct omap_dss_device *dssdev);
730 enum omapdss_version omapdss_get_version(void);
732 int omap_dss_register_driver(struct omap_dss_driver *);
733 void omap_dss_unregister_driver(struct omap_dss_driver *);
735 void omap_dss_get_device(struct omap_dss_device *dssdev);
736 void omap_dss_put_device(struct omap_dss_device *dssdev);
737 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
738 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
739 struct omap_dss_device *omap_dss_find_device(void *data,
740 int (*match)(struct omap_dss_device *dssdev, void *data));
741 const char *omapdss_get_default_display_name(void);
743 int omap_dss_start_device(struct omap_dss_device *dssdev);
744 void omap_dss_stop_device(struct omap_dss_device *dssdev);
746 int dss_feat_get_num_mgrs(void);
747 int dss_feat_get_num_ovls(void);
748 enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
749 enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
750 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
754 int omap_dss_get_num_overlay_managers(void);
755 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
757 int omap_dss_get_num_overlays(void);
758 struct omap_overlay *omap_dss_get_overlay(int num);
760 struct omap_dss_output *omap_dss_get_output(enum omap_dss_output_id id);
761 int omapdss_output_set_device(struct omap_dss_output *out,
762 struct omap_dss_device *dssdev);
763 int omapdss_output_unset_device(struct omap_dss_output *out);
765 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
766 u16 *xres, u16 *yres);
767 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
768 void omapdss_default_get_timings(struct omap_dss_device *dssdev,
769 struct omap_video_timings *timings);
771 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
772 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
773 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
775 u32 dispc_read_irqstatus(void);
776 void dispc_clear_irqstatus(u32 mask);
777 u32 dispc_read_irqenable(void);
778 void dispc_write_irqenable(u32 mask);
780 int dispc_request_irq(irq_handler_t handler, void *dev_id);
781 void dispc_free_irq(void *dev_id);
783 int dispc_runtime_get(void);
784 void dispc_runtime_put(void);
786 void dispc_mgr_enable(enum omap_channel channel, bool enable);
787 bool dispc_mgr_is_enabled(enum omap_channel channel);
788 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
789 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
790 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
791 bool dispc_mgr_go_busy(enum omap_channel channel);
792 void dispc_mgr_go(enum omap_channel channel);
793 void dispc_mgr_set_lcd_config(enum omap_channel channel,
794 const struct dss_lcd_mgr_config *config);
795 void dispc_mgr_set_timings(enum omap_channel channel,
796 const struct omap_video_timings *timings);
797 void dispc_mgr_setup(enum omap_channel channel,
798 const struct omap_overlay_manager_info *info);
800 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
801 const struct omap_overlay_info *oi,
802 const struct omap_video_timings *timings,
803 int *x_predecim, int *y_predecim);
805 int dispc_ovl_enable(enum omap_plane plane, bool enable);
806 bool dispc_ovl_enabled(enum omap_plane plane);
807 void dispc_ovl_set_channel_out(enum omap_plane plane,
808 enum omap_channel channel);
809 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
810 bool replication, const struct omap_video_timings *mgr_timings,
813 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
814 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
816 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
818 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
819 int omapdss_dsi_set_config(struct omap_dss_device *dssdev,
820 const struct omap_dss_dsi_config *config);
822 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
823 void (*callback)(int, void *), void *data);
824 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
825 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
826 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
827 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
828 const struct omap_dsi_pin_config *pin_cfg);
830 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
831 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
832 bool disconnect_lanes, bool enter_ulps);
834 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
835 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
836 void omapdss_dpi_set_timings(struct omap_dss_device *dssdev,
837 struct omap_video_timings *timings);
838 int dpi_check_timings(struct omap_dss_device *dssdev,
839 struct omap_video_timings *timings);
840 void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines);
842 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
843 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
844 void omapdss_sdi_set_timings(struct omap_dss_device *dssdev,
845 struct omap_video_timings *timings);
846 void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs);
848 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
849 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
850 int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *),
852 int omap_rfbi_configure(struct omap_dss_device *dssdev);
853 void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
854 void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev,
856 void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev,
858 void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev,
859 struct rfbi_timings *timings);
861 int omapdss_compat_init(void);
862 void omapdss_compat_uninit(void);
865 void (*start_update)(struct omap_overlay_manager *mgr);
866 int (*enable)(struct omap_overlay_manager *mgr);
867 void (*disable)(struct omap_overlay_manager *mgr);
868 void (*set_timings)(struct omap_overlay_manager *mgr,
869 const struct omap_video_timings *timings);
870 void (*set_lcd_config)(struct omap_overlay_manager *mgr,
871 const struct dss_lcd_mgr_config *config);
872 int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
873 void (*handler)(void *), void *data);
874 void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
875 void (*handler)(void *), void *data);
878 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
879 void dss_uninstall_mgr_ops(void);
881 void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
882 const struct omap_video_timings *timings);
883 void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
884 const struct dss_lcd_mgr_config *config);
885 int dss_mgr_enable(struct omap_overlay_manager *mgr);
886 void dss_mgr_disable(struct omap_overlay_manager *mgr);
887 void dss_mgr_start_update(struct omap_overlay_manager *mgr);
888 int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
889 void (*handler)(void *), void *data);
890 void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
891 void (*handler)(void *), void *data);