1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
5 * Definitions for EMU10K1 (SB Live!) chips
7 #ifndef _UAPI__SOUND_EMU10K1_H
8 #define _UAPI__SOUND_EMU10K1_H
11 #include <linux/types.h>
18 #define EMU10K1_CARD_CREATIVE 0x00000000
19 #define EMU10K1_CARD_EMUAPS 0x00000001
21 #define EMU10K1_FX8010_PCM_COUNT 8
24 * Following definition is copied from linux/types.h to support compiling
25 * this header file in userspace since they are not generally available for
28 #define __EMU10K1_DECLARE_BITMAP(name,bits) \
29 unsigned long name[(bits) / (sizeof(unsigned long) * 8)]
32 #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */
33 #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */
34 #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */
35 #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */
36 #define iMACINT0 0x04 /* R = A + X * Y ; saturation */
37 #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */
38 #define iACC3 0x06 /* R = A + X + Y ; saturation */
39 #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */
40 #define iANDXOR 0x08 /* R = (A & X) ^ Y */
41 #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */
42 #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */
43 #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */
44 #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
45 #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
46 #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
47 #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
50 #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
51 #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
52 #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
53 #define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
54 /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
56 #define C_00000000 0x40
57 #define C_00000001 0x41
58 #define C_00000002 0x42
59 #define C_00000003 0x43
60 #define C_00000004 0x44
61 #define C_00000008 0x45
62 #define C_00000010 0x46
63 #define C_00000020 0x47
64 #define C_00000100 0x48
65 #define C_00010000 0x49
66 #define C_00080000 0x4a
67 #define C_10000000 0x4b
68 #define C_20000000 0x4c
69 #define C_40000000 0x4d
70 #define C_80000000 0x4e
71 #define C_7fffffff 0x4f
72 #define C_ffffffff 0x50
73 #define C_fffffffe 0x51
74 #define C_c0000000 0x52
75 #define C_4f1bbcdc 0x53
76 #define C_5a7ef9db 0x54
77 #define C_00100000 0x55 /* ?? */
78 #define GPR_ACCU 0x56 /* ACCUM, accumulator */
79 #define GPR_COND 0x57 /* CCR, condition register */
80 #define GPR_NOISE0 0x58 /* noise source */
81 #define GPR_NOISE1 0x59 /* noise source */
82 #define GPR_IRQ 0x5a /* IRQ register */
83 #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
84 #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
85 #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
86 #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
87 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
88 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
90 #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
91 #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
92 #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
93 #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
94 #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
95 #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
97 #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
98 #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
99 #define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
100 #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
101 #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
102 #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
103 #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
104 #define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */
105 #define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */
106 #define A_GPR(x) (A_FXGPREGBASE + (x))
108 /* cc_reg constants */
109 #define CC_REG_NORMALIZED C_00000001
110 #define CC_REG_BORROW C_00000002
111 #define CC_REG_MINUS C_00000004
112 #define CC_REG_ZERO C_00000008
113 #define CC_REG_SATURATE C_00000010
114 #define CC_REG_NONZERO C_00000100
117 #define FXBUS_PCM_LEFT 0x00
118 #define FXBUS_PCM_RIGHT 0x01
119 #define FXBUS_PCM_LEFT_REAR 0x02
120 #define FXBUS_PCM_RIGHT_REAR 0x03
121 #define FXBUS_MIDI_LEFT 0x04
122 #define FXBUS_MIDI_RIGHT 0x05
123 #define FXBUS_PCM_CENTER 0x06
124 #define FXBUS_PCM_LFE 0x07
125 #define FXBUS_PCM_LEFT_FRONT 0x08
126 #define FXBUS_PCM_RIGHT_FRONT 0x09
127 #define FXBUS_MIDI_REVERB 0x0c
128 #define FXBUS_MIDI_CHORUS 0x0d
129 #define FXBUS_PCM_LEFT_SIDE 0x0e
130 #define FXBUS_PCM_RIGHT_SIDE 0x0f
131 #define FXBUS_PT_LEFT 0x14
132 #define FXBUS_PT_RIGHT 0x15
135 #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
136 #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
137 #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */
138 #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */
139 #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */
140 #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */
141 #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */
142 #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */
143 #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */
144 #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */
145 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
146 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
147 #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */
148 #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */
151 #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */
152 #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */
153 #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */
154 #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */
155 #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */
156 #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */
157 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
158 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
159 #define EXTOUT_REAR_L 0x08 /* Rear channel - left */
160 #define EXTOUT_REAR_R 0x09 /* Rear channel - right */
161 #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */
162 #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */
163 #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */
164 #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */
165 #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */
166 #define EXTOUT_ACENTER 0x11 /* Analog Center */
167 #define EXTOUT_ALFE 0x12 /* Analog LFE */
170 #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
171 #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
172 #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */
173 #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */
174 #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */
175 #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */
176 #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */
177 #define A_EXTIN_LINE2_R 0x09 /* right */
178 #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */
179 #define A_EXTIN_ADC_R 0x0b /* right */
180 #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */
181 #define A_EXTIN_AUX2_R 0x0d /* - right */
183 /* Audigiy Outputs */
184 #define A_EXTOUT_FRONT_L 0x00 /* digital front left */
185 #define A_EXTOUT_FRONT_R 0x01 /* right */
186 #define A_EXTOUT_CENTER 0x02 /* digital front center */
187 #define A_EXTOUT_LFE 0x03 /* digital front lfe */
188 #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */
189 #define A_EXTOUT_HEADPHONE_R 0x05 /* right */
190 #define A_EXTOUT_REAR_L 0x06 /* digital rear left */
191 #define A_EXTOUT_REAR_R 0x07 /* right */
192 #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */
193 #define A_EXTOUT_AFRONT_R 0x09 /* right */
194 #define A_EXTOUT_ACENTER 0x0a /* analog center */
195 #define A_EXTOUT_ALFE 0x0b /* analog LFE */
196 #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */
197 #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */
198 #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */
199 #define A_EXTOUT_AREAR_R 0x0f /* right */
200 #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */
201 #define A_EXTOUT_AC97_R 0x11 /* right */
202 #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */
203 #define A_EXTOUT_ADC_CAP_R 0x17 /* right */
204 #define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
206 /* Audigy constants */
207 #define A_C_00000000 0xc0
208 #define A_C_00000001 0xc1
209 #define A_C_00000002 0xc2
210 #define A_C_00000003 0xc3
211 #define A_C_00000004 0xc4
212 #define A_C_00000008 0xc5
213 #define A_C_00000010 0xc6
214 #define A_C_00000020 0xc7
215 #define A_C_00000100 0xc8
216 #define A_C_00010000 0xc9
217 #define A_C_00000800 0xca
218 #define A_C_10000000 0xcb
219 #define A_C_20000000 0xcc
220 #define A_C_40000000 0xcd
221 #define A_C_80000000 0xce
222 #define A_C_7fffffff 0xcf
223 #define A_C_ffffffff 0xd0
224 #define A_C_fffffffe 0xd1
225 #define A_C_c0000000 0xd2
226 #define A_C_4f1bbcdc 0xd3
227 #define A_C_5a7ef9db 0xd4
228 #define A_C_00100000 0xd5
229 #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
230 #define A_GPR_COND 0xd7 /* CCR, condition register */
231 #define A_GPR_NOISE0 0xd8 /* noise source */
232 #define A_GPR_NOISE1 0xd9 /* noise source */
233 #define A_GPR_IRQ 0xda /* IRQ register */
234 #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
235 #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
237 /* definitions for debug register */
238 #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
239 #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
240 #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
241 #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */
242 #define EMU10K1_DBG_STEP 0x00004000 /* start single step */
243 #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
244 #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
246 /* tank memory address line */
248 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
249 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
250 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
251 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
252 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
255 struct snd_emu10k1_fx8010_info {
256 unsigned int internal_tram_size; /* in samples */
257 unsigned int external_tram_size; /* in samples */
258 char fxbus_names[16][32]; /* names of FXBUSes */
259 char extin_names[16][32]; /* names of external inputs */
260 char extout_names[32][32]; /* names of external outputs */
261 unsigned int gpr_controls; /* count of GPR controls */
264 #define EMU10K1_GPR_TRANSLATION_NONE 0
265 #define EMU10K1_GPR_TRANSLATION_TABLE100 1
266 #define EMU10K1_GPR_TRANSLATION_BASS 2
267 #define EMU10K1_GPR_TRANSLATION_TREBLE 3
268 #define EMU10K1_GPR_TRANSLATION_ONOFF 4
270 enum emu10k1_ctl_elem_iface {
271 EMU10K1_CTL_ELEM_IFACE_MIXER = 2, /* virtual mixer device */
272 EMU10K1_CTL_ELEM_IFACE_PCM = 3, /* PCM device */
275 struct emu10k1_ctl_elem_id {
276 unsigned int pad; /* don't use */
277 int iface; /* interface identifier */
278 unsigned int device; /* device/client number */
279 unsigned int subdevice; /* subdevice (substream) number */
280 unsigned char name[44]; /* ASCII name of item */
281 unsigned int index; /* index of item */
284 struct snd_emu10k1_fx8010_control_gpr {
285 struct emu10k1_ctl_elem_id id; /* full control ID definition */
286 unsigned int vcount; /* visible count */
287 unsigned int count; /* count of GPR (1..16) */
288 unsigned short gpr[32]; /* GPR number(s) */
289 unsigned int value[32]; /* initial values */
290 unsigned int min; /* minimum range */
291 unsigned int max; /* maximum range */
292 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
293 const unsigned int *tlv;
296 /* old ABI without TLV support */
297 struct snd_emu10k1_fx8010_control_old_gpr {
298 struct emu10k1_ctl_elem_id id;
301 unsigned short gpr[32];
302 unsigned int value[32];
305 unsigned int translation;
308 struct snd_emu10k1_fx8010_code {
311 __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */
312 __u32 *gpr_map; /* initializers */
314 unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */
315 struct snd_emu10k1_fx8010_control_gpr *gpr_add_controls; /* GPR controls to add/replace */
317 unsigned int gpr_del_control_count; /* count of GPR controls to remove */
318 struct emu10k1_ctl_elem_id *gpr_del_controls; /* IDs of GPR controls to remove */
320 unsigned int gpr_list_control_count; /* count of GPR controls to list */
321 unsigned int gpr_list_control_total; /* total count of GPR controls */
322 struct snd_emu10k1_fx8010_control_gpr *gpr_list_controls; /* listed GPR controls */
324 __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */
325 __u32 *tram_data_map; /* data initializers */
326 __u32 *tram_addr_map; /* map initializers */
328 __EMU10K1_DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */
329 __u32 *code; /* one instruction - 64 bits */
332 struct snd_emu10k1_fx8010_tram {
333 unsigned int address; /* 31.bit == 1 -> external TRAM */
334 unsigned int size; /* size in samples (4 bytes) */
335 unsigned int *samples; /* pointer to samples (20-bit) */
336 /* NULL->clear memory */
339 struct snd_emu10k1_fx8010_pcm_rec {
340 unsigned int substream; /* substream number */
341 unsigned int res1; /* reserved */
342 unsigned int channels; /* 16-bit channels count, zero = remove this substream */
343 unsigned int tram_start; /* ring buffer position in TRAM (in samples) */
344 unsigned int buffer_size; /* count of buffered samples */
345 unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */
346 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
347 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
348 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
349 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
350 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
351 unsigned char pad; /* reserved */
352 unsigned char etram[32]; /* external TRAM address & data (one per channel) */
353 unsigned int res2; /* reserved */
356 #define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
358 #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)
359 #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)
360 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
361 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
362 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)
363 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
364 #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
365 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
366 #define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int)
367 #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
368 #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
369 #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
370 #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
371 #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
373 #endif /* _UAPI__SOUND_EMU10K1_H */