1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #ifndef MLX5_ABI_USER_H
35 #define MLX5_ABI_USER_H
37 #include <linux/types.h>
38 #include <linux/if_ether.h> /* For ETH_ALEN. */
41 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
42 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
43 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
44 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3,
45 MLX5_QP_FLAG_TYPE_DCT = 1 << 4,
46 MLX5_QP_FLAG_TYPE_DCI = 1 << 5,
50 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
54 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
57 /* Increment this value if any changes that break userspace ABI
58 * compatibility are made.
60 #define MLX5_IB_UVERBS_ABI_VERSION 1
62 /* Make sure that all structs defined in this file remain laid out so
63 * that they pack the same way on 32-bit and 64-bit architectures (to
64 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
65 * In particular do not use pointer types -- pass pointers in __u64
69 struct mlx5_ib_alloc_ucontext_req {
70 __u32 total_num_bfregs;
71 __u32 num_low_latency_bfregs;
75 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
78 struct mlx5_ib_alloc_ucontext_req_v2 {
79 __u32 total_num_bfregs;
80 __u32 num_low_latency_bfregs;
87 __aligned_u64 lib_caps;
90 enum mlx5_ib_alloc_ucontext_resp_mask {
91 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
94 enum mlx5_user_cmds_supp_uhw {
95 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
96 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
99 /* The eth_min_inline response value is set to off-by-one vs the FW
100 * returned value to allow user-space to deal with older kernels.
102 enum mlx5_user_inline_mode {
103 MLX5_USER_INLINE_MODE_NA,
104 MLX5_USER_INLINE_MODE_NONE,
105 MLX5_USER_INLINE_MODE_L2,
106 MLX5_USER_INLINE_MODE_IP,
107 MLX5_USER_INLINE_MODE_TCP_UDP,
111 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
112 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
113 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
114 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
115 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
118 struct mlx5_ib_alloc_ucontext_resp {
122 __u32 cache_line_size;
123 __u16 max_sq_desc_sz;
124 __u16 max_rq_desc_sz;
125 __u32 max_send_wqebb;
127 __u32 max_srq_recv_wr;
129 __u16 flow_action_flags;
131 __u32 response_length;
135 __u8 clock_info_versions;
136 __aligned_u64 hca_core_clock_offset;
138 __u32 num_uars_per_page;
139 __u32 num_dyn_bfregs;
143 struct mlx5_ib_alloc_pd_resp {
147 struct mlx5_ib_tso_caps {
148 __u32 max_tso; /* Maximum tso payload size in bytes */
150 /* Corresponding bit will be set if qp type from
151 * 'enum ib_qp_type' is supported, e.g.
152 * supported_qpts |= 1 << IB_QPT_UD
154 __u32 supported_qpts;
157 struct mlx5_ib_rss_caps {
158 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
159 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
163 enum mlx5_ib_cqe_comp_res_format {
164 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
165 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
166 MLX5_IB_CQE_RES_RESERVED = 1 << 2,
169 struct mlx5_ib_cqe_comp_caps {
171 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
174 enum mlx5_ib_packet_pacing_cap_flags {
175 MLX5_IB_PP_SUPPORT_BURST = 1 << 0,
178 struct mlx5_packet_pacing_caps {
179 __u32 qp_rate_limit_min;
180 __u32 qp_rate_limit_max; /* In kpbs */
182 /* Corresponding bit will be set if qp type from
183 * 'enum ib_qp_type' is supported, e.g.
184 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
186 __u32 supported_qpts;
187 __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */
191 enum mlx5_ib_mpw_caps {
192 MPW_RESERVED = 1 << 0,
193 MLX5_IB_ALLOW_MPW = 1 << 1,
194 MLX5_IB_SUPPORT_EMPW = 1 << 2,
197 enum mlx5_ib_sw_parsing_offloads {
198 MLX5_IB_SW_PARSING = 1 << 0,
199 MLX5_IB_SW_PARSING_CSUM = 1 << 1,
200 MLX5_IB_SW_PARSING_LSO = 1 << 2,
203 struct mlx5_ib_sw_parsing_caps {
204 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */
206 /* Corresponding bit will be set if qp type from
207 * 'enum ib_qp_type' is supported, e.g.
208 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
210 __u32 supported_qpts;
213 struct mlx5_ib_striding_rq_caps {
214 __u32 min_single_stride_log_num_of_bytes;
215 __u32 max_single_stride_log_num_of_bytes;
216 __u32 min_single_wqe_log_num_of_strides;
217 __u32 max_single_wqe_log_num_of_strides;
219 /* Corresponding bit will be set if qp type from
220 * 'enum ib_qp_type' is supported, e.g.
221 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
223 __u32 supported_qpts;
227 enum mlx5_ib_query_dev_resp_flags {
228 /* Support 128B CQE compression */
229 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
230 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
233 enum mlx5_ib_tunnel_offloads {
234 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
235 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
236 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2
239 struct mlx5_ib_query_device_resp {
241 __u32 response_length;
242 struct mlx5_ib_tso_caps tso_caps;
243 struct mlx5_ib_rss_caps rss_caps;
244 struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
245 struct mlx5_packet_pacing_caps packet_pacing_caps;
246 __u32 mlx5_ib_support_multi_pkt_send_wqes;
247 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */
248 struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
249 struct mlx5_ib_striding_rq_caps striding_rq_caps;
250 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
254 enum mlx5_ib_create_cq_flags {
255 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
258 struct mlx5_ib_create_cq {
259 __aligned_u64 buf_addr;
260 __aligned_u64 db_addr;
263 __u8 cqe_comp_res_format;
267 struct mlx5_ib_create_cq_resp {
272 struct mlx5_ib_resize_cq {
273 __aligned_u64 buf_addr;
279 struct mlx5_ib_create_srq {
280 __aligned_u64 buf_addr;
281 __aligned_u64 db_addr;
283 __u32 reserved0; /* explicit padding (optional on i386) */
288 struct mlx5_ib_create_srq_resp {
293 struct mlx5_ib_create_qp {
294 __aligned_u64 buf_addr;
295 __aligned_u64 db_addr;
303 __aligned_u64 sq_buf_addr;
304 __aligned_u64 access_key;
308 /* RX Hash function flags */
309 enum mlx5_rx_hash_function_flags {
310 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
314 * RX Hash flags, these flags allows to set which incoming packet's field should
315 * participates in RX Hash. Each flag represent certain packet's field,
316 * when the flag is set the field that is represented by the flag will
317 * participate in RX Hash calculation.
318 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
319 * and *TCP and *UDP flags can't be enabled together on the same QP.
321 enum mlx5_rx_hash_fields {
322 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
323 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
324 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
325 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
326 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
327 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
328 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
329 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
330 MLX5_RX_HASH_IPSEC_SPI = 1 << 8,
331 /* Save bits for future fields */
332 MLX5_RX_HASH_INNER = (1UL << 31),
335 struct mlx5_ib_create_qp_rss {
336 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
337 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
338 __u8 rx_key_len; /* valid only for Toeplitz */
340 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
345 struct mlx5_ib_create_qp_resp {
350 struct mlx5_ib_alloc_mw {
357 enum mlx5_ib_create_wq_mask {
358 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
361 struct mlx5_ib_create_wq {
362 __aligned_u64 buf_addr;
363 __aligned_u64 db_addr;
369 __u32 single_stride_log_num_of_bytes;
370 __u32 single_wqe_log_num_of_strides;
371 __u32 two_byte_shift_en;
374 struct mlx5_ib_create_ah_resp {
375 __u32 response_length;
380 struct mlx5_ib_burst_info {
382 __u16 typical_pkt_sz;
386 struct mlx5_ib_modify_qp {
388 struct mlx5_ib_burst_info burst_info;
392 struct mlx5_ib_modify_qp_resp {
393 __u32 response_length;
397 struct mlx5_ib_create_wq_resp {
398 __u32 response_length;
402 struct mlx5_ib_create_rwq_ind_tbl_resp {
403 __u32 response_length;
407 struct mlx5_ib_modify_wq {
412 struct mlx5_ib_clock_info {
416 __aligned_u64 cycles;
421 __aligned_u64 overflow_period;
424 enum mlx5_ib_mmap_cmd {
425 MLX5_IB_MMAP_REGULAR_PAGE = 0,
426 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
427 MLX5_IB_MMAP_WC_PAGE = 2,
428 MLX5_IB_MMAP_NC_PAGE = 3,
429 /* 5 is chosen in order to be compatible with old versions of libmlx5 */
430 MLX5_IB_MMAP_CORE_CLOCK = 5,
431 MLX5_IB_MMAP_ALLOC_WC = 6,
432 MLX5_IB_MMAP_CLOCK_INFO = 7,
433 MLX5_IB_MMAP_DEVICE_MEM = 8,
437 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
440 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
442 MLX5_IB_CLOCK_INFO_V1 = 0,
444 #endif /* MLX5_ABI_USER_H */