1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #ifndef MLX5_ABI_USER_H
35 #define MLX5_ABI_USER_H
37 #include <linux/types.h>
38 #include <linux/if_ether.h> /* For ETH_ALEN. */
41 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
42 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
43 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
47 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
51 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
54 /* Increment this value if any changes that break userspace ABI
55 * compatibility are made.
57 #define MLX5_IB_UVERBS_ABI_VERSION 1
59 /* Make sure that all structs defined in this file remain laid out so
60 * that they pack the same way on 32-bit and 64-bit architectures (to
61 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
62 * In particular do not use pointer types -- pass pointers in __u64
66 struct mlx5_ib_alloc_ucontext_req {
67 __u32 total_num_bfregs;
68 __u32 num_low_latency_bfregs;
72 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
75 struct mlx5_ib_alloc_ucontext_req_v2 {
76 __u32 total_num_bfregs;
77 __u32 num_low_latency_bfregs;
87 enum mlx5_ib_alloc_ucontext_resp_mask {
88 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
91 enum mlx5_user_cmds_supp_uhw {
92 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
93 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
96 /* The eth_min_inline response value is set to off-by-one vs the FW
97 * returned value to allow user-space to deal with older kernels.
99 enum mlx5_user_inline_mode {
100 MLX5_USER_INLINE_MODE_NA,
101 MLX5_USER_INLINE_MODE_NONE,
102 MLX5_USER_INLINE_MODE_L2,
103 MLX5_USER_INLINE_MODE_IP,
104 MLX5_USER_INLINE_MODE_TCP_UDP,
107 struct mlx5_ib_alloc_ucontext_resp {
111 __u32 cache_line_size;
112 __u16 max_sq_desc_sz;
113 __u16 max_rq_desc_sz;
114 __u32 max_send_wqebb;
116 __u32 max_srq_recv_wr;
120 __u32 response_length;
125 __u64 hca_core_clock_offset;
127 __u32 num_uars_per_page;
128 __u32 num_dyn_bfregs;
132 struct mlx5_ib_alloc_pd_resp {
136 struct mlx5_ib_tso_caps {
137 __u32 max_tso; /* Maximum tso payload size in bytes */
139 /* Corresponding bit will be set if qp type from
140 * 'enum ib_qp_type' is supported, e.g.
141 * supported_qpts |= 1 << IB_QPT_UD
143 __u32 supported_qpts;
146 struct mlx5_ib_rss_caps {
147 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
148 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
152 enum mlx5_ib_cqe_comp_res_format {
153 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
154 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
155 MLX5_IB_CQE_RES_RESERVED = 1 << 2,
158 struct mlx5_ib_cqe_comp_caps {
160 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
163 struct mlx5_packet_pacing_caps {
164 __u32 qp_rate_limit_min;
165 __u32 qp_rate_limit_max; /* In kpbs */
167 /* Corresponding bit will be set if qp type from
168 * 'enum ib_qp_type' is supported, e.g.
169 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
171 __u32 supported_qpts;
175 enum mlx5_ib_mpw_caps {
176 MPW_RESERVED = 1 << 0,
177 MLX5_IB_ALLOW_MPW = 1 << 1,
178 MLX5_IB_SUPPORT_EMPW = 1 << 2,
181 enum mlx5_ib_sw_parsing_offloads {
182 MLX5_IB_SW_PARSING = 1 << 0,
183 MLX5_IB_SW_PARSING_CSUM = 1 << 1,
184 MLX5_IB_SW_PARSING_LSO = 1 << 2,
187 struct mlx5_ib_sw_parsing_caps {
188 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */
190 /* Corresponding bit will be set if qp type from
191 * 'enum ib_qp_type' is supported, e.g.
192 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
194 __u32 supported_qpts;
197 struct mlx5_ib_striding_rq_caps {
198 __u32 min_single_stride_log_num_of_bytes;
199 __u32 max_single_stride_log_num_of_bytes;
200 __u32 min_single_wqe_log_num_of_strides;
201 __u32 max_single_wqe_log_num_of_strides;
203 /* Corresponding bit will be set if qp type from
204 * 'enum ib_qp_type' is supported, e.g.
205 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
207 __u32 supported_qpts;
211 enum mlx5_ib_query_dev_resp_flags {
212 /* Support 128B CQE compression */
213 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
214 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
217 enum mlx5_ib_tunnel_offloads {
218 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
219 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
220 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2
223 struct mlx5_ib_query_device_resp {
225 __u32 response_length;
226 struct mlx5_ib_tso_caps tso_caps;
227 struct mlx5_ib_rss_caps rss_caps;
228 struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
229 struct mlx5_packet_pacing_caps packet_pacing_caps;
230 __u32 mlx5_ib_support_multi_pkt_send_wqes;
231 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */
232 struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
233 struct mlx5_ib_striding_rq_caps striding_rq_caps;
234 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
238 enum mlx5_ib_create_cq_flags {
239 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
242 struct mlx5_ib_create_cq {
247 __u8 cqe_comp_res_format;
251 struct mlx5_ib_create_cq_resp {
256 struct mlx5_ib_resize_cq {
263 struct mlx5_ib_create_srq {
267 __u32 reserved0; /* explicit padding (optional on i386) */
272 struct mlx5_ib_create_srq_resp {
277 struct mlx5_ib_create_qp {
289 /* RX Hash function flags */
290 enum mlx5_rx_hash_function_flags {
291 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
295 * RX Hash flags, these flags allows to set which incoming packet's field should
296 * participates in RX Hash. Each flag represent certain packet's field,
297 * when the flag is set the field that is represented by the flag will
298 * participate in RX Hash calculation.
299 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
300 * and *TCP and *UDP flags can't be enabled together on the same QP.
302 enum mlx5_rx_hash_fields {
303 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
304 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
305 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
306 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
307 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
308 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
309 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
310 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
311 /* Save bits for future fields */
312 MLX5_RX_HASH_INNER = (1UL << 31),
315 struct mlx5_ib_create_qp_rss {
316 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
317 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
318 __u8 rx_key_len; /* valid only for Toeplitz */
320 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
325 struct mlx5_ib_create_qp_resp {
329 struct mlx5_ib_alloc_mw {
336 enum mlx5_ib_create_wq_mask {
337 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
340 struct mlx5_ib_create_wq {
348 __u32 single_stride_log_num_of_bytes;
349 __u32 single_wqe_log_num_of_strides;
350 __u32 two_byte_shift_en;
353 struct mlx5_ib_create_ah_resp {
354 __u32 response_length;
359 struct mlx5_ib_create_wq_resp {
360 __u32 response_length;
364 struct mlx5_ib_create_rwq_ind_tbl_resp {
365 __u32 response_length;
369 struct mlx5_ib_modify_wq {
373 #endif /* MLX5_ABI_USER_H */