4 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra
8 * Data type definitions, declarations, prototypes.
10 * Started by: Thomas Gleixner and Ingo Molnar
12 * For licencing details see kernel-base/COPYING
14 #ifndef _UAPI_LINUX_PERF_EVENT_H
15 #define _UAPI_LINUX_PERF_EVENT_H
17 #include <linux/types.h>
18 #include <linux/ioctl.h>
19 #include <asm/byteorder.h>
22 * User-space ABI bits:
29 PERF_TYPE_HARDWARE = 0,
30 PERF_TYPE_SOFTWARE = 1,
31 PERF_TYPE_TRACEPOINT = 2,
32 PERF_TYPE_HW_CACHE = 3,
34 PERF_TYPE_BREAKPOINT = 5,
36 PERF_TYPE_MAX, /* non-ABI */
40 * Generalized performance event event_id types, used by the
41 * attr.event_id parameter of the sys_perf_event_open()
46 * Common hardware events, generalized by the kernel:
48 PERF_COUNT_HW_CPU_CYCLES = 0,
49 PERF_COUNT_HW_INSTRUCTIONS = 1,
50 PERF_COUNT_HW_CACHE_REFERENCES = 2,
51 PERF_COUNT_HW_CACHE_MISSES = 3,
52 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,
53 PERF_COUNT_HW_BRANCH_MISSES = 5,
54 PERF_COUNT_HW_BUS_CYCLES = 6,
55 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,
56 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,
57 PERF_COUNT_HW_REF_CPU_CYCLES = 9,
59 PERF_COUNT_HW_MAX, /* non-ABI */
63 * Generalized hardware cache events:
65 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
66 * { read, write, prefetch } x
67 * { accesses, misses }
69 enum perf_hw_cache_id {
70 PERF_COUNT_HW_CACHE_L1D = 0,
71 PERF_COUNT_HW_CACHE_L1I = 1,
72 PERF_COUNT_HW_CACHE_LL = 2,
73 PERF_COUNT_HW_CACHE_DTLB = 3,
74 PERF_COUNT_HW_CACHE_ITLB = 4,
75 PERF_COUNT_HW_CACHE_BPU = 5,
76 PERF_COUNT_HW_CACHE_NODE = 6,
78 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
81 enum perf_hw_cache_op_id {
82 PERF_COUNT_HW_CACHE_OP_READ = 0,
83 PERF_COUNT_HW_CACHE_OP_WRITE = 1,
84 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
86 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */
89 enum perf_hw_cache_op_result_id {
90 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
91 PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
93 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */
97 * Special "software" events provided by the kernel, even if the hardware
98 * does not support performance events. These events measure various
99 * physical and sw events of the kernel (and allow the profiling of them as
103 PERF_COUNT_SW_CPU_CLOCK = 0,
104 PERF_COUNT_SW_TASK_CLOCK = 1,
105 PERF_COUNT_SW_PAGE_FAULTS = 2,
106 PERF_COUNT_SW_CONTEXT_SWITCHES = 3,
107 PERF_COUNT_SW_CPU_MIGRATIONS = 4,
108 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5,
109 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,
110 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7,
111 PERF_COUNT_SW_EMULATION_FAULTS = 8,
112 PERF_COUNT_SW_DUMMY = 9,
114 PERF_COUNT_SW_MAX, /* non-ABI */
118 * Bits that can be set in attr.sample_type to request information
119 * in the overflow packets.
121 enum perf_event_sample_format {
122 PERF_SAMPLE_IP = 1U << 0,
123 PERF_SAMPLE_TID = 1U << 1,
124 PERF_SAMPLE_TIME = 1U << 2,
125 PERF_SAMPLE_ADDR = 1U << 3,
126 PERF_SAMPLE_READ = 1U << 4,
127 PERF_SAMPLE_CALLCHAIN = 1U << 5,
128 PERF_SAMPLE_ID = 1U << 6,
129 PERF_SAMPLE_CPU = 1U << 7,
130 PERF_SAMPLE_PERIOD = 1U << 8,
131 PERF_SAMPLE_STREAM_ID = 1U << 9,
132 PERF_SAMPLE_RAW = 1U << 10,
133 PERF_SAMPLE_BRANCH_STACK = 1U << 11,
134 PERF_SAMPLE_REGS_USER = 1U << 12,
135 PERF_SAMPLE_STACK_USER = 1U << 13,
136 PERF_SAMPLE_WEIGHT = 1U << 14,
137 PERF_SAMPLE_DATA_SRC = 1U << 15,
138 PERF_SAMPLE_IDENTIFIER = 1U << 16,
139 PERF_SAMPLE_TRANSACTION = 1U << 17,
140 PERF_SAMPLE_REGS_INTR = 1U << 18,
142 PERF_SAMPLE_MAX = 1U << 19, /* non-ABI */
146 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set
148 * If the user does not pass priv level information via branch_sample_type,
149 * the kernel uses the event's priv level. Branch and event priv levels do
150 * not have to match. Branch priv level is checked for permissions.
152 * The branch types can be combined, however BRANCH_ANY covers all types
153 * of branches and therefore it supersedes all the other types.
155 enum perf_branch_sample_type {
156 PERF_SAMPLE_BRANCH_USER = 1U << 0, /* user branches */
157 PERF_SAMPLE_BRANCH_KERNEL = 1U << 1, /* kernel branches */
158 PERF_SAMPLE_BRANCH_HV = 1U << 2, /* hypervisor branches */
160 PERF_SAMPLE_BRANCH_ANY = 1U << 3, /* any branch types */
161 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << 4, /* any call branch */
162 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << 5, /* any return branch */
163 PERF_SAMPLE_BRANCH_IND_CALL = 1U << 6, /* indirect calls */
164 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << 7, /* transaction aborts */
165 PERF_SAMPLE_BRANCH_IN_TX = 1U << 8, /* in transaction */
166 PERF_SAMPLE_BRANCH_NO_TX = 1U << 9, /* not in transaction */
167 PERF_SAMPLE_BRANCH_COND = 1U << 10, /* conditional branches */
169 PERF_SAMPLE_BRANCH_MAX = 1U << 11, /* non-ABI */
172 #define PERF_SAMPLE_BRANCH_PLM_ALL \
173 (PERF_SAMPLE_BRANCH_USER|\
174 PERF_SAMPLE_BRANCH_KERNEL|\
175 PERF_SAMPLE_BRANCH_HV)
178 * Values to determine ABI of the registers dump.
180 enum perf_sample_regs_abi {
181 PERF_SAMPLE_REGS_ABI_NONE = 0,
182 PERF_SAMPLE_REGS_ABI_32 = 1,
183 PERF_SAMPLE_REGS_ABI_64 = 2,
187 * Values for the memory transaction event qualifier, mostly for
188 * abort events. Multiple bits can be set.
191 PERF_TXN_ELISION = (1 << 0), /* From elision */
192 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */
193 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */
194 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */
195 PERF_TXN_RETRY = (1 << 4), /* Retry possible */
196 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */
197 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */
198 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */
200 PERF_TXN_MAX = (1 << 8), /* non-ABI */
202 /* bits 32..63 are reserved for the abort code */
204 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32),
205 PERF_TXN_ABORT_SHIFT = 32,
209 * The format of the data returned by read() on a perf event fd,
210 * as specified by attr.read_format:
212 * struct read_format {
214 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
215 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
216 * { u64 id; } && PERF_FORMAT_ID
217 * } && !PERF_FORMAT_GROUP
220 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
221 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
223 * { u64 id; } && PERF_FORMAT_ID
225 * } && PERF_FORMAT_GROUP
228 enum perf_event_read_format {
229 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0,
230 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1,
231 PERF_FORMAT_ID = 1U << 2,
232 PERF_FORMAT_GROUP = 1U << 3,
234 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */
237 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */
238 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */
239 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */
240 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */
241 /* add: sample_stack_user */
242 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */
245 * Hardware event_id to monitor via a performance monitoring event:
247 struct perf_event_attr {
250 * Major type: hardware/software/tracepoint/etc.
255 * Size of the attr structure, for fwd/bwd compat.
260 * Type specific configuration information.
272 __u64 disabled : 1, /* off by default */
273 inherit : 1, /* children inherit it */
274 pinned : 1, /* must always be on PMU */
275 exclusive : 1, /* only group on PMU */
276 exclude_user : 1, /* don't count user */
277 exclude_kernel : 1, /* ditto kernel */
278 exclude_hv : 1, /* ditto hypervisor */
279 exclude_idle : 1, /* don't count when idle */
280 mmap : 1, /* include mmap data */
281 comm : 1, /* include comm data */
282 freq : 1, /* use freq, not period */
283 inherit_stat : 1, /* per task counts */
284 enable_on_exec : 1, /* next exec enables */
285 task : 1, /* trace fork/exit */
286 watermark : 1, /* wakeup_watermark */
290 * 0 - SAMPLE_IP can have arbitrary skid
291 * 1 - SAMPLE_IP must have constant skid
292 * 2 - SAMPLE_IP requested to have 0 skid
293 * 3 - SAMPLE_IP must have 0 skid
295 * See also PERF_RECORD_MISC_EXACT_IP
297 precise_ip : 2, /* skid constraint */
298 mmap_data : 1, /* non-exec mmap data */
299 sample_id_all : 1, /* sample_type all events */
301 exclude_host : 1, /* don't count in host */
302 exclude_guest : 1, /* don't count in guest */
304 exclude_callchain_kernel : 1, /* exclude kernel callchains */
305 exclude_callchain_user : 1, /* exclude user callchains */
306 mmap2 : 1, /* include mmap with inode data */
307 comm_exec : 1, /* flag comm events that are due to an exec */
311 __u32 wakeup_events; /* wakeup every n events */
312 __u32 wakeup_watermark; /* bytes before wakeup */
318 __u64 config1; /* extension of config */
322 __u64 config2; /* extension of config1 */
324 __u64 branch_sample_type; /* enum perf_branch_sample_type */
327 * Defines set of user regs to dump on samples.
328 * See asm/perf_regs.h for details.
330 __u64 sample_regs_user;
333 * Defines size of the user stack to dump on samples.
335 __u32 sample_stack_user;
340 * Defines set of regs to dump for each sample
342 * - precise = 0: PMU interrupt
343 * - precise > 0: sampled instruction
345 * See asm/perf_regs.h for details.
347 __u64 sample_regs_intr;
350 #define perf_flags(attr) (*(&(attr)->read_format + 1))
353 * Ioctls that can be done on a perf event fd:
355 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0)
356 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1)
357 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2)
358 #define PERF_EVENT_IOC_RESET _IO ('$', 3)
359 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
360 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5)
361 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
362 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
364 enum perf_event_ioc_flags {
365 PERF_IOC_FLAG_GROUP = 1U << 0,
369 * Structure of the page that can be mapped via mmap
371 struct perf_event_mmap_page {
372 __u32 version; /* version number of this structure */
373 __u32 compat_version; /* lowest version this is compat with */
376 * Bits needed to read the hw events in user-space.
378 * u32 seq, time_mult, time_shift, index, width;
379 * u64 count, enabled, running;
380 * u64 cyc, time_offset;
387 * enabled = pc->time_enabled;
388 * running = pc->time_running;
390 * if (pc->cap_usr_time && enabled != running) {
392 * time_offset = pc->time_offset;
393 * time_mult = pc->time_mult;
394 * time_shift = pc->time_shift;
398 * count = pc->offset;
399 * if (pc->cap_user_rdpmc && index) {
400 * width = pc->pmc_width;
401 * pmc = rdpmc(index - 1);
405 * } while (pc->lock != seq);
407 * NOTE: for obvious reason this only works on self-monitoring
410 __u32 lock; /* seqlock for synchronization */
411 __u32 index; /* hardware event identifier */
412 __s64 offset; /* add to hardware event value */
413 __u64 time_enabled; /* time event active */
414 __u64 time_running; /* time event on cpu */
418 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */
419 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */
421 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */
422 cap_user_time : 1, /* The time_* fields are used */
423 cap_user_time_zero : 1, /* The time_zero field is used */
429 * If cap_user_rdpmc this field provides the bit-width of the value
430 * read using the rdpmc() or equivalent instruction. This can be used
431 * to sign extend the result like:
433 * pmc <<= 64 - width;
434 * pmc >>= 64 - width; // signed shift right
440 * If cap_usr_time the below fields can be used to compute the time
441 * delta since time_enabled (in ns) using rdtsc or similar.
446 * quot = (cyc >> time_shift);
447 * rem = cyc & ((1 << time_shift) - 1);
448 * delta = time_offset + quot * time_mult +
449 * ((rem * time_mult) >> time_shift);
451 * Where time_offset,time_mult,time_shift and cyc are read in the
452 * seqcount loop described above. This delta can then be added to
453 * enabled and possible running (if index), improving the scaling:
459 * quot = count / running;
460 * rem = count % running;
461 * count = quot * enabled + (rem * enabled) / running;
467 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
468 * from sample timestamps.
470 * time = timestamp - time_zero;
471 * quot = time / time_mult;
472 * rem = time % time_mult;
473 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult;
477 * quot = cyc >> time_shift;
478 * rem = cyc & ((1 << time_shift) - 1);
479 * timestamp = time_zero + quot * time_mult +
480 * ((rem * time_mult) >> time_shift);
483 __u32 size; /* Header size up to __reserved[] fields. */
486 * Hole for extension of the self monitor capabilities
489 __u8 __reserved[118*8+4]; /* align to 1k. */
492 * Control data for the mmap() data buffer.
494 * User-space reading the @data_head value should issue an smp_rmb(),
495 * after reading this value.
497 * When the mapping is PROT_WRITE the @data_tail value should be
498 * written by userspace to reflect the last read data, after issueing
499 * an smp_mb() to separate the data read from the ->data_tail store.
500 * In this case the kernel will not over-write unread data.
502 * See perf_output_put_handle() for the data ordering.
504 __u64 data_head; /* head in the data section */
505 __u64 data_tail; /* user-space written tail */
508 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0)
509 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0)
510 #define PERF_RECORD_MISC_KERNEL (1 << 0)
511 #define PERF_RECORD_MISC_USER (2 << 0)
512 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0)
513 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
514 #define PERF_RECORD_MISC_GUEST_USER (5 << 0)
517 * PERF_RECORD_MISC_MMAP_DATA and PERF_RECORD_MISC_COMM_EXEC are used on
518 * different events so can reuse the same bit position.
520 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13)
521 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13)
523 * Indicates that the content of PERF_SAMPLE_IP points to
524 * the actual instruction that triggered the event. See also
525 * perf_event_attr::precise_ip.
527 #define PERF_RECORD_MISC_EXACT_IP (1 << 14)
529 * Reserve the last bit to indicate some extended misc field
531 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
533 struct perf_event_header {
539 enum perf_event_type {
542 * If perf_event_attr.sample_id_all is set then all event types will
543 * have the sample_type selected fields related to where/when
544 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU,
545 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed
546 * just after the perf_event_header and the fields already present for
547 * the existing fields, i.e. at the end of the payload. That way a newer
548 * perf.data file will be supported by older perf tools, with these new
549 * optional fields being ignored.
552 * { u32 pid, tid; } && PERF_SAMPLE_TID
553 * { u64 time; } && PERF_SAMPLE_TIME
554 * { u64 id; } && PERF_SAMPLE_ID
555 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
556 * { u32 cpu, res; } && PERF_SAMPLE_CPU
557 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
558 * } && perf_event_attr::sample_id_all
560 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The
561 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed
562 * relative to header.size.
566 * The MMAP events record the PROT_EXEC mappings so that we can
567 * correlate userspace IPs to code. They have the following structure:
570 * struct perf_event_header header;
577 * struct sample_id sample_id;
580 PERF_RECORD_MMAP = 1,
584 * struct perf_event_header header;
587 * struct sample_id sample_id;
590 PERF_RECORD_LOST = 2,
594 * struct perf_event_header header;
598 * struct sample_id sample_id;
601 PERF_RECORD_COMM = 3,
605 * struct perf_event_header header;
609 * struct sample_id sample_id;
612 PERF_RECORD_EXIT = 4,
616 * struct perf_event_header header;
620 * struct sample_id sample_id;
623 PERF_RECORD_THROTTLE = 5,
624 PERF_RECORD_UNTHROTTLE = 6,
628 * struct perf_event_header header;
632 * struct sample_id sample_id;
635 PERF_RECORD_FORK = 7,
639 * struct perf_event_header header;
642 * struct read_format values;
643 * struct sample_id sample_id;
646 PERF_RECORD_READ = 8,
650 * struct perf_event_header header;
653 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.
654 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position
655 * # is fixed relative to header.
658 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
659 * { u64 ip; } && PERF_SAMPLE_IP
660 * { u32 pid, tid; } && PERF_SAMPLE_TID
661 * { u64 time; } && PERF_SAMPLE_TIME
662 * { u64 addr; } && PERF_SAMPLE_ADDR
663 * { u64 id; } && PERF_SAMPLE_ID
664 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
665 * { u32 cpu, res; } && PERF_SAMPLE_CPU
666 * { u64 period; } && PERF_SAMPLE_PERIOD
668 * { struct read_format values; } && PERF_SAMPLE_READ
671 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN
674 * # The RAW record below is opaque data wrt the ABI
676 * # That is, the ABI doesn't make any promises wrt to
677 * # the stability of its content, it may vary depending
678 * # on event, hardware, kernel version and phase of
681 * # In other words, PERF_SAMPLE_RAW contents are not an ABI.
685 * char data[size];}&& PERF_SAMPLE_RAW
688 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK
690 * { u64 abi; # enum perf_sample_regs_abi
691 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
695 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER
697 * { u64 weight; } && PERF_SAMPLE_WEIGHT
698 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC
699 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION
700 * { u64 abi; # enum perf_sample_regs_abi
701 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
704 PERF_RECORD_SAMPLE = 9,
707 * The MMAP2 records are an augmented version of MMAP, they add
708 * maj, min, ino numbers to be used to uniquely identify each mapping
711 * struct perf_event_header header;
720 * u64 ino_generation;
723 * struct sample_id sample_id;
726 PERF_RECORD_MMAP2 = 10,
728 PERF_RECORD_MAX, /* non-ABI */
731 #define PERF_MAX_STACK_DEPTH 127
733 enum perf_callchain_context {
734 PERF_CONTEXT_HV = (__u64)-32,
735 PERF_CONTEXT_KERNEL = (__u64)-128,
736 PERF_CONTEXT_USER = (__u64)-512,
738 PERF_CONTEXT_GUEST = (__u64)-2048,
739 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176,
740 PERF_CONTEXT_GUEST_USER = (__u64)-2560,
742 PERF_CONTEXT_MAX = (__u64)-4095,
745 #define PERF_FLAG_FD_NO_GROUP (1UL << 0)
746 #define PERF_FLAG_FD_OUTPUT (1UL << 1)
747 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */
748 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */
750 union perf_mem_data_src {
753 __u64 mem_op:5, /* type of opcode */
754 mem_lvl:14, /* memory hierarchy level */
755 mem_snoop:5, /* snoop mode */
756 mem_lock:2, /* lock instr */
757 mem_dtlb:7, /* tlb access */
762 /* type of opcode (load/store/prefetch,code) */
763 #define PERF_MEM_OP_NA 0x01 /* not available */
764 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */
765 #define PERF_MEM_OP_STORE 0x04 /* store instruction */
766 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */
767 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
768 #define PERF_MEM_OP_SHIFT 0
770 /* memory hierarchy (memory level, hit or miss) */
771 #define PERF_MEM_LVL_NA 0x01 /* not available */
772 #define PERF_MEM_LVL_HIT 0x02 /* hit level */
773 #define PERF_MEM_LVL_MISS 0x04 /* miss level */
774 #define PERF_MEM_LVL_L1 0x08 /* L1 */
775 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */
776 #define PERF_MEM_LVL_L2 0x20 /* L2 */
777 #define PERF_MEM_LVL_L3 0x40 /* L3 */
778 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */
779 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */
780 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */
781 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */
782 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */
783 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */
784 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */
785 #define PERF_MEM_LVL_SHIFT 5
788 #define PERF_MEM_SNOOP_NA 0x01 /* not available */
789 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */
790 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */
791 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */
792 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */
793 #define PERF_MEM_SNOOP_SHIFT 19
795 /* locked instruction */
796 #define PERF_MEM_LOCK_NA 0x01 /* not available */
797 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */
798 #define PERF_MEM_LOCK_SHIFT 24
801 #define PERF_MEM_TLB_NA 0x01 /* not available */
802 #define PERF_MEM_TLB_HIT 0x02 /* hit level */
803 #define PERF_MEM_TLB_MISS 0x04 /* miss level */
804 #define PERF_MEM_TLB_L1 0x08 /* L1 */
805 #define PERF_MEM_TLB_L2 0x10 /* L2 */
806 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/
807 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */
808 #define PERF_MEM_TLB_SHIFT 26
810 #define PERF_MEM_S(a, s) \
811 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
814 * single taken branch record layout:
816 * from: source instruction (may not always be a branch insn)
818 * mispred: branch target was mispredicted
819 * predicted: branch target was predicted
821 * support for mispred, predicted is optional. In case it
822 * is not supported mispred = predicted = 0.
824 * in_tx: running in a hardware transaction
825 * abort: aborting a hardware transaction
827 struct perf_branch_entry {
830 __u64 mispred:1, /* target mispredicted */
831 predicted:1,/* target predicted */
832 in_tx:1, /* in transaction */
833 abort:1, /* transaction abort */
837 #endif /* _UAPI_LINUX_PERF_EVENT_H */