1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
3 * Copyright (C) 2020-2023 Intel Corporation
6 #ifndef __UAPI_IVPU_DRM_H__
7 #define __UAPI_IVPU_DRM_H__
11 #if defined(__cplusplus)
15 #define DRM_IVPU_DRIVER_MAJOR 1
16 #define DRM_IVPU_DRIVER_MINOR 0
18 #define DRM_IVPU_GET_PARAM 0x00
19 #define DRM_IVPU_SET_PARAM 0x01
20 #define DRM_IVPU_BO_CREATE 0x02
21 #define DRM_IVPU_BO_INFO 0x03
23 #define DRM_IOCTL_IVPU_GET_PARAM \
24 DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param)
26 #define DRM_IOCTL_IVPU_SET_PARAM \
27 DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SET_PARAM, struct drm_ivpu_param)
29 #define DRM_IOCTL_IVPU_BO_CREATE \
30 DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_CREATE, struct drm_ivpu_bo_create)
32 #define DRM_IOCTL_IVPU_BO_INFO \
33 DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_INFO, struct drm_ivpu_bo_info)
38 * VPU contexts have private virtual address space, job queues and priority.
39 * Each context is identified by an unique ID. Context is created on open().
42 #define DRM_IVPU_PARAM_DEVICE_ID 0
43 #define DRM_IVPU_PARAM_DEVICE_REVISION 1
44 #define DRM_IVPU_PARAM_PLATFORM_TYPE 2
45 #define DRM_IVPU_PARAM_CORE_CLOCK_RATE 3
46 #define DRM_IVPU_PARAM_NUM_CONTEXTS 4
47 #define DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS 5
48 #define DRM_IVPU_PARAM_CONTEXT_PRIORITY 6
49 #define DRM_IVPU_PARAM_CONTEXT_ID 7
51 #define DRM_IVPU_PLATFORM_TYPE_SILICON 0
53 #define DRM_IVPU_CONTEXT_PRIORITY_IDLE 0
54 #define DRM_IVPU_CONTEXT_PRIORITY_NORMAL 1
55 #define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 2
56 #define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 3
59 * struct drm_ivpu_param - Get/Set VPU parameters
61 struct drm_ivpu_param {
67 * %DRM_IVPU_PARAM_DEVICE_ID:
68 * PCI Device ID of the VPU device (read-only)
70 * %DRM_IVPU_PARAM_DEVICE_REVISION:
71 * VPU device revision (read-only)
73 * %DRM_IVPU_PARAM_PLATFORM_TYPE:
74 * Returns %DRM_IVPU_PLATFORM_TYPE_SILICON on real hardware or device specific
75 * platform type when executing on a simulator or emulator (read-only)
77 * %DRM_IVPU_PARAM_CORE_CLOCK_RATE:
78 * Current PLL frequency (read-only)
80 * %DRM_IVPU_PARAM_NUM_CONTEXTS:
81 * Maximum number of simultaneously existing contexts (read-only)
83 * %DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
84 * Lowest VPU virtual address available in the current context (read-only)
86 * %DRM_IVPU_PARAM_CONTEXT_PRIORITY:
87 * Value of current context scheduling priority (read-write).
88 * See DRM_IVPU_CONTEXT_PRIORITY_* for possible values.
90 * %DRM_IVPU_PARAM_CONTEXT_ID:
91 * Current context ID, always greater than 0 (read-only)
96 /** @index: Index for params that have multiple instances */
99 /** @value: Param value */
103 #define DRM_IVPU_BO_HIGH_MEM 0x00000001
104 #define DRM_IVPU_BO_MAPPABLE 0x00000002
106 #define DRM_IVPU_BO_CACHED 0x00000000
107 #define DRM_IVPU_BO_UNCACHED 0x00010000
108 #define DRM_IVPU_BO_WC 0x00020000
109 #define DRM_IVPU_BO_CACHE_MASK 0x00030000
111 #define DRM_IVPU_BO_FLAGS \
112 (DRM_IVPU_BO_HIGH_MEM | \
113 DRM_IVPU_BO_MAPPABLE | \
114 DRM_IVPU_BO_CACHE_MASK)
117 * struct drm_ivpu_bo_create - Create BO backed by SHMEM
119 * Create GEM buffer object allocated in SHMEM memory.
121 struct drm_ivpu_bo_create {
122 /** @size: The size in bytes of the allocated memory */
130 * %DRM_IVPU_BO_HIGH_MEM:
132 * Allocate VPU address from >4GB range.
133 * Buffer object with vpu address >4GB can be always accessed by the
134 * VPU DMA engine, but some HW generation may not be able to access
135 * this memory from then firmware running on the VPU management processor.
136 * Suitable for input, output and some scratch buffers.
138 * %DRM_IVPU_BO_MAPPABLE:
140 * Buffer object can be mapped using mmap().
142 * %DRM_IVPU_BO_CACHED:
144 * Allocated BO will be cached on host side (WB) and snooped on the VPU side.
145 * This is the default caching mode.
147 * %DRM_IVPU_BO_UNCACHED:
149 * Allocated BO will not be cached on host side nor snooped on the VPU side.
153 * Allocated BO will use write combining buffer for writes but reads will be
158 /** @handle: Returned GEM object handle */
161 /** @vpu_addr: Returned VPU virtual address */
166 * struct drm_ivpu_bo_info - Query buffer object info
168 struct drm_ivpu_bo_info {
169 /** @handle: Handle of the queried BO */
172 /** @flags: Returned flags used to create the BO */
175 /** @vpu_addr: Returned VPU virtual address */
181 * Returned offset to be used in mmap(). 0 in case the BO is not mappable.
185 /** @size: Returned GEM object size, aligned to PAGE_SIZE */
189 #if defined(__cplusplus)
193 #endif /* __UAPI_IVPU_DRM_H__ */