2 * Copyright 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
29 #if defined(__cplusplus)
36 * In the DRM subsystem, framebuffer pixel formats are described using the
37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
38 * fourcc code, a Format Modifier may optionally be provided, in order to
39 * further describe the buffer's format - for example tiling or compression.
44 * Format modifiers are used in conjunction with a fourcc code, forming a
45 * unique fourcc:modifier pair. This format:modifier pair must fully define the
46 * format and data layout of the buffer, and should be the only way to describe
47 * that particular buffer.
49 * Having multiple fourcc:modifier pairs which describe the same layout should
50 * be avoided, as such aliases run the risk of different drivers exposing
51 * different names for the same data format, forcing userspace to understand
52 * that they are aliases.
54 * Format modifiers may change any property of the buffer, including the number
55 * of planes and/or the required allocation size. Format modifiers are
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * modifier is specific to the modifer being used. For example, some modifiers
58 * may preserve meaning - such as number of planes - from the fourcc code,
59 * whereas others may not.
61 * Vendors should document their modifier usage in as much detail as
62 * possible, to ensure maximum compatibility across devices, drivers and
65 * The authoritative list of format modifier codes is found in
66 * `include/uapi/drm/drm_fourcc.h`
69 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
70 ((__u32)(c) << 16) | ((__u32)(d) << 24))
72 #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
75 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
78 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
81 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
84 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
85 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
88 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
89 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
92 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
93 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
96 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
97 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
98 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
99 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
101 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
102 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
103 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
104 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
106 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
107 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
108 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
109 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
111 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
112 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
113 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
114 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
116 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
117 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
120 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
121 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
124 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
125 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
126 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
127 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
129 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
130 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
131 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
132 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
134 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
135 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
136 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
137 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
139 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
140 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
141 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
142 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
145 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
146 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
147 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
148 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
150 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
154 * index 0 = RGB plane, same format as the corresponding non _A8 format has
155 * index 1 = A plane, [7:0] A
157 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
158 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
159 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
160 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
161 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
162 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
163 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
164 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
168 * index 0 = Y plane, [7:0] Y
169 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
171 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
173 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
174 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
175 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
176 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
177 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
178 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
182 * index 0: Y plane, [7:0] Y
183 * index 1: Cb plane, [7:0] Cb
184 * index 2: Cr plane, [7:0] Cr
186 * index 1: Cr plane, [7:0] Cr
187 * index 2: Cb plane, [7:0] Cb
189 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
190 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
191 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
192 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
193 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
194 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
195 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
196 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
197 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
198 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
204 * Format modifiers describe, typically, a re-ordering or modification
205 * of the data in a plane of an FB. This can be used to express tiled/
206 * swizzled formats, or compression, or a combination of the two.
208 * The upper 8 bits of the format modifier are a vendor-id as assigned
209 * below. The lower 56 bits are assigned as vendor sees fit.
213 #define DRM_FORMAT_MOD_NONE 0
214 #define DRM_FORMAT_MOD_VENDOR_NONE 0
215 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
216 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
217 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
218 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
219 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
220 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
221 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
222 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08
223 /* add more to the end as needed */
225 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
227 #define fourcc_mod_code(vendor, val) \
228 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
231 * Format Modifier tokens:
233 * When adding a new token please document the layout with a code comment,
234 * similar to the fourcc codes above. drm_fourcc.h is considered the
235 * authoritative source for all of these.
241 * This modifier can be used as a sentinel to terminate the format modifiers
242 * list, or to initialize a variable with an invalid modifier. It might also be
243 * used to report an error back to userspace for certain APIs.
245 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
250 * Just plain linear layout. Note that this is different from no specifying any
251 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
252 * which tells the driver to also take driver-internal information into account
253 * and so might actually result in a tiled framebuffer.
255 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
257 /* Intel framebuffer modifiers */
260 * Intel X-tiling layout
262 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
263 * in row-major layout. Within the tile bytes are laid out row-major, with
264 * a platform-dependent stride. On top of that the memory can apply
265 * platform-depending swizzling of some higher address bits into bit6.
267 * This format is highly platforms specific and not useful for cross-driver
268 * sharing. It exists since on a given platform it does uniquely identify the
269 * layout in a simple way for i915-specific userspace.
271 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
274 * Intel Y-tiling layout
276 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
277 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
278 * chunks column-major, with a platform-dependent height. On top of that the
279 * memory can apply platform-depending swizzling of some higher address bits
282 * This format is highly platforms specific and not useful for cross-driver
283 * sharing. It exists since on a given platform it does uniquely identify the
284 * layout in a simple way for i915-specific userspace.
286 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
289 * Intel Yf-tiling layout
291 * This is a tiled layout using 4Kb tiles in row-major layout.
292 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
293 * are arranged in four groups (two wide, two high) with column-major layout.
294 * Each group therefore consits out of four 256 byte units, which are also laid
295 * out as 2x2 column-major.
296 * 256 byte units are made out of four 64 byte blocks of pixels, producing
297 * either a square block or a 2:1 unit.
298 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
299 * in pixel depends on the pixel depth.
301 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
304 * Intel color control surface (CCS) for render compression
306 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
307 * The main surface will be plane index 0 and must be Y/Yf-tiled,
308 * the CCS will be plane index 1.
310 * Each CCS tile matches a 1024x512 pixel area of the main surface.
311 * To match certain aspects of the 3D hardware the CCS is
312 * considered to be made up of normal 128Bx32 Y tiles, Thus
313 * the CCS pitch must be specified in multiples of 128 bytes.
315 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
316 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
317 * But that fact is not relevant unless the memory is accessed
320 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
321 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
324 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
326 * Macroblocks are laid in a Z-shape, and each pixel data is following the
327 * standard NV12 style.
328 * As for NV12, an image is the result of two frame buffers: one for Y,
329 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
330 * Alignment requirements are (for each buffer):
331 * - multiple of 128 pixels for the width
332 * - multiple of 32 pixels for the height
334 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
336 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
339 * Qualcomm Compressed Format
341 * Refers to a compressed variant of the base format that is compressed.
342 * Implementation may be platform and base-format specific.
344 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
345 * Pixel data pitch/stride is aligned with macrotile width.
346 * Pixel data height is aligned with macrotile height.
347 * Entire pixel data buffer is aligned with 4k(bytes).
349 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
351 /* Vivante framebuffer modifiers */
354 * Vivante 4x4 tiling layout
356 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
359 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
362 * Vivante 64x64 super-tiling layout
364 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
365 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
368 * For more information: see
369 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
371 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
374 * Vivante 4x4 tiling layout for dual-pipe
376 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
377 * different base address. Offsets from the base addresses are therefore halved
378 * compared to the non-split tiled layout.
380 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
383 * Vivante 64x64 super-tiling layout for dual-pipe
385 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
386 * starts at a different base address. Offsets from the base addresses are
387 * therefore halved compared to the non-split super-tiled layout.
389 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
391 /* NVIDIA frame buffer modifiers */
394 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
396 * Pixels are arranged in simple tiles of 16 x 16 bytes.
398 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
401 * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
403 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
404 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
406 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
408 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
416 * 5 == THIRTYTWO_GOBS
418 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
421 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
422 fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
424 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
425 fourcc_mod_code(NVIDIA, 0x10)
426 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
427 fourcc_mod_code(NVIDIA, 0x11)
428 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
429 fourcc_mod_code(NVIDIA, 0x12)
430 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
431 fourcc_mod_code(NVIDIA, 0x13)
432 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
433 fourcc_mod_code(NVIDIA, 0x14)
434 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
435 fourcc_mod_code(NVIDIA, 0x15)
438 * Some Broadcom modifiers take parameters, for example the number of
439 * vertical lines in the image. Reserve the lower 32 bits for modifier
440 * type, and the next 24 bits for parameters. Top 8 bits are the
443 #define __fourcc_mod_broadcom_param_shift 8
444 #define __fourcc_mod_broadcom_param_bits 48
445 #define fourcc_mod_broadcom_code(val, params) \
446 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
447 #define fourcc_mod_broadcom_param(m) \
448 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
449 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
450 #define fourcc_mod_broadcom_mod(m) \
451 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
452 __fourcc_mod_broadcom_param_shift))
455 * Broadcom VC4 "T" format
457 * This is the primary layout that the V3D GPU can texture from (it
458 * can't do linear). The T format has:
460 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
461 * pixels at 32 bit depth.
463 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
466 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
467 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
468 * they're (TR, BR, BL, TL), where bottom left is start of memory.
470 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
471 * tiles) or right-to-left (odd rows of 4k tiles).
473 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
476 * Broadcom SAND format
478 * This is the native format that the H.264 codec block uses. For VC4
479 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
481 * The image can be considered to be split into columns, and the
482 * columns are placed consecutively into memory. The width of those
483 * columns can be either 32, 64, 128, or 256 pixels, but in practice
484 * only 128 pixel columns are used.
486 * The pitch between the start of each column is set to optimally
487 * switch between SDRAM banks. This is passed as the number of lines
488 * of column width in the modifier (we can't use the stride value due
489 * to various core checks that look at it , so you should set the
490 * stride to width*cpp).
492 * Note that the column height for this format modifier is the same
493 * for all of the planes, assuming that each column contains both Y
494 * and UV. Some SAND-using hardware stores UV in a separate tiled
495 * image from Y to reduce the column height, which is not supported
496 * with these modifiers.
499 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
500 fourcc_mod_broadcom_code(2, v)
501 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
502 fourcc_mod_broadcom_code(3, v)
503 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
504 fourcc_mod_broadcom_code(4, v)
505 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
506 fourcc_mod_broadcom_code(5, v)
508 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
509 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
510 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
511 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
512 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
513 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
514 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
515 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
517 /* Broadcom UIF format
519 * This is the common format for the current Broadcom multimedia
520 * blocks, including V3D 3.x and newer, newer video codecs, and
523 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
524 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
525 * stored in columns, with padding between the columns to ensure that
526 * moving from one column to the next doesn't hit the same SDRAM page
529 * To calculate the padding, it is assumed that each hardware block
530 * and the software driving it knows the platform's SDRAM page size,
531 * number of banks, and XOR address, and that it's identical between
532 * all blocks using the format. This tiling modifier will use XOR as
533 * necessary to reduce the padding. If a hardware block can't do XOR,
534 * the assumption is that a no-XOR tiling modifier will be created.
536 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
539 * Arm Framebuffer Compression (AFBC) modifiers
541 * AFBC is a proprietary lossless image compression protocol and format.
542 * It provides fine-grained random access and minimizes the amount of data
543 * transferred between IP blocks.
545 * AFBC has several features which may be supported and/or used, which are
546 * represented using bits in the modifier. Not all combinations are valid,
547 * and different devices or use-cases may support different combinations.
549 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
552 * AFBC superblock size
554 * Indicates the superblock size(s) used for the AFBC buffer. The buffer
555 * size (in pixels) must be aligned to a multiple of the superblock size.
556 * Four lowest significant bits(LSBs) are reserved for block size.
558 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
559 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
560 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
563 * AFBC lossless colorspace transform
565 * Indicates that the buffer makes use of the AFBC lossless colorspace
568 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
573 * Indicates that the payload of each superblock is split. The second
574 * half of the payload is positioned at a predefined offset from the start
575 * of the superblock payload.
577 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
582 * This flag indicates that the payload of each superblock must be stored at a
583 * predefined position relative to the other superblocks in the same AFBC
584 * buffer. This order is the same order used by the header buffer. In this mode
585 * each superblock is given the same amount of space as an uncompressed
586 * superblock of the particular format would require, rounding up to the next
587 * multiple of 128 bytes in size.
589 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
592 * AFBC copy-block restrict
594 * Buffers with this flag must obey the copy-block restriction. The restriction
595 * is such that there are no copy-blocks referring across the border of 8x8
596 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
598 #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
603 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
604 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
605 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
606 * larger bpp formats. The order between the tiles is scan line.
607 * When the tiled layout is used, the buffer size (in pixels) must be aligned
610 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
613 * AFBC solid color blocks
615 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
616 * can be reduced if a whole superblock is a single color.
618 #define AFBC_FORMAT_MOD_SC (1ULL << 9)
620 #if defined(__cplusplus)
624 #endif /* DRM_FOURCC_H */