1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
6 * Copyright(c) 2018 Intel Corporation. All rights reserved.
9 #ifndef __INCLUDE_SOUND_SOF_DAI_INTEL_H__
10 #define __INCLUDE_SOUND_SOF_DAI_INTEL_H__
12 #include <sound/sof/header.h>
15 #define SOF_DAI_INTEL_SSP_QUIRK_TINTE (1 << 0)
17 #define SOF_DAI_INTEL_SSP_QUIRK_PINTE (1 << 1)
19 #define SOF_DAI_INTEL_SSP_QUIRK_SMTATF (1 << 2)
21 #define SOF_DAI_INTEL_SSP_QUIRK_MMRATF (1 << 3)
22 /* ssc2: PSPSTWFDFD */
23 #define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD (1 << 4)
24 /* ssc2: PSPSRWFDFD */
25 #define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD (1 << 5)
27 #define SOF_DAI_INTEL_SSP_QUIRK_LBM (1 << 6)
29 /* here is the possibility to define others aux macros */
31 #define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX 38
32 #define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX 31
34 /* SSP clocks control settings
36 * Macros for clks_control field in sof_ipc_dai_ssp_params struct.
40 #define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE BIT(0)
42 #define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE BIT(1)
43 /* mclk keep active */
44 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA BIT(2)
45 /* bclk keep active */
46 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA BIT(3)
48 #define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4)
50 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5)
52 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
53 struct sof_ipc_dai_ssp_params {
54 struct sof_ipc_hdr hdr;
58 uint32_t mclk_rate; /* mclk frequency in Hz */
59 uint32_t fsync_rate; /* fsync frequency in Hz */
60 uint32_t bclk_rate; /* bclk frequency in Hz */
68 uint32_t sample_valid_bits;
69 uint16_t tdm_slot_width;
70 uint16_t reserved2; /* alignment */
73 uint32_t mclk_direction;
75 uint16_t frame_pulse_width;
76 uint16_t tdm_per_slot_padding_flag;
77 uint32_t clks_control;
81 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
82 struct sof_ipc_dai_hda_params {
83 struct sof_ipc_hdr hdr;
87 /* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */
89 /* This struct is defined per 2ch PDM controller available in the platform.
90 * Normally it is sufficient to set the used microphone specific enables to 1
91 * and keep other parameters as zero. The customizations are:
93 * 1. If a device mixes different microphones types with different polarity
94 * and/or the absolute polarity matters the PCM signal from a microphone
95 * can be inverted with the controls.
97 * 2. If the microphones in a stereo pair do not appear in captured stream
98 * in desired order due to board schematics choises they can be swapped with
99 * the clk_edge parameter.
101 * 3. If PDM bit errors are seen in capture (poor quality) the skew parameter
102 * that delays the sampling time of data by half cycles of DMIC source clock
103 * can be tried for improvement. However there is no guarantee for this to fix
104 * data integrity problems.
106 struct sof_ipc_dai_dmic_pdm_ctrl {
107 struct sof_ipc_hdr hdr;
108 uint16_t id; /**< PDM controller ID */
110 uint16_t enable_mic_a; /**< Use A (left) channel mic (0 or 1)*/
111 uint16_t enable_mic_b; /**< Use B (right) channel mic (0 or 1)*/
113 uint16_t polarity_mic_a; /**< Optionally invert mic A signal (0 or 1) */
114 uint16_t polarity_mic_b; /**< Optionally invert mic B signal (0 or 1) */
116 uint16_t clk_edge; /**< Optionally swap data clock edge (0 or 1) */
117 uint16_t skew; /**< Adjust PDM data sampling vs. clock (0..15) */
119 uint16_t reserved[3]; /**< Make sure the total size is 4 bytes aligned */
122 /* This struct contains the global settings for all 2ch PDM controllers. The
123 * version number used in configuration data is checked vs. version used by
124 * device driver src/drivers/dmic.c need to match. It is incremented from
125 * initial value 1 if updates done for the to driver would alter the operation
128 * Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max)
129 * parameters need to be set as defined in microphone data sheet. E.g. clock
130 * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are
131 * multi-mode capable and there may be denied mic clock frequencies between
132 * the modes. In such case set the clock range limits of the desired mode to
133 * avoid the driver to set clock to an illegal rate.
135 * The duty cycle could be set to 48-52% if not known. Generally these
136 * parameters can be altered within data sheet specified limits to match
137 * required audio application performance power.
139 * The microphone clock needs to be usually about 50-80 times the used audio
140 * sample rate. With highest sample rates above 48 kHz this can relaxed
143 * The parameter wake_up_time describes how long time the microphone needs
144 * for the data line to produce valid output from mic clock start. The driver
145 * will mute the captured audio for the given time. The min_clock_on_time
146 * parameter is used to prevent too short clock bursts to happen. The driver
147 * will keep the clock active after capture stop if this time is not yet
148 * met. The unit for both is microseconds (us). Exceed of 100 ms will be
149 * treated as an error.
151 struct sof_ipc_dai_dmic_params {
152 struct sof_ipc_hdr hdr;
153 uint32_t driver_ipc_version; /**< Version (1..N) */
155 uint32_t pdmclk_min; /**< Minimum microphone clock in Hz (100000..N) */
156 uint32_t pdmclk_max; /**< Maximum microphone clock in Hz (min...N) */
158 uint32_t fifo_fs; /**< FIFO sample rate in Hz (8000..96000) */
159 uint32_t reserved_1; /**< Reserved */
160 uint16_t fifo_bits; /**< FIFO word length (16 or 32) */
161 uint16_t reserved_2; /**< Reserved */
163 uint16_t duty_min; /**< Min. mic clock duty cycle in % (20..80) */
164 uint16_t duty_max; /**< Max. mic clock duty cycle in % (min..80) */
166 uint32_t num_pdm_active; /**< Number of active pdm controllers */
168 uint32_t wake_up_time; /**< Time from clock start to data (us) */
169 uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */
170 uint32_t unmute_ramp_time; /**< Length of logarithmic gain ramp (ms) */
172 /* reserved for future use */
173 uint32_t reserved[5];
175 /**< variable number of pdm controller config */
176 struct sof_ipc_dai_dmic_pdm_ctrl pdm[0];