1 /* SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2005 David Brownell
9 #include <linux/device.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/slab.h>
12 #include <linux/kthread.h>
13 #include <linux/completion.h>
14 #include <linux/scatterlist.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/ptp_clock_kernel.h>
19 struct property_entry;
20 struct spi_controller;
22 struct spi_controller_mem_ops;
25 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
26 * and SPI infrastructure.
28 extern struct bus_type spi_bus_type;
31 * struct spi_statistics - statistics for spi transfers
32 * @lock: lock protecting this structure
34 * @messages: number of spi-messages handled
35 * @transfers: number of spi_transfers handled
36 * @errors: number of errors during spi_transfer
37 * @timedout: number of timeouts during spi_transfer
39 * @spi_sync: number of times spi_sync is used
40 * @spi_sync_immediate:
41 * number of times spi_sync is executed immediately
42 * in calling context without queuing and scheduling
43 * @spi_async: number of times spi_async is used
45 * @bytes: number of bytes transferred to/from device
46 * @bytes_tx: number of bytes sent to device
47 * @bytes_rx: number of bytes received from device
49 * @transfer_bytes_histo:
50 * transfer bytes histogramm
52 * @transfers_split_maxsize:
53 * number of transfers that have been split because of
56 struct spi_statistics {
57 spinlock_t lock; /* lock for the whole structure */
59 unsigned long messages;
60 unsigned long transfers;
62 unsigned long timedout;
64 unsigned long spi_sync;
65 unsigned long spi_sync_immediate;
66 unsigned long spi_async;
68 unsigned long long bytes;
69 unsigned long long bytes_rx;
70 unsigned long long bytes_tx;
72 #define SPI_STATISTICS_HISTO_SIZE 17
73 unsigned long transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE];
75 unsigned long transfers_split_maxsize;
78 void spi_statistics_add_transfer_stats(struct spi_statistics *stats,
79 struct spi_transfer *xfer,
80 struct spi_controller *ctlr);
82 #define SPI_STATISTICS_ADD_TO_FIELD(stats, field, count) \
84 unsigned long flags; \
85 spin_lock_irqsave(&(stats)->lock, flags); \
86 (stats)->field += count; \
87 spin_unlock_irqrestore(&(stats)->lock, flags); \
90 #define SPI_STATISTICS_INCREMENT_FIELD(stats, field) \
91 SPI_STATISTICS_ADD_TO_FIELD(stats, field, 1)
94 * struct spi_delay - SPI delay information
95 * @value: Value for the delay
96 * @unit: Unit for the delay
99 #define SPI_DELAY_UNIT_USECS 0
100 #define SPI_DELAY_UNIT_NSECS 1
101 #define SPI_DELAY_UNIT_SCK 2
106 extern int spi_delay_to_ns(struct spi_delay *_delay, struct spi_transfer *xfer);
107 extern int spi_delay_exec(struct spi_delay *_delay, struct spi_transfer *xfer);
110 * struct spi_device - Controller side proxy for an SPI slave device
111 * @dev: Driver model representation of the device.
112 * @controller: SPI controller used with the device.
113 * @master: Copy of controller, for backwards compatibility.
114 * @max_speed_hz: Maximum clock rate to be used with this chip
115 * (on this board); may be changed by the device's driver.
116 * The spi_transfer.speed_hz can override this for each transfer.
117 * @chip_select: Chipselect, distinguishing chips handled by @controller.
118 * @mode: The spi mode defines how data is clocked out and in.
119 * This may be changed by the device's driver.
120 * The "active low" default for chipselect mode can be overridden
121 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for
122 * each word in a transfer (by specifying SPI_LSB_FIRST).
123 * @bits_per_word: Data transfers involve one or more words; word sizes
124 * like eight or 12 bits are common. In-memory wordsizes are
125 * powers of two bytes (e.g. 20 bit samples use 32 bits).
126 * This may be changed by the device's driver, or left at the
127 * default (0) indicating protocol words are eight bit bytes.
128 * The spi_transfer.bits_per_word can override this for each transfer.
129 * @rt: Make the pump thread real time priority.
130 * @irq: Negative, or the number passed to request_irq() to receive
131 * interrupts from this device.
132 * @controller_state: Controller's runtime state
133 * @controller_data: Board-specific definitions for controller, such as
134 * FIFO initialization parameters; from board_info.controller_data
135 * @modalias: Name of the driver to use with this device, or an alias
136 * for that name. This appears in the sysfs "modalias" attribute
137 * for driver coldplugging, and in uevents used for hotplugging
138 * @driver_override: If the name of a driver is written to this attribute, then
139 * the device will bind to the named driver and only the named driver.
140 * @cs_gpio: LEGACY: gpio number of the chipselect line (optional, -ENOENT when
141 * not using a GPIO line) use cs_gpiod in new drivers by opting in on
143 * @cs_gpiod: gpio descriptor of the chipselect line (optional, NULL when
144 * not using a GPIO line)
145 * @word_delay: delay to be inserted between consecutive
146 * words of a transfer
148 * @statistics: statistics for the spi_device
150 * A @spi_device is used to interchange data between an SPI slave
151 * (usually a discrete chip) and CPU memory.
153 * In @dev, the platform_data is used to hold information about this
154 * device that's meaningful to the device's protocol driver, but not
155 * to its controller. One example might be an identifier for a chip
156 * variant with slightly different functionality; another might be
157 * information about how this particular board wires the chip's pins.
161 struct spi_controller *controller;
162 struct spi_controller *master; /* compatibility layer */
168 #define SPI_CPHA 0x01 /* clock phase */
169 #define SPI_CPOL 0x02 /* clock polarity */
170 #define SPI_MODE_0 (0|0) /* (original MicroWire) */
171 #define SPI_MODE_1 (0|SPI_CPHA)
172 #define SPI_MODE_2 (SPI_CPOL|0)
173 #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
174 #define SPI_CS_HIGH 0x04 /* chipselect active high? */
175 #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
176 #define SPI_3WIRE 0x10 /* SI/SO signals shared */
177 #define SPI_LOOP 0x20 /* loopback mode */
178 #define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */
179 #define SPI_READY 0x80 /* slave pulls low to pause */
180 #define SPI_TX_DUAL 0x100 /* transmit with 2 wires */
181 #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
182 #define SPI_RX_DUAL 0x400 /* receive with 2 wires */
183 #define SPI_RX_QUAD 0x800 /* receive with 4 wires */
184 #define SPI_CS_WORD 0x1000 /* toggle cs after each word */
185 #define SPI_TX_OCTAL 0x2000 /* transmit with 8 wires */
186 #define SPI_RX_OCTAL 0x4000 /* receive with 8 wires */
187 #define SPI_3WIRE_HIZ 0x8000 /* high impedance turnaround */
189 void *controller_state;
190 void *controller_data;
191 char modalias[SPI_NAME_SIZE];
192 const char *driver_override;
193 int cs_gpio; /* LEGACY: chip select gpio */
194 struct gpio_desc *cs_gpiod; /* chip select gpio desc */
195 struct spi_delay word_delay; /* inter-word delay */
198 struct spi_statistics statistics;
201 * likely need more hooks for more protocol options affecting how
202 * the controller talks to each chip, like:
203 * - memory packing (12 bit samples into low bits, others zeroed)
205 * - chipselect delays
210 static inline struct spi_device *to_spi_device(struct device *dev)
212 return dev ? container_of(dev, struct spi_device, dev) : NULL;
215 /* most drivers won't need to care about device refcounting */
216 static inline struct spi_device *spi_dev_get(struct spi_device *spi)
218 return (spi && get_device(&spi->dev)) ? spi : NULL;
221 static inline void spi_dev_put(struct spi_device *spi)
224 put_device(&spi->dev);
227 /* ctldata is for the bus_controller driver's runtime state */
228 static inline void *spi_get_ctldata(struct spi_device *spi)
230 return spi->controller_state;
233 static inline void spi_set_ctldata(struct spi_device *spi, void *state)
235 spi->controller_state = state;
238 /* device driver data */
240 static inline void spi_set_drvdata(struct spi_device *spi, void *data)
242 dev_set_drvdata(&spi->dev, data);
245 static inline void *spi_get_drvdata(struct spi_device *spi)
247 return dev_get_drvdata(&spi->dev);
254 * struct spi_driver - Host side "protocol" driver
255 * @id_table: List of SPI devices supported by this driver
256 * @probe: Binds this driver to the spi device. Drivers can verify
257 * that the device is actually present, and may need to configure
258 * characteristics (such as bits_per_word) which weren't needed for
259 * the initial configuration done during system setup.
260 * @remove: Unbinds this driver from the spi device
261 * @shutdown: Standard shutdown callback used during system state
262 * transitions such as powerdown/halt and kexec
263 * @driver: SPI device drivers should initialize the name and owner
264 * field of this structure.
266 * This represents the kind of device driver that uses SPI messages to
267 * interact with the hardware at the other end of a SPI link. It's called
268 * a "protocol" driver because it works through messages rather than talking
269 * directly to SPI hardware (which is what the underlying SPI controller
270 * driver does to pass those messages). These protocols are defined in the
271 * specification for the device(s) supported by the driver.
273 * As a rule, those device protocols represent the lowest level interface
274 * supported by a driver, and it will support upper level interfaces too.
275 * Examples of such upper levels include frameworks like MTD, networking,
276 * MMC, RTC, filesystem character device nodes, and hardware monitoring.
279 const struct spi_device_id *id_table;
280 int (*probe)(struct spi_device *spi);
281 int (*remove)(struct spi_device *spi);
282 void (*shutdown)(struct spi_device *spi);
283 struct device_driver driver;
286 static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
288 return drv ? container_of(drv, struct spi_driver, driver) : NULL;
291 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv);
294 * spi_unregister_driver - reverse effect of spi_register_driver
295 * @sdrv: the driver to unregister
298 static inline void spi_unregister_driver(struct spi_driver *sdrv)
301 driver_unregister(&sdrv->driver);
304 /* use a define to avoid include chaining to get THIS_MODULE */
305 #define spi_register_driver(driver) \
306 __spi_register_driver(THIS_MODULE, driver)
309 * module_spi_driver() - Helper macro for registering a SPI driver
310 * @__spi_driver: spi_driver struct
312 * Helper macro for SPI drivers which do not do anything special in module
313 * init/exit. This eliminates a lot of boilerplate. Each module may only
314 * use this macro once, and calling it replaces module_init() and module_exit()
316 #define module_spi_driver(__spi_driver) \
317 module_driver(__spi_driver, spi_register_driver, \
318 spi_unregister_driver)
321 * struct spi_controller - interface to SPI master or slave controller
322 * @dev: device interface to this driver
323 * @list: link with the global spi_controller list
324 * @bus_num: board-specific (and often SOC-specific) identifier for a
325 * given SPI controller.
326 * @num_chipselect: chipselects are used to distinguish individual
327 * SPI slaves, and are numbered from zero to num_chipselects.
328 * each slave has a chipselect signal, but it's common that not
329 * every chipselect is connected to a slave.
330 * @dma_alignment: SPI controller constraint on DMA buffers alignment.
331 * @mode_bits: flags understood by this controller driver
332 * @buswidth_override_bits: flags to override for this controller driver
333 * @bits_per_word_mask: A mask indicating which values of bits_per_word are
334 * supported by the driver. Bit n indicates that a bits_per_word n+1 is
335 * supported. If set, the SPI core will reject any transfer with an
336 * unsupported bits_per_word. If not set, this value is simply ignored,
337 * and it's up to the individual driver to perform any validation.
338 * @min_speed_hz: Lowest supported transfer speed
339 * @max_speed_hz: Highest supported transfer speed
340 * @flags: other constraints relevant to this driver
341 * @slave: indicates that this is an SPI slave controller
342 * @max_transfer_size: function that returns the max transfer size for
343 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
344 * @max_message_size: function that returns the max message size for
345 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
346 * @io_mutex: mutex for physical bus access
347 * @bus_lock_spinlock: spinlock for SPI bus locking
348 * @bus_lock_mutex: mutex for exclusion of multiple callers
349 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use
350 * @setup: updates the device mode and clocking records used by a
351 * device's SPI controller; protocol code may call this. This
352 * must fail if an unrecognized or unsupported mode is requested.
353 * It's always safe to call this unless transfers are pending on
354 * the device whose settings are being modified.
355 * @set_cs_timing: optional hook for SPI devices to request SPI master
356 * controller for configuring specific CS setup time, hold time and inactive
357 * delay interms of clock counts
358 * @transfer: adds a message to the controller's transfer queue.
359 * @cleanup: frees controller-specific state
360 * @can_dma: determine whether this controller supports DMA
361 * @queued: whether this controller is providing an internal message queue
362 * @kworker: pointer to thread struct for message pump
363 * @pump_messages: work struct for scheduling work to the message pump
364 * @queue_lock: spinlock to syncronise access to message queue
365 * @queue: message queue
366 * @idling: the device is entering idle state
367 * @cur_msg: the currently in-flight message
368 * @cur_msg_prepared: spi_prepare_message was called for the currently
370 * @cur_msg_mapped: message has been mapped for DMA
371 * @last_cs_enable: was enable true on the last call to set_cs.
372 * @last_cs_mode_high: was (mode & SPI_CS_HIGH) true on the last call to set_cs.
373 * @xfer_completion: used by core transfer_one_message()
374 * @busy: message pump is busy
375 * @running: message pump is running
376 * @rt: whether this queue is set to run as a realtime task
377 * @auto_runtime_pm: the core should ensure a runtime PM reference is held
378 * while the hardware is prepared, using the parent
379 * device for the spidev
380 * @max_dma_len: Maximum length of a DMA transfer for the device.
381 * @prepare_transfer_hardware: a message will soon arrive from the queue
382 * so the subsystem requests the driver to prepare the transfer hardware
383 * by issuing this call
384 * @transfer_one_message: the subsystem calls the driver to transfer a single
385 * message while queuing transfers that arrive in the meantime. When the
386 * driver is finished with this message, it must call
387 * spi_finalize_current_message() so the subsystem can issue the next
389 * @unprepare_transfer_hardware: there are currently no more messages on the
390 * queue so the subsystem notifies the driver that it may relax the
391 * hardware by issuing this call
393 * @set_cs: set the logic level of the chip select line. May be called
394 * from interrupt context.
395 * @prepare_message: set up the controller to transfer a single message,
396 * for example doing DMA mapping. Called from threaded
398 * @transfer_one: transfer a single spi_transfer.
400 * - return 0 if the transfer is finished,
401 * - return 1 if the transfer is still in progress. When
402 * the driver is finished with this transfer it must
403 * call spi_finalize_current_transfer() so the subsystem
404 * can issue the next transfer. Note: transfer_one and
405 * transfer_one_message are mutually exclusive; when both
406 * are set, the generic subsystem does not call your
407 * transfer_one callback.
408 * @handle_err: the subsystem calls the driver to handle an error that occurs
409 * in the generic implementation of transfer_one_message().
410 * @mem_ops: optimized/dedicated operations for interactions with SPI memory.
411 * This field is optional and should only be implemented if the
412 * controller has native support for memory like operations.
413 * @unprepare_message: undo any work done by prepare_message().
414 * @slave_abort: abort the ongoing transfer request on an SPI slave controller
415 * @cs_setup: delay to be introduced by the controller after CS is asserted
416 * @cs_hold: delay to be introduced by the controller before CS is deasserted
417 * @cs_inactive: delay to be introduced by the controller after CS is
418 * deasserted. If @cs_change_delay is used from @spi_transfer, then the
419 * two delays will be added up.
420 * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per
421 * CS number. Any individual value may be -ENOENT for CS lines that
422 * are not GPIOs (driven by the SPI controller itself). Use the cs_gpiods
424 * @cs_gpiods: Array of GPIO descs to use as chip select lines; one per CS
425 * number. Any individual value may be NULL for CS lines that
426 * are not GPIOs (driven by the SPI controller itself).
427 * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab
428 * GPIO descriptors rather than using global GPIO numbers grabbed by the
429 * driver. This will fill in @cs_gpiods and @cs_gpios should not be used,
430 * and SPI devices will have the cs_gpiod assigned rather than cs_gpio.
431 * @unused_native_cs: When cs_gpiods is used, spi_register_controller() will
432 * fill in this field with the first unused native CS, to be used by SPI
433 * controller drivers that need to drive a native CS when using GPIO CS.
434 * @max_native_cs: When cs_gpiods is used, and this field is filled in,
435 * spi_register_controller() will validate all native CS (including the
436 * unused native CS) against this value.
437 * @statistics: statistics for the spi_controller
438 * @dma_tx: DMA transmit channel
439 * @dma_rx: DMA receive channel
440 * @dummy_rx: dummy receive buffer for full-duplex devices
441 * @dummy_tx: dummy transmit buffer for full-duplex devices
442 * @fw_translate_cs: If the boot firmware uses different numbering scheme
443 * what Linux expects, this optional hook can be used to translate
445 * @ptp_sts_supported: If the driver sets this to true, it must provide a
446 * time snapshot in @spi_transfer->ptp_sts as close as possible to the
447 * moment in time when @spi_transfer->ptp_sts_word_pre and
448 * @spi_transfer->ptp_sts_word_post were transmitted.
449 * If the driver does not set this, the SPI core takes the snapshot as
450 * close to the driver hand-over as possible.
451 * @irq_flags: Interrupt enable state during PTP system timestamping
452 * @fallback: fallback to pio if dma transfer return failure with
453 * SPI_TRANS_FAIL_NO_START.
455 * Each SPI controller can communicate with one or more @spi_device
456 * children. These make a small bus, sharing MOSI, MISO and SCK signals
457 * but not chip select signals. Each device may be configured to use a
458 * different clock rate, since those shared signals are ignored unless
459 * the chip is selected.
461 * The driver for an SPI controller manages access to those devices through
462 * a queue of spi_message transactions, copying data between CPU memory and
463 * an SPI slave device. For each such message it queues, it calls the
464 * message's completion function when the transaction completes.
466 struct spi_controller {
469 struct list_head list;
471 /* other than negative (== assign one dynamically), bus_num is fully
472 * board-specific. usually that simplifies to being SOC-specific.
473 * example: one SOC has three SPI controllers, numbered 0..2,
474 * and one board's schematics might show it using SPI-2. software
475 * would normally use bus_num=2 for that controller.
479 /* chipselects will be integral to many controllers; some others
480 * might use board-specific GPIOs.
484 /* some SPI controllers pose alignment requirements on DMAable
485 * buffers; let protocol drivers know about these requirements.
489 /* spi_device.mode flags understood by this controller driver */
492 /* spi_device.mode flags override flags for this controller */
493 u32 buswidth_override_bits;
495 /* bitmask of supported bits_per_word for transfers */
496 u32 bits_per_word_mask;
497 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
498 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)
500 /* limits on transfer speed */
504 /* other constraints relevant to this driver */
506 #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* can't do full duplex */
507 #define SPI_CONTROLLER_NO_RX BIT(1) /* can't do buffer read */
508 #define SPI_CONTROLLER_NO_TX BIT(2) /* can't do buffer write */
509 #define SPI_CONTROLLER_MUST_RX BIT(3) /* requires rx */
510 #define SPI_CONTROLLER_MUST_TX BIT(4) /* requires tx */
512 #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */
514 /* flag indicating this is an SPI slave controller */
518 * on some hardware transfer / message size may be constrained
519 * the limit may depend on device transfer settings
521 size_t (*max_transfer_size)(struct spi_device *spi);
522 size_t (*max_message_size)(struct spi_device *spi);
525 struct mutex io_mutex;
527 /* lock and mutex for SPI bus locking */
528 spinlock_t bus_lock_spinlock;
529 struct mutex bus_lock_mutex;
531 /* flag indicating that the SPI bus is locked for exclusive use */
534 /* Setup mode and clock, etc (spi driver may call many times).
536 * IMPORTANT: this may be called when transfers to another
537 * device are active. DO NOT UPDATE SHARED REGISTERS in ways
538 * which could break those transfers.
540 int (*setup)(struct spi_device *spi);
543 * set_cs_timing() method is for SPI controllers that supports
544 * configuring CS timing.
546 * This hook allows SPI client drivers to request SPI controllers
547 * to configure specific CS timing through spi_set_cs_timing() after
550 int (*set_cs_timing)(struct spi_device *spi, struct spi_delay *setup,
551 struct spi_delay *hold, struct spi_delay *inactive);
553 /* bidirectional bulk transfers
555 * + The transfer() method may not sleep; its main role is
556 * just to add the message to the queue.
557 * + For now there's no remove-from-queue operation, or
558 * any other request management
559 * + To a given spi_device, message queueing is pure fifo
561 * + The controller's main job is to process its message queue,
562 * selecting a chip (for masters), then transferring data
563 * + If there are multiple spi_device children, the i/o queue
564 * arbitration algorithm is unspecified (round robin, fifo,
565 * priority, reservations, preemption, etc)
567 * + Chipselect stays active during the entire message
568 * (unless modified by spi_transfer.cs_change != 0).
569 * + The message transfers use clock and SPI mode parameters
570 * previously established by setup() for this device
572 int (*transfer)(struct spi_device *spi,
573 struct spi_message *mesg);
575 /* called on release() to free memory provided by spi_controller */
576 void (*cleanup)(struct spi_device *spi);
579 * Used to enable core support for DMA handling, if can_dma()
580 * exists and returns true then the transfer will be mapped
581 * prior to transfer_one() being called. The driver should
582 * not modify or store xfer and dma_tx and dma_rx must be set
583 * while the device is prepared.
585 bool (*can_dma)(struct spi_controller *ctlr,
586 struct spi_device *spi,
587 struct spi_transfer *xfer);
590 * These hooks are for drivers that want to use the generic
591 * controller transfer queueing mechanism. If these are used, the
592 * transfer() function above must NOT be specified by the driver.
593 * Over time we expect SPI drivers to be phased over to this API.
596 struct kthread_worker *kworker;
597 struct kthread_work pump_messages;
598 spinlock_t queue_lock;
599 struct list_head queue;
600 struct spi_message *cur_msg;
605 bool auto_runtime_pm;
606 bool cur_msg_prepared;
609 bool last_cs_mode_high;
611 struct completion xfer_completion;
614 int (*prepare_transfer_hardware)(struct spi_controller *ctlr);
615 int (*transfer_one_message)(struct spi_controller *ctlr,
616 struct spi_message *mesg);
617 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr);
618 int (*prepare_message)(struct spi_controller *ctlr,
619 struct spi_message *message);
620 int (*unprepare_message)(struct spi_controller *ctlr,
621 struct spi_message *message);
622 int (*slave_abort)(struct spi_controller *ctlr);
625 * These hooks are for drivers that use a generic implementation
626 * of transfer_one_message() provied by the core.
628 void (*set_cs)(struct spi_device *spi, bool enable);
629 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi,
630 struct spi_transfer *transfer);
631 void (*handle_err)(struct spi_controller *ctlr,
632 struct spi_message *message);
634 /* Optimized handlers for SPI memory-like operations. */
635 const struct spi_controller_mem_ops *mem_ops;
638 struct spi_delay cs_setup;
639 struct spi_delay cs_hold;
640 struct spi_delay cs_inactive;
642 /* gpio chip select */
644 struct gpio_desc **cs_gpiods;
645 bool use_gpio_descriptors;
650 struct spi_statistics statistics;
652 /* DMA channels for use with core dmaengine helpers */
653 struct dma_chan *dma_tx;
654 struct dma_chan *dma_rx;
656 /* dummy data for full duplex devices */
660 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
663 * Driver sets this field to indicate it is able to snapshot SPI
664 * transfers (needed e.g. for reading the time of POSIX clocks)
666 bool ptp_sts_supported;
668 /* Interrupt enable state during PTP system timestamping */
669 unsigned long irq_flags;
672 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr)
674 return dev_get_drvdata(&ctlr->dev);
677 static inline void spi_controller_set_devdata(struct spi_controller *ctlr,
680 dev_set_drvdata(&ctlr->dev, data);
683 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr)
685 if (!ctlr || !get_device(&ctlr->dev))
690 static inline void spi_controller_put(struct spi_controller *ctlr)
693 put_device(&ctlr->dev);
696 static inline bool spi_controller_is_slave(struct spi_controller *ctlr)
698 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave;
701 /* PM calls that need to be issued by the driver */
702 extern int spi_controller_suspend(struct spi_controller *ctlr);
703 extern int spi_controller_resume(struct spi_controller *ctlr);
705 /* Calls the driver make to interact with the message queue */
706 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr);
707 extern void spi_finalize_current_message(struct spi_controller *ctlr);
708 extern void spi_finalize_current_transfer(struct spi_controller *ctlr);
710 /* Helper calls for driver to timestamp transfer */
711 void spi_take_timestamp_pre(struct spi_controller *ctlr,
712 struct spi_transfer *xfer,
713 size_t progress, bool irqs_off);
714 void spi_take_timestamp_post(struct spi_controller *ctlr,
715 struct spi_transfer *xfer,
716 size_t progress, bool irqs_off);
718 /* the spi driver core manages memory for the spi_controller classdev */
719 extern struct spi_controller *__spi_alloc_controller(struct device *host,
720 unsigned int size, bool slave);
722 static inline struct spi_controller *spi_alloc_master(struct device *host,
725 return __spi_alloc_controller(host, size, false);
728 static inline struct spi_controller *spi_alloc_slave(struct device *host,
731 if (!IS_ENABLED(CONFIG_SPI_SLAVE))
734 return __spi_alloc_controller(host, size, true);
737 extern int spi_register_controller(struct spi_controller *ctlr);
738 extern int devm_spi_register_controller(struct device *dev,
739 struct spi_controller *ctlr);
740 extern void spi_unregister_controller(struct spi_controller *ctlr);
742 extern struct spi_controller *spi_busnum_to_master(u16 busnum);
745 * SPI resource management while processing a SPI message
748 typedef void (*spi_res_release_t)(struct spi_controller *ctlr,
749 struct spi_message *msg,
753 * struct spi_res - spi resource management structure
755 * @release: release code called prior to freeing this resource
756 * @data: extra data allocated for the specific use-case
758 * this is based on ideas from devres, but focused on life-cycle
759 * management during spi_message processing
762 struct list_head entry;
763 spi_res_release_t release;
764 unsigned long long data[]; /* guarantee ull alignment */
767 extern void *spi_res_alloc(struct spi_device *spi,
768 spi_res_release_t release,
769 size_t size, gfp_t gfp);
770 extern void spi_res_add(struct spi_message *message, void *res);
771 extern void spi_res_free(void *res);
773 extern void spi_res_release(struct spi_controller *ctlr,
774 struct spi_message *message);
776 /*---------------------------------------------------------------------------*/
779 * I/O INTERFACE between SPI controller and protocol drivers
781 * Protocol drivers use a queue of spi_messages, each transferring data
782 * between the controller and memory buffers.
784 * The spi_messages themselves consist of a series of read+write transfer
785 * segments. Those segments always read the same number of bits as they
786 * write; but one or the other is easily ignored by passing a null buffer
787 * pointer. (This is unlike most types of I/O API, because SPI hardware
790 * NOTE: Allocation of spi_transfer and spi_message memory is entirely
791 * up to the protocol driver, which guarantees the integrity of both (as
792 * well as the data buffers) for as long as the message is queued.
796 * struct spi_transfer - a read/write buffer pair
797 * @tx_buf: data to be written (dma-safe memory), or NULL
798 * @rx_buf: data to be read (dma-safe memory), or NULL
799 * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped
800 * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped
801 * @tx_nbits: number of bits used for writing. If 0 the default
802 * (SPI_NBITS_SINGLE) is used.
803 * @rx_nbits: number of bits used for reading. If 0 the default
804 * (SPI_NBITS_SINGLE) is used.
805 * @len: size of rx and tx buffers (in bytes)
806 * @speed_hz: Select a speed other than the device default for this
807 * transfer. If 0 the default (from @spi_device) is used.
808 * @bits_per_word: select a bits_per_word other than the device default
809 * for this transfer. If 0 the default (from @spi_device) is used.
810 * @cs_change: affects chipselect after this transfer completes
811 * @cs_change_delay: delay between cs deassert and assert when
812 * @cs_change is set and @spi_transfer is not the last in @spi_message
813 * @delay: delay to be introduced after this transfer before
814 * (optionally) changing the chipselect status, then starting
815 * the next transfer or completing this @spi_message.
816 * @delay_usecs: microseconds to delay after this transfer before
817 * (optionally) changing the chipselect status, then starting
818 * the next transfer or completing this @spi_message.
819 * @word_delay: inter word delay to be introduced after each word size
820 * (set by bits_per_word) transmission.
821 * @effective_speed_hz: the effective SCK-speed that was used to
822 * transfer this transfer. Set to 0 if the spi bus driver does
824 * @transfer_list: transfers are sequenced through @spi_message.transfers
825 * @tx_sg: Scatterlist for transmit, currently not for client use
826 * @rx_sg: Scatterlist for receive, currently not for client use
827 * @ptp_sts_word_pre: The word (subject to bits_per_word semantics) offset
828 * within @tx_buf for which the SPI device is requesting that the time
829 * snapshot for this transfer begins. Upon completing the SPI transfer,
830 * this value may have changed compared to what was requested, depending
831 * on the available snapshotting resolution (DMA transfer,
832 * @ptp_sts_supported is false, etc).
833 * @ptp_sts_word_post: See @ptp_sts_word_post. The two can be equal (meaning
834 * that a single byte should be snapshotted).
835 * If the core takes care of the timestamp (if @ptp_sts_supported is false
836 * for this controller), it will set @ptp_sts_word_pre to 0, and
837 * @ptp_sts_word_post to the length of the transfer. This is done
838 * purposefully (instead of setting to spi_transfer->len - 1) to denote
839 * that a transfer-level snapshot taken from within the driver may still
840 * be of higher quality.
841 * @ptp_sts: Pointer to a memory location held by the SPI slave device where a
842 * PTP system timestamp structure may lie. If drivers use PIO or their
843 * hardware has some sort of assist for retrieving exact transfer timing,
844 * they can (and should) assert @ptp_sts_supported and populate this
845 * structure using the ptp_read_system_*ts helper functions.
846 * The timestamp must represent the time at which the SPI slave device has
847 * processed the word, i.e. the "pre" timestamp should be taken before
848 * transmitting the "pre" word, and the "post" timestamp after receiving
849 * transmit confirmation from the controller for the "post" word.
850 * @timestamped: true if the transfer has been timestamped
851 * @error: Error status logged by spi controller driver.
853 * SPI transfers always write the same number of bytes as they read.
854 * Protocol drivers should always provide @rx_buf and/or @tx_buf.
855 * In some cases, they may also want to provide DMA addresses for
856 * the data being transferred; that may reduce overhead, when the
857 * underlying driver uses dma.
859 * If the transmit buffer is null, zeroes will be shifted out
860 * while filling @rx_buf. If the receive buffer is null, the data
861 * shifted in will be discarded. Only "len" bytes shift out (or in).
862 * It's an error to try to shift out a partial word. (For example, by
863 * shifting out three bytes with word size of sixteen or twenty bits;
864 * the former uses two bytes per word, the latter uses four bytes.)
866 * In-memory data values are always in native CPU byte order, translated
867 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So
868 * for example when bits_per_word is sixteen, buffers are 2N bytes long
869 * (@len = 2N) and hold N sixteen bit words in CPU byte order.
871 * When the word size of the SPI transfer is not a power-of-two multiple
872 * of eight bits, those in-memory words include extra bits. In-memory
873 * words are always seen by protocol drivers as right-justified, so the
874 * undefined (rx) or unused (tx) bits are always the most significant bits.
876 * All SPI transfers start with the relevant chipselect active. Normally
877 * it stays selected until after the last transfer in a message. Drivers
878 * can affect the chipselect signal using cs_change.
880 * (i) If the transfer isn't the last one in the message, this flag is
881 * used to make the chipselect briefly go inactive in the middle of the
882 * message. Toggling chipselect in this way may be needed to terminate
883 * a chip command, letting a single spi_message perform all of group of
884 * chip transactions together.
886 * (ii) When the transfer is the last one in the message, the chip may
887 * stay selected until the next transfer. On multi-device SPI busses
888 * with nothing blocking messages going to other devices, this is just
889 * a performance hint; starting a message to another device deselects
890 * this one. But in other cases, this can be used to ensure correctness.
891 * Some devices need protocol transactions to be built from a series of
892 * spi_message submissions, where the content of one message is determined
893 * by the results of previous messages and where the whole transaction
894 * ends when the chipselect goes intactive.
896 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information
897 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
898 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
899 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
901 * The code that submits an spi_message (and its spi_transfers)
902 * to the lower layers is responsible for managing its memory.
903 * Zero-initialize every field you don't set up explicitly, to
904 * insulate against future API updates. After you submit a message
905 * and its transfers, ignore them until its completion callback.
907 struct spi_transfer {
908 /* it's ok if tx_buf == rx_buf (right?)
909 * for MicroWire, one buffer must be null
910 * buffers must work with dma_*map_single() calls, unless
911 * spi_message.is_dma_mapped reports a pre-existing mapping
919 struct sg_table tx_sg;
920 struct sg_table rx_sg;
922 unsigned cs_change:1;
925 #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
926 #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */
927 #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
930 struct spi_delay delay;
931 struct spi_delay cs_change_delay;
932 struct spi_delay word_delay;
935 u32 effective_speed_hz;
937 unsigned int ptp_sts_word_pre;
938 unsigned int ptp_sts_word_post;
940 struct ptp_system_timestamp *ptp_sts;
944 struct list_head transfer_list;
946 #define SPI_TRANS_FAIL_NO_START BIT(0)
951 * struct spi_message - one multi-segment SPI transaction
952 * @transfers: list of transfer segments in this transaction
953 * @spi: SPI device to which the transaction is queued
954 * @is_dma_mapped: if true, the caller provided both dma and cpu virtual
955 * addresses for each transfer buffer
956 * @complete: called to report transaction completions
957 * @context: the argument to complete() when it's called
958 * @frame_length: the total number of bytes in the message
959 * @actual_length: the total number of bytes that were transferred in all
960 * successful segments
961 * @status: zero for success, else negative errno
962 * @queue: for use by whichever driver currently owns the message
963 * @state: for use by whichever driver currently owns the message
964 * @resources: for resource management when the spi message is processed
966 * A @spi_message is used to execute an atomic sequence of data transfers,
967 * each represented by a struct spi_transfer. The sequence is "atomic"
968 * in the sense that no other spi_message may use that SPI bus until that
969 * sequence completes. On some systems, many such sequences can execute as
970 * a single programmed DMA transfer. On all systems, these messages are
971 * queued, and might complete after transactions to other devices. Messages
972 * sent to a given spi_device are always executed in FIFO order.
974 * The code that submits an spi_message (and its spi_transfers)
975 * to the lower layers is responsible for managing its memory.
976 * Zero-initialize every field you don't set up explicitly, to
977 * insulate against future API updates. After you submit a message
978 * and its transfers, ignore them until its completion callback.
981 struct list_head transfers;
983 struct spi_device *spi;
985 unsigned is_dma_mapped:1;
987 /* REVISIT: we might want a flag affecting the behavior of the
988 * last transfer ... allowing things like "read 16 bit length L"
989 * immediately followed by "read L bytes". Basically imposing
990 * a specific message scheduling algorithm.
992 * Some controller drivers (message-at-a-time queue processing)
993 * could provide that as their default scheduling algorithm. But
994 * others (with multi-message pipelines) could need a flag to
995 * tell them about such special cases.
998 /* completion is reported through a callback */
999 void (*complete)(void *context);
1001 unsigned frame_length;
1002 unsigned actual_length;
1005 /* for optional use by whatever driver currently owns the
1006 * spi_message ... between calls to spi_async and then later
1007 * complete(), that's the spi_controller controller driver.
1009 struct list_head queue;
1012 /* list of spi_res reources when the spi message is processed */
1013 struct list_head resources;
1016 static inline void spi_message_init_no_memset(struct spi_message *m)
1018 INIT_LIST_HEAD(&m->transfers);
1019 INIT_LIST_HEAD(&m->resources);
1022 static inline void spi_message_init(struct spi_message *m)
1024 memset(m, 0, sizeof *m);
1025 spi_message_init_no_memset(m);
1029 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m)
1031 list_add_tail(&t->transfer_list, &m->transfers);
1035 spi_transfer_del(struct spi_transfer *t)
1037 list_del(&t->transfer_list);
1041 spi_transfer_delay_exec(struct spi_transfer *t)
1045 if (t->delay_usecs) {
1046 d.value = t->delay_usecs;
1047 d.unit = SPI_DELAY_UNIT_USECS;
1048 return spi_delay_exec(&d, NULL);
1051 return spi_delay_exec(&t->delay, t);
1055 * spi_message_init_with_transfers - Initialize spi_message and append transfers
1056 * @m: spi_message to be initialized
1057 * @xfers: An array of spi transfers
1058 * @num_xfers: Number of items in the xfer array
1060 * This function initializes the given spi_message and adds each spi_transfer in
1061 * the given array to the message.
1064 spi_message_init_with_transfers(struct spi_message *m,
1065 struct spi_transfer *xfers, unsigned int num_xfers)
1069 spi_message_init(m);
1070 for (i = 0; i < num_xfers; ++i)
1071 spi_message_add_tail(&xfers[i], m);
1074 /* It's fine to embed message and transaction structures in other data
1075 * structures so long as you don't free them while they're in use.
1078 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags)
1080 struct spi_message *m;
1082 m = kzalloc(sizeof(struct spi_message)
1083 + ntrans * sizeof(struct spi_transfer),
1087 struct spi_transfer *t = (struct spi_transfer *)(m + 1);
1089 spi_message_init_no_memset(m);
1090 for (i = 0; i < ntrans; i++, t++)
1091 spi_message_add_tail(t, m);
1096 static inline void spi_message_free(struct spi_message *m)
1101 extern int spi_set_cs_timing(struct spi_device *spi,
1102 struct spi_delay *setup,
1103 struct spi_delay *hold,
1104 struct spi_delay *inactive);
1106 extern int spi_setup(struct spi_device *spi);
1107 extern int spi_async(struct spi_device *spi, struct spi_message *message);
1108 extern int spi_async_locked(struct spi_device *spi,
1109 struct spi_message *message);
1110 extern int spi_slave_abort(struct spi_device *spi);
1112 static inline size_t
1113 spi_max_message_size(struct spi_device *spi)
1115 struct spi_controller *ctlr = spi->controller;
1117 if (!ctlr->max_message_size)
1119 return ctlr->max_message_size(spi);
1122 static inline size_t
1123 spi_max_transfer_size(struct spi_device *spi)
1125 struct spi_controller *ctlr = spi->controller;
1126 size_t tr_max = SIZE_MAX;
1127 size_t msg_max = spi_max_message_size(spi);
1129 if (ctlr->max_transfer_size)
1130 tr_max = ctlr->max_transfer_size(spi);
1132 /* transfer size limit must not be greater than messsage size limit */
1133 return min(tr_max, msg_max);
1137 * spi_is_bpw_supported - Check if bits per word is supported
1139 * @bpw: Bits per word
1141 * This function checks to see if the SPI controller supports @bpw.
1144 * True if @bpw is supported, false otherwise.
1146 static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw)
1148 u32 bpw_mask = spi->master->bits_per_word_mask;
1150 if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw)))
1156 /*---------------------------------------------------------------------------*/
1158 /* SPI transfer replacement methods which make use of spi_res */
1160 struct spi_replaced_transfers;
1161 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr,
1162 struct spi_message *msg,
1163 struct spi_replaced_transfers *res);
1165 * struct spi_replaced_transfers - structure describing the spi_transfer
1166 * replacements that have occurred
1167 * so that they can get reverted
1168 * @release: some extra release code to get executed prior to
1169 * relasing this structure
1170 * @extradata: pointer to some extra data if requested or NULL
1171 * @replaced_transfers: transfers that have been replaced and which need
1173 * @replaced_after: the transfer after which the @replaced_transfers
1174 * are to get re-inserted
1175 * @inserted: number of transfers inserted
1176 * @inserted_transfers: array of spi_transfers of array-size @inserted,
1177 * that have been replacing replaced_transfers
1179 * note: that @extradata will point to @inserted_transfers[@inserted]
1180 * if some extra allocation is requested, so alignment will be the same
1181 * as for spi_transfers
1183 struct spi_replaced_transfers {
1184 spi_replaced_release_t release;
1186 struct list_head replaced_transfers;
1187 struct list_head *replaced_after;
1189 struct spi_transfer inserted_transfers[];
1192 extern struct spi_replaced_transfers *spi_replace_transfers(
1193 struct spi_message *msg,
1194 struct spi_transfer *xfer_first,
1197 spi_replaced_release_t release,
1198 size_t extradatasize,
1201 /*---------------------------------------------------------------------------*/
1203 /* SPI transfer transformation methods */
1205 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr,
1206 struct spi_message *msg,
1210 /*---------------------------------------------------------------------------*/
1212 /* All these synchronous SPI transfer routines are utilities layered
1213 * over the core async transfer primitive. Here, "synchronous" means
1214 * they will sleep uninterruptibly until the async transfer completes.
1217 extern int spi_sync(struct spi_device *spi, struct spi_message *message);
1218 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message);
1219 extern int spi_bus_lock(struct spi_controller *ctlr);
1220 extern int spi_bus_unlock(struct spi_controller *ctlr);
1223 * spi_sync_transfer - synchronous SPI data transfer
1224 * @spi: device with which data will be exchanged
1225 * @xfers: An array of spi_transfers
1226 * @num_xfers: Number of items in the xfer array
1227 * Context: can sleep
1229 * Does a synchronous SPI data transfer of the given spi_transfer array.
1231 * For more specific semantics see spi_sync().
1233 * Return: zero on success, else a negative error code.
1236 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers,
1237 unsigned int num_xfers)
1239 struct spi_message msg;
1241 spi_message_init_with_transfers(&msg, xfers, num_xfers);
1243 return spi_sync(spi, &msg);
1247 * spi_write - SPI synchronous write
1248 * @spi: device to which data will be written
1250 * @len: data buffer size
1251 * Context: can sleep
1253 * This function writes the buffer @buf.
1254 * Callable only from contexts that can sleep.
1256 * Return: zero on success, else a negative error code.
1259 spi_write(struct spi_device *spi, const void *buf, size_t len)
1261 struct spi_transfer t = {
1266 return spi_sync_transfer(spi, &t, 1);
1270 * spi_read - SPI synchronous read
1271 * @spi: device from which data will be read
1273 * @len: data buffer size
1274 * Context: can sleep
1276 * This function reads the buffer @buf.
1277 * Callable only from contexts that can sleep.
1279 * Return: zero on success, else a negative error code.
1282 spi_read(struct spi_device *spi, void *buf, size_t len)
1284 struct spi_transfer t = {
1289 return spi_sync_transfer(spi, &t, 1);
1292 /* this copies txbuf and rxbuf data; for small transfers only! */
1293 extern int spi_write_then_read(struct spi_device *spi,
1294 const void *txbuf, unsigned n_tx,
1295 void *rxbuf, unsigned n_rx);
1298 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
1299 * @spi: device with which data will be exchanged
1300 * @cmd: command to be written before data is read back
1301 * Context: can sleep
1303 * Callable only from contexts that can sleep.
1305 * Return: the (unsigned) eight bit number returned by the
1306 * device, or else a negative error code.
1308 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd)
1313 status = spi_write_then_read(spi, &cmd, 1, &result, 1);
1315 /* return negative errno or unsigned value */
1316 return (status < 0) ? status : result;
1320 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
1321 * @spi: device with which data will be exchanged
1322 * @cmd: command to be written before data is read back
1323 * Context: can sleep
1325 * The number is returned in wire-order, which is at least sometimes
1328 * Callable only from contexts that can sleep.
1330 * Return: the (unsigned) sixteen bit number returned by the
1331 * device, or else a negative error code.
1333 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd)
1338 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
1340 /* return negative errno or unsigned value */
1341 return (status < 0) ? status : result;
1345 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read
1346 * @spi: device with which data will be exchanged
1347 * @cmd: command to be written before data is read back
1348 * Context: can sleep
1350 * This function is similar to spi_w8r16, with the exception that it will
1351 * convert the read 16 bit data word from big-endian to native endianness.
1353 * Callable only from contexts that can sleep.
1355 * Return: the (unsigned) sixteen bit number returned by the device in cpu
1356 * endianness, or else a negative error code.
1358 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd)
1364 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
1368 return be16_to_cpu(result);
1371 /*---------------------------------------------------------------------------*/
1374 * INTERFACE between board init code and SPI infrastructure.
1376 * No SPI driver ever sees these SPI device table segments, but
1377 * it's how the SPI core (or adapters that get hotplugged) grows
1378 * the driver model tree.
1380 * As a rule, SPI devices can't be probed. Instead, board init code
1381 * provides a table listing the devices which are present, with enough
1382 * information to bind and set up the device's driver. There's basic
1383 * support for nonstatic configurations too; enough to handle adding
1384 * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
1388 * struct spi_board_info - board-specific template for a SPI device
1389 * @modalias: Initializes spi_device.modalias; identifies the driver.
1390 * @platform_data: Initializes spi_device.platform_data; the particular
1391 * data stored there is driver-specific.
1392 * @properties: Additional device properties for the device.
1393 * @controller_data: Initializes spi_device.controller_data; some
1394 * controllers need hints about hardware setup, e.g. for DMA.
1395 * @irq: Initializes spi_device.irq; depends on how the board is wired.
1396 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits
1397 * from the chip datasheet and board-specific signal quality issues.
1398 * @bus_num: Identifies which spi_controller parents the spi_device; unused
1399 * by spi_new_device(), and otherwise depends on board wiring.
1400 * @chip_select: Initializes spi_device.chip_select; depends on how
1401 * the board is wired.
1402 * @mode: Initializes spi_device.mode; based on the chip datasheet, board
1403 * wiring (some devices support both 3WIRE and standard modes), and
1404 * possibly presence of an inverter in the chipselect path.
1406 * When adding new SPI devices to the device tree, these structures serve
1407 * as a partial device template. They hold information which can't always
1408 * be determined by drivers. Information that probe() can establish (such
1409 * as the default transfer wordsize) is not included here.
1411 * These structures are used in two places. Their primary role is to
1412 * be stored in tables of board-specific device descriptors, which are
1413 * declared early in board initialization and then used (much later) to
1414 * populate a controller's device tree after the that controller's driver
1415 * initializes. A secondary (and atypical) role is as a parameter to
1416 * spi_new_device() call, which happens after those controller drivers
1417 * are active in some dynamic board configuration models.
1419 struct spi_board_info {
1420 /* the device name and module name are coupled, like platform_bus;
1421 * "modalias" is normally the driver name.
1423 * platform_data goes to spi_device.dev.platform_data,
1424 * controller_data goes to spi_device.controller_data,
1425 * device properties are copied and attached to spi_device,
1428 char modalias[SPI_NAME_SIZE];
1429 const void *platform_data;
1430 const struct property_entry *properties;
1431 void *controller_data;
1434 /* slower signaling on noisy or low voltage boards */
1438 /* bus_num is board specific and matches the bus_num of some
1439 * spi_controller that will probably be registered later.
1441 * chip_select reflects how this chip is wired to that master;
1442 * it's less than num_chipselect.
1447 /* mode becomes spi_device.mode, and is essential for chips
1448 * where the default of SPI_CS_HIGH = 0 is wrong.
1452 /* ... may need additional spi_device chip config data here.
1453 * avoid stuff protocol drivers can set; but include stuff
1454 * needed to behave without being bound to a driver:
1455 * - quirks like clock rate mattering when not selected
1461 spi_register_board_info(struct spi_board_info const *info, unsigned n);
1463 /* board init code may ignore whether SPI is configured or not */
1465 spi_register_board_info(struct spi_board_info const *info, unsigned n)
1469 /* If you're hotplugging an adapter with devices (parport, usb, etc)
1470 * use spi_new_device() to describe each device. You can also call
1471 * spi_unregister_device() to start making that device vanish, but
1472 * normally that would be handled by spi_unregister_controller().
1474 * You can also use spi_alloc_device() and spi_add_device() to use a two
1475 * stage registration sequence for each spi_device. This gives the caller
1476 * some more control over the spi_device structure before it is registered,
1477 * but requires that caller to initialize fields that would otherwise
1478 * be defined using the board info.
1480 extern struct spi_device *
1481 spi_alloc_device(struct spi_controller *ctlr);
1484 spi_add_device(struct spi_device *spi);
1486 extern struct spi_device *
1487 spi_new_device(struct spi_controller *, struct spi_board_info *);
1489 extern void spi_unregister_device(struct spi_device *spi);
1491 extern const struct spi_device_id *
1492 spi_get_device_id(const struct spi_device *sdev);
1495 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer)
1497 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers);
1500 /* OF support code */
1501 #if IS_ENABLED(CONFIG_OF)
1503 /* must call put_device() when done with returned spi_device device */
1504 extern struct spi_device *
1505 of_find_spi_device_by_node(struct device_node *node);
1509 static inline struct spi_device *
1510 of_find_spi_device_by_node(struct device_node *node)
1515 #endif /* IS_ENABLED(CONFIG_OF) */
1517 /* Compatibility layer */
1518 #define spi_master spi_controller
1520 #define SPI_MASTER_HALF_DUPLEX SPI_CONTROLLER_HALF_DUPLEX
1521 #define SPI_MASTER_NO_RX SPI_CONTROLLER_NO_RX
1522 #define SPI_MASTER_NO_TX SPI_CONTROLLER_NO_TX
1523 #define SPI_MASTER_MUST_RX SPI_CONTROLLER_MUST_RX
1524 #define SPI_MASTER_MUST_TX SPI_CONTROLLER_MUST_TX
1526 #define spi_master_get_devdata(_ctlr) spi_controller_get_devdata(_ctlr)
1527 #define spi_master_set_devdata(_ctlr, _data) \
1528 spi_controller_set_devdata(_ctlr, _data)
1529 #define spi_master_get(_ctlr) spi_controller_get(_ctlr)
1530 #define spi_master_put(_ctlr) spi_controller_put(_ctlr)
1531 #define spi_master_suspend(_ctlr) spi_controller_suspend(_ctlr)
1532 #define spi_master_resume(_ctlr) spi_controller_resume(_ctlr)
1534 #define spi_register_master(_ctlr) spi_register_controller(_ctlr)
1535 #define devm_spi_register_master(_dev, _ctlr) \
1536 devm_spi_register_controller(_dev, _ctlr)
1537 #define spi_unregister_master(_ctlr) spi_unregister_controller(_ctlr)
1539 #endif /* __LINUX_SPI_H */