1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
7 #include <linux/irqreturn.h>
8 #include <linux/soundwire/sdw.h>
10 #define SDW_SHIM_BASE 0x2C000
11 #define SDW_ALH_BASE 0x2C800
12 #define SDW_SHIM_BASE_ACE 0x38000
13 #define SDW_ALH_BASE_ACE 0x24000
14 #define SDW_LINK_BASE 0x30000
15 #define SDW_LINK_SIZE 0x10000
17 /* Intel SHIM Registers Definition */
19 #define SDW_SHIM_LCAP 0x0
20 #define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0)
23 #define SDW_SHIM_LCTL 0x4
25 #define SDW_SHIM_LCTL_SPA BIT(0)
26 #define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
27 #define SDW_SHIM_LCTL_CPA BIT(8)
28 #define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
31 #define SDW_SHIM_SYNC 0xC
33 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
34 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
35 #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
36 #define SDW_SHIM_SYNC_SYNCCPU BIT(15)
37 #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
38 #define SDW_SHIM_SYNC_CMDSYNC BIT(16)
39 #define SDW_SHIM_SYNC_SYNCGO BIT(24)
41 /* Control stream capabililities and channel mask */
42 #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
43 #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
44 #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
45 #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
46 #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
48 /* PCM Stream capabilities */
49 #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
51 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
52 #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
53 #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
55 /* PCM Stream Channel Map */
56 #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
58 /* PCM Stream Channel Count */
59 #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
61 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
62 #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
63 #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
64 #define SDW_SHIM_PCMSYCM_DIR BIT(15)
67 #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
69 #define SDW_SHIM_IOCTL_MIF BIT(0)
70 #define SDW_SHIM_IOCTL_CO BIT(1)
71 #define SDW_SHIM_IOCTL_COE BIT(2)
72 #define SDW_SHIM_IOCTL_DO BIT(3)
73 #define SDW_SHIM_IOCTL_DOE BIT(4)
74 #define SDW_SHIM_IOCTL_BKE BIT(5)
75 #define SDW_SHIM_IOCTL_WPDD BIT(6)
76 #define SDW_SHIM_IOCTL_CIBD BIT(8)
77 #define SDW_SHIM_IOCTL_DIBD BIT(9)
80 #define SDW_SHIM_WAKEEN 0x190
82 #define SDW_SHIM_WAKEEN_ENABLE BIT(0)
85 #define SDW_SHIM_WAKESTS 0x192
87 #define SDW_SHIM_WAKESTS_STATUS BIT(0)
89 /* AC Timing control */
90 #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
92 #define SDW_SHIM_CTMCTL_DACTQE BIT(0)
93 #define SDW_SHIM_CTMCTL_DODS BIT(1)
94 #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
96 /* Intel ALH Register definitions */
97 #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
98 #define SDW_ALH_NUM_STREAMS 64
100 #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
101 #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
102 #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
105 * struct sdw_intel_stream_params_data: configuration passed during
106 * the @params_stream callback, e.g. for interaction with DSP
109 struct sdw_intel_stream_params_data {
111 struct snd_soc_dai *dai;
112 struct snd_pcm_hw_params *hw_params;
118 * struct sdw_intel_stream_free_data: configuration passed during
119 * the @free_stream callback, e.g. for interaction with DSP
122 struct sdw_intel_stream_free_data {
124 struct snd_soc_dai *dai;
129 * struct sdw_intel_ops: Intel audio driver callback ops
132 struct sdw_intel_ops {
133 int (*params_stream)(struct device *dev,
134 struct sdw_intel_stream_params_data *params_data);
135 int (*free_stream)(struct device *dev,
136 struct sdw_intel_stream_free_data *free_data);
137 int (*trigger)(struct snd_soc_dai *dai, int cmd, int stream);
141 * struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables
142 * @handle: ACPI controller handle
143 * @count: link count found with "sdw-master-count" property
144 * @link_mask: bit-wise mask listing links enabled by BIOS menu
146 * this structure could be expanded to e.g. provide all the _ADR
147 * information in case the link_mask is not sufficient to identify
148 * platform capabilities.
150 struct sdw_intel_acpi_info {
156 struct sdw_intel_link_dev;
158 /* Intel clock-stop/pm_runtime quirk definitions */
161 * Force the clock to remain on during pm_runtime suspend. This might
162 * be needed if Slave devices do not have an alternate clock source or
163 * if the latency requirements are very strict.
165 #define SDW_INTEL_CLK_STOP_NOT_ALLOWED BIT(0)
168 * Stop the bus during pm_runtime suspend. If set, a complete bus
169 * reset and re-enumeration will be performed when the bus
170 * restarts. This mode shall not be used if Slave devices can generate
173 #define SDW_INTEL_CLK_STOP_TEARDOWN BIT(1)
176 * Stop the bus during pm_suspend if Slaves are not wake capable
177 * (e.g. speaker amplifiers). The clock-stop mode is typically
178 * slightly higher power than when the IP is completely powered-off.
180 #define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY BIT(2)
183 * Require a bus reset (and complete re-enumeration) when exiting
184 * clock stop modes. This may be needed if the controller power was
185 * turned off and all context lost. This quirk shall not be used if a
186 * Slave device needs to remain enumerated and keep its context,
187 * e.g. to provide the reasons for the wake, report acoustic events or
188 * pass a history buffer.
190 #define SDW_INTEL_CLK_STOP_BUS_RESET BIT(3)
192 struct sdw_intel_slave_id {
194 struct sdw_slave_id id;
198 * struct sdw_intel_ctx - context allocated by the controller
201 * @mmio_base: mmio base of SoundWire registers, only used to check
202 * hardware capabilities after all power dependencies are settled.
203 * @link_mask: bit-wise mask listing SoundWire links reported by the
205 * @num_slaves: total number of devices exposed across all enabled links
206 * @handle: ACPI parent handle
207 * @ldev: information for each link (controller-specific and kept
209 * @ids: array of slave_id, representing Slaves exposed across all enabled
211 * @link_list: list to handle interrupts across all links
212 * @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
213 * @shim_mask: flags to track initialization of SHIM shared registers
214 * @shim_base: sdw shim base.
215 * @alh_base: sdw alh base.
217 struct sdw_intel_ctx {
219 void __iomem *mmio_base;
223 struct sdw_intel_link_dev **ldev;
224 struct sdw_intel_slave_id *ids;
225 struct list_head link_list;
226 struct mutex shim_lock; /* lock for access to shared SHIM registers */
233 * struct sdw_intel_res - Soundwire Intel global resource structure,
234 * typically populated by the DSP driver
237 * @mmio_base: mmio base of SoundWire registers
238 * @irq: interrupt number
239 * @handle: ACPI parent handle
240 * @parent: parent device
242 * @dev: device implementing hwparams and free callbacks
243 * @link_mask: bit-wise mask listing links selected by the DSP driver
244 * This mask may be a subset of the one reported by the controller since
245 * machine-specific quirks are handled in the DSP driver.
246 * @clock_stop_quirks: mask array of possible behaviors requested by the
247 * DSP driver. The quirks are common for all links for now.
248 * @shim_base: sdw shim base.
249 * @alh_base: sdw alh base.
251 struct sdw_intel_res {
253 void __iomem *mmio_base;
256 struct device *parent;
257 const struct sdw_intel_ops *ops;
260 u32 clock_stop_quirks;
266 * On Intel platforms, the SoundWire IP has dependencies on power
267 * rails shared with the DSP, and the initialization steps are split
268 * in three. First an ACPI scan to check what the firmware describes
269 * in DSDT tables, then an allocation step (with no hardware
270 * configuration but with all the relevant devices created) and last
271 * the actual hardware configuration. The final stage is a global
272 * interrupt enable which is controlled by the DSP driver. Splitting
273 * these phases helps simplify the boot flow and make early decisions
274 * on e.g. which machine driver to select (I2S mode, HDaudio or
277 int sdw_intel_acpi_scan(acpi_handle *parent_handle,
278 struct sdw_intel_acpi_info *info);
280 void sdw_intel_process_wakeen_event(struct sdw_intel_ctx *ctx);
282 struct sdw_intel_ctx *
283 sdw_intel_probe(struct sdw_intel_res *res);
285 int sdw_intel_startup(struct sdw_intel_ctx *ctx);
287 void sdw_intel_exit(struct sdw_intel_ctx *ctx);
289 void sdw_intel_enable_irq(void __iomem *mmio_base, bool enable);
291 irqreturn_t sdw_intel_thread(int irq, void *dev_id);
293 #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1)