1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /* QLogic qed NIC Driver
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
9 #include <linux/types.h>
10 #include <linux/delay.h>
11 #include <linux/list.h>
12 #include <linux/slab.h>
13 #include <linux/qed/qed_if.h>
14 #include <linux/qed/qed_ll2_if.h>
15 #include <linux/qed/rdma_common.h>
17 #define QED_RDMA_MAX_CNQ_SIZE (0xFFFF)
21 enum qed_roce_qp_state {
22 QED_ROCE_QP_STATE_RESET,
23 QED_ROCE_QP_STATE_INIT,
24 QED_ROCE_QP_STATE_RTR,
25 QED_ROCE_QP_STATE_RTS,
26 QED_ROCE_QP_STATE_SQD,
27 QED_ROCE_QP_STATE_ERR,
31 enum qed_rdma_qp_type {
33 QED_RDMA_QP_TYPE_XRC_INI,
34 QED_RDMA_QP_TYPE_XRC_TGT,
35 QED_RDMA_QP_TYPE_INVAL = 0xffff,
38 enum qed_rdma_tid_type {
39 QED_RDMA_TID_REGISTERED_MR,
44 struct qed_rdma_events {
46 void (*affiliated_event)(void *context, u8 fw_event_code,
48 void (*unaffiliated_event)(void *context, u8 event_code);
51 struct qed_rdma_device {
66 u8 max_qp_resp_rd_atomic_resc;
67 u8 max_qp_req_rd_atomic_resc;
68 u64 max_dev_resp_rd_atomic_resc;
76 u32 max_mr_mw_fmr_pbl;
77 u64 max_mr_mw_fmr_size;
85 /* Abilty to support RNR-NAK generation */
87 #define QED_RDMA_DEV_CAP_RNR_NAK_MASK 0x1
88 #define QED_RDMA_DEV_CAP_RNR_NAK_SHIFT 0
89 /* Abilty to support shutdown port */
90 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_MASK 0x1
91 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_SHIFT 1
92 /* Abilty to support port active event */
93 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_MASK 0x1
94 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_SHIFT 2
95 /* Abilty to support port change event */
96 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_MASK 0x1
97 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_SHIFT 3
98 /* Abilty to support system image GUID */
99 #define QED_RDMA_DEV_CAP_SYS_IMAGE_MASK 0x1
100 #define QED_RDMA_DEV_CAP_SYS_IMAGE_SHIFT 4
101 /* Abilty to support bad P_Key counter support */
102 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_MASK 0x1
103 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_SHIFT 5
104 /* Abilty to support atomic operations */
105 #define QED_RDMA_DEV_CAP_ATOMIC_OP_MASK 0x1
106 #define QED_RDMA_DEV_CAP_ATOMIC_OP_SHIFT 6
107 #define QED_RDMA_DEV_CAP_RESIZE_CQ_MASK 0x1
108 #define QED_RDMA_DEV_CAP_RESIZE_CQ_SHIFT 7
109 /* Abilty to support modifying the maximum number of
110 * outstanding work requests per QP
112 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_MASK 0x1
113 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_SHIFT 8
114 /* Abilty to support automatic path migration */
115 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_MASK 0x1
116 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_SHIFT 9
117 /* Abilty to support the base memory management extensions */
118 #define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_MASK 0x1
119 #define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_SHIFT 10
120 #define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_MASK 0x1
121 #define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_SHIFT 11
122 /* Abilty to support multipile page sizes per memory region */
123 #define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_MASK 0x1
124 #define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_SHIFT 12
125 /* Abilty to support block list physical buffer list */
126 #define QED_RDMA_DEV_CAP_BLOCK_MODE_MASK 0x1
127 #define QED_RDMA_DEV_CAP_BLOCK_MODE_SHIFT 13
128 /* Abilty to support zero based virtual addresses */
129 #define QED_RDMA_DEV_CAP_ZBVA_MASK 0x1
130 #define QED_RDMA_DEV_CAP_ZBVA_SHIFT 14
131 /* Abilty to support local invalidate fencing */
132 #define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_MASK 0x1
133 #define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_SHIFT 15
134 /* Abilty to support Loopback on QP */
135 #define QED_RDMA_DEV_CAP_LB_INDICATOR_MASK 0x1
136 #define QED_RDMA_DEV_CAP_LB_INDICATOR_SHIFT 16
140 u32 bad_pkey_counter;
141 struct qed_rdma_events events;
144 enum qed_port_state {
149 enum qed_roce_capability {
150 QED_ROCE_V1 = 1 << 0,
151 QED_ROCE_V2 = 1 << 1,
154 struct qed_rdma_port {
155 enum qed_port_state port_state;
158 u8 source_gid_table_len;
159 void *source_gid_table_ptr;
161 void *pkey_table_ptr;
162 u32 pkey_bad_counter;
163 enum qed_roce_capability capability;
166 struct qed_rdma_cnq_params {
171 /* The CQ Mode affects the CQ doorbell transaction size.
172 * 64/32 bit machines should configure to 32/16 bits respectively.
174 enum qed_rdma_cq_mode {
175 QED_RDMA_CQ_MODE_16_BITS,
176 QED_RDMA_CQ_MODE_32_BITS,
179 struct qed_roce_dcqcn_params {
180 u8 notification_point;
183 /* fields for notification point */
184 u32 cnp_send_timeout;
186 /* fields for reaction point */
193 u32 dcqcn_timeout_us;
196 struct qed_rdma_start_in_params {
197 struct qed_rdma_events *events;
198 struct qed_rdma_cnq_params cnq_pbl_list[128];
200 enum qed_rdma_cq_mode cq_mode;
201 struct qed_roce_dcqcn_params dcqcn_params;
203 u8 mac_addr[ETH_ALEN];
207 struct qed_rdma_add_user_out_params {
209 void __iomem *dpi_addr;
230 struct qed_rdma_register_tid_in_params {
232 enum qed_rdma_tid_type tid_type;
243 u8 pbl_page_size_log;
254 struct qed_rdma_create_cq_in_params {
262 u8 pbl_page_size_log;
267 struct qed_rdma_create_srq_in_params {
274 /* XRC related only */
275 bool reserved_key_en;
281 struct qed_rdma_destroy_cq_in_params {
285 struct qed_rdma_destroy_cq_out_params {
289 struct qed_rdma_create_qp_in_params {
292 u32 qp_handle_async_lo;
293 u32 qp_handle_async_hi;
296 bool fmr_and_reserved_lkey;
309 enum qed_rdma_qp_type qp_type;
311 #define QED_ROCE_EDPM_MODE_MASK 0x1
312 #define QED_ROCE_EDPM_MODE_SHIFT 0
315 struct qed_rdma_create_qp_out_params {
319 dma_addr_t rq_pbl_phys;
321 dma_addr_t sq_pbl_phys;
324 struct qed_rdma_modify_qp_in_params {
326 #define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_MASK 0x1
327 #define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_SHIFT 0
328 #define QED_ROCE_MODIFY_QP_VALID_PKEY_MASK 0x1
329 #define QED_ROCE_MODIFY_QP_VALID_PKEY_SHIFT 1
330 #define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_MASK 0x1
331 #define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_SHIFT 2
332 #define QED_ROCE_MODIFY_QP_VALID_DEST_QP_MASK 0x1
333 #define QED_ROCE_MODIFY_QP_VALID_DEST_QP_SHIFT 3
334 #define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_MASK 0x1
335 #define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_SHIFT 4
336 #define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_MASK 0x1
337 #define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_SHIFT 5
338 #define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_MASK 0x1
339 #define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_SHIFT 6
340 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_MASK 0x1
341 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_SHIFT 7
342 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_MASK 0x1
343 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_SHIFT 8
344 #define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_MASK 0x1
345 #define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_SHIFT 9
346 #define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_MASK 0x1
347 #define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_SHIFT 10
348 #define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_MASK 0x1
349 #define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_SHIFT 11
350 #define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_MASK 0x1
351 #define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_SHIFT 12
352 #define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_MASK 0x1
353 #define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_SHIFT 13
354 #define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_MASK 0x1
355 #define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_SHIFT 14
357 enum qed_roce_qp_state new_state;
359 bool incoming_rdma_read_en;
360 bool incoming_rdma_write_en;
361 bool incoming_atomic_en;
362 bool e2e_flow_control_en;
366 u8 traffic_class_tos;
377 u8 max_rd_atomic_resp;
378 u8 max_rd_atomic_req;
382 u8 min_rnr_nak_timer;
384 u8 remote_mac_addr[6];
385 u8 local_mac_addr[6];
387 enum roce_mode roce_mode;
390 struct qed_rdma_query_qp_out_params {
391 enum qed_roce_qp_state state;
397 bool incoming_rdma_read_en;
398 bool incoming_rdma_write_en;
399 bool incoming_atomic_en;
400 bool e2e_flow_control_en;
405 u8 traffic_class_tos;
409 u8 min_rnr_nak_timer;
412 u8 max_dest_rd_atomic;
416 struct qed_rdma_create_srq_out_params {
420 struct qed_rdma_destroy_srq_in_params {
425 struct qed_rdma_modify_srq_in_params {
431 struct qed_rdma_stats_out_params {
438 struct qed_rdma_counters_out_params {
451 #define QED_ROCE_TX_HEAD_FAILURE (1)
452 #define QED_ROCE_TX_FRAG_FAILURE (2)
454 enum qed_iwarp_event_type {
455 QED_IWARP_EVENT_MPA_REQUEST, /* Passive side request received */
456 QED_IWARP_EVENT_PASSIVE_COMPLETE, /* ack on mpa response */
457 QED_IWARP_EVENT_ACTIVE_COMPLETE, /* Active side reply received */
458 QED_IWARP_EVENT_DISCONNECT,
459 QED_IWARP_EVENT_CLOSE,
460 QED_IWARP_EVENT_IRQ_FULL,
461 QED_IWARP_EVENT_RQ_EMPTY,
462 QED_IWARP_EVENT_LLP_TIMEOUT,
463 QED_IWARP_EVENT_REMOTE_PROTECTION_ERROR,
464 QED_IWARP_EVENT_CQ_OVERFLOW,
465 QED_IWARP_EVENT_QP_CATASTROPHIC,
466 QED_IWARP_EVENT_ACTIVE_MPA_REPLY,
467 QED_IWARP_EVENT_LOCAL_ACCESS_ERROR,
468 QED_IWARP_EVENT_REMOTE_OPERATION_ERROR,
469 QED_IWARP_EVENT_TERMINATE_RECEIVED,
470 QED_IWARP_EVENT_SRQ_LIMIT,
471 QED_IWARP_EVENT_SRQ_EMPTY,
474 enum qed_tcp_ip_version {
479 struct qed_iwarp_cm_info {
480 enum qed_tcp_ip_version ip_version;
488 u16 private_data_len;
489 const void *private_data;
492 struct qed_iwarp_cm_event_params {
493 enum qed_iwarp_event_type event;
494 const struct qed_iwarp_cm_info *cm_info;
495 void *ep_context; /* To be passed to accept call */
499 typedef int (*iwarp_event_handler) (void *context,
500 struct qed_iwarp_cm_event_params *event);
502 struct qed_iwarp_connect_in {
503 iwarp_event_handler event_cb;
505 struct qed_rdma_qp *qp;
506 struct qed_iwarp_cm_info cm_info;
508 u8 remote_mac_addr[ETH_ALEN];
509 u8 local_mac_addr[ETH_ALEN];
512 struct qed_iwarp_connect_out {
516 struct qed_iwarp_listen_in {
517 iwarp_event_handler event_cb;
518 void *cb_context; /* passed to event_cb */
520 enum qed_tcp_ip_version ip_version;
526 struct qed_iwarp_listen_out {
530 struct qed_iwarp_accept_in {
533 struct qed_rdma_qp *qp;
534 const void *private_data;
535 u16 private_data_len;
540 struct qed_iwarp_reject_in {
543 const void *private_data;
544 u16 private_data_len;
547 struct qed_iwarp_send_rtr_in {
551 struct qed_roce_ll2_header {
557 struct qed_roce_ll2_buffer {
562 struct qed_roce_ll2_packet {
563 struct qed_roce_ll2_header header;
565 struct qed_roce_ll2_buffer payload[RDMA_MAX_SGE_PER_SQ_WQE];
567 enum qed_ll2_tx_dest tx_dest;
575 struct qed_dev_rdma_info {
576 struct qed_dev_info common;
577 enum qed_rdma_type rdma_type;
581 struct qed_rdma_ops {
582 const struct qed_common_ops *common;
584 int (*fill_dev_info)(struct qed_dev *cdev,
585 struct qed_dev_rdma_info *info);
586 void *(*rdma_get_rdma_ctx)(struct qed_dev *cdev);
588 int (*rdma_init)(struct qed_dev *dev,
589 struct qed_rdma_start_in_params *iparams);
591 int (*rdma_add_user)(void *rdma_cxt,
592 struct qed_rdma_add_user_out_params *oparams);
594 void (*rdma_remove_user)(void *rdma_cxt, u16 dpi);
595 int (*rdma_stop)(void *rdma_cxt);
596 struct qed_rdma_device* (*rdma_query_device)(void *rdma_cxt);
597 struct qed_rdma_port* (*rdma_query_port)(void *rdma_cxt);
598 int (*rdma_get_start_sb)(struct qed_dev *cdev);
599 int (*rdma_get_min_cnq_msix)(struct qed_dev *cdev);
600 void (*rdma_cnq_prod_update)(void *rdma_cxt, u8 cnq_index, u16 prod);
601 int (*rdma_get_rdma_int)(struct qed_dev *cdev,
602 struct qed_int_info *info);
603 int (*rdma_set_rdma_int)(struct qed_dev *cdev, u16 cnt);
604 int (*rdma_alloc_pd)(void *rdma_cxt, u16 *pd);
605 void (*rdma_dealloc_pd)(void *rdma_cxt, u16 pd);
606 int (*rdma_alloc_xrcd)(void *rdma_cxt, u16 *xrcd);
607 void (*rdma_dealloc_xrcd)(void *rdma_cxt, u16 xrcd);
608 int (*rdma_create_cq)(void *rdma_cxt,
609 struct qed_rdma_create_cq_in_params *params,
611 int (*rdma_destroy_cq)(void *rdma_cxt,
612 struct qed_rdma_destroy_cq_in_params *iparams,
613 struct qed_rdma_destroy_cq_out_params *oparams);
615 (*rdma_create_qp)(void *rdma_cxt,
616 struct qed_rdma_create_qp_in_params *iparams,
617 struct qed_rdma_create_qp_out_params *oparams);
619 int (*rdma_modify_qp)(void *roce_cxt, struct qed_rdma_qp *qp,
620 struct qed_rdma_modify_qp_in_params *iparams);
622 int (*rdma_query_qp)(void *rdma_cxt, struct qed_rdma_qp *qp,
623 struct qed_rdma_query_qp_out_params *oparams);
624 int (*rdma_destroy_qp)(void *rdma_cxt, struct qed_rdma_qp *qp);
627 (*rdma_register_tid)(void *rdma_cxt,
628 struct qed_rdma_register_tid_in_params *iparams);
630 int (*rdma_deregister_tid)(void *rdma_cxt, u32 itid);
631 int (*rdma_alloc_tid)(void *rdma_cxt, u32 *itid);
632 void (*rdma_free_tid)(void *rdma_cxt, u32 itid);
634 int (*rdma_create_srq)(void *rdma_cxt,
635 struct qed_rdma_create_srq_in_params *iparams,
636 struct qed_rdma_create_srq_out_params *oparams);
637 int (*rdma_destroy_srq)(void *rdma_cxt,
638 struct qed_rdma_destroy_srq_in_params *iparams);
639 int (*rdma_modify_srq)(void *rdma_cxt,
640 struct qed_rdma_modify_srq_in_params *iparams);
642 int (*ll2_acquire_connection)(void *rdma_cxt,
643 struct qed_ll2_acquire_data *data);
645 int (*ll2_establish_connection)(void *rdma_cxt, u8 connection_handle);
646 int (*ll2_terminate_connection)(void *rdma_cxt, u8 connection_handle);
647 void (*ll2_release_connection)(void *rdma_cxt, u8 connection_handle);
649 int (*ll2_prepare_tx_packet)(void *rdma_cxt,
650 u8 connection_handle,
651 struct qed_ll2_tx_pkt_info *pkt,
654 int (*ll2_set_fragment_of_tx_packet)(void *rdma_cxt,
655 u8 connection_handle,
658 int (*ll2_post_rx_buffer)(void *rdma_cxt, u8 connection_handle,
659 dma_addr_t addr, u16 buf_len, void *cookie,
661 int (*ll2_get_stats)(void *rdma_cxt,
662 u8 connection_handle,
663 struct qed_ll2_stats *p_stats);
664 int (*ll2_set_mac_filter)(struct qed_dev *cdev,
666 const u8 *new_mac_address);
668 int (*iwarp_set_engine_affin)(struct qed_dev *cdev, bool b_reset);
670 int (*iwarp_connect)(void *rdma_cxt,
671 struct qed_iwarp_connect_in *iparams,
672 struct qed_iwarp_connect_out *oparams);
674 int (*iwarp_create_listen)(void *rdma_cxt,
675 struct qed_iwarp_listen_in *iparams,
676 struct qed_iwarp_listen_out *oparams);
678 int (*iwarp_accept)(void *rdma_cxt,
679 struct qed_iwarp_accept_in *iparams);
681 int (*iwarp_reject)(void *rdma_cxt,
682 struct qed_iwarp_reject_in *iparams);
684 int (*iwarp_destroy_listen)(void *rdma_cxt, void *handle);
686 int (*iwarp_send_rtr)(void *rdma_cxt,
687 struct qed_iwarp_send_rtr_in *iparams);
690 const struct qed_rdma_ops *qed_get_rdma_ops(void);