1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /* QLogic qed NIC Driver
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/netdevice.h>
13 #include <linux/pci.h>
14 #include <linux/skbuff.h>
15 #include <asm/byteorder.h>
17 #include <linux/compiler.h>
18 #include <linux/kernel.h>
19 #include <linux/list.h>
20 #include <linux/slab.h>
21 #include <linux/qed/common_hsi.h>
22 #include <linux/qed/qed_chain.h>
23 #include <linux/io-64-nonatomic-lo-hi.h>
25 enum dcbx_protocol_type {
29 DCBX_PROTOCOL_ROCE_V2,
31 DCBX_MAX_PROTOCOL_TYPE
34 #define QED_ROCE_PROTOCOL_INDEX (3)
36 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
37 #define QED_LLDP_PORT_ID_STAT_LEN 4
38 #define QED_DCBX_MAX_APP_PROTOCOL 32
39 #define QED_MAX_PFC_PRIORITIES 8
40 #define QED_DCBX_DSCP_SIZE 64
42 struct qed_dcbx_lldp_remote {
43 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
44 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
51 struct qed_dcbx_lldp_local {
52 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
53 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
56 struct qed_dcbx_app_prio {
64 struct qed_dbcx_pfc_params {
67 u8 prio[QED_MAX_PFC_PRIORITIES];
71 enum qed_dcbx_sf_ieee_type {
72 QED_DCBX_SF_IEEE_ETHTYPE,
73 QED_DCBX_SF_IEEE_TCP_PORT,
74 QED_DCBX_SF_IEEE_UDP_PORT,
75 QED_DCBX_SF_IEEE_TCP_UDP_PORT
78 struct qed_app_entry {
80 enum qed_dcbx_sf_ieee_type sf_ieee;
84 enum dcbx_protocol_type proto_type;
87 struct qed_dcbx_params {
88 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
97 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
98 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
99 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
100 struct qed_dbcx_pfc_params pfc;
104 struct qed_dcbx_admin_params {
105 struct qed_dcbx_params params;
109 struct qed_dcbx_remote_params {
110 struct qed_dcbx_params params;
114 struct qed_dcbx_operational_params {
115 struct qed_dcbx_app_prio app_prio;
116 struct qed_dcbx_params params;
125 struct qed_dcbx_get {
126 struct qed_dcbx_operational_params operational;
127 struct qed_dcbx_lldp_remote lldp_remote;
128 struct qed_dcbx_lldp_local lldp_local;
129 struct qed_dcbx_remote_params remote;
130 struct qed_dcbx_admin_params local;
133 enum qed_nvm_images {
134 QED_NVM_IMAGE_ISCSI_CFG,
135 QED_NVM_IMAGE_FCOE_CFG,
137 QED_NVM_IMAGE_NVM_CFG1,
138 QED_NVM_IMAGE_DEFAULT_CFG,
139 QED_NVM_IMAGE_NVM_META,
142 struct qed_link_eee_params {
144 #define QED_EEE_1G_ADV BIT(0)
145 #define QED_EEE_10G_ADV BIT(1)
147 /* Capabilities are represented using QED_EEE_*_ADV values */
160 struct qed_mfw_tlv_eth {
162 bool lso_maxoff_size_set;
164 bool lso_minseg_size_set;
168 bool tx_descr_size_set;
170 bool rx_descr_size_set;
174 bool tcp4_offloads_set;
176 bool tcp6_offloads_set;
178 bool tx_descr_qdepth_set;
180 bool rx_descr_qdepth_set;
182 #define QED_MFW_TLV_IOV_OFFLOAD_NONE (0)
183 #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1)
184 #define QED_MFW_TLV_IOV_OFFLOAD_VEB (2)
185 #define QED_MFW_TLV_IOV_OFFLOAD_VEPA (3)
186 bool iov_offload_set;
192 bool num_txqs_full_set;
194 bool num_rxqs_full_set;
197 #define QED_MFW_TLV_TIME_SIZE 14
198 struct qed_mfw_tlv_time {
208 struct qed_mfw_tlv_fcoe {
210 bool scsi_timeout_set;
224 bool num_npiv_ids_set;
226 bool switch_name_set;
228 bool switch_portnum_set;
230 bool switch_portid_set;
232 bool vendor_name_set;
234 bool switch_model_set;
235 u8 switch_fw_version[8];
236 bool switch_fw_version_set;
242 #define QED_MFW_TLV_PORT_STATE_OFFLINE (0)
243 #define QED_MFW_TLV_PORT_STATE_LOOP (1)
244 #define QED_MFW_TLV_PORT_STATE_P2P (2)
245 #define QED_MFW_TLV_PORT_STATE_FABRIC (3)
247 u16 fip_tx_descr_size;
248 bool fip_tx_descr_size_set;
249 u16 fip_rx_descr_size;
250 bool fip_rx_descr_size_set;
252 bool link_failures_set;
253 u8 fcoe_boot_progress;
254 bool fcoe_boot_progress_set;
260 bool fcoe_txq_depth_set;
262 bool fcoe_rxq_depth_set;
264 bool fcoe_rx_frames_set;
266 bool fcoe_rx_bytes_set;
268 bool fcoe_tx_frames_set;
270 bool fcoe_tx_bytes_set;
273 u32 crc_err_src_fcid[5];
274 bool crc_err_src_fcid_set[5];
275 struct qed_mfw_tlv_time crc_err[5];
281 bool primtive_err_set;
283 bool disparity_err_set;
284 u16 code_violation_err;
285 bool code_violation_err_set;
287 bool flogi_param_set[4];
288 struct qed_mfw_tlv_time flogi_tstamp;
289 u32 flogi_acc_param[4];
290 bool flogi_acc_param_set[4];
291 struct qed_mfw_tlv_time flogi_acc_tstamp;
294 struct qed_mfw_tlv_time flogi_rjt_tstamp;
307 u32 plogi_dst_fcid[5];
308 bool plogi_dst_fcid_set[5];
309 struct qed_mfw_tlv_time plogi_tstamp[5];
310 u32 plogi_acc_src_fcid[5];
311 bool plogi_acc_src_fcid_set[5];
312 struct qed_mfw_tlv_time plogi_acc_tstamp[5];
319 u32 plogo_src_fcid[5];
320 bool plogo_src_fcid_set[5];
321 struct qed_mfw_tlv_time plogo_tstamp[5];
333 bool rx_abts_acc_set;
335 bool rx_abts_rjt_set;
336 u32 abts_dst_fcid[5];
337 bool abts_dst_fcid_set[5];
338 struct qed_mfw_tlv_time abts_tstamp[5];
341 u32 rx_rscn_nport[4];
342 bool rx_rscn_nport_set[4];
346 bool abort_task_sets_set;
370 bool scsi_cond_met_set;
375 u8 scsi_inter_cond_met;
376 bool scsi_inter_cond_met_set;
377 u8 scsi_rsv_conflicts;
378 bool scsi_rsv_conflicts_set;
380 bool scsi_tsk_full_set;
382 bool scsi_aca_active_set;
384 bool scsi_tsk_abort_set;
386 bool scsi_rx_chk_set[5];
387 struct qed_mfw_tlv_time scsi_chk_tstamp[5];
390 struct qed_mfw_tlv_iscsi {
392 bool target_llmnr_set;
394 bool header_digest_set;
396 bool data_digest_set;
398 #define QED_MFW_TLV_AUTH_METHOD_NONE (1)
399 #define QED_MFW_TLV_AUTH_METHOD_CHAP (2)
400 #define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3)
401 bool auth_method_set;
402 u16 boot_taget_portal;
403 bool boot_taget_portal_set;
407 bool tx_desc_size_set;
409 bool rx_desc_size_set;
411 bool boot_progress_set;
413 bool tx_desc_qdepth_set;
415 bool rx_desc_qdepth_set;
426 enum qed_db_rec_width {
431 enum qed_db_rec_space {
436 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
437 (void __iomem *)(reg_addr))
439 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
441 #define DIRECT_REG_WR64(reg_addr, val) writeq((u64)val, \
442 (void __iomem *)(reg_addr))
444 #define QED_COALESCE_MAX 0x1FF
445 #define QED_DEFAULT_RX_USECS 12
446 #define QED_DEFAULT_TX_USECS 48
451 struct qed_eth_pf_params {
452 /* The following parameters are used during HW-init
453 * and these parameters need to be passed as arguments
454 * to update_pf_params routine invoked before slowpath start
458 /* per-VF number of CIDs */
460 #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32)
462 /* To enable arfs, previous to HW-init a positive number needs to be
463 * set [as filters require allocated searcher ILT memory].
464 * This will set the maximal number of configured steering-filters.
466 u32 num_arfs_filters;
469 struct qed_fcoe_pf_params {
470 /* The following parameters are used during protocol-init */
471 u64 glbl_q_params_addr;
472 u64 bdq_pbl_base_addr[2];
474 /* The following parameters are used during HW-init
475 * and these parameters need to be passed as arguments
476 * to update_pf_params routine invoked before slowpath start
481 /* The following parameters are used during protocol-init */
482 u16 sq_num_pbl_pages;
485 u16 cmdq_num_entries;
486 u16 rq_buffer_log_size;
489 u16 bdq_xoff_threshold[2];
490 u16 bdq_xon_threshold[2];
492 u8 num_cqs; /* num of global CQs */
498 u8 bdq_pbl_num_entries[2];
501 /* Most of the parameters below are described in the FW iSCSI / TCP HSI */
502 struct qed_iscsi_pf_params {
503 u64 glbl_q_params_addr;
504 u64 bdq_pbl_base_addr[3];
506 u16 cmdq_num_entries;
510 /* The following parameters are used during HW-init
511 * and these parameters need to be passed as arguments
512 * to update_pf_params routine invoked before slowpath start
517 /* The following parameters are used during protocol-init */
518 u16 half_way_close_timeout;
519 u16 bdq_xoff_threshold[3];
520 u16 bdq_xon_threshold[3];
521 u16 cmdq_xoff_threshold;
522 u16 cmdq_xon_threshold;
525 u8 num_sq_pages_in_ring;
526 u8 num_r2tq_pages_in_ring;
527 u8 num_uhq_pages_in_ring;
539 u8 soc_num_of_blocks_log;
540 u8 bdq_pbl_num_entries[3];
543 struct qed_rdma_pf_params {
544 /* Supplied to QED during resource allocation (may affect the ILT and
547 u32 min_dpis; /* number of requested DPIs */
548 u32 num_qps; /* number of requested Queue Pairs */
549 u32 num_srqs; /* number of requested SRQ */
550 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
551 u8 gl_pi; /* protocol index */
553 /* Will allocate rate limiters to be used with QPs */
557 struct qed_pf_params {
558 struct qed_eth_pf_params eth_pf_params;
559 struct qed_fcoe_pf_params fcoe_pf_params;
560 struct qed_iscsi_pf_params iscsi_pf_params;
561 struct qed_rdma_pf_params rdma_pf_params;
572 struct status_block_e4 *sb_virt;
574 u32 sb_ack; /* Last given ack */
576 void __iomem *igu_addr;
578 #define QED_SB_INFO_INIT 0x1
579 #define QED_SB_INFO_SETUP 0x2
581 struct qed_dev *cdev;
584 enum qed_hw_err_type {
586 QED_HW_ERR_MFW_RESP_FAIL,
588 QED_HW_ERR_DMAE_FAIL,
589 QED_HW_ERR_RAMROD_FAIL,
590 QED_HW_ERR_FW_ASSERT,
600 struct qed_dev_info {
601 unsigned long pci_mem_start;
602 unsigned long pci_mem_end;
603 unsigned int pci_irq;
616 #define QED_MFW_VERSION_0_MASK 0x000000FF
617 #define QED_MFW_VERSION_0_OFFSET 0
618 #define QED_MFW_VERSION_1_MASK 0x0000FF00
619 #define QED_MFW_VERSION_1_OFFSET 8
620 #define QED_MFW_VERSION_2_MASK 0x00FF0000
621 #define QED_MFW_VERSION_2_OFFSET 16
622 #define QED_MFW_VERSION_3_MASK 0xFF000000
623 #define QED_MFW_VERSION_3_OFFSET 24
626 bool b_inter_pf_switch;
636 #define QED_MBI_VERSION_0_MASK 0x000000FF
637 #define QED_MBI_VERSION_0_OFFSET 0
638 #define QED_MBI_VERSION_1_MASK 0x0000FF00
639 #define QED_MBI_VERSION_1_OFFSET 8
640 #define QED_MBI_VERSION_2_MASK 0x00FF0000
641 #define QED_MBI_VERSION_2_OFFSET 16
643 enum qed_dev_type dev_type;
645 /* Output parameters for qede */
654 QED_SB_TYPE_L2_QUEUE,
666 QED_FEC_MODE_NONE = BIT(0),
667 QED_FEC_MODE_FIRECODE = BIT(1),
668 QED_FEC_MODE_RS = BIT(2),
669 QED_FEC_MODE_AUTO = BIT(3),
670 QED_FEC_MODE_UNSUPPORTED = BIT(4),
673 struct qed_link_params {
677 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
678 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
679 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
680 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
681 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
682 #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5)
683 #define QED_LINK_OVERRIDE_FEC_CONFIG BIT(6)
686 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv_speeds);
690 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
691 #define QED_LINK_PAUSE_RX_ENABLE BIT(1)
692 #define QED_LINK_PAUSE_TX_ENABLE BIT(2)
695 #define QED_LINK_LOOPBACK_NONE BIT(0)
696 #define QED_LINK_LOOPBACK_INT_PHY BIT(1)
697 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
698 #define QED_LINK_LOOPBACK_EXT BIT(3)
699 #define QED_LINK_LOOPBACK_MAC BIT(4)
700 #define QED_LINK_LOOPBACK_CNIG_AH_ONLY_0123 BIT(5)
701 #define QED_LINK_LOOPBACK_CNIG_AH_ONLY_2301 BIT(6)
702 #define QED_LINK_LOOPBACK_PCS_AH_ONLY BIT(7)
703 #define QED_LINK_LOOPBACK_REVERSE_MAC_AH_ONLY BIT(8)
704 #define QED_LINK_LOOPBACK_INT_PHY_FEA_AH_ONLY BIT(9)
706 struct qed_link_eee_params eee;
710 struct qed_link_output {
713 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported_caps);
714 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised_caps);
715 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp_caps);
717 u32 speed; /* In Mb/s */
718 u8 duplex; /* In DUPLEX defs */
719 u8 port; /* In PORT defs */
723 /* EEE - capability & param */
727 struct qed_link_eee_params eee;
733 struct qed_probe_params {
734 enum qed_protocol protocol;
741 #define QED_DRV_VER_STR_SIZE 12
742 struct qed_slowpath_params {
748 u8 name[QED_DRV_VER_STR_SIZE];
751 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
753 struct qed_int_info {
754 struct msix_entry *msix;
757 /* This should be updated by the protocol driver */
761 struct qed_generic_tlvs {
762 #define QED_TLV_IP_CSUM BIT(0)
763 #define QED_TLV_LSO BIT(1)
765 #define QED_TLV_MAC_COUNT 3
766 u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN];
769 #define QED_I2C_DEV_ADDR_A0 0xA0
770 #define QED_I2C_DEV_ADDR_A2 0xA2
772 #define QED_NVM_SIGNATURE 0x12435687
774 enum qed_nvm_flash_cmd {
775 QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
776 QED_NVM_FLASH_CMD_FILE_START = 0x3,
777 QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
778 QED_NVM_FLASH_CMD_NVM_CFG_ID = 0x5,
779 QED_NVM_FLASH_CMD_NVM_MAX,
782 struct qed_common_cb_ops {
783 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
784 void (*link_update)(void *dev, struct qed_link_output *link);
785 void (*schedule_recovery_handler)(void *dev);
786 void (*schedule_hw_err_handler)(void *dev,
787 enum qed_hw_err_type err_type);
788 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
789 void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data);
790 void (*get_protocol_tlv_data)(void *dev, void *data);
791 void (*bw_update)(void *dev);
794 struct qed_selftest_ops {
796 * @brief selftest_interrupt - Perform interrupt test
800 * @return 0 on success, error otherwise.
802 int (*selftest_interrupt)(struct qed_dev *cdev);
805 * @brief selftest_memory - Perform memory test
809 * @return 0 on success, error otherwise.
811 int (*selftest_memory)(struct qed_dev *cdev);
814 * @brief selftest_register - Perform register test
818 * @return 0 on success, error otherwise.
820 int (*selftest_register)(struct qed_dev *cdev);
823 * @brief selftest_clock - Perform clock test
827 * @return 0 on success, error otherwise.
829 int (*selftest_clock)(struct qed_dev *cdev);
832 * @brief selftest_nvram - Perform nvram test
836 * @return 0 on success, error otherwise.
838 int (*selftest_nvram) (struct qed_dev *cdev);
841 struct qed_common_ops {
842 struct qed_selftest_ops *selftest;
844 struct qed_dev* (*probe)(struct pci_dev *dev,
845 struct qed_probe_params *params);
847 void (*remove)(struct qed_dev *cdev);
849 int (*set_power_state)(struct qed_dev *cdev,
852 void (*set_name) (struct qed_dev *cdev, char name[]);
854 /* Client drivers need to make this call before slowpath_start.
855 * PF params required for the call before slowpath_start is
856 * documented within the qed_pf_params structure definition.
858 void (*update_pf_params)(struct qed_dev *cdev,
859 struct qed_pf_params *params);
860 int (*slowpath_start)(struct qed_dev *cdev,
861 struct qed_slowpath_params *params);
863 int (*slowpath_stop)(struct qed_dev *cdev);
865 /* Requests to use `cnt' interrupts for fastpath.
866 * upon success, returns number of interrupts allocated for fastpath.
868 int (*set_fp_int)(struct qed_dev *cdev,
871 /* Fills `info' with pointers required for utilizing interrupts */
872 int (*get_fp_int)(struct qed_dev *cdev,
873 struct qed_int_info *info);
875 u32 (*sb_init)(struct qed_dev *cdev,
876 struct qed_sb_info *sb_info,
878 dma_addr_t sb_phy_addr,
880 enum qed_sb_type type);
882 u32 (*sb_release)(struct qed_dev *cdev,
883 struct qed_sb_info *sb_info,
885 enum qed_sb_type type);
887 void (*simd_handler_config)(struct qed_dev *cdev,
890 void (*handler)(void *));
892 void (*simd_handler_clean)(struct qed_dev *cdev,
894 int (*dbg_grc)(struct qed_dev *cdev,
895 void *buffer, u32 *num_dumped_bytes);
897 int (*dbg_grc_size)(struct qed_dev *cdev);
899 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);
901 int (*dbg_all_data_size) (struct qed_dev *cdev);
904 * @brief can_link_change - can the instance change the link or not
908 * @return true if link-change is allowed, false otherwise.
910 bool (*can_link_change)(struct qed_dev *cdev);
913 * @brief set_link - set links according to params
916 * @param params - values used to override the default link configuration
918 * @return 0 on success, error otherwise.
920 int (*set_link)(struct qed_dev *cdev,
921 struct qed_link_params *params);
924 * @brief get_link - returns the current link state.
927 * @param if_link - structure to be filled with current link configuration.
929 void (*get_link)(struct qed_dev *cdev,
930 struct qed_link_output *if_link);
933 * @brief - drains chip in case Tx completions fail to arrive due to pause.
937 int (*drain)(struct qed_dev *cdev);
940 * @brief update_msglvl - update module debug level
946 void (*update_msglvl)(struct qed_dev *cdev,
950 int (*chain_alloc)(struct qed_dev *cdev,
951 struct qed_chain *chain,
952 struct qed_chain_init_params *params);
954 void (*chain_free)(struct qed_dev *cdev,
955 struct qed_chain *p_chain);
958 * @brief nvm_flash - Flash nvm data.
961 * @param name - file containing the data
963 * @return 0 on success, error otherwise.
965 int (*nvm_flash)(struct qed_dev *cdev, const char *name);
968 * @brief nvm_get_image - reads an entire image from nvram
971 * @param type - type of the request nvram image
972 * @param buf - preallocated buffer to fill with the image
973 * @param len - length of the allocated buffer
975 * @return 0 on success, error otherwise
977 int (*nvm_get_image)(struct qed_dev *cdev,
978 enum qed_nvm_images type, u8 *buf, u16 len);
981 * @brief set_coalesce - Configure Rx coalesce value in usec
984 * @param rx_coal - Rx coalesce value in usec
985 * @param tx_coal - Tx coalesce value in usec
986 * @param qid - Queue index
987 * @param sb_id - Status Block Id
989 * @return 0 on success, error otherwise.
991 int (*set_coalesce)(struct qed_dev *cdev,
992 u16 rx_coal, u16 tx_coal, void *handle);
995 * @brief set_led - Configure LED mode
998 * @param mode - LED mode
1000 * @return 0 on success, error otherwise.
1002 int (*set_led)(struct qed_dev *cdev,
1003 enum qed_led_mode mode);
1006 * @brief attn_clr_enable - Prevent attentions from being reasserted
1011 void (*attn_clr_enable)(struct qed_dev *cdev, bool clr_enable);
1014 * @brief db_recovery_add - add doorbell information to the doorbell
1015 * recovery mechanism.
1018 * @param db_addr - doorbell address
1019 * @param db_data - address of where db_data is stored
1020 * @param db_is_32b - doorbell is 32b pr 64b
1021 * @param db_is_user - doorbell recovery addresses are user or kernel space
1023 int (*db_recovery_add)(struct qed_dev *cdev,
1024 void __iomem *db_addr,
1026 enum qed_db_rec_width db_width,
1027 enum qed_db_rec_space db_space);
1030 * @brief db_recovery_del - remove doorbell information from the doorbell
1031 * recovery mechanism. db_data serves as key (db_addr is not unique).
1034 * @param db_addr - doorbell address
1035 * @param db_data - address where db_data is stored. Serves as key for the
1038 int (*db_recovery_del)(struct qed_dev *cdev,
1039 void __iomem *db_addr, void *db_data);
1042 * @brief recovery_process - Trigger a recovery process
1046 * @return 0 on success, error otherwise.
1048 int (*recovery_process)(struct qed_dev *cdev);
1051 * @brief recovery_prolog - Execute the prolog operations of a recovery process
1055 * @return 0 on success, error otherwise.
1057 int (*recovery_prolog)(struct qed_dev *cdev);
1060 * @brief update_drv_state - API to inform the change in the driver state.
1066 int (*update_drv_state)(struct qed_dev *cdev, bool active);
1069 * @brief update_mac - API to inform the change in the mac address
1075 int (*update_mac)(struct qed_dev *cdev, u8 *mac);
1078 * @brief update_mtu - API to inform the change in the mtu
1084 int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
1087 * @brief update_wol - update of changes in the WoL configuration
1090 * @param enabled - true iff WoL should be enabled.
1092 int (*update_wol) (struct qed_dev *cdev, bool enabled);
1095 * @brief read_module_eeprom
1098 * @param buf - buffer
1099 * @param dev_addr - PHY device memory region
1100 * @param offset - offset into eeprom contents to be read
1101 * @param len - buffer length, i.e., max bytes to be read
1103 int (*read_module_eeprom)(struct qed_dev *cdev,
1104 char *buf, u8 dev_addr, u32 offset, u32 len);
1107 * @brief get_affin_hwfn_idx
1111 u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
1114 * @brief read_nvm_cfg - Read NVM config attribute value.
1116 * @param buf - buffer
1117 * @param cmd - NVM CFG command id
1118 * @param entity_id - Entity id
1121 int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
1124 * @brief read_nvm_cfg - Read NVM config attribute value.
1126 * @param cmd - NVM CFG command id
1128 * @return config id length, 0 on error.
1130 int (*read_nvm_cfg_len)(struct qed_dev *cdev, u32 cmd);
1133 * @brief set_grc_config - Configure value for grc config id.
1135 * @param cfg_id - grc config id
1136 * @param val - grc config value
1139 int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val);
1142 #define MASK_FIELD(_name, _value) \
1143 ((_value) &= (_name ## _MASK))
1145 #define FIELD_VALUE(_name, _value) \
1146 ((_value & _name ## _MASK) << _name ## _SHIFT)
1148 #define SET_FIELD(value, name, flag) \
1150 (value) &= ~(name ## _MASK << name ## _SHIFT); \
1151 (value) |= (((u64)flag) << (name ## _SHIFT)); \
1154 #define GET_FIELD(value, name) \
1155 (((value) >> (name ## _SHIFT)) & name ## _MASK)
1157 #define GET_MFW_FIELD(name, field) \
1158 (((name) & (field ## _MASK)) >> (field ## _OFFSET))
1160 #define SET_MFW_FIELD(name, field, value) \
1162 (name) &= ~(field ## _MASK); \
1163 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK));\
1166 #define DB_ADDR_SHIFT(addr) ((addr) << DB_PWM_ADDR_OFFSET_SHIFT)
1168 /* Debug print definitions */
1169 #define DP_ERR(cdev, fmt, ...) \
1171 pr_err("[%s:%d(%s)]" fmt, \
1172 __func__, __LINE__, \
1173 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1177 #define DP_NOTICE(cdev, fmt, ...) \
1179 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
1180 pr_notice("[%s:%d(%s)]" fmt, \
1181 __func__, __LINE__, \
1182 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1188 #define DP_INFO(cdev, fmt, ...) \
1190 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
1191 pr_notice("[%s:%d(%s)]" fmt, \
1192 __func__, __LINE__, \
1193 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1198 #define DP_VERBOSE(cdev, module, fmt, ...) \
1200 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
1201 ((cdev)->dp_module & module))) { \
1202 pr_notice("[%s:%d(%s)]" fmt, \
1203 __func__, __LINE__, \
1204 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1210 QED_LEVEL_VERBOSE = 0x0,
1211 QED_LEVEL_INFO = 0x1,
1212 QED_LEVEL_NOTICE = 0x2,
1213 QED_LEVEL_ERR = 0x3,
1216 #define QED_LOG_LEVEL_SHIFT (30)
1217 #define QED_LOG_VERBOSE_MASK (0x3fffffff)
1218 #define QED_LOG_INFO_MASK (0x40000000)
1219 #define QED_LOG_NOTICE_MASK (0x80000000)
1222 QED_MSG_SPQ = 0x10000,
1223 QED_MSG_STATS = 0x20000,
1224 QED_MSG_DCB = 0x40000,
1225 QED_MSG_IOV = 0x80000,
1226 QED_MSG_SP = 0x100000,
1227 QED_MSG_STORAGE = 0x200000,
1228 QED_MSG_CXT = 0x800000,
1229 QED_MSG_LL2 = 0x1000000,
1230 QED_MSG_ILT = 0x2000000,
1231 QED_MSG_RDMA = 0x4000000,
1232 QED_MSG_DEBUG = 0x8000000,
1233 /* to be added...up to 0x8000000 */
1242 struct qed_eth_stats_common {
1243 u64 no_buff_discards;
1244 u64 packet_too_big_discard;
1252 u64 mftag_filter_discards;
1253 u64 mac_filter_discards;
1254 u64 gft_filter_drop;
1261 u64 tx_err_drop_pkts;
1262 u64 tpa_coalesced_pkts;
1263 u64 tpa_coalesced_events;
1265 u64 tpa_not_coalesced_pkts;
1266 u64 tpa_coalesced_bytes;
1269 u64 rx_64_byte_packets;
1270 u64 rx_65_to_127_byte_packets;
1271 u64 rx_128_to_255_byte_packets;
1272 u64 rx_256_to_511_byte_packets;
1273 u64 rx_512_to_1023_byte_packets;
1274 u64 rx_1024_to_1518_byte_packets;
1276 u64 rx_mac_crtl_frames;
1277 u64 rx_pause_frames;
1279 u64 rx_align_errors;
1280 u64 rx_carrier_errors;
1281 u64 rx_oversize_packets;
1283 u64 rx_undersize_packets;
1285 u64 tx_64_byte_packets;
1286 u64 tx_65_to_127_byte_packets;
1287 u64 tx_128_to_255_byte_packets;
1288 u64 tx_256_to_511_byte_packets;
1289 u64 tx_512_to_1023_byte_packets;
1290 u64 tx_1024_to_1518_byte_packets;
1291 u64 tx_pause_frames;
1296 u64 rx_mac_uc_packets;
1297 u64 rx_mac_mc_packets;
1298 u64 rx_mac_bc_packets;
1299 u64 rx_mac_frames_ok;
1301 u64 tx_mac_uc_packets;
1302 u64 tx_mac_mc_packets;
1303 u64 tx_mac_bc_packets;
1304 u64 tx_mac_ctrl_frames;
1305 u64 link_change_count;
1308 struct qed_eth_stats_bb {
1309 u64 rx_1519_to_1522_byte_packets;
1310 u64 rx_1519_to_2047_byte_packets;
1311 u64 rx_2048_to_4095_byte_packets;
1312 u64 rx_4096_to_9216_byte_packets;
1313 u64 rx_9217_to_16383_byte_packets;
1314 u64 tx_1519_to_2047_byte_packets;
1315 u64 tx_2048_to_4095_byte_packets;
1316 u64 tx_4096_to_9216_byte_packets;
1317 u64 tx_9217_to_16383_byte_packets;
1318 u64 tx_lpi_entry_count;
1319 u64 tx_total_collisions;
1322 struct qed_eth_stats_ah {
1323 u64 rx_1519_to_max_byte_packets;
1324 u64 tx_1519_to_max_byte_packets;
1327 struct qed_eth_stats {
1328 struct qed_eth_stats_common common;
1331 struct qed_eth_stats_bb bb;
1332 struct qed_eth_stats_ah ah;
1336 #define QED_SB_IDX 0x0002
1339 #define TX_PI(tc) (RX_PI + 1 + tc)
1341 struct qed_sb_cnt_info {
1342 /* Original, current, and free SBs for PF */
1347 /* Original, current and free SBS for child VFs */
1353 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
1358 prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
1359 STATUS_BLOCK_E4_PROD_INDEX_MASK;
1360 if (sb_info->sb_ack != prod) {
1361 sb_info->sb_ack = prod;
1371 * @brief This function creates an update command for interrupts that is
1372 * written to the IGU.
1374 * @param sb_info - This is the structure allocated and
1375 * initialized per status block. Assumption is
1376 * that it was initialized using qed_sb_init
1377 * @param int_cmd - Enable/Disable/Nop
1378 * @param upd_flg - whether igu consumer should be
1381 * @return inline void
1383 static inline void qed_sb_ack(struct qed_sb_info *sb_info,
1384 enum igu_int_cmd int_cmd,
1389 igu_ack = ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1390 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1391 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1392 (IGU_SEG_ACCESS_REG <<
1393 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1395 DIRECT_REG_WR(sb_info->igu_addr, igu_ack);
1397 /* Both segments (interrupts & acks) are written to same place address;
1398 * Need to guarantee all commands will be received (in-order) by HW.
1403 static inline void __internal_ram_wr(void *p_hwfn,
1411 for (i = 0; i < size / sizeof(*data); i++)
1412 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
1415 static inline void internal_ram_wr(void __iomem *addr,
1419 __internal_ram_wr(NULL, addr, size, data);
1425 QED_RSS_IPV4_TCP = 0x4,
1426 QED_RSS_IPV6_TCP = 0x8,
1427 QED_RSS_IPV4_UDP = 0x10,
1428 QED_RSS_IPV6_UDP = 0x20,
1431 #define QED_RSS_IND_TABLE_SIZE 128
1432 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */