1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
26 #include <linux/args.h>
27 #include <linux/mod_devicetable.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
40 #include <linux/resource_ext.h>
41 #include <linux/msi_api.h>
42 #include <uapi/linux/pci.h>
44 #include <linux/pci_ids.h>
46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 PCI_STATUS_SIG_SYSTEM_ERROR | \
48 PCI_STATUS_REC_MASTER_ABORT | \
49 PCI_STATUS_REC_TARGET_ABORT | \
50 PCI_STATUS_SIG_TARGET_ABORT | \
53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
54 #define PCI_NUM_RESET_METHODS 7
56 #define PCI_RESET_PROBE true
57 #define PCI_RESET_DO_RESET false
60 * The PCI interface treats multi-function devices as independent
61 * devices. The slot/function address of each device is encoded
62 * in a single byte as follows:
67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
75 /* pci_slot represents a physical slot */
77 struct pci_bus *bus; /* Bus this slot is on */
78 struct list_head list; /* Node in list of slots */
79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
84 static inline const char *pci_slot_name(const struct pci_slot *slot)
86 return kobject_name(&slot->kobj);
89 /* File state for mmap()s on /proc/bus/pci/X/Y */
95 /* For PCI devices, the region numbers are assigned this way: */
97 /* #0-5: standard PCI resources */
99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
101 /* #6: expansion ROM resource */
104 /* Device-specific resources */
105 #ifdef CONFIG_PCI_IOV
107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
110 /* PCI-to-PCI (P2P) bridge windows */
111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
115 /* CardBus bridge windows */
116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
121 /* Total number of bridge resources for P2P and CardBus */
122 #define PCI_BRIDGE_RESOURCE_NUM 4
124 /* Resources assigned to buses behind the bridge */
125 PCI_BRIDGE_RESOURCES,
126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
127 PCI_BRIDGE_RESOURCE_NUM - 1,
129 /* Total resources associated with a PCI device */
132 /* Preserve this for compatibility */
133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
137 * enum pci_interrupt_pin - PCI INTx interrupt values
138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
139 * @PCI_INTERRUPT_INTA: PCI INTA pin
140 * @PCI_INTERRUPT_INTB: PCI INTB pin
141 * @PCI_INTERRUPT_INTC: PCI INTC pin
142 * @PCI_INTERRUPT_INTD: PCI INTD pin
144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
145 * PCI_INTERRUPT_PIN register.
147 enum pci_interrupt_pin {
148 PCI_INTERRUPT_UNKNOWN,
155 /* The number of legacy PCI INTx interrupts */
156 #define PCI_NUM_INTX 4
159 * Reading from a device that doesn't respond typically returns ~0. A
160 * successful read from a device may also return ~0, so you need additional
161 * information to reliably identify errors.
163 #define PCI_ERROR_RESPONSE (~0ULL)
164 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
165 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
168 * pci_power_t values must match the bits in the Capabilities PME_Support
169 * and Control/Status PowerState fields in the Power Management capability.
171 typedef int __bitwise pci_power_t;
173 #define PCI_D0 ((pci_power_t __force) 0)
174 #define PCI_D1 ((pci_power_t __force) 1)
175 #define PCI_D2 ((pci_power_t __force) 2)
176 #define PCI_D3hot ((pci_power_t __force) 3)
177 #define PCI_D3cold ((pci_power_t __force) 4)
178 #define PCI_UNKNOWN ((pci_power_t __force) 5)
179 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
181 /* Remember to update this when the list above changes! */
182 extern const char *pci_power_names[];
184 static inline const char *pci_power_name(pci_power_t state)
186 return pci_power_names[1 + (__force int) state];
190 * typedef pci_channel_state_t
192 * The pci_channel state describes connectivity between the CPU and
193 * the PCI device. If some PCI bus between here and the PCI device
194 * has crashed or locked up, this info is reflected here.
196 typedef unsigned int __bitwise pci_channel_state_t;
199 /* I/O channel is in normal state */
200 pci_channel_io_normal = (__force pci_channel_state_t) 1,
202 /* I/O to channel is blocked */
203 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
205 /* PCI card is dead */
206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
209 typedef unsigned int __bitwise pcie_reset_state_t;
211 enum pcie_reset_state {
212 /* Reset is NOT asserted (Use to deassert reset) */
213 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
215 /* Use #PERST to reset PCIe device */
216 pcie_warm_reset = (__force pcie_reset_state_t) 2,
218 /* Use PCIe Hot Reset to reset device */
219 pcie_hot_reset = (__force pcie_reset_state_t) 3
222 typedef unsigned short __bitwise pci_dev_flags_t;
224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
226 /* Device configuration is irrevocably lost if disabled into D3 */
227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
228 /* Provide indication device is assigned by a Virtual Machine Manager */
229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
230 /* Flag for quirk use to store if quirk-specific ACS is enabled */
231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
234 /* Do not use bus resets for device */
235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
236 /* Do not use PM reset even if device advertises NoSoftRst- */
237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
238 /* Get VPD from function 0 VPD */
239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
240 /* A non-root bridge where translation occurs, stop alias search here */
241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
242 /* Do not use FLR even if device advertises PCI_AF_CAP */
243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
244 /* Don't use Relaxed Ordering for TLPs directed at this device */
245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
246 /* Device does honor MSI masking despite saying otherwise */
247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
250 enum pci_irq_reroute_variant {
251 INTEL_IRQ_REROUTE_VARIANT = 1,
252 MAX_IRQ_REROUTE_VARIANTS = 3
255 typedef unsigned short __bitwise pci_bus_flags_t;
257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
263 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
264 enum pcie_link_width {
265 PCIE_LNK_WIDTH_RESRV = 0x00,
273 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
276 /* See matching string table in pci_speed_string() */
278 PCI_SPEED_33MHz = 0x00,
279 PCI_SPEED_66MHz = 0x01,
280 PCI_SPEED_66MHz_PCIX = 0x02,
281 PCI_SPEED_100MHz_PCIX = 0x03,
282 PCI_SPEED_133MHz_PCIX = 0x04,
283 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
284 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
285 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
286 PCI_SPEED_66MHz_PCIX_266 = 0x09,
287 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
288 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
294 PCI_SPEED_66MHz_PCIX_533 = 0x11,
295 PCI_SPEED_100MHz_PCIX_533 = 0x12,
296 PCI_SPEED_133MHz_PCIX_533 = 0x13,
297 PCIE_SPEED_2_5GT = 0x14,
298 PCIE_SPEED_5_0GT = 0x15,
299 PCIE_SPEED_8_0GT = 0x16,
300 PCIE_SPEED_16_0GT = 0x17,
301 PCIE_SPEED_32_0GT = 0x18,
302 PCIE_SPEED_64_0GT = 0x19,
303 PCI_SPEED_UNKNOWN = 0xff,
306 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
307 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
316 struct pcie_link_state;
321 /* The pci_dev structure describes PCI devices */
323 struct list_head bus_list; /* Node in per-bus list */
324 struct pci_bus *bus; /* Bus this device is on */
325 struct pci_bus *subordinate; /* Bus this device bridges to */
327 void *sysdata; /* Hook for sys-specific extension */
328 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
329 struct pci_slot *slot; /* Physical slot this device is in */
331 unsigned int devfn; /* Encoded device & function index */
332 unsigned short vendor;
333 unsigned short device;
334 unsigned short subsystem_vendor;
335 unsigned short subsystem_device;
336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
337 u8 revision; /* PCI revision, low byte of class word */
338 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
339 #ifdef CONFIG_PCIEAER
340 u16 aer_cap; /* AER capability offset */
341 struct aer_stats *aer_stats; /* AER stats for this device */
343 #ifdef CONFIG_PCIEPORTBUS
344 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
345 struct pci_dev *rcec; /* Associated RCEC device */
347 u32 devcap; /* PCIe Device Capabilities */
348 u8 pcie_cap; /* PCIe capability offset */
349 u8 msi_cap; /* MSI capability offset */
350 u8 msix_cap; /* MSI-X capability offset */
351 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
352 u8 rom_base_reg; /* Config register controlling ROM */
353 u8 pin; /* Interrupt pin this device uses */
354 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
355 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
357 struct pci_driver *driver; /* Driver bound to this device */
358 u64 dma_mask; /* Mask of the bits of bus address this
359 device implements. Normally this is
360 0xffffffff. You only need to change
361 this if your device has broken DMA
362 or supports 64-bit transfers. */
364 struct device_dma_parameters dma_parms;
366 pci_power_t current_state; /* Current operating state. In ACPI,
367 this is D0-D3, D0 being fully
368 functional, and D3 being off. */
369 u8 pm_cap; /* PM capability offset */
370 unsigned int imm_ready:1; /* Supports Immediate Readiness */
371 unsigned int pme_support:5; /* Bitmask of states from which PME#
373 unsigned int pme_poll:1; /* Poll device's PME status bit */
374 unsigned int d1_support:1; /* Low power state D1 is supported */
375 unsigned int d2_support:1; /* Low power state D2 is supported */
376 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
377 unsigned int no_d3cold:1; /* D3cold is forbidden */
378 unsigned int bridge_d3:1; /* Allow D3 for bridge */
379 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
380 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
381 decoding during BAR sizing */
382 unsigned int wakeup_prepared:1;
383 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
384 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
385 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
386 controlled exclusively by
388 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
390 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
391 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
393 #ifdef CONFIG_PCIEASPM
394 struct pcie_link_state *link_state; /* ASPM link state */
395 u16 l1ss; /* L1SS Capability pointer */
396 unsigned int ltr_path:1; /* Latency Tolerance Reporting
397 supported from root to here */
399 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
400 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
402 pci_channel_state_t error_state; /* Current connectivity state */
403 struct device dev; /* Generic device interface */
405 int cfg_size; /* Size of config space */
408 * Instead of touching interrupt line and base address registers
409 * directly, use the values stored here. They might be different!
412 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
413 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */
415 bool match_driver; /* Skip attaching driver */
417 unsigned int transparent:1; /* Subtractive decode bridge */
418 unsigned int io_window:1; /* Bridge has I/O window */
419 unsigned int pref_window:1; /* Bridge has pref mem window */
420 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
421 unsigned int multifunction:1; /* Multi-function device */
423 unsigned int is_busmaster:1; /* Is busmaster */
424 unsigned int no_msi:1; /* May not use MSI */
425 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
426 unsigned int block_cfg_access:1; /* Config space access blocked */
427 unsigned int broken_parity_status:1; /* Generates false positive parity */
428 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
429 unsigned int msi_enabled:1;
430 unsigned int msix_enabled:1;
431 unsigned int ari_enabled:1; /* ARI forwarding */
432 unsigned int ats_enabled:1; /* Address Translation Svc */
433 unsigned int pasid_enabled:1; /* Process Address Space ID */
434 unsigned int pri_enabled:1; /* Page Request Interface */
435 unsigned int is_managed:1; /* Managed via devres */
436 unsigned int is_msi_managed:1; /* MSI release via devres installed */
437 unsigned int needs_freset:1; /* Requires fundamental reset */
438 unsigned int state_saved:1;
439 unsigned int is_physfn:1;
440 unsigned int is_virtfn:1;
441 unsigned int is_hotplug_bridge:1;
442 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
443 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
445 * Devices marked being untrusted are the ones that can potentially
446 * execute DMA attacks and similar. They are typically connected
447 * through external ports such as Thunderbolt but not limited to
448 * that. When an IOMMU is enabled they should be getting full
449 * mappings to make sure they cannot access arbitrary memory.
451 unsigned int untrusted:1;
453 * Info from the platform, e.g., ACPI or device tree, may mark a
454 * device as "external-facing". An external-facing device is
455 * itself internal but devices downstream from it are external.
457 unsigned int external_facing:1;
458 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
459 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
460 unsigned int irq_managed:1;
461 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
462 unsigned int is_probed:1; /* Device probing in progress */
463 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
464 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
465 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
466 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
467 unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */
468 pci_dev_flags_t dev_flags;
469 atomic_t enable_cnt; /* pci_enable_device has been called */
471 spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */
472 u32 saved_config_space[16]; /* Config space saved at suspend time */
473 struct hlist_head saved_cap_space;
474 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
475 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
477 #ifdef CONFIG_HOTPLUG_PCI_PCIE
478 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
480 #ifdef CONFIG_PCIE_PTM
481 u16 ptm_cap; /* PTM Capability */
482 unsigned int ptm_root:1;
483 unsigned int ptm_enabled:1;
486 #ifdef CONFIG_PCI_MSI
487 void __iomem *msix_base;
488 raw_spinlock_t msi_lock;
491 #ifdef CONFIG_PCIE_DPC
493 unsigned int dpc_rp_extensions:1;
496 #ifdef CONFIG_PCI_ATS
498 struct pci_sriov *sriov; /* PF: SR-IOV info */
499 struct pci_dev *physfn; /* VF: related PF */
501 u16 ats_cap; /* ATS Capability offset */
502 u8 ats_stu; /* ATS Smallest Translation Unit */
504 #ifdef CONFIG_PCI_PRI
505 u16 pri_cap; /* PRI Capability offset */
506 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
507 unsigned int pasid_required:1; /* PRG Response PASID Required */
509 #ifdef CONFIG_PCI_PASID
510 u16 pasid_cap; /* PASID Capability offset */
513 #ifdef CONFIG_PCI_P2PDMA
514 struct pci_p2pdma __rcu *p2pdma;
516 #ifdef CONFIG_PCI_DOE
517 struct xarray doe_mbs; /* Data Object Exchange mailboxes */
519 u16 acs_cap; /* ACS Capability offset */
520 phys_addr_t rom; /* Physical address if not from BAR */
521 size_t romlen; /* Length if not from BAR */
523 * Driver name to force a match. Do not set directly, because core
524 * frees it. Use driver_set_override() to set or clear it.
526 const char *driver_override;
528 unsigned long priv_flags; /* Private flags for the PCI driver */
530 /* These methods index pci_reset_fn_methods[] */
531 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
534 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
536 #ifdef CONFIG_PCI_IOV
543 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
545 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
546 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
548 static inline int pci_channel_offline(struct pci_dev *pdev)
550 return (pdev->error_state != pci_channel_io_normal);
554 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
555 * Group number is limited to a 16-bit value, therefore (int)-1 is
556 * not a valid PCI domain number, and can be used as a sentinel
557 * value indicating ->domain_nr is not set by the driver (and
558 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
559 * pci_bus_find_domain_nr()).
561 #define PCI_DOMAIN_NR_NOT_SET (-1)
563 struct pci_host_bridge {
565 struct pci_bus *bus; /* Root bus */
567 struct pci_ops *child_ops;
571 struct list_head windows; /* resource_entry */
572 struct list_head dma_ranges; /* dma ranges resource list */
573 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
574 int (*map_irq)(const struct pci_dev *, u8, u8);
575 void (*release_fn)(struct pci_host_bridge *);
577 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
578 unsigned int no_ext_tags:1; /* No Extended Tags */
579 unsigned int no_inc_mrrs:1; /* No Increase MRRS */
580 unsigned int native_aer:1; /* OS may use PCIe AER */
581 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
582 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
583 unsigned int native_pme:1; /* OS may use PCIe PME */
584 unsigned int native_ltr:1; /* OS may use PCIe LTR */
585 unsigned int native_dpc:1; /* OS may use PCIe DPC */
586 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */
587 unsigned int preserve_config:1; /* Preserve FW resource setup */
588 unsigned int size_windows:1; /* Enable root bus sizing */
589 unsigned int msi_domain:1; /* Bridge wants MSI domain */
591 /* Resource alignment requirements */
592 resource_size_t (*align_resource)(struct pci_dev *dev,
593 const struct resource *res,
594 resource_size_t start,
595 resource_size_t size,
596 resource_size_t align);
597 unsigned long private[] ____cacheline_aligned;
600 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
602 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
604 return (void *)bridge->private;
607 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
609 return container_of(priv, struct pci_host_bridge, private);
612 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
613 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
615 void pci_free_host_bridge(struct pci_host_bridge *bridge);
616 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
618 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
619 void (*release_fn)(struct pci_host_bridge *),
622 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
625 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
626 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
627 * buses below host bridges or subtractive decode bridges) go in the list.
628 * Use pci_bus_for_each_resource() to iterate through all the resources.
632 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
633 * and there's no way to program the bridge with the details of the window.
634 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
635 * decode bit set, because they are explicit and can be programmed with _SRS.
637 #define PCI_SUBTRACTIVE_DECODE 0x1
639 struct pci_bus_resource {
640 struct list_head list;
641 struct resource *res;
645 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
648 struct list_head node; /* Node in list of buses */
649 struct pci_bus *parent; /* Parent bus this bridge is on */
650 struct list_head children; /* List of child buses */
651 struct list_head devices; /* List of devices on this bus */
652 struct pci_dev *self; /* Bridge device as seen by parent */
653 struct list_head slots; /* List of slots on this bus;
654 protected by pci_slot_mutex */
655 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
656 struct list_head resources; /* Address space routed to this bus */
657 struct resource busn_res; /* Bus numbers routed to this bus */
659 struct pci_ops *ops; /* Configuration access functions */
660 void *sysdata; /* Hook for sys-specific extension */
661 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
663 unsigned char number; /* Bus number */
664 unsigned char primary; /* Number of primary bridge */
665 unsigned char max_bus_speed; /* enum pci_bus_speed */
666 unsigned char cur_bus_speed; /* enum pci_bus_speed */
667 #ifdef CONFIG_PCI_DOMAINS_GENERIC
673 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
674 pci_bus_flags_t bus_flags; /* Inherited by child buses */
675 struct device *bridge;
677 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
678 struct bin_attribute *legacy_mem; /* Legacy mem */
679 unsigned int is_added:1;
680 unsigned int unsafe_warn:1; /* warned about RW1C config write */
683 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
685 static inline u16 pci_dev_id(struct pci_dev *dev)
687 return PCI_DEVID(dev->bus->number, dev->devfn);
691 * Returns true if the PCI bus is root (behind host-PCI bridge),
694 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
695 * This is incorrect because "virtual" buses added for SR-IOV (via
696 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
698 static inline bool pci_is_root_bus(struct pci_bus *pbus)
700 return !(pbus->parent);
704 * pci_is_bridge - check if the PCI device is a bridge
707 * Return true if the PCI device is bridge whether it has subordinate
710 static inline bool pci_is_bridge(struct pci_dev *dev)
712 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
713 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
717 * pci_is_vga - check if the PCI device is a VGA device
720 * The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define
721 * VGA Base Class and Sub-Classes:
723 * 03 00 PCI_CLASS_DISPLAY_VGA VGA-compatible or 8514-compatible
724 * 00 01 PCI_CLASS_NOT_DEFINED_VGA VGA-compatible (before Class Code)
726 * Return true if the PCI device is a VGA device and uses the legacy VGA
727 * resources ([mem 0xa0000-0xbffff], [io 0x3b0-0x3bb], [io 0x3c0-0x3df] and
730 static inline bool pci_is_vga(struct pci_dev *pdev)
732 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
735 if ((pdev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA)
741 #define for_each_pci_bridge(dev, bus) \
742 list_for_each_entry(dev, &bus->devices, bus_list) \
743 if (!pci_is_bridge(dev)) {} else
745 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
747 dev = pci_physfn(dev);
748 if (pci_is_root_bus(dev->bus))
751 return dev->bus->self;
754 #ifdef CONFIG_PCI_MSI
755 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
757 return pci_dev->msi_enabled || pci_dev->msix_enabled;
760 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
763 /* Error values that may be returned by PCI functions */
764 #define PCIBIOS_SUCCESSFUL 0x00
765 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
766 #define PCIBIOS_BAD_VENDOR_ID 0x83
767 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
768 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
769 #define PCIBIOS_SET_FAILED 0x88
770 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
772 /* Translate above to generic errno for passing back through non-PCI code */
773 static inline int pcibios_err_to_errno(int err)
775 if (err <= PCIBIOS_SUCCESSFUL)
776 return err; /* Assume already errno */
779 case PCIBIOS_FUNC_NOT_SUPPORTED:
781 case PCIBIOS_BAD_VENDOR_ID:
783 case PCIBIOS_DEVICE_NOT_FOUND:
785 case PCIBIOS_BAD_REGISTER_NUMBER:
787 case PCIBIOS_SET_FAILED:
789 case PCIBIOS_BUFFER_TOO_SMALL:
796 /* Low-level architecture-dependent routines */
799 int (*add_bus)(struct pci_bus *bus);
800 void (*remove_bus)(struct pci_bus *bus);
801 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
802 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
803 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
807 * ACPI needs to be able to access PCI config space before we've done a
808 * PCI bus scan and created pci_bus structures.
810 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
811 int reg, int len, u32 *val);
812 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
813 int reg, int len, u32 val);
815 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
816 typedef u64 pci_bus_addr_t;
818 typedef u32 pci_bus_addr_t;
821 struct pci_bus_region {
822 pci_bus_addr_t start;
827 spinlock_t lock; /* Protects list, index */
828 struct list_head list; /* For IDs added at runtime */
833 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
834 * a set of callbacks in struct pci_error_handlers, that device driver
835 * will be notified of PCI bus errors, and will be driven to recovery
836 * when an error occurs.
839 typedef unsigned int __bitwise pci_ers_result_t;
841 enum pci_ers_result {
842 /* No result/none/not supported in device driver */
843 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
845 /* Device driver can recover without slot reset */
846 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
848 /* Device driver wants slot to be reset */
849 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
851 /* Device has completely failed, is unrecoverable */
852 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
854 /* Device driver is fully recovered and operational */
855 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
857 /* No AER capabilities registered for the driver */
858 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
861 /* PCI bus error event callbacks */
862 struct pci_error_handlers {
863 /* PCI bus error detected on this device */
864 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
865 pci_channel_state_t error);
867 /* MMIO has been re-enabled, but not DMA */
868 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
870 /* PCI slot has been reset */
871 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
873 /* PCI function reset prepare or completed */
874 void (*reset_prepare)(struct pci_dev *dev);
875 void (*reset_done)(struct pci_dev *dev);
877 /* Device driver may resume normal operations */
878 void (*resume)(struct pci_dev *dev);
880 /* Allow device driver to record more details of a correctable error */
881 void (*cor_error_detected)(struct pci_dev *dev);
888 * struct pci_driver - PCI driver structure
889 * @name: Driver name.
890 * @id_table: Pointer to table of device IDs the driver is
891 * interested in. Most drivers should export this
892 * table using MODULE_DEVICE_TABLE(pci,...).
893 * @probe: This probing function gets called (during execution
894 * of pci_register_driver() for already existing
895 * devices or later if a new device gets inserted) for
896 * all PCI devices which match the ID table and are not
897 * "owned" by the other drivers yet. This function gets
898 * passed a "struct pci_dev \*" for each device whose
899 * entry in the ID table matches the device. The probe
900 * function returns zero when the driver chooses to
901 * take "ownership" of the device or an error code
902 * (negative number) otherwise.
903 * The probe function always gets called from process
904 * context, so it can sleep.
905 * @remove: The remove() function gets called whenever a device
906 * being handled by this driver is removed (either during
907 * deregistration of the driver or when it's manually
908 * pulled out of a hot-pluggable slot).
909 * The remove function always gets called from process
910 * context, so it can sleep.
911 * @suspend: Put device into low power state.
912 * @resume: Wake device from low power state.
913 * (Please see Documentation/power/pci.rst for descriptions
914 * of PCI Power Management and the related functions.)
915 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
916 * Intended to stop any idling DMA operations.
917 * Useful for enabling wake-on-lan (NIC) or changing
918 * the power state of a device before reboot.
919 * e.g. drivers/net/e100.c.
920 * @sriov_configure: Optional driver callback to allow configuration of
921 * number of VFs to enable via sysfs "sriov_numvfs" file.
922 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
923 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
924 * This will change MSI-X Table Size in the VF Message Control
926 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
927 * MSI-X vectors available for distribution to the VFs.
928 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
929 * @groups: Sysfs attribute groups.
930 * @dev_groups: Attributes attached to the device that will be
931 * created once it is bound to the driver.
932 * @driver: Driver model structure.
933 * @dynids: List of dynamically added device IDs.
934 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
935 * For most device drivers, no need to care about this flag
936 * as long as all DMAs are handled through the kernel DMA API.
937 * For some special ones, for example VFIO drivers, they know
938 * how to manage the DMA themselves and set this flag so that
939 * the IOMMU layer will allow them to setup and manage their
940 * own I/O address space.
944 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
945 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
946 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
947 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
948 int (*resume)(struct pci_dev *dev); /* Device woken up */
949 void (*shutdown)(struct pci_dev *dev);
950 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
951 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
952 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
953 const struct pci_error_handlers *err_handler;
954 const struct attribute_group **groups;
955 const struct attribute_group **dev_groups;
956 struct device_driver driver;
957 struct pci_dynids dynids;
958 bool driver_managed_dma;
961 static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
963 return drv ? container_of(drv, struct pci_driver, driver) : NULL;
967 * PCI_DEVICE - macro used to describe a specific PCI device
968 * @vend: the 16 bit PCI Vendor ID
969 * @dev: the 16 bit PCI Device ID
971 * This macro is used to create a struct pci_device_id that matches a
972 * specific device. The subvendor and subdevice fields will be set to
975 #define PCI_DEVICE(vend,dev) \
976 .vendor = (vend), .device = (dev), \
977 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
980 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
981 * override_only flags.
982 * @vend: the 16 bit PCI Vendor ID
983 * @dev: the 16 bit PCI Device ID
984 * @driver_override: the 32 bit PCI Device override_only
986 * This macro is used to create a struct pci_device_id that matches only a
987 * driver_override device. The subvendor and subdevice fields will be set to
990 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
991 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
992 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
995 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
996 * "driver_override" PCI device.
997 * @vend: the 16 bit PCI Vendor ID
998 * @dev: the 16 bit PCI Device ID
1000 * This macro is used to create a struct pci_device_id that matches a
1001 * specific device. The subvendor and subdevice fields will be set to
1002 * PCI_ANY_ID and the driver_override will be set to
1003 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
1005 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
1006 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
1009 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
1010 * @vend: the 16 bit PCI Vendor ID
1011 * @dev: the 16 bit PCI Device ID
1012 * @subvend: the 16 bit PCI Subvendor ID
1013 * @subdev: the 16 bit PCI Subdevice ID
1015 * This macro is used to create a struct pci_device_id that matches a
1016 * specific device with subsystem information.
1018 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1019 .vendor = (vend), .device = (dev), \
1020 .subvendor = (subvend), .subdevice = (subdev)
1023 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
1024 * @dev_class: the class, subclass, prog-if triple for this device
1025 * @dev_class_mask: the class mask for this device
1027 * This macro is used to create a struct pci_device_id that matches a
1028 * specific PCI class. The vendor, device, subvendor, and subdevice
1029 * fields will be set to PCI_ANY_ID.
1031 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
1032 .class = (dev_class), .class_mask = (dev_class_mask), \
1033 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1034 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1037 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
1038 * @vend: the vendor name
1039 * @dev: the 16 bit PCI Device ID
1041 * This macro is used to create a struct pci_device_id that matches a
1042 * specific PCI device. The subvendor, and subdevice fields will be set
1043 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1046 #define PCI_VDEVICE(vend, dev) \
1047 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1048 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1051 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1052 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1053 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1054 * @data: the driver data to be filled
1056 * This macro is used to create a struct pci_device_id that matches a
1057 * specific PCI device. The subvendor, and subdevice fields will be set
1060 #define PCI_DEVICE_DATA(vend, dev, data) \
1061 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1062 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1063 .driver_data = (kernel_ulong_t)(data)
1066 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1067 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1068 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1069 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1070 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1071 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1072 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1075 #define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */
1076 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1077 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1078 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1080 #define PCI_IRQ_LEGACY PCI_IRQ_INTX /* Deprecated! Use PCI_IRQ_INTX */
1082 /* These external functions are only available when PCI support is enabled */
1085 extern unsigned int pci_flags;
1087 static inline void pci_set_flags(int flags) { pci_flags = flags; }
1088 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
1089 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
1090 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1092 void pcie_bus_configure_settings(struct pci_bus *bus);
1094 enum pcie_bus_config_types {
1095 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1096 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1097 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1098 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1099 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1102 extern enum pcie_bus_config_types pcie_bus_config;
1104 extern struct bus_type pci_bus_type;
1106 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1107 * code, or PCI core code. */
1108 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1109 /* Some device drivers need know if PCI is initiated */
1110 int no_pci_devices(void);
1112 void pcibios_resource_survey_bus(struct pci_bus *bus);
1113 void pcibios_bus_add_device(struct pci_dev *pdev);
1114 void pcibios_add_bus(struct pci_bus *bus);
1115 void pcibios_remove_bus(struct pci_bus *bus);
1116 void pcibios_fixup_bus(struct pci_bus *);
1117 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1118 /* Architecture-specific versions may override this (weak) */
1119 char *pcibios_setup(char *str);
1121 /* Used only when drivers/pci/setup.c is used */
1122 resource_size_t pcibios_align_resource(void *, const struct resource *,
1126 /* Weak but can be overridden by arch */
1127 void pci_fixup_cardbus(struct pci_bus *);
1129 /* Generic PCI functions used internally */
1131 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1132 struct resource *res);
1133 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1134 struct pci_bus_region *region);
1135 void pcibios_scan_specific_bus(int busn);
1136 struct pci_bus *pci_find_bus(int domain, int busnr);
1137 void pci_bus_add_devices(const struct pci_bus *bus);
1138 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1139 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1140 struct pci_ops *ops, void *sysdata,
1141 struct list_head *resources);
1142 int pci_host_probe(struct pci_host_bridge *bridge);
1143 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1144 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1145 void pci_bus_release_busn_res(struct pci_bus *b);
1146 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1147 struct pci_ops *ops, void *sysdata,
1148 struct list_head *resources);
1149 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1150 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1152 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1154 struct hotplug_slot *hotplug);
1155 void pci_destroy_slot(struct pci_slot *slot);
1157 void pci_dev_assign_slot(struct pci_dev *dev);
1159 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1161 int pci_scan_slot(struct pci_bus *bus, int devfn);
1162 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1163 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1164 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1165 void pci_bus_add_device(struct pci_dev *dev);
1166 void pci_read_bridge_bases(struct pci_bus *child);
1167 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1168 struct resource *res);
1169 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1170 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1171 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1172 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1173 void pci_dev_put(struct pci_dev *dev);
1174 DEFINE_FREE(pci_dev_put, struct pci_dev *, if (_T) pci_dev_put(_T))
1175 void pci_remove_bus(struct pci_bus *b);
1176 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1177 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1178 void pci_stop_root_bus(struct pci_bus *bus);
1179 void pci_remove_root_bus(struct pci_bus *bus);
1180 void pci_setup_cardbus(struct pci_bus *bus);
1181 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1182 void pci_sort_breadthfirst(void);
1183 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1184 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1186 /* Generic PCI functions exported to card drivers */
1188 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1189 u8 pci_find_capability(struct pci_dev *dev, int cap);
1190 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1191 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1192 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1193 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1194 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1195 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1196 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1197 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1199 u64 pci_get_dsn(struct pci_dev *dev);
1201 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1202 struct pci_dev *from);
1203 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1204 unsigned int ss_vendor, unsigned int ss_device,
1205 struct pci_dev *from);
1206 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1207 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1208 unsigned int devfn);
1209 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1210 struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from);
1212 int pci_dev_present(const struct pci_device_id *ids);
1214 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1215 int where, u8 *val);
1216 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1217 int where, u16 *val);
1218 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1219 int where, u32 *val);
1220 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1222 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1223 int where, u16 val);
1224 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1225 int where, u32 val);
1227 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1228 int where, int size, u32 *val);
1229 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1230 int where, int size, u32 val);
1231 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1232 int where, int size, u32 *val);
1233 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1234 int where, int size, u32 val);
1236 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1238 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1239 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1240 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1241 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1242 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1243 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1244 void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,
1245 u32 clear, u32 set);
1247 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1248 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1249 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1250 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1251 int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos,
1252 u16 clear, u16 set);
1253 int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos,
1254 u16 clear, u16 set);
1255 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1256 u32 clear, u32 set);
1259 * pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers
1260 * @dev: PCI device structure of the PCI Express device
1261 * @pos: PCI Express Capability Register
1262 * @clear: Clear bitmask
1265 * Perform a Read-Modify-Write (RMW) operation using @clear and @set
1266 * bitmasks on PCI Express Capability Register at @pos. Certain PCI Express
1267 * Capability Registers are accessed concurrently in RMW fashion, hence
1268 * require locking which is handled transparently to the caller.
1270 static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev,
1275 case PCI_EXP_LNKCTL:
1277 return pcie_capability_clear_and_set_word_locked(dev, pos,
1280 return pcie_capability_clear_and_set_word_unlocked(dev, pos,
1285 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1288 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1291 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1294 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1297 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1300 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1303 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1306 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1309 /* User-space driven config access */
1310 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1311 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1312 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1313 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1314 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1315 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1317 int __must_check pci_enable_device(struct pci_dev *dev);
1318 int __must_check pci_enable_device_io(struct pci_dev *dev);
1319 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1320 int __must_check pci_reenable_device(struct pci_dev *);
1321 int __must_check pcim_enable_device(struct pci_dev *pdev);
1322 void pcim_pin_device(struct pci_dev *pdev);
1324 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1327 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1328 * writable and no quirk has marked the feature broken.
1330 return !pdev->broken_intx_masking;
1333 static inline int pci_is_enabled(struct pci_dev *pdev)
1335 return (atomic_read(&pdev->enable_cnt) > 0);
1338 static inline int pci_is_managed(struct pci_dev *pdev)
1340 return pdev->is_managed;
1343 void pci_disable_device(struct pci_dev *dev);
1345 extern unsigned int pcibios_max_latency;
1346 void pci_set_master(struct pci_dev *dev);
1347 void pci_clear_master(struct pci_dev *dev);
1349 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1350 int pci_set_cacheline_size(struct pci_dev *dev);
1351 int __must_check pci_set_mwi(struct pci_dev *dev);
1352 int __must_check pcim_set_mwi(struct pci_dev *dev);
1353 int pci_try_set_mwi(struct pci_dev *dev);
1354 void pci_clear_mwi(struct pci_dev *dev);
1355 void pci_disable_parity(struct pci_dev *dev);
1356 void pci_intx(struct pci_dev *dev, int enable);
1357 bool pci_check_and_mask_intx(struct pci_dev *dev);
1358 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1359 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1360 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1361 int pcix_get_max_mmrbc(struct pci_dev *dev);
1362 int pcix_get_mmrbc(struct pci_dev *dev);
1363 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1364 int pcie_get_readrq(struct pci_dev *dev);
1365 int pcie_set_readrq(struct pci_dev *dev, int rq);
1366 int pcie_get_mps(struct pci_dev *dev);
1367 int pcie_set_mps(struct pci_dev *dev, int mps);
1368 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1369 enum pci_bus_speed *speed,
1370 enum pcie_link_width *width);
1371 int pcie_link_speed_mbps(struct pci_dev *pdev);
1372 void pcie_print_link_status(struct pci_dev *dev);
1373 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1374 int pcie_flr(struct pci_dev *dev);
1375 int __pci_reset_function_locked(struct pci_dev *dev);
1376 int pci_reset_function(struct pci_dev *dev);
1377 int pci_reset_function_locked(struct pci_dev *dev);
1378 int pci_try_reset_function(struct pci_dev *dev);
1379 int pci_probe_reset_slot(struct pci_slot *slot);
1380 int pci_probe_reset_bus(struct pci_bus *bus);
1381 int pci_reset_bus(struct pci_dev *dev);
1382 void pci_reset_secondary_bus(struct pci_dev *dev);
1383 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1384 void pci_update_resource(struct pci_dev *dev, int resno);
1385 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1386 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1387 void pci_release_resource(struct pci_dev *dev, int resno);
1388 static inline int pci_rebar_bytes_to_size(u64 bytes)
1390 bytes = roundup_pow_of_two(bytes);
1392 /* Return BAR size as defined in the resizable BAR specification */
1393 return max(ilog2(bytes), 20) - 20;
1396 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1397 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1398 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1399 bool pci_device_is_present(struct pci_dev *pdev);
1400 void pci_ignore_hotplug(struct pci_dev *dev);
1401 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1402 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1404 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1405 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1406 const char *fmt, ...);
1407 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1409 /* ROM control related routines */
1410 int pci_enable_rom(struct pci_dev *pdev);
1411 void pci_disable_rom(struct pci_dev *pdev);
1412 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1413 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1415 /* Power management related routines */
1416 int pci_save_state(struct pci_dev *dev);
1417 void pci_restore_state(struct pci_dev *dev);
1418 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1419 int pci_load_saved_state(struct pci_dev *dev,
1420 struct pci_saved_state *state);
1421 int pci_load_and_free_saved_state(struct pci_dev *dev,
1422 struct pci_saved_state **state);
1423 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1424 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1425 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1426 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1427 void pci_pme_active(struct pci_dev *dev, bool enable);
1428 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1429 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1430 int pci_prepare_to_sleep(struct pci_dev *dev);
1431 int pci_back_from_sleep(struct pci_dev *dev);
1432 bool pci_dev_run_wake(struct pci_dev *dev);
1433 void pci_d3cold_enable(struct pci_dev *dev);
1434 void pci_d3cold_disable(struct pci_dev *dev);
1435 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1436 void pci_resume_bus(struct pci_bus *bus);
1437 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1439 /* For use by arch with custom probe code */
1440 void set_pcie_port_type(struct pci_dev *pdev);
1441 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1443 /* Functions for PCI Hotplug drivers to use */
1444 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1445 unsigned int pci_rescan_bus(struct pci_bus *bus);
1446 void pci_lock_rescan_remove(void);
1447 void pci_unlock_rescan_remove(void);
1449 /* Vital Product Data routines */
1450 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1451 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1452 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1453 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1455 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1456 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1457 void pci_bus_assign_resources(const struct pci_bus *bus);
1458 void pci_bus_claim_resources(struct pci_bus *bus);
1459 void pci_bus_size_bridges(struct pci_bus *bus);
1460 int pci_claim_resource(struct pci_dev *, int);
1461 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1462 void pci_assign_unassigned_resources(void);
1463 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1464 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1465 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1466 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1467 int pci_enable_resources(struct pci_dev *, int mask);
1468 void pci_assign_irq(struct pci_dev *dev);
1469 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1470 #define HAVE_PCI_REQ_REGIONS 2
1471 int __must_check pci_request_regions(struct pci_dev *, const char *);
1472 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1473 void pci_release_regions(struct pci_dev *);
1474 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1475 void pci_release_region(struct pci_dev *, int);
1476 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1477 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1478 void pci_release_selected_regions(struct pci_dev *, int);
1480 static inline __must_check struct resource *
1481 pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset,
1482 unsigned int len, const char *name)
1484 return __request_region(&pdev->driver_exclusive_resource, offset, len,
1485 name, IORESOURCE_EXCLUSIVE);
1488 static inline void pci_release_config_region(struct pci_dev *pdev,
1489 unsigned int offset,
1492 __release_region(&pdev->driver_exclusive_resource, offset, len);
1495 /* drivers/pci/bus.c */
1496 void pci_add_resource(struct list_head *resources, struct resource *res);
1497 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1498 resource_size_t offset);
1499 void pci_free_resource_list(struct list_head *resources);
1500 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1501 unsigned int flags);
1502 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1503 void pci_bus_remove_resources(struct pci_bus *bus);
1504 void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res);
1505 int devm_request_pci_bus_resources(struct device *dev,
1506 struct list_head *resources);
1508 /* Temporary until new and working PCI SBR API in place */
1509 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1511 #define __pci_bus_for_each_res0(bus, res, ...) \
1512 for (unsigned int __b = 0; \
1513 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \
1516 #define __pci_bus_for_each_res1(bus, res, __b) \
1518 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \
1522 * pci_bus_for_each_resource - iterate over PCI bus resources
1524 * @res: pointer to the current resource
1525 * @...: optional index of the current resource
1527 * Iterate over PCI bus resources. The first part is to go over PCI bus
1528 * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries.
1529 * After that continue with the separate list of the additional resources,
1530 * if not empty. That's why the Logical OR is being used.
1534 * struct pci_bus *bus = ...;
1535 * struct resource *res;
1538 * // With optional index
1539 * pci_bus_for_each_resource(bus, res, i)
1540 * pr_info("PCI bus resource[%u]: %pR\n", i, res);
1543 * pci_bus_for_each_resource(bus, res)
1544 * _do_something_(res);
1546 #define pci_bus_for_each_resource(bus, res, ...) \
1547 CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \
1548 (bus, res, __VA_ARGS__)
1550 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1551 struct resource *res, resource_size_t size,
1552 resource_size_t align, resource_size_t min,
1553 unsigned long type_mask,
1554 resource_size_t (*alignf)(void *,
1555 const struct resource *,
1561 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1562 resource_size_t size);
1563 unsigned long pci_address_to_pio(phys_addr_t addr);
1564 phys_addr_t pci_pio_to_address(unsigned long pio);
1565 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1566 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1567 phys_addr_t phys_addr);
1568 void pci_unmap_iospace(struct resource *res);
1569 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1570 resource_size_t offset,
1571 resource_size_t size);
1572 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1573 struct resource *res);
1575 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1577 struct pci_bus_region region;
1579 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1580 return region.start;
1583 /* Proper probing supporting hot-pluggable devices */
1584 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1585 const char *mod_name);
1587 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1588 #define pci_register_driver(driver) \
1589 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1591 void pci_unregister_driver(struct pci_driver *dev);
1594 * module_pci_driver() - Helper macro for registering a PCI driver
1595 * @__pci_driver: pci_driver struct
1597 * Helper macro for PCI drivers which do not do anything special in module
1598 * init/exit. This eliminates a lot of boilerplate. Each module may only
1599 * use this macro once, and calling it replaces module_init() and module_exit()
1601 #define module_pci_driver(__pci_driver) \
1602 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1605 * builtin_pci_driver() - Helper macro for registering a PCI driver
1606 * @__pci_driver: pci_driver struct
1608 * Helper macro for PCI drivers which do not do anything special in their
1609 * init code. This eliminates a lot of boilerplate. Each driver may only
1610 * use this macro once, and calling it replaces device_initcall(...)
1612 #define builtin_pci_driver(__pci_driver) \
1613 builtin_driver(__pci_driver, pci_register_driver)
1615 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1616 int pci_add_dynid(struct pci_driver *drv,
1617 unsigned int vendor, unsigned int device,
1618 unsigned int subvendor, unsigned int subdevice,
1619 unsigned int class, unsigned int class_mask,
1620 unsigned long driver_data);
1621 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1622 struct pci_dev *dev);
1623 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1626 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1628 int pci_cfg_space_size(struct pci_dev *dev);
1629 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1630 void pci_setup_bridge(struct pci_bus *bus);
1631 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1632 unsigned long type);
1634 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1635 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1637 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1638 unsigned int command_bits, u32 flags);
1641 * Virtual interrupts allow for more interrupts to be allocated
1642 * than the device has interrupts for. These are not programmed
1643 * into the device's MSI-X table and must be handled by some
1644 * other driver means.
1646 #define PCI_IRQ_VIRTUAL (1 << 4)
1648 #define PCI_IRQ_ALL_TYPES \
1649 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1651 #include <linux/dmapool.h>
1654 u32 vector; /* Kernel uses to write allocated vector */
1655 u16 entry; /* Driver uses to specify entry, OS writes */
1658 struct msi_domain_template;
1660 #ifdef CONFIG_PCI_MSI
1661 int pci_msi_vec_count(struct pci_dev *dev);
1662 void pci_disable_msi(struct pci_dev *dev);
1663 int pci_msix_vec_count(struct pci_dev *dev);
1664 void pci_disable_msix(struct pci_dev *dev);
1665 void pci_restore_msi_state(struct pci_dev *dev);
1666 int pci_msi_enabled(void);
1667 int pci_enable_msi(struct pci_dev *dev);
1668 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1669 int minvec, int maxvec);
1670 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1671 struct msix_entry *entries, int nvec)
1673 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1678 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1679 unsigned int max_vecs, unsigned int flags);
1680 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1681 unsigned int max_vecs, unsigned int flags,
1682 struct irq_affinity *affd);
1684 bool pci_msix_can_alloc_dyn(struct pci_dev *dev);
1685 struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1686 const struct irq_affinity_desc *affdesc);
1687 void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map);
1689 void pci_free_irq_vectors(struct pci_dev *dev);
1690 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1691 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1692 bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template,
1693 unsigned int hwsize, void *data);
1694 struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie,
1695 const struct irq_affinity_desc *affdesc);
1696 void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map);
1699 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1700 static inline void pci_disable_msi(struct pci_dev *dev) { }
1701 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1702 static inline void pci_disable_msix(struct pci_dev *dev) { }
1703 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1704 static inline int pci_msi_enabled(void) { return 0; }
1705 static inline int pci_enable_msi(struct pci_dev *dev)
1707 static inline int pci_enable_msix_range(struct pci_dev *dev,
1708 struct msix_entry *entries, int minvec, int maxvec)
1710 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1711 struct msix_entry *entries, int nvec)
1715 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1716 unsigned int max_vecs, unsigned int flags,
1717 struct irq_affinity *aff_desc)
1719 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1724 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1725 unsigned int max_vecs, unsigned int flags)
1727 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,
1731 static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev)
1733 static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1734 const struct irq_affinity_desc *affdesc)
1736 struct msi_map map = { .index = -ENOSYS, };
1741 static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map)
1745 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1749 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1751 if (WARN_ON_ONCE(nr > 0))
1755 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1758 return cpu_possible_mask;
1761 static inline bool pci_create_ims_domain(struct pci_dev *pdev,
1762 const struct msi_domain_template *template,
1763 unsigned int hwsize, void *data)
1766 static inline struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev,
1767 union msi_instance_cookie *icookie,
1768 const struct irq_affinity_desc *affdesc)
1770 struct msi_map map = { .index = -ENOSYS, };
1775 static inline void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map)
1782 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1783 * @d: the INTx IRQ domain
1784 * @node: the DT node for the device whose interrupt we're translating
1785 * @intspec: the interrupt specifier data from the DT
1786 * @intsize: the number of entries in @intspec
1787 * @out_hwirq: pointer at which to write the hwirq number
1788 * @out_type: pointer at which to write the interrupt type
1790 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1791 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1792 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1793 * INTx value to obtain the hwirq number.
1795 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1797 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1798 struct device_node *node,
1800 unsigned int intsize,
1801 unsigned long *out_hwirq,
1802 unsigned int *out_type)
1804 const u32 intx = intspec[0];
1806 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1809 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1813 #ifdef CONFIG_PCIEPORTBUS
1814 extern bool pcie_ports_disabled;
1815 extern bool pcie_ports_native;
1817 #define pcie_ports_disabled true
1818 #define pcie_ports_native false
1821 #define PCIE_LINK_STATE_L0S BIT(0)
1822 #define PCIE_LINK_STATE_L1 BIT(1)
1823 #define PCIE_LINK_STATE_CLKPM BIT(2)
1824 #define PCIE_LINK_STATE_L1_1 BIT(3)
1825 #define PCIE_LINK_STATE_L1_2 BIT(4)
1826 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1827 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1828 #define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |\
1829 PCIE_LINK_STATE_CLKPM | PCIE_LINK_STATE_L1_1 |\
1830 PCIE_LINK_STATE_L1_2 | PCIE_LINK_STATE_L1_1_PCIPM |\
1831 PCIE_LINK_STATE_L1_2_PCIPM)
1833 #ifdef CONFIG_PCIEASPM
1834 int pci_disable_link_state(struct pci_dev *pdev, int state);
1835 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1836 int pci_enable_link_state(struct pci_dev *pdev, int state);
1837 int pci_enable_link_state_locked(struct pci_dev *pdev, int state);
1838 void pcie_no_aspm(void);
1839 bool pcie_aspm_support_enabled(void);
1840 bool pcie_aspm_enabled(struct pci_dev *pdev);
1842 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1844 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1846 static inline int pci_enable_link_state(struct pci_dev *pdev, int state)
1848 static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state)
1850 static inline void pcie_no_aspm(void) { }
1851 static inline bool pcie_aspm_support_enabled(void) { return false; }
1852 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1855 #ifdef CONFIG_PCIEAER
1856 bool pci_aer_available(void);
1858 static inline bool pci_aer_available(void) { return false; }
1861 bool pci_ats_disabled(void);
1863 #ifdef CONFIG_PCIE_PTM
1864 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1865 void pci_disable_ptm(struct pci_dev *dev);
1866 bool pcie_ptm_enabled(struct pci_dev *dev);
1868 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1870 static inline void pci_disable_ptm(struct pci_dev *dev) { }
1871 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1875 void pci_cfg_access_lock(struct pci_dev *dev);
1876 bool pci_cfg_access_trylock(struct pci_dev *dev);
1877 void pci_cfg_access_unlock(struct pci_dev *dev);
1879 void pci_dev_lock(struct pci_dev *dev);
1880 int pci_dev_trylock(struct pci_dev *dev);
1881 void pci_dev_unlock(struct pci_dev *dev);
1882 DEFINE_GUARD(pci_dev, struct pci_dev *, pci_dev_lock(_T), pci_dev_unlock(_T))
1885 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1886 * a PCI domain is defined to be a set of PCI buses which share
1887 * configuration space.
1889 #ifdef CONFIG_PCI_DOMAINS
1890 extern int pci_domains_supported;
1892 enum { pci_domains_supported = 0 };
1893 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1894 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1895 #endif /* CONFIG_PCI_DOMAINS */
1898 * Generic implementation for PCI domain support. If your
1899 * architecture does not need custom management of PCI
1900 * domains then this implementation will be used
1902 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1903 static inline int pci_domain_nr(struct pci_bus *bus)
1905 return bus->domain_nr;
1908 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1910 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1913 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1914 void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent);
1917 /* Some architectures require additional setup to direct VGA traffic */
1918 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1919 unsigned int command_bits, u32 flags);
1920 void pci_register_set_vga_state(arch_set_vga_state_t func);
1923 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1925 return pci_request_selected_regions(pdev,
1926 pci_select_bars(pdev, IORESOURCE_IO), name);
1930 pci_release_io_regions(struct pci_dev *pdev)
1932 return pci_release_selected_regions(pdev,
1933 pci_select_bars(pdev, IORESOURCE_IO));
1937 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1939 return pci_request_selected_regions(pdev,
1940 pci_select_bars(pdev, IORESOURCE_MEM), name);
1944 pci_release_mem_regions(struct pci_dev *pdev)
1946 return pci_release_selected_regions(pdev,
1947 pci_select_bars(pdev, IORESOURCE_MEM));
1950 #else /* CONFIG_PCI is not enabled */
1952 static inline void pci_set_flags(int flags) { }
1953 static inline void pci_add_flags(int flags) { }
1954 static inline void pci_clear_flags(int flags) { }
1955 static inline int pci_has_flag(int flag) { return 0; }
1958 * If the system does not have PCI, clearly these return errors. Define
1959 * these as simple inline functions to avoid hair in drivers.
1961 #define _PCI_NOP(o, s, t) \
1962 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1964 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1966 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1967 _PCI_NOP(o, word, u16 x) \
1968 _PCI_NOP(o, dword, u32 x)
1969 _PCI_NOP_ALL(read, *)
1970 _PCI_NOP_ALL(write,)
1972 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1973 unsigned int device,
1974 struct pci_dev *from)
1977 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1978 unsigned int device,
1979 unsigned int ss_vendor,
1980 unsigned int ss_device,
1981 struct pci_dev *from)
1984 static inline struct pci_dev *pci_get_class(unsigned int class,
1985 struct pci_dev *from)
1988 static inline struct pci_dev *pci_get_base_class(unsigned int class,
1989 struct pci_dev *from)
1992 static inline int pci_dev_present(const struct pci_device_id *ids)
1995 #define no_pci_devices() (1)
1996 #define pci_dev_put(dev) do { } while (0)
1998 static inline void pci_set_master(struct pci_dev *dev) { }
1999 static inline void pci_clear_master(struct pci_dev *dev) { }
2000 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
2001 static inline void pci_disable_device(struct pci_dev *dev) { }
2002 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
2003 static inline int pci_assign_resource(struct pci_dev *dev, int i)
2005 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
2006 struct module *owner,
2007 const char *mod_name)
2009 static inline int pci_register_driver(struct pci_driver *drv)
2011 static inline void pci_unregister_driver(struct pci_driver *drv) { }
2012 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
2014 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
2017 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
2020 static inline u64 pci_get_dsn(struct pci_dev *dev)
2023 /* Power management related routines */
2024 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
2025 static inline void pci_restore_state(struct pci_dev *dev) { }
2026 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2028 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2030 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
2033 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
2037 static inline struct resource *pci_find_resource(struct pci_dev *dev,
2038 struct resource *res)
2040 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2042 static inline void pci_release_regions(struct pci_dev *dev) { }
2044 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
2045 phys_addr_t addr, resource_size_t size)
2048 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
2050 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
2052 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
2055 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
2056 unsigned int bus, unsigned int devfn)
2059 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
2060 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
2062 #define dev_is_pci(d) (false)
2063 #define dev_is_pf(d) (false)
2064 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2066 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
2067 struct device_node *node,
2069 unsigned int intsize,
2070 unsigned long *out_hwirq,
2071 unsigned int *out_type)
2074 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
2075 struct pci_dev *dev)
2077 static inline bool pci_ats_disabled(void) { return true; }
2079 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
2085 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
2086 unsigned int max_vecs, unsigned int flags,
2087 struct irq_affinity *aff_desc)
2092 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
2093 unsigned int max_vecs, unsigned int flags)
2097 #endif /* CONFIG_PCI */
2099 /* Include architecture-dependent settings and functions */
2101 #include <asm/pci.h>
2104 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
2105 * is expected to be an offset within that region.
2108 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
2109 struct vm_area_struct *vma,
2110 enum pci_mmap_state mmap_state, int write_combine);
2112 #ifndef arch_can_pci_mmap_wc
2113 #define arch_can_pci_mmap_wc() 0
2116 #ifndef arch_can_pci_mmap_io
2117 #define arch_can_pci_mmap_io() 0
2118 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
2120 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
2123 #ifndef pci_root_bus_fwnode
2124 #define pci_root_bus_fwnode(bus) NULL
2128 * These helpers provide future and backwards compatibility
2129 * for accessing popular PCI BAR info
2131 #define pci_resource_n(dev, bar) (&(dev)->resource[(bar)])
2132 #define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start)
2133 #define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end)
2134 #define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags)
2135 #define pci_resource_len(dev,bar) \
2136 (pci_resource_end((dev), (bar)) ? \
2137 resource_size(pci_resource_n((dev), (bar))) : 0)
2139 #define __pci_dev_for_each_res0(dev, res, ...) \
2140 for (unsigned int __b = 0; \
2141 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \
2144 #define __pci_dev_for_each_res1(dev, res, __b) \
2146 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \
2149 #define pci_dev_for_each_resource(dev, res, ...) \
2150 CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \
2151 (dev, res, __VA_ARGS__)
2154 * Similar to the helpers above, these manipulate per-pci_dev
2155 * driver-specific data. They are really just a wrapper around
2156 * the generic device structure functions of these calls.
2158 static inline void *pci_get_drvdata(struct pci_dev *pdev)
2160 return dev_get_drvdata(&pdev->dev);
2163 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
2165 dev_set_drvdata(&pdev->dev, data);
2168 static inline const char *pci_name(const struct pci_dev *pdev)
2170 return dev_name(&pdev->dev);
2173 void pci_resource_to_user(const struct pci_dev *dev, int bar,
2174 const struct resource *rsrc,
2175 resource_size_t *start, resource_size_t *end);
2178 * The world is not perfect and supplies us with broken PCI devices.
2179 * For at least a part of these bugs we need a work-around, so both
2180 * generic (drivers/pci/quirks.c) and per-architecture code can define
2181 * fixup hooks to be called for particular buggy devices.
2185 u16 vendor; /* Or PCI_ANY_ID */
2186 u16 device; /* Or PCI_ANY_ID */
2187 u32 class; /* Or PCI_ANY_ID */
2188 unsigned int class_shift; /* should be 0, 8, 16 */
2189 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2192 void (*hook)(struct pci_dev *dev);
2196 enum pci_fixup_pass {
2197 pci_fixup_early, /* Before probing BARs */
2198 pci_fixup_header, /* After reading configuration header */
2199 pci_fixup_final, /* Final phase of device fixups */
2200 pci_fixup_enable, /* pci_enable_device() time */
2201 pci_fixup_resume, /* pci_device_resume() */
2202 pci_fixup_suspend, /* pci_device_suspend() */
2203 pci_fixup_resume_early, /* pci_device_resume_early() */
2204 pci_fixup_suspend_late, /* pci_device_suspend_late() */
2207 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2208 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2209 class_shift, hook) \
2210 __ADDRESSABLE(hook) \
2211 asm(".section " #sec ", \"a\" \n" \
2213 ".short " #vendor ", " #device " \n" \
2214 ".long " #class ", " #class_shift " \n" \
2215 ".long " #hook " - . \n" \
2219 * Clang's LTO may rename static functions in C, but has no way to
2220 * handle such renamings when referenced from inline asm. To work
2221 * around this, create global C stubs for these cases.
2223 #ifdef CONFIG_LTO_CLANG
2224 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2225 class_shift, hook, stub) \
2226 void stub(struct pci_dev *dev); \
2227 void stub(struct pci_dev *dev) \
2231 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2234 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2235 class_shift, hook, stub) \
2236 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2240 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2241 class_shift, hook) \
2242 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2243 class_shift, hook, __UNIQUE_ID(hook))
2245 /* Anonymous variables would be nice... */
2246 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2247 class_shift, hook) \
2248 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2249 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2250 = { vendor, device, class, class_shift, hook };
2253 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2254 class_shift, hook) \
2255 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2256 hook, vendor, device, class, class_shift, hook)
2257 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2258 class_shift, hook) \
2259 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2260 hook, vendor, device, class, class_shift, hook)
2261 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2262 class_shift, hook) \
2263 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2264 hook, vendor, device, class, class_shift, hook)
2265 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2266 class_shift, hook) \
2267 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2268 hook, vendor, device, class, class_shift, hook)
2269 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2270 class_shift, hook) \
2271 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2272 resume##hook, vendor, device, class, class_shift, hook)
2273 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2274 class_shift, hook) \
2275 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2276 resume_early##hook, vendor, device, class, class_shift, hook)
2277 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2278 class_shift, hook) \
2279 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2280 suspend##hook, vendor, device, class, class_shift, hook)
2281 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2282 class_shift, hook) \
2283 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2284 suspend_late##hook, vendor, device, class, class_shift, hook)
2286 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2287 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2288 hook, vendor, device, PCI_ANY_ID, 0, hook)
2289 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2290 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2291 hook, vendor, device, PCI_ANY_ID, 0, hook)
2292 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2293 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2294 hook, vendor, device, PCI_ANY_ID, 0, hook)
2295 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2296 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2297 hook, vendor, device, PCI_ANY_ID, 0, hook)
2298 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2299 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2300 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2301 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2302 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2303 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2304 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2305 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2306 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2307 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2308 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2309 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2311 #ifdef CONFIG_PCI_QUIRKS
2312 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2314 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2315 struct pci_dev *dev) { }
2318 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2319 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2320 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2321 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2322 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2324 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2326 extern int pci_pci_problems;
2327 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2328 #define PCIPCI_TRITON 2
2329 #define PCIPCI_NATOMA 4
2330 #define PCIPCI_VIAETBF 8
2331 #define PCIPCI_VSFX 16
2332 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2333 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2335 extern unsigned long pci_cardbus_io_size;
2336 extern unsigned long pci_cardbus_mem_size;
2337 extern u8 pci_dfl_cache_line_size;
2338 extern u8 pci_cache_line_size;
2340 /* Architecture-specific versions may override these (weak) */
2341 void pcibios_disable_device(struct pci_dev *dev);
2342 void pcibios_set_master(struct pci_dev *dev);
2343 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2344 enum pcie_reset_state state);
2345 int pcibios_device_add(struct pci_dev *dev);
2346 void pcibios_release_device(struct pci_dev *dev);
2348 void pcibios_penalize_isa_irq(int irq, int active);
2350 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2352 int pcibios_alloc_irq(struct pci_dev *dev);
2353 void pcibios_free_irq(struct pci_dev *dev);
2354 resource_size_t pcibios_default_alignment(void);
2356 #if !defined(HAVE_PCI_MMAP) && !defined(ARCH_GENERIC_PCI_MMAP_RESOURCE)
2357 extern int pci_create_resource_files(struct pci_dev *dev);
2358 extern void pci_remove_resource_files(struct pci_dev *dev);
2361 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2362 void __init pci_mmcfg_early_init(void);
2363 void __init pci_mmcfg_late_init(void);
2365 static inline void pci_mmcfg_early_init(void) { }
2366 static inline void pci_mmcfg_late_init(void) { }
2369 int pci_ext_cfg_avail(void);
2371 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2372 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2374 #ifdef CONFIG_PCI_IOV
2375 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2376 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2377 int pci_iov_vf_id(struct pci_dev *dev);
2378 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
2379 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2380 void pci_disable_sriov(struct pci_dev *dev);
2382 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2383 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2384 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2385 int pci_num_vf(struct pci_dev *dev);
2386 int pci_vfs_assigned(struct pci_dev *dev);
2387 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2388 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2389 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2390 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2391 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2393 /* Arch may override these (weak) */
2394 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2395 int pcibios_sriov_disable(struct pci_dev *pdev);
2396 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2398 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2402 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2407 static inline int pci_iov_vf_id(struct pci_dev *dev)
2412 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2413 struct pci_driver *pf_driver)
2415 return ERR_PTR(-EINVAL);
2418 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2421 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2422 struct pci_dev *virtfn, int id)
2426 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2430 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2432 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2433 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2434 static inline int pci_vfs_assigned(struct pci_dev *dev)
2436 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2438 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2440 #define pci_sriov_configure_simple NULL
2441 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2443 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2446 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2447 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2448 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2452 * pci_pcie_cap - get the saved PCIe capability offset
2455 * PCIe capability offset is calculated at PCI device initialization
2456 * time and saved in the data structure. This function returns saved
2457 * PCIe capability offset. Using this instead of pci_find_capability()
2458 * reduces unnecessary search in the PCI configuration space. If you
2459 * need to calculate PCIe capability offset from raw device for some
2460 * reasons, please use pci_find_capability() instead.
2462 static inline int pci_pcie_cap(struct pci_dev *dev)
2464 return dev->pcie_cap;
2468 * pci_is_pcie - check if the PCI device is PCI Express capable
2471 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2473 static inline bool pci_is_pcie(struct pci_dev *dev)
2475 return pci_pcie_cap(dev);
2479 * pcie_caps_reg - get the PCIe Capabilities Register
2482 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2484 return dev->pcie_flags_reg;
2488 * pci_pcie_type - get the PCIe device/port type
2491 static inline int pci_pcie_type(const struct pci_dev *dev)
2493 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2497 * pcie_find_root_port - Get the PCIe root port device
2500 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2501 * for a given PCI/PCIe Device.
2503 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2506 if (pci_is_pcie(dev) &&
2507 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2509 dev = pci_upstream_bridge(dev);
2515 void pci_request_acs(void);
2516 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2517 bool pci_acs_path_enabled(struct pci_dev *start,
2518 struct pci_dev *end, u16 acs_flags);
2519 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2521 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2522 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2524 /* Large Resource Data Type Tag Item Names */
2525 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2526 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2527 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2529 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2530 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2531 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2533 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2534 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2535 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2536 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2537 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2540 * pci_vpd_alloc - Allocate buffer and read VPD into it
2542 * @size: pointer to field where VPD length is returned
2544 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2546 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2549 * pci_vpd_find_id_string - Locate id string in VPD
2550 * @buf: Pointer to buffered VPD data
2551 * @len: The length of the buffer area in which to search
2552 * @size: Pointer to field where length of id string is returned
2554 * Returns the index of the id string or -ENOENT if not found.
2556 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2559 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2560 * @buf: Pointer to buffered VPD data
2561 * @len: The length of the buffer area in which to search
2562 * @kw: The keyword to search for
2563 * @size: Pointer to field where length of found keyword data is returned
2565 * Returns the index of the information field keyword data or -ENOENT if
2568 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2569 const char *kw, unsigned int *size);
2572 * pci_vpd_check_csum - Check VPD checksum
2573 * @buf: Pointer to buffered VPD data
2576 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2578 int pci_vpd_check_csum(const void *buf, unsigned int len);
2580 /* PCI <-> OF binding helpers */
2584 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2585 bool pci_host_of_has_msi_map(struct device *dev);
2587 /* Arch may override this (weak) */
2588 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2590 #else /* CONFIG_OF */
2591 static inline struct irq_domain *
2592 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2593 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2594 #endif /* CONFIG_OF */
2596 static inline struct device_node *
2597 pci_device_to_OF_node(const struct pci_dev *pdev)
2599 return pdev ? pdev->dev.of_node : NULL;
2602 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2604 return bus ? bus->dev.of_node : NULL;
2608 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2611 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2612 bool pci_pr3_present(struct pci_dev *pdev);
2614 static inline struct irq_domain *
2615 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2616 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2620 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2622 return pdev->dev.archdata.edev;
2626 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2627 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2628 int pci_for_each_dma_alias(struct pci_dev *pdev,
2629 int (*fn)(struct pci_dev *pdev,
2630 u16 alias, void *data), void *data);
2632 /* Helper functions for operation of device flag */
2633 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2635 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2637 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2639 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2641 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2643 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2647 * pci_ari_enabled - query ARI forwarding status
2650 * Returns true if ARI forwarding is enabled.
2652 static inline bool pci_ari_enabled(struct pci_bus *bus)
2654 return bus->self && bus->self->ari_enabled;
2658 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2659 * @pdev: PCI device to check
2661 * Walk upwards from @pdev and check for each encountered bridge if it's part
2662 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2663 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2665 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2667 struct pci_dev *parent = pdev;
2669 if (pdev->is_thunderbolt)
2672 while ((parent = pci_upstream_bridge(parent)))
2673 if (parent->is_thunderbolt)
2679 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2680 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2683 #include <linux/dma-mapping.h>
2685 #define pci_printk(level, pdev, fmt, arg...) \
2686 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2688 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2689 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2690 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2691 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2692 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2693 #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg)
2694 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2695 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2696 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2698 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2699 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2701 #define pci_info_ratelimited(pdev, fmt, arg...) \
2702 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2704 #define pci_WARN(pdev, condition, fmt, arg...) \
2705 WARN(condition, "%s %s: " fmt, \
2706 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2708 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2709 WARN_ONCE(condition, "%s %s: " fmt, \
2710 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2712 #endif /* LINUX_PCI_H */