1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
27 #include <linux/mod_devicetable.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
43 #include <linux/pci_ids.h>
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
52 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
53 #define PCI_NUM_RESET_METHODS 7
55 #define PCI_RESET_PROBE true
56 #define PCI_RESET_DO_RESET false
59 * The PCI interface treats multi-function devices as independent
60 * devices. The slot/function address of each device is encoded
61 * in a single byte as follows:
66 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
67 * In the interest of not exposing interfaces to user-space unnecessarily,
68 * the following kernel-only defines are being added here.
70 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
71 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
72 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74 /* pci_slot represents a physical slot */
76 struct pci_bus *bus; /* Bus this slot is on */
77 struct list_head list; /* Node in list of slots */
78 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
79 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
83 static inline const char *pci_slot_name(const struct pci_slot *slot)
85 return kobject_name(&slot->kobj);
88 /* File state for mmap()s on /proc/bus/pci/X/Y */
94 /* For PCI devices, the region numbers are assigned this way: */
96 /* #0-5: standard PCI resources */
98 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
100 /* #6: expansion ROM resource */
103 /* Device-specific resources */
104 #ifdef CONFIG_PCI_IOV
106 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
109 /* PCI-to-PCI (P2P) bridge windows */
110 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
111 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
112 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114 /* CardBus bridge windows */
115 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
116 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
117 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
118 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120 /* Total number of bridge resources for P2P and CardBus */
121 #define PCI_BRIDGE_RESOURCE_NUM 4
123 /* Resources assigned to buses behind the bridge */
124 PCI_BRIDGE_RESOURCES,
125 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
126 PCI_BRIDGE_RESOURCE_NUM - 1,
128 /* Total resources associated with a PCI device */
131 /* Preserve this for compatibility */
132 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
136 * enum pci_interrupt_pin - PCI INTx interrupt values
137 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
138 * @PCI_INTERRUPT_INTA: PCI INTA pin
139 * @PCI_INTERRUPT_INTB: PCI INTB pin
140 * @PCI_INTERRUPT_INTC: PCI INTC pin
141 * @PCI_INTERRUPT_INTD: PCI INTD pin
143 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
144 * PCI_INTERRUPT_PIN register.
146 enum pci_interrupt_pin {
147 PCI_INTERRUPT_UNKNOWN,
154 /* The number of legacy PCI INTx interrupts */
155 #define PCI_NUM_INTX 4
158 * Reading from a device that doesn't respond typically returns ~0. A
159 * successful read from a device may also return ~0, so you need additional
160 * information to reliably identify errors.
162 #define PCI_ERROR_RESPONSE (~0ULL)
163 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
164 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
167 * pci_power_t values must match the bits in the Capabilities PME_Support
168 * and Control/Status PowerState fields in the Power Management capability.
170 typedef int __bitwise pci_power_t;
172 #define PCI_D0 ((pci_power_t __force) 0)
173 #define PCI_D1 ((pci_power_t __force) 1)
174 #define PCI_D2 ((pci_power_t __force) 2)
175 #define PCI_D3hot ((pci_power_t __force) 3)
176 #define PCI_D3cold ((pci_power_t __force) 4)
177 #define PCI_UNKNOWN ((pci_power_t __force) 5)
178 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
180 /* Remember to update this when the list above changes! */
181 extern const char *pci_power_names[];
183 static inline const char *pci_power_name(pci_power_t state)
185 return pci_power_names[1 + (__force int) state];
189 * typedef pci_channel_state_t
191 * The pci_channel state describes connectivity between the CPU and
192 * the PCI device. If some PCI bus between here and the PCI device
193 * has crashed or locked up, this info is reflected here.
195 typedef unsigned int __bitwise pci_channel_state_t;
198 /* I/O channel is in normal state */
199 pci_channel_io_normal = (__force pci_channel_state_t) 1,
201 /* I/O to channel is blocked */
202 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
204 /* PCI card is dead */
205 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
208 typedef unsigned int __bitwise pcie_reset_state_t;
210 enum pcie_reset_state {
211 /* Reset is NOT asserted (Use to deassert reset) */
212 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
214 /* Use #PERST to reset PCIe device */
215 pcie_warm_reset = (__force pcie_reset_state_t) 2,
217 /* Use PCIe Hot Reset to reset device */
218 pcie_hot_reset = (__force pcie_reset_state_t) 3
221 typedef unsigned short __bitwise pci_dev_flags_t;
223 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
224 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
225 /* Device configuration is irrevocably lost if disabled into D3 */
226 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
227 /* Provide indication device is assigned by a Virtual Machine Manager */
228 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
229 /* Flag for quirk use to store if quirk-specific ACS is enabled */
230 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
231 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
232 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
233 /* Do not use bus resets for device */
234 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
235 /* Do not use PM reset even if device advertises NoSoftRst- */
236 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
237 /* Get VPD from function 0 VPD */
238 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
239 /* A non-root bridge where translation occurs, stop alias search here */
240 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
241 /* Do not use FLR even if device advertises PCI_AF_CAP */
242 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
243 /* Don't use Relaxed Ordering for TLPs directed at this device */
244 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
245 /* Device does honor MSI masking despite saying otherwise */
246 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
249 enum pci_irq_reroute_variant {
250 INTEL_IRQ_REROUTE_VARIANT = 1,
251 MAX_IRQ_REROUTE_VARIANTS = 3
254 typedef unsigned short __bitwise pci_bus_flags_t;
256 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
257 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
258 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
259 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
262 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
263 enum pcie_link_width {
264 PCIE_LNK_WIDTH_RESRV = 0x00,
272 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
275 /* See matching string table in pci_speed_string() */
277 PCI_SPEED_33MHz = 0x00,
278 PCI_SPEED_66MHz = 0x01,
279 PCI_SPEED_66MHz_PCIX = 0x02,
280 PCI_SPEED_100MHz_PCIX = 0x03,
281 PCI_SPEED_133MHz_PCIX = 0x04,
282 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
283 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
284 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
285 PCI_SPEED_66MHz_PCIX_266 = 0x09,
286 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
287 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
293 PCI_SPEED_66MHz_PCIX_533 = 0x11,
294 PCI_SPEED_100MHz_PCIX_533 = 0x12,
295 PCI_SPEED_133MHz_PCIX_533 = 0x13,
296 PCIE_SPEED_2_5GT = 0x14,
297 PCIE_SPEED_5_0GT = 0x15,
298 PCIE_SPEED_8_0GT = 0x16,
299 PCIE_SPEED_16_0GT = 0x17,
300 PCIE_SPEED_32_0GT = 0x18,
301 PCIE_SPEED_64_0GT = 0x19,
302 PCI_SPEED_UNKNOWN = 0xff,
305 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
306 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
315 struct pcie_link_state;
320 /* The pci_dev structure describes PCI devices */
322 struct list_head bus_list; /* Node in per-bus list */
323 struct pci_bus *bus; /* Bus this device is on */
324 struct pci_bus *subordinate; /* Bus this device bridges to */
326 void *sysdata; /* Hook for sys-specific extension */
327 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
328 struct pci_slot *slot; /* Physical slot this device is in */
330 unsigned int devfn; /* Encoded device & function index */
331 unsigned short vendor;
332 unsigned short device;
333 unsigned short subsystem_vendor;
334 unsigned short subsystem_device;
335 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
336 u8 revision; /* PCI revision, low byte of class word */
337 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
338 #ifdef CONFIG_PCIEAER
339 u16 aer_cap; /* AER capability offset */
340 struct aer_stats *aer_stats; /* AER stats for this device */
342 #ifdef CONFIG_PCIEPORTBUS
343 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
344 struct pci_dev *rcec; /* Associated RCEC device */
346 u32 devcap; /* PCIe Device Capabilities */
347 u8 pcie_cap; /* PCIe capability offset */
348 u8 msi_cap; /* MSI capability offset */
349 u8 msix_cap; /* MSI-X capability offset */
350 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
351 u8 rom_base_reg; /* Config register controlling ROM */
352 u8 pin; /* Interrupt pin this device uses */
353 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
354 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
356 struct pci_driver *driver; /* Driver bound to this device */
357 u64 dma_mask; /* Mask of the bits of bus address this
358 device implements. Normally this is
359 0xffffffff. You only need to change
360 this if your device has broken DMA
361 or supports 64-bit transfers. */
363 struct device_dma_parameters dma_parms;
365 pci_power_t current_state; /* Current operating state. In ACPI,
366 this is D0-D3, D0 being fully
367 functional, and D3 being off. */
368 unsigned int imm_ready:1; /* Supports Immediate Readiness */
369 u8 pm_cap; /* PM capability offset */
370 unsigned int pme_support:5; /* Bitmask of states from which PME#
372 unsigned int pme_poll:1; /* Poll device's PME status bit */
373 unsigned int d1_support:1; /* Low power state D1 is supported */
374 unsigned int d2_support:1; /* Low power state D2 is supported */
375 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
376 unsigned int no_d3cold:1; /* D3cold is forbidden */
377 unsigned int bridge_d3:1; /* Allow D3 for bridge */
378 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
379 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
380 decoding during BAR sizing */
381 unsigned int wakeup_prepared:1;
382 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
383 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
384 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
385 controlled exclusively by
387 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
389 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
390 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
392 #ifdef CONFIG_PCIEASPM
393 struct pcie_link_state *link_state; /* ASPM link state */
394 unsigned int ltr_path:1; /* Latency Tolerance Reporting
395 supported from root to here */
396 u16 l1ss; /* L1SS Capability pointer */
398 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
399 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
401 pci_channel_state_t error_state; /* Current connectivity state */
402 struct device dev; /* Generic device interface */
404 int cfg_size; /* Size of config space */
407 * Instead of touching interrupt line and base address registers
408 * directly, use the values stored here. They might be different!
411 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
413 bool match_driver; /* Skip attaching driver */
415 unsigned int transparent:1; /* Subtractive decode bridge */
416 unsigned int io_window:1; /* Bridge has I/O window */
417 unsigned int pref_window:1; /* Bridge has pref mem window */
418 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
419 unsigned int multifunction:1; /* Multi-function device */
421 unsigned int is_busmaster:1; /* Is busmaster */
422 unsigned int no_msi:1; /* May not use MSI */
423 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
424 unsigned int block_cfg_access:1; /* Config space access blocked */
425 unsigned int broken_parity_status:1; /* Generates false positive parity */
426 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
427 unsigned int msi_enabled:1;
428 unsigned int msix_enabled:1;
429 unsigned int ari_enabled:1; /* ARI forwarding */
430 unsigned int ats_enabled:1; /* Address Translation Svc */
431 unsigned int pasid_enabled:1; /* Process Address Space ID */
432 unsigned int pri_enabled:1; /* Page Request Interface */
433 unsigned int is_managed:1; /* Managed via devres */
434 unsigned int is_msi_managed:1; /* MSI release via devres installed */
435 unsigned int needs_freset:1; /* Requires fundamental reset */
436 unsigned int state_saved:1;
437 unsigned int is_physfn:1;
438 unsigned int is_virtfn:1;
439 unsigned int is_hotplug_bridge:1;
440 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
441 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
443 * Devices marked being untrusted are the ones that can potentially
444 * execute DMA attacks and similar. They are typically connected
445 * through external ports such as Thunderbolt but not limited to
446 * that. When an IOMMU is enabled they should be getting full
447 * mappings to make sure they cannot access arbitrary memory.
449 unsigned int untrusted:1;
451 * Info from the platform, e.g., ACPI or device tree, may mark a
452 * device as "external-facing". An external-facing device is
453 * itself internal but devices downstream from it are external.
455 unsigned int external_facing:1;
456 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
457 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
458 unsigned int irq_managed:1;
459 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
460 unsigned int is_probed:1; /* Device probing in progress */
461 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
462 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
463 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
464 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
465 pci_dev_flags_t dev_flags;
466 atomic_t enable_cnt; /* pci_enable_device has been called */
468 u32 saved_config_space[16]; /* Config space saved at suspend time */
469 struct hlist_head saved_cap_space;
470 int rom_attr_enabled; /* Display of ROM attribute enabled? */
471 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
472 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
474 #ifdef CONFIG_HOTPLUG_PCI_PCIE
475 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
477 #ifdef CONFIG_PCIE_PTM
478 unsigned int ptm_root:1;
479 unsigned int ptm_enabled:1;
482 #ifdef CONFIG_PCI_MSI
483 void __iomem *msix_base;
484 raw_spinlock_t msi_lock;
487 #ifdef CONFIG_PCIE_DPC
489 unsigned int dpc_rp_extensions:1;
492 #ifdef CONFIG_PCI_ATS
494 struct pci_sriov *sriov; /* PF: SR-IOV info */
495 struct pci_dev *physfn; /* VF: related PF */
497 u16 ats_cap; /* ATS Capability offset */
498 u8 ats_stu; /* ATS Smallest Translation Unit */
500 #ifdef CONFIG_PCI_PRI
501 u16 pri_cap; /* PRI Capability offset */
502 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
503 unsigned int pasid_required:1; /* PRG Response PASID Required */
505 #ifdef CONFIG_PCI_PASID
506 u16 pasid_cap; /* PASID Capability offset */
509 #ifdef CONFIG_PCI_P2PDMA
510 struct pci_p2pdma __rcu *p2pdma;
512 u16 acs_cap; /* ACS Capability offset */
513 phys_addr_t rom; /* Physical address if not from BAR */
514 size_t romlen; /* Length if not from BAR */
515 char *driver_override; /* Driver name to force a match */
517 unsigned long priv_flags; /* Private flags for the PCI driver */
519 /* These methods index pci_reset_fn_methods[] */
520 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
523 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
525 #ifdef CONFIG_PCI_IOV
532 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
534 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
535 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
537 static inline int pci_channel_offline(struct pci_dev *pdev)
539 return (pdev->error_state != pci_channel_io_normal);
543 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
544 * Group number is limited to a 16-bit value, therefore (int)-1 is
545 * not a valid PCI domain number, and can be used as a sentinel
546 * value indicating ->domain_nr is not set by the driver (and
547 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
548 * pci_bus_find_domain_nr()).
550 #define PCI_DOMAIN_NR_NOT_SET (-1)
552 struct pci_host_bridge {
554 struct pci_bus *bus; /* Root bus */
556 struct pci_ops *child_ops;
560 struct list_head windows; /* resource_entry */
561 struct list_head dma_ranges; /* dma ranges resource list */
562 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
563 int (*map_irq)(const struct pci_dev *, u8, u8);
564 void (*release_fn)(struct pci_host_bridge *);
566 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
567 unsigned int no_ext_tags:1; /* No Extended Tags */
568 unsigned int native_aer:1; /* OS may use PCIe AER */
569 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
570 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
571 unsigned int native_pme:1; /* OS may use PCIe PME */
572 unsigned int native_ltr:1; /* OS may use PCIe LTR */
573 unsigned int native_dpc:1; /* OS may use PCIe DPC */
574 unsigned int preserve_config:1; /* Preserve FW resource setup */
575 unsigned int size_windows:1; /* Enable root bus sizing */
576 unsigned int msi_domain:1; /* Bridge wants MSI domain */
578 /* Resource alignment requirements */
579 resource_size_t (*align_resource)(struct pci_dev *dev,
580 const struct resource *res,
581 resource_size_t start,
582 resource_size_t size,
583 resource_size_t align);
584 unsigned long private[] ____cacheline_aligned;
587 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
589 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
591 return (void *)bridge->private;
594 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
596 return container_of(priv, struct pci_host_bridge, private);
599 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
600 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
602 void pci_free_host_bridge(struct pci_host_bridge *bridge);
603 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
605 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
606 void (*release_fn)(struct pci_host_bridge *),
609 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
612 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
613 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
614 * buses below host bridges or subtractive decode bridges) go in the list.
615 * Use pci_bus_for_each_resource() to iterate through all the resources.
619 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
620 * and there's no way to program the bridge with the details of the window.
621 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
622 * decode bit set, because they are explicit and can be programmed with _SRS.
624 #define PCI_SUBTRACTIVE_DECODE 0x1
626 struct pci_bus_resource {
627 struct list_head list;
628 struct resource *res;
632 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
635 struct list_head node; /* Node in list of buses */
636 struct pci_bus *parent; /* Parent bus this bridge is on */
637 struct list_head children; /* List of child buses */
638 struct list_head devices; /* List of devices on this bus */
639 struct pci_dev *self; /* Bridge device as seen by parent */
640 struct list_head slots; /* List of slots on this bus;
641 protected by pci_slot_mutex */
642 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
643 struct list_head resources; /* Address space routed to this bus */
644 struct resource busn_res; /* Bus numbers routed to this bus */
646 struct pci_ops *ops; /* Configuration access functions */
647 void *sysdata; /* Hook for sys-specific extension */
648 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
650 unsigned char number; /* Bus number */
651 unsigned char primary; /* Number of primary bridge */
652 unsigned char max_bus_speed; /* enum pci_bus_speed */
653 unsigned char cur_bus_speed; /* enum pci_bus_speed */
654 #ifdef CONFIG_PCI_DOMAINS_GENERIC
660 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
661 pci_bus_flags_t bus_flags; /* Inherited by child buses */
662 struct device *bridge;
664 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
665 struct bin_attribute *legacy_mem; /* Legacy mem */
666 unsigned int is_added:1;
667 unsigned int unsafe_warn:1; /* warned about RW1C config write */
670 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
672 static inline u16 pci_dev_id(struct pci_dev *dev)
674 return PCI_DEVID(dev->bus->number, dev->devfn);
678 * Returns true if the PCI bus is root (behind host-PCI bridge),
681 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
682 * This is incorrect because "virtual" buses added for SR-IOV (via
683 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
685 static inline bool pci_is_root_bus(struct pci_bus *pbus)
687 return !(pbus->parent);
691 * pci_is_bridge - check if the PCI device is a bridge
694 * Return true if the PCI device is bridge whether it has subordinate
697 static inline bool pci_is_bridge(struct pci_dev *dev)
699 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
700 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
703 #define for_each_pci_bridge(dev, bus) \
704 list_for_each_entry(dev, &bus->devices, bus_list) \
705 if (!pci_is_bridge(dev)) {} else
707 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
709 dev = pci_physfn(dev);
710 if (pci_is_root_bus(dev->bus))
713 return dev->bus->self;
716 #ifdef CONFIG_PCI_MSI
717 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
719 return pci_dev->msi_enabled || pci_dev->msix_enabled;
722 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
725 /* Error values that may be returned by PCI functions */
726 #define PCIBIOS_SUCCESSFUL 0x00
727 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
728 #define PCIBIOS_BAD_VENDOR_ID 0x83
729 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
730 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
731 #define PCIBIOS_SET_FAILED 0x88
732 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
734 /* Translate above to generic errno for passing back through non-PCI code */
735 static inline int pcibios_err_to_errno(int err)
737 if (err <= PCIBIOS_SUCCESSFUL)
738 return err; /* Assume already errno */
741 case PCIBIOS_FUNC_NOT_SUPPORTED:
743 case PCIBIOS_BAD_VENDOR_ID:
745 case PCIBIOS_DEVICE_NOT_FOUND:
747 case PCIBIOS_BAD_REGISTER_NUMBER:
749 case PCIBIOS_SET_FAILED:
751 case PCIBIOS_BUFFER_TOO_SMALL:
758 /* Low-level architecture-dependent routines */
761 int (*add_bus)(struct pci_bus *bus);
762 void (*remove_bus)(struct pci_bus *bus);
763 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
764 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
765 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
769 * ACPI needs to be able to access PCI config space before we've done a
770 * PCI bus scan and created pci_bus structures.
772 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
773 int reg, int len, u32 *val);
774 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
775 int reg, int len, u32 val);
777 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
778 typedef u64 pci_bus_addr_t;
780 typedef u32 pci_bus_addr_t;
783 struct pci_bus_region {
784 pci_bus_addr_t start;
789 spinlock_t lock; /* Protects list, index */
790 struct list_head list; /* For IDs added at runtime */
795 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
796 * a set of callbacks in struct pci_error_handlers, that device driver
797 * will be notified of PCI bus errors, and will be driven to recovery
798 * when an error occurs.
801 typedef unsigned int __bitwise pci_ers_result_t;
803 enum pci_ers_result {
804 /* No result/none/not supported in device driver */
805 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
807 /* Device driver can recover without slot reset */
808 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
810 /* Device driver wants slot to be reset */
811 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
813 /* Device has completely failed, is unrecoverable */
814 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
816 /* Device driver is fully recovered and operational */
817 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
819 /* No AER capabilities registered for the driver */
820 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
823 /* PCI bus error event callbacks */
824 struct pci_error_handlers {
825 /* PCI bus error detected on this device */
826 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
827 pci_channel_state_t error);
829 /* MMIO has been re-enabled, but not DMA */
830 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
832 /* PCI slot has been reset */
833 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
835 /* PCI function reset prepare or completed */
836 void (*reset_prepare)(struct pci_dev *dev);
837 void (*reset_done)(struct pci_dev *dev);
839 /* Device driver may resume normal operations */
840 void (*resume)(struct pci_dev *dev);
847 * struct pci_driver - PCI driver structure
848 * @node: List of driver structures.
849 * @name: Driver name.
850 * @id_table: Pointer to table of device IDs the driver is
851 * interested in. Most drivers should export this
852 * table using MODULE_DEVICE_TABLE(pci,...).
853 * @probe: This probing function gets called (during execution
854 * of pci_register_driver() for already existing
855 * devices or later if a new device gets inserted) for
856 * all PCI devices which match the ID table and are not
857 * "owned" by the other drivers yet. This function gets
858 * passed a "struct pci_dev \*" for each device whose
859 * entry in the ID table matches the device. The probe
860 * function returns zero when the driver chooses to
861 * take "ownership" of the device or an error code
862 * (negative number) otherwise.
863 * The probe function always gets called from process
864 * context, so it can sleep.
865 * @remove: The remove() function gets called whenever a device
866 * being handled by this driver is removed (either during
867 * deregistration of the driver or when it's manually
868 * pulled out of a hot-pluggable slot).
869 * The remove function always gets called from process
870 * context, so it can sleep.
871 * @suspend: Put device into low power state.
872 * @resume: Wake device from low power state.
873 * (Please see Documentation/power/pci.rst for descriptions
874 * of PCI Power Management and the related functions.)
875 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
876 * Intended to stop any idling DMA operations.
877 * Useful for enabling wake-on-lan (NIC) or changing
878 * the power state of a device before reboot.
879 * e.g. drivers/net/e100.c.
880 * @sriov_configure: Optional driver callback to allow configuration of
881 * number of VFs to enable via sysfs "sriov_numvfs" file.
882 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
883 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
884 * This will change MSI-X Table Size in the VF Message Control
886 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
887 * MSI-X vectors available for distribution to the VFs.
888 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
889 * @groups: Sysfs attribute groups.
890 * @dev_groups: Attributes attached to the device that will be
891 * created once it is bound to the driver.
892 * @driver: Driver model structure.
893 * @dynids: List of dynamically added device IDs.
896 struct list_head node;
898 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
899 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
900 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
901 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
902 int (*resume)(struct pci_dev *dev); /* Device woken up */
903 void (*shutdown)(struct pci_dev *dev);
904 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
905 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
906 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
907 const struct pci_error_handlers *err_handler;
908 const struct attribute_group **groups;
909 const struct attribute_group **dev_groups;
910 struct device_driver driver;
911 struct pci_dynids dynids;
914 static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
916 return drv ? container_of(drv, struct pci_driver, driver) : NULL;
920 * PCI_DEVICE - macro used to describe a specific PCI device
921 * @vend: the 16 bit PCI Vendor ID
922 * @dev: the 16 bit PCI Device ID
924 * This macro is used to create a struct pci_device_id that matches a
925 * specific device. The subvendor and subdevice fields will be set to
928 #define PCI_DEVICE(vend,dev) \
929 .vendor = (vend), .device = (dev), \
930 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
933 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
934 * override_only flags.
935 * @vend: the 16 bit PCI Vendor ID
936 * @dev: the 16 bit PCI Device ID
937 * @driver_override: the 32 bit PCI Device override_only
939 * This macro is used to create a struct pci_device_id that matches only a
940 * driver_override device. The subvendor and subdevice fields will be set to
943 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
944 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
945 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
948 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
949 * "driver_override" PCI device.
950 * @vend: the 16 bit PCI Vendor ID
951 * @dev: the 16 bit PCI Device ID
953 * This macro is used to create a struct pci_device_id that matches a
954 * specific device. The subvendor and subdevice fields will be set to
955 * PCI_ANY_ID and the driver_override will be set to
956 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
958 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
959 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
962 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
963 * @vend: the 16 bit PCI Vendor ID
964 * @dev: the 16 bit PCI Device ID
965 * @subvend: the 16 bit PCI Subvendor ID
966 * @subdev: the 16 bit PCI Subdevice ID
968 * This macro is used to create a struct pci_device_id that matches a
969 * specific device with subsystem information.
971 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
972 .vendor = (vend), .device = (dev), \
973 .subvendor = (subvend), .subdevice = (subdev)
976 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
977 * @dev_class: the class, subclass, prog-if triple for this device
978 * @dev_class_mask: the class mask for this device
980 * This macro is used to create a struct pci_device_id that matches a
981 * specific PCI class. The vendor, device, subvendor, and subdevice
982 * fields will be set to PCI_ANY_ID.
984 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
985 .class = (dev_class), .class_mask = (dev_class_mask), \
986 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
987 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
990 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
991 * @vend: the vendor name
992 * @dev: the 16 bit PCI Device ID
994 * This macro is used to create a struct pci_device_id that matches a
995 * specific PCI device. The subvendor, and subdevice fields will be set
996 * to PCI_ANY_ID. The macro allows the next field to follow as the device
999 #define PCI_VDEVICE(vend, dev) \
1000 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1001 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1004 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1005 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1006 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1007 * @data: the driver data to be filled
1009 * This macro is used to create a struct pci_device_id that matches a
1010 * specific PCI device. The subvendor, and subdevice fields will be set
1013 #define PCI_DEVICE_DATA(vend, dev, data) \
1014 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1015 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1016 .driver_data = (kernel_ulong_t)(data)
1019 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1020 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1021 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1022 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1023 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1024 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1025 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1028 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1029 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1030 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1031 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1033 /* These external functions are only available when PCI support is enabled */
1036 extern unsigned int pci_flags;
1038 static inline void pci_set_flags(int flags) { pci_flags = flags; }
1039 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
1040 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
1041 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1043 void pcie_bus_configure_settings(struct pci_bus *bus);
1045 enum pcie_bus_config_types {
1046 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1047 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1048 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1049 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1050 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1053 extern enum pcie_bus_config_types pcie_bus_config;
1055 extern struct bus_type pci_bus_type;
1057 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1058 * code, or PCI core code. */
1059 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1060 /* Some device drivers need know if PCI is initiated */
1061 int no_pci_devices(void);
1063 void pcibios_resource_survey_bus(struct pci_bus *bus);
1064 void pcibios_bus_add_device(struct pci_dev *pdev);
1065 void pcibios_add_bus(struct pci_bus *bus);
1066 void pcibios_remove_bus(struct pci_bus *bus);
1067 void pcibios_fixup_bus(struct pci_bus *);
1068 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1069 /* Architecture-specific versions may override this (weak) */
1070 char *pcibios_setup(char *str);
1072 /* Used only when drivers/pci/setup.c is used */
1073 resource_size_t pcibios_align_resource(void *, const struct resource *,
1077 /* Weak but can be overridden by arch */
1078 void pci_fixup_cardbus(struct pci_bus *);
1080 /* Generic PCI functions used internally */
1082 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1083 struct resource *res);
1084 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1085 struct pci_bus_region *region);
1086 void pcibios_scan_specific_bus(int busn);
1087 struct pci_bus *pci_find_bus(int domain, int busnr);
1088 void pci_bus_add_devices(const struct pci_bus *bus);
1089 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1090 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1091 struct pci_ops *ops, void *sysdata,
1092 struct list_head *resources);
1093 int pci_host_probe(struct pci_host_bridge *bridge);
1094 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1095 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1096 void pci_bus_release_busn_res(struct pci_bus *b);
1097 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1098 struct pci_ops *ops, void *sysdata,
1099 struct list_head *resources);
1100 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1101 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1103 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1105 struct hotplug_slot *hotplug);
1106 void pci_destroy_slot(struct pci_slot *slot);
1108 void pci_dev_assign_slot(struct pci_dev *dev);
1110 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1112 int pci_scan_slot(struct pci_bus *bus, int devfn);
1113 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1114 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1115 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1116 void pci_bus_add_device(struct pci_dev *dev);
1117 void pci_read_bridge_bases(struct pci_bus *child);
1118 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1119 struct resource *res);
1120 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1121 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1122 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1123 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1124 void pci_dev_put(struct pci_dev *dev);
1125 void pci_remove_bus(struct pci_bus *b);
1126 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1127 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1128 void pci_stop_root_bus(struct pci_bus *bus);
1129 void pci_remove_root_bus(struct pci_bus *bus);
1130 void pci_setup_cardbus(struct pci_bus *bus);
1131 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1132 void pci_sort_breadthfirst(void);
1133 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1134 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1136 /* Generic PCI functions exported to card drivers */
1138 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1139 u8 pci_find_capability(struct pci_dev *dev, int cap);
1140 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1141 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1142 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1143 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1144 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1145 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1146 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1147 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1149 u64 pci_get_dsn(struct pci_dev *dev);
1151 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1152 struct pci_dev *from);
1153 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1154 unsigned int ss_vendor, unsigned int ss_device,
1155 struct pci_dev *from);
1156 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1157 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1158 unsigned int devfn);
1159 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1160 int pci_dev_present(const struct pci_device_id *ids);
1162 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1163 int where, u8 *val);
1164 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1165 int where, u16 *val);
1166 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1167 int where, u32 *val);
1168 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1170 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1171 int where, u16 val);
1172 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1173 int where, u32 val);
1175 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1176 int where, int size, u32 *val);
1177 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1178 int where, int size, u32 val);
1179 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1180 int where, int size, u32 *val);
1181 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1182 int where, int size, u32 val);
1184 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1186 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1187 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1188 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1189 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1190 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1191 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1193 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1194 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1195 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1196 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1197 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1198 u16 clear, u16 set);
1199 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1200 u32 clear, u32 set);
1202 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1205 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1208 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1211 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1214 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1217 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1220 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1223 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1226 /* User-space driven config access */
1227 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1228 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1229 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1230 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1231 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1232 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1234 int __must_check pci_enable_device(struct pci_dev *dev);
1235 int __must_check pci_enable_device_io(struct pci_dev *dev);
1236 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1237 int __must_check pci_reenable_device(struct pci_dev *);
1238 int __must_check pcim_enable_device(struct pci_dev *pdev);
1239 void pcim_pin_device(struct pci_dev *pdev);
1241 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1244 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1245 * writable and no quirk has marked the feature broken.
1247 return !pdev->broken_intx_masking;
1250 static inline int pci_is_enabled(struct pci_dev *pdev)
1252 return (atomic_read(&pdev->enable_cnt) > 0);
1255 static inline int pci_is_managed(struct pci_dev *pdev)
1257 return pdev->is_managed;
1260 void pci_disable_device(struct pci_dev *dev);
1262 extern unsigned int pcibios_max_latency;
1263 void pci_set_master(struct pci_dev *dev);
1264 void pci_clear_master(struct pci_dev *dev);
1266 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1267 int pci_set_cacheline_size(struct pci_dev *dev);
1268 int __must_check pci_set_mwi(struct pci_dev *dev);
1269 int __must_check pcim_set_mwi(struct pci_dev *dev);
1270 int pci_try_set_mwi(struct pci_dev *dev);
1271 void pci_clear_mwi(struct pci_dev *dev);
1272 void pci_disable_parity(struct pci_dev *dev);
1273 void pci_intx(struct pci_dev *dev, int enable);
1274 bool pci_check_and_mask_intx(struct pci_dev *dev);
1275 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1276 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1277 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1278 int pcix_get_max_mmrbc(struct pci_dev *dev);
1279 int pcix_get_mmrbc(struct pci_dev *dev);
1280 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1281 int pcie_get_readrq(struct pci_dev *dev);
1282 int pcie_set_readrq(struct pci_dev *dev, int rq);
1283 int pcie_get_mps(struct pci_dev *dev);
1284 int pcie_set_mps(struct pci_dev *dev, int mps);
1285 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1286 enum pci_bus_speed *speed,
1287 enum pcie_link_width *width);
1288 void pcie_print_link_status(struct pci_dev *dev);
1289 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1290 int pcie_flr(struct pci_dev *dev);
1291 int __pci_reset_function_locked(struct pci_dev *dev);
1292 int pci_reset_function(struct pci_dev *dev);
1293 int pci_reset_function_locked(struct pci_dev *dev);
1294 int pci_try_reset_function(struct pci_dev *dev);
1295 int pci_probe_reset_slot(struct pci_slot *slot);
1296 int pci_probe_reset_bus(struct pci_bus *bus);
1297 int pci_reset_bus(struct pci_dev *dev);
1298 void pci_reset_secondary_bus(struct pci_dev *dev);
1299 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1300 void pci_update_resource(struct pci_dev *dev, int resno);
1301 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1302 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1303 void pci_release_resource(struct pci_dev *dev, int resno);
1304 static inline int pci_rebar_bytes_to_size(u64 bytes)
1306 bytes = roundup_pow_of_two(bytes);
1308 /* Return BAR size as defined in the resizable BAR specification */
1309 return max(ilog2(bytes), 20) - 20;
1312 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1313 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1314 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1315 bool pci_device_is_present(struct pci_dev *pdev);
1316 void pci_ignore_hotplug(struct pci_dev *dev);
1317 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1318 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1320 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1321 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1322 const char *fmt, ...);
1323 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1325 /* ROM control related routines */
1326 int pci_enable_rom(struct pci_dev *pdev);
1327 void pci_disable_rom(struct pci_dev *pdev);
1328 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1329 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1331 /* Power management related routines */
1332 int pci_save_state(struct pci_dev *dev);
1333 void pci_restore_state(struct pci_dev *dev);
1334 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1335 int pci_load_saved_state(struct pci_dev *dev,
1336 struct pci_saved_state *state);
1337 int pci_load_and_free_saved_state(struct pci_dev *dev,
1338 struct pci_saved_state **state);
1339 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1340 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1341 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1342 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1343 void pci_pme_active(struct pci_dev *dev, bool enable);
1344 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1345 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1346 int pci_prepare_to_sleep(struct pci_dev *dev);
1347 int pci_back_from_sleep(struct pci_dev *dev);
1348 bool pci_dev_run_wake(struct pci_dev *dev);
1349 void pci_d3cold_enable(struct pci_dev *dev);
1350 void pci_d3cold_disable(struct pci_dev *dev);
1351 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1352 void pci_resume_bus(struct pci_bus *bus);
1353 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1355 /* For use by arch with custom probe code */
1356 void set_pcie_port_type(struct pci_dev *pdev);
1357 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1359 /* Functions for PCI Hotplug drivers to use */
1360 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1361 unsigned int pci_rescan_bus(struct pci_bus *bus);
1362 void pci_lock_rescan_remove(void);
1363 void pci_unlock_rescan_remove(void);
1365 /* Vital Product Data routines */
1366 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1367 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1368 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1369 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1371 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1372 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1373 void pci_bus_assign_resources(const struct pci_bus *bus);
1374 void pci_bus_claim_resources(struct pci_bus *bus);
1375 void pci_bus_size_bridges(struct pci_bus *bus);
1376 int pci_claim_resource(struct pci_dev *, int);
1377 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1378 void pci_assign_unassigned_resources(void);
1379 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1380 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1381 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1382 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1383 void pdev_enable_device(struct pci_dev *);
1384 int pci_enable_resources(struct pci_dev *, int mask);
1385 void pci_assign_irq(struct pci_dev *dev);
1386 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1387 #define HAVE_PCI_REQ_REGIONS 2
1388 int __must_check pci_request_regions(struct pci_dev *, const char *);
1389 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1390 void pci_release_regions(struct pci_dev *);
1391 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1392 void pci_release_region(struct pci_dev *, int);
1393 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1394 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1395 void pci_release_selected_regions(struct pci_dev *, int);
1397 /* drivers/pci/bus.c */
1398 void pci_add_resource(struct list_head *resources, struct resource *res);
1399 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1400 resource_size_t offset);
1401 void pci_free_resource_list(struct list_head *resources);
1402 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1403 unsigned int flags);
1404 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1405 void pci_bus_remove_resources(struct pci_bus *bus);
1406 int devm_request_pci_bus_resources(struct device *dev,
1407 struct list_head *resources);
1409 /* Temporary until new and working PCI SBR API in place */
1410 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1412 #define pci_bus_for_each_resource(bus, res, i) \
1414 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1417 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1418 struct resource *res, resource_size_t size,
1419 resource_size_t align, resource_size_t min,
1420 unsigned long type_mask,
1421 resource_size_t (*alignf)(void *,
1422 const struct resource *,
1428 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1429 resource_size_t size);
1430 unsigned long pci_address_to_pio(phys_addr_t addr);
1431 phys_addr_t pci_pio_to_address(unsigned long pio);
1432 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1433 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1434 phys_addr_t phys_addr);
1435 void pci_unmap_iospace(struct resource *res);
1436 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1437 resource_size_t offset,
1438 resource_size_t size);
1439 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1440 struct resource *res);
1442 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1444 struct pci_bus_region region;
1446 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1447 return region.start;
1450 /* Proper probing supporting hot-pluggable devices */
1451 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1452 const char *mod_name);
1454 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1455 #define pci_register_driver(driver) \
1456 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1458 void pci_unregister_driver(struct pci_driver *dev);
1461 * module_pci_driver() - Helper macro for registering a PCI driver
1462 * @__pci_driver: pci_driver struct
1464 * Helper macro for PCI drivers which do not do anything special in module
1465 * init/exit. This eliminates a lot of boilerplate. Each module may only
1466 * use this macro once, and calling it replaces module_init() and module_exit()
1468 #define module_pci_driver(__pci_driver) \
1469 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1472 * builtin_pci_driver() - Helper macro for registering a PCI driver
1473 * @__pci_driver: pci_driver struct
1475 * Helper macro for PCI drivers which do not do anything special in their
1476 * init code. This eliminates a lot of boilerplate. Each driver may only
1477 * use this macro once, and calling it replaces device_initcall(...)
1479 #define builtin_pci_driver(__pci_driver) \
1480 builtin_driver(__pci_driver, pci_register_driver)
1482 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1483 int pci_add_dynid(struct pci_driver *drv,
1484 unsigned int vendor, unsigned int device,
1485 unsigned int subvendor, unsigned int subdevice,
1486 unsigned int class, unsigned int class_mask,
1487 unsigned long driver_data);
1488 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1489 struct pci_dev *dev);
1490 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1493 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1495 int pci_cfg_space_size(struct pci_dev *dev);
1496 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1497 void pci_setup_bridge(struct pci_bus *bus);
1498 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1499 unsigned long type);
1501 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1502 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1504 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1505 unsigned int command_bits, u32 flags);
1508 * Virtual interrupts allow for more interrupts to be allocated
1509 * than the device has interrupts for. These are not programmed
1510 * into the device's MSI-X table and must be handled by some
1511 * other driver means.
1513 #define PCI_IRQ_VIRTUAL (1 << 4)
1515 #define PCI_IRQ_ALL_TYPES \
1516 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1518 #include <linux/dmapool.h>
1521 u32 vector; /* Kernel uses to write allocated vector */
1522 u16 entry; /* Driver uses to specify entry, OS writes */
1525 #ifdef CONFIG_PCI_MSI
1526 int pci_msi_vec_count(struct pci_dev *dev);
1527 void pci_disable_msi(struct pci_dev *dev);
1528 int pci_msix_vec_count(struct pci_dev *dev);
1529 void pci_disable_msix(struct pci_dev *dev);
1530 void pci_restore_msi_state(struct pci_dev *dev);
1531 int pci_msi_enabled(void);
1532 int pci_enable_msi(struct pci_dev *dev);
1533 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1534 int minvec, int maxvec);
1535 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1536 struct msix_entry *entries, int nvec)
1538 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1543 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1544 unsigned int max_vecs, unsigned int flags,
1545 struct irq_affinity *affd);
1547 void pci_free_irq_vectors(struct pci_dev *dev);
1548 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1549 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1552 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1553 static inline void pci_disable_msi(struct pci_dev *dev) { }
1554 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1555 static inline void pci_disable_msix(struct pci_dev *dev) { }
1556 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1557 static inline int pci_msi_enabled(void) { return 0; }
1558 static inline int pci_enable_msi(struct pci_dev *dev)
1560 static inline int pci_enable_msix_range(struct pci_dev *dev,
1561 struct msix_entry *entries, int minvec, int maxvec)
1563 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1564 struct msix_entry *entries, int nvec)
1568 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1569 unsigned int max_vecs, unsigned int flags,
1570 struct irq_affinity *aff_desc)
1572 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1577 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1581 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1583 if (WARN_ON_ONCE(nr > 0))
1587 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1590 return cpu_possible_mask;
1595 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1596 * @d: the INTx IRQ domain
1597 * @node: the DT node for the device whose interrupt we're translating
1598 * @intspec: the interrupt specifier data from the DT
1599 * @intsize: the number of entries in @intspec
1600 * @out_hwirq: pointer at which to write the hwirq number
1601 * @out_type: pointer at which to write the interrupt type
1603 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1604 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1605 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1606 * INTx value to obtain the hwirq number.
1608 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1610 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1611 struct device_node *node,
1613 unsigned int intsize,
1614 unsigned long *out_hwirq,
1615 unsigned int *out_type)
1617 const u32 intx = intspec[0];
1619 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1622 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1626 #ifdef CONFIG_PCIEPORTBUS
1627 extern bool pcie_ports_disabled;
1628 extern bool pcie_ports_native;
1630 #define pcie_ports_disabled true
1631 #define pcie_ports_native false
1634 #define PCIE_LINK_STATE_L0S BIT(0)
1635 #define PCIE_LINK_STATE_L1 BIT(1)
1636 #define PCIE_LINK_STATE_CLKPM BIT(2)
1637 #define PCIE_LINK_STATE_L1_1 BIT(3)
1638 #define PCIE_LINK_STATE_L1_2 BIT(4)
1639 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1640 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1642 #ifdef CONFIG_PCIEASPM
1643 int pci_disable_link_state(struct pci_dev *pdev, int state);
1644 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1645 void pcie_no_aspm(void);
1646 bool pcie_aspm_support_enabled(void);
1647 bool pcie_aspm_enabled(struct pci_dev *pdev);
1649 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1651 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1653 static inline void pcie_no_aspm(void) { }
1654 static inline bool pcie_aspm_support_enabled(void) { return false; }
1655 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1658 #ifdef CONFIG_PCIEAER
1659 bool pci_aer_available(void);
1661 static inline bool pci_aer_available(void) { return false; }
1664 bool pci_ats_disabled(void);
1666 #ifdef CONFIG_PCIE_PTM
1667 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1668 bool pcie_ptm_enabled(struct pci_dev *dev);
1670 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1672 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1676 void pci_cfg_access_lock(struct pci_dev *dev);
1677 bool pci_cfg_access_trylock(struct pci_dev *dev);
1678 void pci_cfg_access_unlock(struct pci_dev *dev);
1680 void pci_dev_lock(struct pci_dev *dev);
1681 int pci_dev_trylock(struct pci_dev *dev);
1682 void pci_dev_unlock(struct pci_dev *dev);
1685 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1686 * a PCI domain is defined to be a set of PCI buses which share
1687 * configuration space.
1689 #ifdef CONFIG_PCI_DOMAINS
1690 extern int pci_domains_supported;
1692 enum { pci_domains_supported = 0 };
1693 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1694 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1695 #endif /* CONFIG_PCI_DOMAINS */
1698 * Generic implementation for PCI domain support. If your
1699 * architecture does not need custom management of PCI
1700 * domains then this implementation will be used
1702 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1703 static inline int pci_domain_nr(struct pci_bus *bus)
1705 return bus->domain_nr;
1708 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1710 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1713 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1716 /* Some architectures require additional setup to direct VGA traffic */
1717 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1718 unsigned int command_bits, u32 flags);
1719 void pci_register_set_vga_state(arch_set_vga_state_t func);
1722 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1724 return pci_request_selected_regions(pdev,
1725 pci_select_bars(pdev, IORESOURCE_IO), name);
1729 pci_release_io_regions(struct pci_dev *pdev)
1731 return pci_release_selected_regions(pdev,
1732 pci_select_bars(pdev, IORESOURCE_IO));
1736 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1738 return pci_request_selected_regions(pdev,
1739 pci_select_bars(pdev, IORESOURCE_MEM), name);
1743 pci_release_mem_regions(struct pci_dev *pdev)
1745 return pci_release_selected_regions(pdev,
1746 pci_select_bars(pdev, IORESOURCE_MEM));
1749 #else /* CONFIG_PCI is not enabled */
1751 static inline void pci_set_flags(int flags) { }
1752 static inline void pci_add_flags(int flags) { }
1753 static inline void pci_clear_flags(int flags) { }
1754 static inline int pci_has_flag(int flag) { return 0; }
1757 * If the system does not have PCI, clearly these return errors. Define
1758 * these as simple inline functions to avoid hair in drivers.
1760 #define _PCI_NOP(o, s, t) \
1761 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1763 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1765 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1766 _PCI_NOP(o, word, u16 x) \
1767 _PCI_NOP(o, dword, u32 x)
1768 _PCI_NOP_ALL(read, *)
1769 _PCI_NOP_ALL(write,)
1771 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1772 unsigned int device,
1773 struct pci_dev *from)
1776 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1777 unsigned int device,
1778 unsigned int ss_vendor,
1779 unsigned int ss_device,
1780 struct pci_dev *from)
1783 static inline struct pci_dev *pci_get_class(unsigned int class,
1784 struct pci_dev *from)
1788 static inline int pci_dev_present(const struct pci_device_id *ids)
1791 #define no_pci_devices() (1)
1792 #define pci_dev_put(dev) do { } while (0)
1794 static inline void pci_set_master(struct pci_dev *dev) { }
1795 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1796 static inline void pci_disable_device(struct pci_dev *dev) { }
1797 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1798 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1800 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1801 struct module *owner,
1802 const char *mod_name)
1804 static inline int pci_register_driver(struct pci_driver *drv)
1806 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1807 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1809 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1812 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1815 static inline u64 pci_get_dsn(struct pci_dev *dev)
1818 /* Power management related routines */
1819 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1820 static inline void pci_restore_state(struct pci_dev *dev) { }
1821 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1823 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1825 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1828 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1832 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1833 struct resource *res)
1835 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1837 static inline void pci_release_regions(struct pci_dev *dev) { }
1839 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1840 phys_addr_t addr, resource_size_t size)
1843 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1845 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1847 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1850 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1851 unsigned int bus, unsigned int devfn)
1854 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1855 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1857 #define dev_is_pci(d) (false)
1858 #define dev_is_pf(d) (false)
1859 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1861 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1862 struct device_node *node,
1864 unsigned int intsize,
1865 unsigned long *out_hwirq,
1866 unsigned int *out_type)
1869 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1870 struct pci_dev *dev)
1872 static inline bool pci_ats_disabled(void) { return true; }
1874 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1880 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1881 unsigned int max_vecs, unsigned int flags,
1882 struct irq_affinity *aff_desc)
1886 #endif /* CONFIG_PCI */
1889 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1890 unsigned int max_vecs, unsigned int flags)
1892 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1896 /* Include architecture-dependent settings and functions */
1898 #include <asm/pci.h>
1900 /* These two functions provide almost identical functionality. Depending
1901 * on the architecture, one will be implemented as a wrapper around the
1902 * other (in drivers/pci/mmap.c).
1904 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1905 * is expected to be an offset within that region.
1907 * pci_mmap_page_range() is the legacy architecture-specific interface,
1908 * which accepts a "user visible" resource address converted by
1909 * pci_resource_to_user(), as used in the legacy mmap() interface in
1912 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1913 struct vm_area_struct *vma,
1914 enum pci_mmap_state mmap_state, int write_combine);
1915 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1916 struct vm_area_struct *vma,
1917 enum pci_mmap_state mmap_state, int write_combine);
1919 #ifndef arch_can_pci_mmap_wc
1920 #define arch_can_pci_mmap_wc() 0
1923 #ifndef arch_can_pci_mmap_io
1924 #define arch_can_pci_mmap_io() 0
1925 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1927 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1930 #ifndef pci_root_bus_fwnode
1931 #define pci_root_bus_fwnode(bus) NULL
1935 * These helpers provide future and backwards compatibility
1936 * for accessing popular PCI BAR info
1938 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1939 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1940 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1941 #define pci_resource_len(dev,bar) \
1942 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
1944 (pci_resource_end((dev), (bar)) - \
1945 pci_resource_start((dev), (bar)) + 1))
1948 * Similar to the helpers above, these manipulate per-pci_dev
1949 * driver-specific data. They are really just a wrapper around
1950 * the generic device structure functions of these calls.
1952 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1954 return dev_get_drvdata(&pdev->dev);
1957 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1959 dev_set_drvdata(&pdev->dev, data);
1962 static inline const char *pci_name(const struct pci_dev *pdev)
1964 return dev_name(&pdev->dev);
1967 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1968 const struct resource *rsrc,
1969 resource_size_t *start, resource_size_t *end);
1972 * The world is not perfect and supplies us with broken PCI devices.
1973 * For at least a part of these bugs we need a work-around, so both
1974 * generic (drivers/pci/quirks.c) and per-architecture code can define
1975 * fixup hooks to be called for particular buggy devices.
1979 u16 vendor; /* Or PCI_ANY_ID */
1980 u16 device; /* Or PCI_ANY_ID */
1981 u32 class; /* Or PCI_ANY_ID */
1982 unsigned int class_shift; /* should be 0, 8, 16 */
1983 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1986 void (*hook)(struct pci_dev *dev);
1990 enum pci_fixup_pass {
1991 pci_fixup_early, /* Before probing BARs */
1992 pci_fixup_header, /* After reading configuration header */
1993 pci_fixup_final, /* Final phase of device fixups */
1994 pci_fixup_enable, /* pci_enable_device() time */
1995 pci_fixup_resume, /* pci_device_resume() */
1996 pci_fixup_suspend, /* pci_device_suspend() */
1997 pci_fixup_resume_early, /* pci_device_resume_early() */
1998 pci_fixup_suspend_late, /* pci_device_suspend_late() */
2001 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2002 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2003 class_shift, hook) \
2004 __ADDRESSABLE(hook) \
2005 asm(".section " #sec ", \"a\" \n" \
2007 ".short " #vendor ", " #device " \n" \
2008 ".long " #class ", " #class_shift " \n" \
2009 ".long " #hook " - . \n" \
2013 * Clang's LTO may rename static functions in C, but has no way to
2014 * handle such renamings when referenced from inline asm. To work
2015 * around this, create global C stubs for these cases.
2017 #ifdef CONFIG_LTO_CLANG
2018 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2019 class_shift, hook, stub) \
2020 void __cficanonical stub(struct pci_dev *dev); \
2021 void __cficanonical stub(struct pci_dev *dev) \
2025 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2028 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2029 class_shift, hook, stub) \
2030 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2034 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2035 class_shift, hook) \
2036 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2037 class_shift, hook, __UNIQUE_ID(hook))
2039 /* Anonymous variables would be nice... */
2040 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2041 class_shift, hook) \
2042 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2043 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2044 = { vendor, device, class, class_shift, hook };
2047 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2048 class_shift, hook) \
2049 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2050 hook, vendor, device, class, class_shift, hook)
2051 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2052 class_shift, hook) \
2053 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2054 hook, vendor, device, class, class_shift, hook)
2055 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2056 class_shift, hook) \
2057 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2058 hook, vendor, device, class, class_shift, hook)
2059 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2060 class_shift, hook) \
2061 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2062 hook, vendor, device, class, class_shift, hook)
2063 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2064 class_shift, hook) \
2065 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2066 resume##hook, vendor, device, class, class_shift, hook)
2067 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2068 class_shift, hook) \
2069 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2070 resume_early##hook, vendor, device, class, class_shift, hook)
2071 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2072 class_shift, hook) \
2073 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2074 suspend##hook, vendor, device, class, class_shift, hook)
2075 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2076 class_shift, hook) \
2077 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2078 suspend_late##hook, vendor, device, class, class_shift, hook)
2080 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2081 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2082 hook, vendor, device, PCI_ANY_ID, 0, hook)
2083 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2084 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2085 hook, vendor, device, PCI_ANY_ID, 0, hook)
2086 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2087 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2088 hook, vendor, device, PCI_ANY_ID, 0, hook)
2089 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2090 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2091 hook, vendor, device, PCI_ANY_ID, 0, hook)
2092 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2093 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2094 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2095 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2096 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2097 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2098 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2099 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2100 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2101 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2102 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2103 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2105 #ifdef CONFIG_PCI_QUIRKS
2106 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2108 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2109 struct pci_dev *dev) { }
2112 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2113 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2114 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2115 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2116 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2118 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2120 extern int pci_pci_problems;
2121 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2122 #define PCIPCI_TRITON 2
2123 #define PCIPCI_NATOMA 4
2124 #define PCIPCI_VIAETBF 8
2125 #define PCIPCI_VSFX 16
2126 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2127 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2129 extern unsigned long pci_cardbus_io_size;
2130 extern unsigned long pci_cardbus_mem_size;
2131 extern u8 pci_dfl_cache_line_size;
2132 extern u8 pci_cache_line_size;
2134 /* Architecture-specific versions may override these (weak) */
2135 void pcibios_disable_device(struct pci_dev *dev);
2136 void pcibios_set_master(struct pci_dev *dev);
2137 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2138 enum pcie_reset_state state);
2139 int pcibios_device_add(struct pci_dev *dev);
2140 void pcibios_release_device(struct pci_dev *dev);
2142 void pcibios_penalize_isa_irq(int irq, int active);
2144 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2146 int pcibios_alloc_irq(struct pci_dev *dev);
2147 void pcibios_free_irq(struct pci_dev *dev);
2148 resource_size_t pcibios_default_alignment(void);
2150 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2151 void __init pci_mmcfg_early_init(void);
2152 void __init pci_mmcfg_late_init(void);
2154 static inline void pci_mmcfg_early_init(void) { }
2155 static inline void pci_mmcfg_late_init(void) { }
2158 int pci_ext_cfg_avail(void);
2160 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2161 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2163 #ifdef CONFIG_PCI_IOV
2164 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2165 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2166 int pci_iov_vf_id(struct pci_dev *dev);
2167 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
2168 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2169 void pci_disable_sriov(struct pci_dev *dev);
2171 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2172 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2173 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2174 int pci_num_vf(struct pci_dev *dev);
2175 int pci_vfs_assigned(struct pci_dev *dev);
2176 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2177 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2178 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2179 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2180 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2182 /* Arch may override these (weak) */
2183 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2184 int pcibios_sriov_disable(struct pci_dev *pdev);
2185 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2187 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2191 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2196 static inline int pci_iov_vf_id(struct pci_dev *dev)
2201 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2202 struct pci_driver *pf_driver)
2204 return ERR_PTR(-EINVAL);
2207 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2210 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2211 struct pci_dev *virtfn, int id)
2215 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2219 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2221 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2222 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2223 static inline int pci_vfs_assigned(struct pci_dev *dev)
2225 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2227 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2229 #define pci_sriov_configure_simple NULL
2230 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2232 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2235 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2236 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2237 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2241 * pci_pcie_cap - get the saved PCIe capability offset
2244 * PCIe capability offset is calculated at PCI device initialization
2245 * time and saved in the data structure. This function returns saved
2246 * PCIe capability offset. Using this instead of pci_find_capability()
2247 * reduces unnecessary search in the PCI configuration space. If you
2248 * need to calculate PCIe capability offset from raw device for some
2249 * reasons, please use pci_find_capability() instead.
2251 static inline int pci_pcie_cap(struct pci_dev *dev)
2253 return dev->pcie_cap;
2257 * pci_is_pcie - check if the PCI device is PCI Express capable
2260 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2262 static inline bool pci_is_pcie(struct pci_dev *dev)
2264 return pci_pcie_cap(dev);
2268 * pcie_caps_reg - get the PCIe Capabilities Register
2271 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2273 return dev->pcie_flags_reg;
2277 * pci_pcie_type - get the PCIe device/port type
2280 static inline int pci_pcie_type(const struct pci_dev *dev)
2282 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2286 * pcie_find_root_port - Get the PCIe root port device
2289 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2290 * for a given PCI/PCIe Device.
2292 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2295 if (pci_is_pcie(dev) &&
2296 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2298 dev = pci_upstream_bridge(dev);
2304 void pci_request_acs(void);
2305 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2306 bool pci_acs_path_enabled(struct pci_dev *start,
2307 struct pci_dev *end, u16 acs_flags);
2308 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2310 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2311 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2313 /* Large Resource Data Type Tag Item Names */
2314 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2315 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2316 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2318 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2319 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2320 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2322 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2323 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2324 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2325 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2326 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2329 * pci_vpd_alloc - Allocate buffer and read VPD into it
2331 * @size: pointer to field where VPD length is returned
2333 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2335 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2338 * pci_vpd_find_id_string - Locate id string in VPD
2339 * @buf: Pointer to buffered VPD data
2340 * @len: The length of the buffer area in which to search
2341 * @size: Pointer to field where length of id string is returned
2343 * Returns the index of the id string or -ENOENT if not found.
2345 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2348 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2349 * @buf: Pointer to buffered VPD data
2350 * @len: The length of the buffer area in which to search
2351 * @kw: The keyword to search for
2352 * @size: Pointer to field where length of found keyword data is returned
2354 * Returns the index of the information field keyword data or -ENOENT if
2357 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2358 const char *kw, unsigned int *size);
2361 * pci_vpd_check_csum - Check VPD checksum
2362 * @buf: Pointer to buffered VPD data
2365 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2367 int pci_vpd_check_csum(const void *buf, unsigned int len);
2369 /* PCI <-> OF binding helpers */
2373 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2374 bool pci_host_of_has_msi_map(struct device *dev);
2376 /* Arch may override this (weak) */
2377 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2379 #else /* CONFIG_OF */
2380 static inline struct irq_domain *
2381 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2382 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2383 #endif /* CONFIG_OF */
2385 static inline struct device_node *
2386 pci_device_to_OF_node(const struct pci_dev *pdev)
2388 return pdev ? pdev->dev.of_node : NULL;
2391 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2393 return bus ? bus->dev.of_node : NULL;
2397 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2400 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2401 bool pci_pr3_present(struct pci_dev *pdev);
2403 static inline struct irq_domain *
2404 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2405 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2409 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2411 return pdev->dev.archdata.edev;
2415 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2416 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2417 int pci_for_each_dma_alias(struct pci_dev *pdev,
2418 int (*fn)(struct pci_dev *pdev,
2419 u16 alias, void *data), void *data);
2421 /* Helper functions for operation of device flag */
2422 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2424 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2426 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2428 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2430 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2432 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2436 * pci_ari_enabled - query ARI forwarding status
2439 * Returns true if ARI forwarding is enabled.
2441 static inline bool pci_ari_enabled(struct pci_bus *bus)
2443 return bus->self && bus->self->ari_enabled;
2447 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2448 * @pdev: PCI device to check
2450 * Walk upwards from @pdev and check for each encountered bridge if it's part
2451 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2452 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2454 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2456 struct pci_dev *parent = pdev;
2458 if (pdev->is_thunderbolt)
2461 while ((parent = pci_upstream_bridge(parent)))
2462 if (parent->is_thunderbolt)
2468 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2469 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2472 #include <linux/dma-mapping.h>
2474 #define pci_printk(level, pdev, fmt, arg...) \
2475 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2477 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2478 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2479 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2480 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2481 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2482 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2483 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2484 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2486 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2487 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2489 #define pci_info_ratelimited(pdev, fmt, arg...) \
2490 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2492 #define pci_WARN(pdev, condition, fmt, arg...) \
2493 WARN(condition, "%s %s: " fmt, \
2494 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2496 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2497 WARN_ONCE(condition, "%s %s: " fmt, \
2498 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2500 #endif /* LINUX_PCI_H */