1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
21 #include <linux/mod_devicetable.h>
23 #include <linux/types.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/list.h>
27 #include <linux/compiler.h>
28 #include <linux/errno.h>
29 #include <linux/kobject.h>
30 #include <linux/atomic.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
34 #include <linux/resource_ext.h>
35 #include <uapi/linux/pci.h>
37 #include <linux/pci_ids.h>
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
48 * In the interest of not exposing interfaces to user-space unnecessarily,
49 * the following kernel-only defines are being added here.
51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
55 /* pci_slot represents a physical slot */
57 struct pci_bus *bus; /* Bus this slot is on */
58 struct list_head list; /* Node in list of slots */
59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
64 static inline const char *pci_slot_name(const struct pci_slot *slot)
66 return kobject_name(&slot->kobj);
69 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 /* For PCI devices, the region numbers are assigned this way: */
77 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCE_END = 5,
81 /* #6: expansion ROM resource */
84 /* Device-specific resources */
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90 /* Resources assigned to buses behind the bridge */
91 #define PCI_BRIDGE_RESOURCE_NUM 4
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
97 /* Total resources associated with a PCI device */
100 /* Preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
105 * enum pci_interrupt_pin - PCI INTx interrupt values
106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
107 * @PCI_INTERRUPT_INTA: PCI INTA pin
108 * @PCI_INTERRUPT_INTB: PCI INTB pin
109 * @PCI_INTERRUPT_INTC: PCI INTC pin
110 * @PCI_INTERRUPT_INTD: PCI INTD pin
112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
113 * PCI_INTERRUPT_PIN register.
115 enum pci_interrupt_pin {
116 PCI_INTERRUPT_UNKNOWN,
123 /* The number of legacy PCI INTx interrupts */
124 #define PCI_NUM_INTX 4
127 * pci_power_t values must match the bits in the Capabilities PME_Support
128 * and Control/Status PowerState fields in the Power Management capability.
130 typedef int __bitwise pci_power_t;
132 #define PCI_D0 ((pci_power_t __force) 0)
133 #define PCI_D1 ((pci_power_t __force) 1)
134 #define PCI_D2 ((pci_power_t __force) 2)
135 #define PCI_D3hot ((pci_power_t __force) 3)
136 #define PCI_D3cold ((pci_power_t __force) 4)
137 #define PCI_UNKNOWN ((pci_power_t __force) 5)
138 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
140 /* Remember to update this when the list above changes! */
141 extern const char *pci_power_names[];
143 static inline const char *pci_power_name(pci_power_t state)
145 return pci_power_names[1 + (__force int) state];
148 #define PCI_PM_D2_DELAY 200
149 #define PCI_PM_D3_WAIT 10
150 #define PCI_PM_D3COLD_WAIT 100
151 #define PCI_PM_BUS_WAIT 50
154 * The pci_channel state describes connectivity between the CPU and
155 * the PCI device. If some PCI bus between here and the PCI device
156 * has crashed or locked up, this info is reflected here.
158 typedef unsigned int __bitwise pci_channel_state_t;
160 enum pci_channel_state {
161 /* I/O channel is in normal state */
162 pci_channel_io_normal = (__force pci_channel_state_t) 1,
164 /* I/O to channel is blocked */
165 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
167 /* PCI card is dead */
168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
171 typedef unsigned int __bitwise pcie_reset_state_t;
173 enum pcie_reset_state {
174 /* Reset is NOT asserted (Use to deassert reset) */
175 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
177 /* Use #PERST to reset PCIe device */
178 pcie_warm_reset = (__force pcie_reset_state_t) 2,
180 /* Use PCIe Hot Reset to reset device */
181 pcie_hot_reset = (__force pcie_reset_state_t) 3
184 typedef unsigned short __bitwise pci_dev_flags_t;
186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
188 /* Device configuration is irrevocably lost if disabled into D3 */
189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
190 /* Provide indication device is assigned by a Virtual Machine Manager */
191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
192 /* Flag for quirk use to store if quirk-specific ACS is enabled */
193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
196 /* Do not use bus resets for device */
197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
198 /* Do not use PM reset even if device advertises NoSoftRst- */
199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
200 /* Get VPD from function 0 VPD */
201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
202 /* A non-root bridge where translation occurs, stop alias search here */
203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
204 /* Do not use FLR even if device advertises PCI_AF_CAP */
205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
206 /* Don't use Relaxed Ordering for TLPs directed at this device */
207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
210 enum pci_irq_reroute_variant {
211 INTEL_IRQ_REROUTE_VARIANT = 1,
212 MAX_IRQ_REROUTE_VARIANTS = 3
215 typedef unsigned short __bitwise pci_bus_flags_t;
217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
222 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
223 enum pcie_link_width {
224 PCIE_LNK_WIDTH_RESRV = 0x00,
232 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
235 /* Based on the PCI Hotplug Spec, but some values are made up by us */
237 PCI_SPEED_33MHz = 0x00,
238 PCI_SPEED_66MHz = 0x01,
239 PCI_SPEED_66MHz_PCIX = 0x02,
240 PCI_SPEED_100MHz_PCIX = 0x03,
241 PCI_SPEED_133MHz_PCIX = 0x04,
242 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
243 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
244 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
245 PCI_SPEED_66MHz_PCIX_266 = 0x09,
246 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
247 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
253 PCI_SPEED_66MHz_PCIX_533 = 0x11,
254 PCI_SPEED_100MHz_PCIX_533 = 0x12,
255 PCI_SPEED_133MHz_PCIX_533 = 0x13,
256 PCIE_SPEED_2_5GT = 0x14,
257 PCIE_SPEED_5_0GT = 0x15,
258 PCIE_SPEED_8_0GT = 0x16,
259 PCIE_SPEED_16_0GT = 0x17,
260 PCI_SPEED_UNKNOWN = 0xff,
263 struct pci_cap_saved_data {
270 struct pci_cap_saved_state {
271 struct hlist_node next;
272 struct pci_cap_saved_data cap;
276 struct pcie_link_state;
281 /* The pci_dev structure describes PCI devices */
283 struct list_head bus_list; /* Node in per-bus list */
284 struct pci_bus *bus; /* Bus this device is on */
285 struct pci_bus *subordinate; /* Bus this device bridges to */
287 void *sysdata; /* Hook for sys-specific extension */
288 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
289 struct pci_slot *slot; /* Physical slot this device is in */
291 unsigned int devfn; /* Encoded device & function index */
292 unsigned short vendor;
293 unsigned short device;
294 unsigned short subsystem_vendor;
295 unsigned short subsystem_device;
296 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
297 u8 revision; /* PCI revision, low byte of class word */
298 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
299 #ifdef CONFIG_PCIEAER
300 u16 aer_cap; /* AER capability offset */
302 u8 pcie_cap; /* PCIe capability offset */
303 u8 msi_cap; /* MSI capability offset */
304 u8 msix_cap; /* MSI-X capability offset */
305 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
306 u8 rom_base_reg; /* Config register controlling ROM */
307 u8 pin; /* Interrupt pin this device uses */
308 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
309 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
311 struct pci_driver *driver; /* Driver bound to this device */
312 u64 dma_mask; /* Mask of the bits of bus address this
313 device implements. Normally this is
314 0xffffffff. You only need to change
315 this if your device has broken DMA
316 or supports 64-bit transfers. */
318 struct device_dma_parameters dma_parms;
320 pci_power_t current_state; /* Current operating state. In ACPI,
321 this is D0-D3, D0 being fully
322 functional, and D3 being off. */
323 u8 pm_cap; /* PM capability offset */
324 unsigned int pme_support:5; /* Bitmask of states from which PME#
326 unsigned int pme_poll:1; /* Poll device's PME status bit */
327 unsigned int d1_support:1; /* Low power state D1 is supported */
328 unsigned int d2_support:1; /* Low power state D2 is supported */
329 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
330 unsigned int no_d3cold:1; /* D3cold is forbidden */
331 unsigned int bridge_d3:1; /* Allow D3 for bridge */
332 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
333 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
334 decoding during BAR sizing */
335 unsigned int wakeup_prepared:1;
336 unsigned int runtime_d3cold:1; /* Whether go through runtime
337 D3cold, not set for devices
338 powered on/off by the
339 corresponding bridge */
340 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
341 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
342 controlled exclusively by
344 unsigned int d3_delay; /* D3->D0 transition time in ms */
345 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
347 #ifdef CONFIG_PCIEASPM
348 struct pcie_link_state *link_state; /* ASPM link state */
349 unsigned int ltr_path:1; /* Latency Tolerance Reporting
350 supported from root to here */
353 pci_channel_state_t error_state; /* Current connectivity state */
354 struct device dev; /* Generic device interface */
356 int cfg_size; /* Size of config space */
359 * Instead of touching interrupt line and base address registers
360 * directly, use the values stored here. They might be different!
363 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
365 bool match_driver; /* Skip attaching driver */
367 unsigned int transparent:1; /* Subtractive decode bridge */
368 unsigned int multifunction:1; /* Multi-function device */
370 unsigned int is_added:1;
371 unsigned int is_busmaster:1; /* Is busmaster */
372 unsigned int no_msi:1; /* May not use MSI */
373 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
374 unsigned int block_cfg_access:1; /* Config space access blocked */
375 unsigned int broken_parity_status:1; /* Generates false positive parity */
376 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
377 unsigned int msi_enabled:1;
378 unsigned int msix_enabled:1;
379 unsigned int ari_enabled:1; /* ARI forwarding */
380 unsigned int ats_enabled:1; /* Address Translation Svc */
381 unsigned int pasid_enabled:1; /* Process Address Space ID */
382 unsigned int pri_enabled:1; /* Page Request Interface */
383 unsigned int is_managed:1;
384 unsigned int needs_freset:1; /* Requires fundamental reset */
385 unsigned int state_saved:1;
386 unsigned int is_physfn:1;
387 unsigned int is_virtfn:1;
388 unsigned int reset_fn:1;
389 unsigned int is_hotplug_bridge:1;
390 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
391 unsigned int __aer_firmware_first_valid:1;
392 unsigned int __aer_firmware_first:1;
393 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
394 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
395 unsigned int irq_managed:1;
396 unsigned int has_secondary_link:1;
397 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
398 unsigned int is_probed:1; /* Device probing in progress */
399 pci_dev_flags_t dev_flags;
400 atomic_t enable_cnt; /* pci_enable_device has been called */
402 u32 saved_config_space[16]; /* Config space saved at suspend time */
403 struct hlist_head saved_cap_space;
404 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
405 int rom_attr_enabled; /* Display of ROM attribute enabled? */
406 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
407 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
409 #ifdef CONFIG_HOTPLUG_PCI_PCIE
410 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
412 #ifdef CONFIG_PCIE_PTM
413 unsigned int ptm_root:1;
414 unsigned int ptm_enabled:1;
417 #ifdef CONFIG_PCI_MSI
418 const struct attribute_group **msi_irq_groups;
421 #ifdef CONFIG_PCI_ATS
423 struct pci_sriov *sriov; /* PF: SR-IOV info */
424 struct pci_dev *physfn; /* VF: related PF */
426 u16 ats_cap; /* ATS Capability offset */
427 u8 ats_stu; /* ATS Smallest Translation Unit */
428 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
430 #ifdef CONFIG_PCI_PRI
431 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
433 #ifdef CONFIG_PCI_PASID
436 phys_addr_t rom; /* Physical address if not from BAR */
437 size_t romlen; /* Length if not from BAR */
438 char *driver_override; /* Driver name to force a match */
440 unsigned long priv_flags; /* Private flags for the PCI driver */
443 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
445 #ifdef CONFIG_PCI_IOV
452 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
454 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
455 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
457 static inline int pci_channel_offline(struct pci_dev *pdev)
459 return (pdev->error_state != pci_channel_io_normal);
462 struct pci_host_bridge {
464 struct pci_bus *bus; /* Root bus */
468 struct list_head windows; /* resource_entry */
469 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
470 int (*map_irq)(const struct pci_dev *, u8, u8);
471 void (*release_fn)(struct pci_host_bridge *);
473 struct msi_controller *msi;
474 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
475 unsigned int no_ext_tags:1; /* No Extended Tags */
476 unsigned int native_aer:1; /* OS may use PCIe AER */
477 unsigned int native_hotplug:1; /* OS may use PCIe hotplug */
478 unsigned int native_pme:1; /* OS may use PCIe PME */
479 /* Resource alignment requirements */
480 resource_size_t (*align_resource)(struct pci_dev *dev,
481 const struct resource *res,
482 resource_size_t start,
483 resource_size_t size,
484 resource_size_t align);
485 unsigned long private[0] ____cacheline_aligned;
488 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
490 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
492 return (void *)bridge->private;
495 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
497 return container_of(priv, struct pci_host_bridge, private);
500 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
501 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
503 void pci_free_host_bridge(struct pci_host_bridge *bridge);
504 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
506 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
507 void (*release_fn)(struct pci_host_bridge *),
510 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
513 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
514 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
515 * buses below host bridges or subtractive decode bridges) go in the list.
516 * Use pci_bus_for_each_resource() to iterate through all the resources.
520 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
521 * and there's no way to program the bridge with the details of the window.
522 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
523 * decode bit set, because they are explicit and can be programmed with _SRS.
525 #define PCI_SUBTRACTIVE_DECODE 0x1
527 struct pci_bus_resource {
528 struct list_head list;
529 struct resource *res;
533 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
536 struct list_head node; /* Node in list of buses */
537 struct pci_bus *parent; /* Parent bus this bridge is on */
538 struct list_head children; /* List of child buses */
539 struct list_head devices; /* List of devices on this bus */
540 struct pci_dev *self; /* Bridge device as seen by parent */
541 struct list_head slots; /* List of slots on this bus;
542 protected by pci_slot_mutex */
543 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
544 struct list_head resources; /* Address space routed to this bus */
545 struct resource busn_res; /* Bus numbers routed to this bus */
547 struct pci_ops *ops; /* Configuration access functions */
548 struct msi_controller *msi; /* MSI controller */
549 void *sysdata; /* Hook for sys-specific extension */
550 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
552 unsigned char number; /* Bus number */
553 unsigned char primary; /* Number of primary bridge */
554 unsigned char max_bus_speed; /* enum pci_bus_speed */
555 unsigned char cur_bus_speed; /* enum pci_bus_speed */
556 #ifdef CONFIG_PCI_DOMAINS_GENERIC
562 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
563 pci_bus_flags_t bus_flags; /* Inherited by child buses */
564 struct device *bridge;
566 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
567 struct bin_attribute *legacy_mem; /* Legacy mem */
568 unsigned int is_added:1;
571 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
574 * Returns true if the PCI bus is root (behind host-PCI bridge),
577 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
578 * This is incorrect because "virtual" buses added for SR-IOV (via
579 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
581 static inline bool pci_is_root_bus(struct pci_bus *pbus)
583 return !(pbus->parent);
587 * pci_is_bridge - check if the PCI device is a bridge
590 * Return true if the PCI device is bridge whether it has subordinate
593 static inline bool pci_is_bridge(struct pci_dev *dev)
595 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
596 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
599 #define for_each_pci_bridge(dev, bus) \
600 list_for_each_entry(dev, &bus->devices, bus_list) \
601 if (!pci_is_bridge(dev)) {} else
603 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
605 dev = pci_physfn(dev);
606 if (pci_is_root_bus(dev->bus))
609 return dev->bus->self;
612 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
613 void pci_put_host_bridge_device(struct device *dev);
615 #ifdef CONFIG_PCI_MSI
616 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
618 return pci_dev->msi_enabled || pci_dev->msix_enabled;
621 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
624 /* Error values that may be returned by PCI functions */
625 #define PCIBIOS_SUCCESSFUL 0x00
626 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
627 #define PCIBIOS_BAD_VENDOR_ID 0x83
628 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
629 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
630 #define PCIBIOS_SET_FAILED 0x88
631 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
633 /* Translate above to generic errno for passing back through non-PCI code */
634 static inline int pcibios_err_to_errno(int err)
636 if (err <= PCIBIOS_SUCCESSFUL)
637 return err; /* Assume already errno */
640 case PCIBIOS_FUNC_NOT_SUPPORTED:
642 case PCIBIOS_BAD_VENDOR_ID:
644 case PCIBIOS_DEVICE_NOT_FOUND:
646 case PCIBIOS_BAD_REGISTER_NUMBER:
648 case PCIBIOS_SET_FAILED:
650 case PCIBIOS_BUFFER_TOO_SMALL:
657 /* Low-level architecture-dependent routines */
660 int (*add_bus)(struct pci_bus *bus);
661 void (*remove_bus)(struct pci_bus *bus);
662 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
663 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
664 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
668 * ACPI needs to be able to access PCI config space before we've done a
669 * PCI bus scan and created pci_bus structures.
671 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
672 int reg, int len, u32 *val);
673 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
674 int reg, int len, u32 val);
676 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
677 typedef u64 pci_bus_addr_t;
679 typedef u32 pci_bus_addr_t;
682 struct pci_bus_region {
683 pci_bus_addr_t start;
688 spinlock_t lock; /* Protects list, index */
689 struct list_head list; /* For IDs added at runtime */
694 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
695 * a set of callbacks in struct pci_error_handlers, that device driver
696 * will be notified of PCI bus errors, and will be driven to recovery
697 * when an error occurs.
700 typedef unsigned int __bitwise pci_ers_result_t;
702 enum pci_ers_result {
703 /* No result/none/not supported in device driver */
704 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
706 /* Device driver can recover without slot reset */
707 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
709 /* Device driver wants slot to be reset */
710 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
712 /* Device has completely failed, is unrecoverable */
713 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
715 /* Device driver is fully recovered and operational */
716 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
718 /* No AER capabilities registered for the driver */
719 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
722 /* PCI bus error event callbacks */
723 struct pci_error_handlers {
724 /* PCI bus error detected on this device */
725 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
726 enum pci_channel_state error);
728 /* MMIO has been re-enabled, but not DMA */
729 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
731 /* PCI slot has been reset */
732 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
734 /* PCI function reset prepare or completed */
735 void (*reset_prepare)(struct pci_dev *dev);
736 void (*reset_done)(struct pci_dev *dev);
738 /* Device driver may resume normal operations */
739 void (*resume)(struct pci_dev *dev);
745 struct list_head node;
747 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
748 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
749 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
750 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
751 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
752 int (*resume_early)(struct pci_dev *dev);
753 int (*resume) (struct pci_dev *dev); /* Device woken up */
754 void (*shutdown) (struct pci_dev *dev);
755 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */
756 const struct pci_error_handlers *err_handler;
757 const struct attribute_group **groups;
758 struct device_driver driver;
759 struct pci_dynids dynids;
762 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
765 * PCI_DEVICE - macro used to describe a specific PCI device
766 * @vend: the 16 bit PCI Vendor ID
767 * @dev: the 16 bit PCI Device ID
769 * This macro is used to create a struct pci_device_id that matches a
770 * specific device. The subvendor and subdevice fields will be set to
773 #define PCI_DEVICE(vend,dev) \
774 .vendor = (vend), .device = (dev), \
775 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
778 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
779 * @vend: the 16 bit PCI Vendor ID
780 * @dev: the 16 bit PCI Device ID
781 * @subvend: the 16 bit PCI Subvendor ID
782 * @subdev: the 16 bit PCI Subdevice ID
784 * This macro is used to create a struct pci_device_id that matches a
785 * specific device with subsystem information.
787 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
788 .vendor = (vend), .device = (dev), \
789 .subvendor = (subvend), .subdevice = (subdev)
792 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
793 * @dev_class: the class, subclass, prog-if triple for this device
794 * @dev_class_mask: the class mask for this device
796 * This macro is used to create a struct pci_device_id that matches a
797 * specific PCI class. The vendor, device, subvendor, and subdevice
798 * fields will be set to PCI_ANY_ID.
800 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
801 .class = (dev_class), .class_mask = (dev_class_mask), \
802 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
803 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
806 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
807 * @vend: the vendor name
808 * @dev: the 16 bit PCI Device ID
810 * This macro is used to create a struct pci_device_id that matches a
811 * specific PCI device. The subvendor, and subdevice fields will be set
812 * to PCI_ANY_ID. The macro allows the next field to follow as the device
815 #define PCI_VDEVICE(vend, dev) \
816 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
817 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
820 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
821 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
822 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
823 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
824 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
825 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
826 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
829 /* These external functions are only available when PCI support is enabled */
832 extern unsigned int pci_flags;
834 static inline void pci_set_flags(int flags) { pci_flags = flags; }
835 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
836 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
837 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
839 void pcie_bus_configure_settings(struct pci_bus *bus);
841 enum pcie_bus_config_types {
842 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
843 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
844 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
845 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
846 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
849 extern enum pcie_bus_config_types pcie_bus_config;
851 extern struct bus_type pci_bus_type;
853 /* Do NOT directly access these two variables, unless you are arch-specific PCI
854 * code, or PCI core code. */
855 extern struct list_head pci_root_buses; /* List of all known PCI buses */
856 /* Some device drivers need know if PCI is initiated */
857 int no_pci_devices(void);
859 void pcibios_resource_survey_bus(struct pci_bus *bus);
860 void pcibios_bus_add_device(struct pci_dev *pdev);
861 void pcibios_add_bus(struct pci_bus *bus);
862 void pcibios_remove_bus(struct pci_bus *bus);
863 void pcibios_fixup_bus(struct pci_bus *);
864 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
865 /* Architecture-specific versions may override this (weak) */
866 char *pcibios_setup(char *str);
868 /* Used only when drivers/pci/setup.c is used */
869 resource_size_t pcibios_align_resource(void *, const struct resource *,
873 /* Weak but can be overriden by arch */
874 void pci_fixup_cardbus(struct pci_bus *);
876 /* Generic PCI functions used internally */
878 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
879 struct resource *res);
880 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
881 struct pci_bus_region *region);
882 void pcibios_scan_specific_bus(int busn);
883 struct pci_bus *pci_find_bus(int domain, int busnr);
884 void pci_bus_add_devices(const struct pci_bus *bus);
885 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
886 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
887 struct pci_ops *ops, void *sysdata,
888 struct list_head *resources);
889 int pci_host_probe(struct pci_host_bridge *bridge);
890 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
891 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
892 void pci_bus_release_busn_res(struct pci_bus *b);
893 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
894 struct pci_ops *ops, void *sysdata,
895 struct list_head *resources);
896 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
897 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
899 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
900 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
902 struct hotplug_slot *hotplug);
903 void pci_destroy_slot(struct pci_slot *slot);
905 void pci_dev_assign_slot(struct pci_dev *dev);
907 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
909 int pci_scan_slot(struct pci_bus *bus, int devfn);
910 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
911 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
912 unsigned int pci_scan_child_bus(struct pci_bus *bus);
913 void pci_bus_add_device(struct pci_dev *dev);
914 void pci_read_bridge_bases(struct pci_bus *child);
915 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
916 struct resource *res);
917 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
918 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
919 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
920 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
921 struct pci_dev *pci_dev_get(struct pci_dev *dev);
922 void pci_dev_put(struct pci_dev *dev);
923 void pci_remove_bus(struct pci_bus *b);
924 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
925 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
926 void pci_stop_root_bus(struct pci_bus *bus);
927 void pci_remove_root_bus(struct pci_bus *bus);
928 void pci_setup_cardbus(struct pci_bus *bus);
929 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
930 void pci_sort_breadthfirst(void);
931 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
932 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
934 /* Generic PCI functions exported to card drivers */
936 enum pci_lost_interrupt_reason {
937 PCI_LOST_IRQ_NO_INFORMATION = 0,
938 PCI_LOST_IRQ_DISABLE_MSI,
939 PCI_LOST_IRQ_DISABLE_MSIX,
940 PCI_LOST_IRQ_DISABLE_ACPI,
942 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
943 int pci_find_capability(struct pci_dev *dev, int cap);
944 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
945 int pci_find_ext_capability(struct pci_dev *dev, int cap);
946 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
947 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
948 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
949 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
951 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
952 struct pci_dev *from);
953 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
954 unsigned int ss_vendor, unsigned int ss_device,
955 struct pci_dev *from);
956 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
957 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
959 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
960 int pci_dev_present(const struct pci_device_id *ids);
962 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
964 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
965 int where, u16 *val);
966 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
967 int where, u32 *val);
968 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
970 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
972 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
975 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
976 int where, int size, u32 *val);
977 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
978 int where, int size, u32 val);
979 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
980 int where, int size, u32 *val);
981 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
982 int where, int size, u32 val);
984 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
986 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
987 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
988 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
989 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
990 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
991 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
993 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
994 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
995 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
996 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
997 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
999 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1000 u32 clear, u32 set);
1002 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1005 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1008 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1011 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1014 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1017 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1020 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1023 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1026 /* User-space driven config access */
1027 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1028 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1029 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1030 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1031 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1032 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1034 int __must_check pci_enable_device(struct pci_dev *dev);
1035 int __must_check pci_enable_device_io(struct pci_dev *dev);
1036 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1037 int __must_check pci_reenable_device(struct pci_dev *);
1038 int __must_check pcim_enable_device(struct pci_dev *pdev);
1039 void pcim_pin_device(struct pci_dev *pdev);
1041 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1044 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1045 * writable and no quirk has marked the feature broken.
1047 return !pdev->broken_intx_masking;
1050 static inline int pci_is_enabled(struct pci_dev *pdev)
1052 return (atomic_read(&pdev->enable_cnt) > 0);
1055 static inline int pci_is_managed(struct pci_dev *pdev)
1057 return pdev->is_managed;
1060 void pci_disable_device(struct pci_dev *dev);
1062 extern unsigned int pcibios_max_latency;
1063 void pci_set_master(struct pci_dev *dev);
1064 void pci_clear_master(struct pci_dev *dev);
1066 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1067 int pci_set_cacheline_size(struct pci_dev *dev);
1068 #define HAVE_PCI_SET_MWI
1069 int __must_check pci_set_mwi(struct pci_dev *dev);
1070 int __must_check pcim_set_mwi(struct pci_dev *dev);
1071 int pci_try_set_mwi(struct pci_dev *dev);
1072 void pci_clear_mwi(struct pci_dev *dev);
1073 void pci_intx(struct pci_dev *dev, int enable);
1074 bool pci_check_and_mask_intx(struct pci_dev *dev);
1075 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1076 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1077 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1078 int pcix_get_max_mmrbc(struct pci_dev *dev);
1079 int pcix_get_mmrbc(struct pci_dev *dev);
1080 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1081 int pcie_get_readrq(struct pci_dev *dev);
1082 int pcie_set_readrq(struct pci_dev *dev, int rq);
1083 int pcie_get_mps(struct pci_dev *dev);
1084 int pcie_set_mps(struct pci_dev *dev, int mps);
1085 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1086 enum pcie_link_width *width);
1087 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1088 enum pci_bus_speed *speed,
1089 enum pcie_link_width *width);
1090 void pcie_print_link_status(struct pci_dev *dev);
1091 int pcie_flr(struct pci_dev *dev);
1092 int __pci_reset_function_locked(struct pci_dev *dev);
1093 int pci_reset_function(struct pci_dev *dev);
1094 int pci_reset_function_locked(struct pci_dev *dev);
1095 int pci_try_reset_function(struct pci_dev *dev);
1096 int pci_probe_reset_slot(struct pci_slot *slot);
1097 int pci_reset_slot(struct pci_slot *slot);
1098 int pci_try_reset_slot(struct pci_slot *slot);
1099 int pci_probe_reset_bus(struct pci_bus *bus);
1100 int pci_reset_bus(struct pci_bus *bus);
1101 int pci_try_reset_bus(struct pci_bus *bus);
1102 void pci_reset_secondary_bus(struct pci_dev *dev);
1103 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1104 int pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1105 void pci_update_resource(struct pci_dev *dev, int resno);
1106 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1107 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1108 void pci_release_resource(struct pci_dev *dev, int resno);
1109 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1110 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1111 bool pci_device_is_present(struct pci_dev *pdev);
1112 void pci_ignore_hotplug(struct pci_dev *dev);
1114 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1115 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1116 const char *fmt, ...);
1117 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1119 /* ROM control related routines */
1120 int pci_enable_rom(struct pci_dev *pdev);
1121 void pci_disable_rom(struct pci_dev *pdev);
1122 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1123 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1124 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1125 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1127 /* Power management related routines */
1128 int pci_save_state(struct pci_dev *dev);
1129 void pci_restore_state(struct pci_dev *dev);
1130 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1131 int pci_load_saved_state(struct pci_dev *dev,
1132 struct pci_saved_state *state);
1133 int pci_load_and_free_saved_state(struct pci_dev *dev,
1134 struct pci_saved_state **state);
1135 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1136 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1138 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1139 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1140 u16 cap, unsigned int size);
1141 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1142 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1143 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1144 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1145 void pci_pme_active(struct pci_dev *dev, bool enable);
1146 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1147 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1148 int pci_prepare_to_sleep(struct pci_dev *dev);
1149 int pci_back_from_sleep(struct pci_dev *dev);
1150 bool pci_dev_run_wake(struct pci_dev *dev);
1151 bool pci_check_pme_status(struct pci_dev *dev);
1152 void pci_pme_wakeup_bus(struct pci_bus *bus);
1153 void pci_d3cold_enable(struct pci_dev *dev);
1154 void pci_d3cold_disable(struct pci_dev *dev);
1155 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1156 void pci_wakeup_bus(struct pci_bus *bus);
1157 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1159 /* PCI Virtual Channel */
1160 int pci_save_vc_state(struct pci_dev *dev);
1161 void pci_restore_vc_state(struct pci_dev *dev);
1162 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1164 /* For use by arch with custom probe code */
1165 void set_pcie_port_type(struct pci_dev *pdev);
1166 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1168 /* Functions for PCI Hotplug drivers to use */
1169 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1170 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1171 unsigned int pci_rescan_bus(struct pci_bus *bus);
1172 void pci_lock_rescan_remove(void);
1173 void pci_unlock_rescan_remove(void);
1175 /* Vital Product Data routines */
1176 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1177 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1178 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1180 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1181 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1182 void pci_bus_assign_resources(const struct pci_bus *bus);
1183 void pci_bus_claim_resources(struct pci_bus *bus);
1184 void pci_bus_size_bridges(struct pci_bus *bus);
1185 int pci_claim_resource(struct pci_dev *, int);
1186 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1187 void pci_assign_unassigned_resources(void);
1188 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1189 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1190 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1191 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1192 void pdev_enable_device(struct pci_dev *);
1193 int pci_enable_resources(struct pci_dev *, int mask);
1194 void pci_assign_irq(struct pci_dev *dev);
1195 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1196 #define HAVE_PCI_REQ_REGIONS 2
1197 int __must_check pci_request_regions(struct pci_dev *, const char *);
1198 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1199 void pci_release_regions(struct pci_dev *);
1200 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1201 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1202 void pci_release_region(struct pci_dev *, int);
1203 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1204 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1205 void pci_release_selected_regions(struct pci_dev *, int);
1207 /* drivers/pci/bus.c */
1208 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1209 void pci_bus_put(struct pci_bus *bus);
1210 void pci_add_resource(struct list_head *resources, struct resource *res);
1211 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1212 resource_size_t offset);
1213 void pci_free_resource_list(struct list_head *resources);
1214 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1215 unsigned int flags);
1216 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1217 void pci_bus_remove_resources(struct pci_bus *bus);
1218 int devm_request_pci_bus_resources(struct device *dev,
1219 struct list_head *resources);
1221 #define pci_bus_for_each_resource(bus, res, i) \
1223 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1226 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1227 struct resource *res, resource_size_t size,
1228 resource_size_t align, resource_size_t min,
1229 unsigned long type_mask,
1230 resource_size_t (*alignf)(void *,
1231 const struct resource *,
1237 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1238 resource_size_t size);
1239 unsigned long pci_address_to_pio(phys_addr_t addr);
1240 phys_addr_t pci_pio_to_address(unsigned long pio);
1241 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1242 void pci_unmap_iospace(struct resource *res);
1243 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1244 resource_size_t offset,
1245 resource_size_t size);
1246 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1247 struct resource *res);
1249 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1251 struct pci_bus_region region;
1253 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1254 return region.start;
1257 /* Proper probing supporting hot-pluggable devices */
1258 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1259 const char *mod_name);
1261 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1262 #define pci_register_driver(driver) \
1263 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1265 void pci_unregister_driver(struct pci_driver *dev);
1268 * module_pci_driver() - Helper macro for registering a PCI driver
1269 * @__pci_driver: pci_driver struct
1271 * Helper macro for PCI drivers which do not do anything special in module
1272 * init/exit. This eliminates a lot of boilerplate. Each module may only
1273 * use this macro once, and calling it replaces module_init() and module_exit()
1275 #define module_pci_driver(__pci_driver) \
1276 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1279 * builtin_pci_driver() - Helper macro for registering a PCI driver
1280 * @__pci_driver: pci_driver struct
1282 * Helper macro for PCI drivers which do not do anything special in their
1283 * init code. This eliminates a lot of boilerplate. Each driver may only
1284 * use this macro once, and calling it replaces device_initcall(...)
1286 #define builtin_pci_driver(__pci_driver) \
1287 builtin_driver(__pci_driver, pci_register_driver)
1289 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1290 int pci_add_dynid(struct pci_driver *drv,
1291 unsigned int vendor, unsigned int device,
1292 unsigned int subvendor, unsigned int subdevice,
1293 unsigned int class, unsigned int class_mask,
1294 unsigned long driver_data);
1295 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1296 struct pci_dev *dev);
1297 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1300 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1302 int pci_cfg_space_size(struct pci_dev *dev);
1303 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1304 void pci_setup_bridge(struct pci_bus *bus);
1305 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1306 unsigned long type);
1308 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1309 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1311 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1312 unsigned int command_bits, u32 flags);
1314 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1315 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1316 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1317 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1318 #define PCI_IRQ_ALL_TYPES \
1319 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1321 /* kmem_cache style wrapper around pci_alloc_consistent() */
1323 #include <linux/pci-dma.h>
1324 #include <linux/dmapool.h>
1326 #define pci_pool dma_pool
1327 #define pci_pool_create(name, pdev, size, align, allocation) \
1328 dma_pool_create(name, &pdev->dev, size, align, allocation)
1329 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1330 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1331 #define pci_pool_zalloc(pool, flags, handle) \
1332 dma_pool_zalloc(pool, flags, handle)
1333 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1336 u32 vector; /* Kernel uses to write allocated vector */
1337 u16 entry; /* Driver uses to specify entry, OS writes */
1340 #ifdef CONFIG_PCI_MSI
1341 int pci_msi_vec_count(struct pci_dev *dev);
1342 void pci_disable_msi(struct pci_dev *dev);
1343 int pci_msix_vec_count(struct pci_dev *dev);
1344 void pci_disable_msix(struct pci_dev *dev);
1345 void pci_restore_msi_state(struct pci_dev *dev);
1346 int pci_msi_enabled(void);
1347 int pci_enable_msi(struct pci_dev *dev);
1348 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1349 int minvec, int maxvec);
1350 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1351 struct msix_entry *entries, int nvec)
1353 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1358 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1359 unsigned int max_vecs, unsigned int flags,
1360 const struct irq_affinity *affd);
1362 void pci_free_irq_vectors(struct pci_dev *dev);
1363 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1364 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1365 int pci_irq_get_node(struct pci_dev *pdev, int vec);
1368 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1369 static inline void pci_disable_msi(struct pci_dev *dev) { }
1370 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1371 static inline void pci_disable_msix(struct pci_dev *dev) { }
1372 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1373 static inline int pci_msi_enabled(void) { return 0; }
1374 static inline int pci_enable_msi(struct pci_dev *dev)
1376 static inline int pci_enable_msix_range(struct pci_dev *dev,
1377 struct msix_entry *entries, int minvec, int maxvec)
1379 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1380 struct msix_entry *entries, int nvec)
1384 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1385 unsigned int max_vecs, unsigned int flags,
1386 const struct irq_affinity *aff_desc)
1388 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1393 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1397 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1399 if (WARN_ON_ONCE(nr > 0))
1403 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1406 return cpu_possible_mask;
1409 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1411 return first_online_node;
1416 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1417 unsigned int max_vecs, unsigned int flags)
1419 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1424 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1425 * @d: the INTx IRQ domain
1426 * @node: the DT node for the device whose interrupt we're translating
1427 * @intspec: the interrupt specifier data from the DT
1428 * @intsize: the number of entries in @intspec
1429 * @out_hwirq: pointer at which to write the hwirq number
1430 * @out_type: pointer at which to write the interrupt type
1432 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1433 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1434 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1435 * INTx value to obtain the hwirq number.
1437 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1439 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1440 struct device_node *node,
1442 unsigned int intsize,
1443 unsigned long *out_hwirq,
1444 unsigned int *out_type)
1446 const u32 intx = intspec[0];
1448 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1451 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1455 #ifdef CONFIG_PCIEPORTBUS
1456 extern bool pcie_ports_disabled;
1458 #define pcie_ports_disabled true
1461 #ifdef CONFIG_PCIEASPM
1462 bool pcie_aspm_support_enabled(void);
1464 static inline bool pcie_aspm_support_enabled(void) { return false; }
1467 #ifdef CONFIG_PCIEAER
1468 void pci_no_aer(void);
1469 bool pci_aer_available(void);
1470 int pci_aer_init(struct pci_dev *dev);
1472 static inline void pci_no_aer(void) { }
1473 static inline bool pci_aer_available(void) { return false; }
1474 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1477 #ifdef CONFIG_PCIE_ECRC
1478 void pcie_set_ecrc_checking(struct pci_dev *dev);
1479 void pcie_ecrc_get_policy(char *str);
1481 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1482 static inline void pcie_ecrc_get_policy(char *str) { }
1485 #ifdef CONFIG_PCI_ATS
1486 /* Address Translation Service */
1487 void pci_ats_init(struct pci_dev *dev);
1488 int pci_enable_ats(struct pci_dev *dev, int ps);
1489 void pci_disable_ats(struct pci_dev *dev);
1490 int pci_ats_queue_depth(struct pci_dev *dev);
1492 static inline void pci_ats_init(struct pci_dev *d) { }
1493 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1494 static inline void pci_disable_ats(struct pci_dev *d) { }
1495 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1498 #ifdef CONFIG_PCIE_PTM
1499 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1501 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1505 void pci_cfg_access_lock(struct pci_dev *dev);
1506 bool pci_cfg_access_trylock(struct pci_dev *dev);
1507 void pci_cfg_access_unlock(struct pci_dev *dev);
1510 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1511 * a PCI domain is defined to be a set of PCI buses which share
1512 * configuration space.
1514 #ifdef CONFIG_PCI_DOMAINS
1515 extern int pci_domains_supported;
1516 int pci_get_new_domain_nr(void);
1518 enum { pci_domains_supported = 0 };
1519 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1520 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1521 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1522 #endif /* CONFIG_PCI_DOMAINS */
1525 * Generic implementation for PCI domain support. If your
1526 * architecture does not need custom management of PCI
1527 * domains then this implementation will be used
1529 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1530 static inline int pci_domain_nr(struct pci_bus *bus)
1532 return bus->domain_nr;
1535 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1537 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1540 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1543 /* Some architectures require additional setup to direct VGA traffic */
1544 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1545 unsigned int command_bits, u32 flags);
1546 void pci_register_set_vga_state(arch_set_vga_state_t func);
1549 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1551 return pci_request_selected_regions(pdev,
1552 pci_select_bars(pdev, IORESOURCE_IO), name);
1556 pci_release_io_regions(struct pci_dev *pdev)
1558 return pci_release_selected_regions(pdev,
1559 pci_select_bars(pdev, IORESOURCE_IO));
1563 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1565 return pci_request_selected_regions(pdev,
1566 pci_select_bars(pdev, IORESOURCE_MEM), name);
1570 pci_release_mem_regions(struct pci_dev *pdev)
1572 return pci_release_selected_regions(pdev,
1573 pci_select_bars(pdev, IORESOURCE_MEM));
1576 #else /* CONFIG_PCI is not enabled */
1578 static inline void pci_set_flags(int flags) { }
1579 static inline void pci_add_flags(int flags) { }
1580 static inline void pci_clear_flags(int flags) { }
1581 static inline int pci_has_flag(int flag) { return 0; }
1584 * If the system does not have PCI, clearly these return errors. Define
1585 * these as simple inline functions to avoid hair in drivers.
1587 #define _PCI_NOP(o, s, t) \
1588 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1590 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1592 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1593 _PCI_NOP(o, word, u16 x) \
1594 _PCI_NOP(o, dword, u32 x)
1595 _PCI_NOP_ALL(read, *)
1596 _PCI_NOP_ALL(write,)
1598 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1599 unsigned int device,
1600 struct pci_dev *from)
1603 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1604 unsigned int device,
1605 unsigned int ss_vendor,
1606 unsigned int ss_device,
1607 struct pci_dev *from)
1610 static inline struct pci_dev *pci_get_class(unsigned int class,
1611 struct pci_dev *from)
1614 #define pci_dev_present(ids) (0)
1615 #define no_pci_devices() (1)
1616 #define pci_dev_put(dev) do { } while (0)
1618 static inline void pci_set_master(struct pci_dev *dev) { }
1619 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1620 static inline void pci_disable_device(struct pci_dev *dev) { }
1621 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1623 static inline int __pci_register_driver(struct pci_driver *drv,
1624 struct module *owner)
1626 static inline int pci_register_driver(struct pci_driver *drv)
1628 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1629 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1631 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1634 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1637 /* Power management related routines */
1638 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1639 static inline void pci_restore_state(struct pci_dev *dev) { }
1640 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1642 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1644 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1647 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1651 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1652 struct resource *res)
1654 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1656 static inline void pci_release_regions(struct pci_dev *dev) { }
1658 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1660 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1661 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1663 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1665 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1667 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1670 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1671 unsigned int bus, unsigned int devfn)
1674 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1675 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1676 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1678 #define dev_is_pci(d) (false)
1679 #define dev_is_pf(d) (false)
1680 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1682 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1683 struct device_node *node,
1685 unsigned int intsize,
1686 unsigned long *out_hwirq,
1687 unsigned int *out_type)
1689 #endif /* CONFIG_PCI */
1691 /* Include architecture-dependent settings and functions */
1693 #include <asm/pci.h>
1695 /* These two functions provide almost identical functionality. Depennding
1696 * on the architecture, one will be implemented as a wrapper around the
1697 * other (in drivers/pci/mmap.c).
1699 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1700 * is expected to be an offset within that region.
1702 * pci_mmap_page_range() is the legacy architecture-specific interface,
1703 * which accepts a "user visible" resource address converted by
1704 * pci_resource_to_user(), as used in the legacy mmap() interface in
1707 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1708 struct vm_area_struct *vma,
1709 enum pci_mmap_state mmap_state, int write_combine);
1710 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1711 struct vm_area_struct *vma,
1712 enum pci_mmap_state mmap_state, int write_combine);
1714 #ifndef arch_can_pci_mmap_wc
1715 #define arch_can_pci_mmap_wc() 0
1718 #ifndef arch_can_pci_mmap_io
1719 #define arch_can_pci_mmap_io() 0
1720 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1722 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1725 #ifndef pci_root_bus_fwnode
1726 #define pci_root_bus_fwnode(bus) NULL
1730 * These helpers provide future and backwards compatibility
1731 * for accessing popular PCI BAR info
1733 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1734 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1735 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1736 #define pci_resource_len(dev,bar) \
1737 ((pci_resource_start((dev), (bar)) == 0 && \
1738 pci_resource_end((dev), (bar)) == \
1739 pci_resource_start((dev), (bar))) ? 0 : \
1741 (pci_resource_end((dev), (bar)) - \
1742 pci_resource_start((dev), (bar)) + 1))
1745 * Similar to the helpers above, these manipulate per-pci_dev
1746 * driver-specific data. They are really just a wrapper around
1747 * the generic device structure functions of these calls.
1749 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1751 return dev_get_drvdata(&pdev->dev);
1754 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1756 dev_set_drvdata(&pdev->dev, data);
1759 static inline const char *pci_name(const struct pci_dev *pdev)
1761 return dev_name(&pdev->dev);
1766 * Some archs don't want to expose struct resource to userland as-is
1767 * in sysfs and /proc
1769 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1770 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1771 const struct resource *rsrc,
1772 resource_size_t *start, resource_size_t *end);
1774 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1775 const struct resource *rsrc, resource_size_t *start,
1776 resource_size_t *end)
1778 *start = rsrc->start;
1781 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1785 * The world is not perfect and supplies us with broken PCI devices.
1786 * For at least a part of these bugs we need a work-around, so both
1787 * generic (drivers/pci/quirks.c) and per-architecture code can define
1788 * fixup hooks to be called for particular buggy devices.
1792 u16 vendor; /* Or PCI_ANY_ID */
1793 u16 device; /* Or PCI_ANY_ID */
1794 u32 class; /* Or PCI_ANY_ID */
1795 unsigned int class_shift; /* should be 0, 8, 16 */
1796 void (*hook)(struct pci_dev *dev);
1799 enum pci_fixup_pass {
1800 pci_fixup_early, /* Before probing BARs */
1801 pci_fixup_header, /* After reading configuration header */
1802 pci_fixup_final, /* Final phase of device fixups */
1803 pci_fixup_enable, /* pci_enable_device() time */
1804 pci_fixup_resume, /* pci_device_resume() */
1805 pci_fixup_suspend, /* pci_device_suspend() */
1806 pci_fixup_resume_early, /* pci_device_resume_early() */
1807 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1810 /* Anonymous variables would be nice... */
1811 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1812 class_shift, hook) \
1813 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1814 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1815 = { vendor, device, class, class_shift, hook };
1817 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1818 class_shift, hook) \
1819 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1820 hook, vendor, device, class, class_shift, hook)
1821 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1822 class_shift, hook) \
1823 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1824 hook, vendor, device, class, class_shift, hook)
1825 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1826 class_shift, hook) \
1827 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1828 hook, vendor, device, class, class_shift, hook)
1829 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1830 class_shift, hook) \
1831 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1832 hook, vendor, device, class, class_shift, hook)
1833 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1834 class_shift, hook) \
1835 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1836 resume##hook, vendor, device, class, class_shift, hook)
1837 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1838 class_shift, hook) \
1839 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1840 resume_early##hook, vendor, device, class, class_shift, hook)
1841 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1842 class_shift, hook) \
1843 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1844 suspend##hook, vendor, device, class, class_shift, hook)
1845 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1846 class_shift, hook) \
1847 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1848 suspend_late##hook, vendor, device, class, class_shift, hook)
1850 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1851 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1852 hook, vendor, device, PCI_ANY_ID, 0, hook)
1853 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1854 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1855 hook, vendor, device, PCI_ANY_ID, 0, hook)
1856 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1857 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1858 hook, vendor, device, PCI_ANY_ID, 0, hook)
1859 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1860 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1861 hook, vendor, device, PCI_ANY_ID, 0, hook)
1862 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1863 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1864 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1865 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1866 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1867 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1868 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1869 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1870 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1871 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1872 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1873 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1875 #ifdef CONFIG_PCI_QUIRKS
1876 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1877 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1878 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1880 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1881 struct pci_dev *dev) { }
1882 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1887 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1893 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1894 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1895 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1896 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1897 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1899 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1901 extern int pci_pci_problems;
1902 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1903 #define PCIPCI_TRITON 2
1904 #define PCIPCI_NATOMA 4
1905 #define PCIPCI_VIAETBF 8
1906 #define PCIPCI_VSFX 16
1907 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1908 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1910 extern unsigned long pci_cardbus_io_size;
1911 extern unsigned long pci_cardbus_mem_size;
1912 extern u8 pci_dfl_cache_line_size;
1913 extern u8 pci_cache_line_size;
1915 extern unsigned long pci_hotplug_io_size;
1916 extern unsigned long pci_hotplug_mem_size;
1917 extern unsigned long pci_hotplug_bus_size;
1919 /* Architecture-specific versions may override these (weak) */
1920 void pcibios_disable_device(struct pci_dev *dev);
1921 void pcibios_set_master(struct pci_dev *dev);
1922 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1923 enum pcie_reset_state state);
1924 int pcibios_add_device(struct pci_dev *dev);
1925 void pcibios_release_device(struct pci_dev *dev);
1926 void pcibios_penalize_isa_irq(int irq, int active);
1927 int pcibios_alloc_irq(struct pci_dev *dev);
1928 void pcibios_free_irq(struct pci_dev *dev);
1929 resource_size_t pcibios_default_alignment(void);
1931 #ifdef CONFIG_HIBERNATE_CALLBACKS
1932 extern struct dev_pm_ops pcibios_pm_ops;
1935 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1936 void __init pci_mmcfg_early_init(void);
1937 void __init pci_mmcfg_late_init(void);
1939 static inline void pci_mmcfg_early_init(void) { }
1940 static inline void pci_mmcfg_late_init(void) { }
1943 int pci_ext_cfg_avail(void);
1945 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1946 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1948 #ifdef CONFIG_PCI_IOV
1949 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1950 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1952 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1953 void pci_disable_sriov(struct pci_dev *dev);
1954 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
1955 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
1956 int pci_num_vf(struct pci_dev *dev);
1957 int pci_vfs_assigned(struct pci_dev *dev);
1958 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1959 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1960 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1961 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
1963 /* Arch may override these (weak) */
1964 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
1965 int pcibios_sriov_disable(struct pci_dev *pdev);
1966 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1968 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1972 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1976 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1978 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
1982 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1984 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1985 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1986 static inline int pci_vfs_assigned(struct pci_dev *dev)
1988 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1990 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1992 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1994 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
1997 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1998 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1999 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2003 * pci_pcie_cap - get the saved PCIe capability offset
2006 * PCIe capability offset is calculated at PCI device initialization
2007 * time and saved in the data structure. This function returns saved
2008 * PCIe capability offset. Using this instead of pci_find_capability()
2009 * reduces unnecessary search in the PCI configuration space. If you
2010 * need to calculate PCIe capability offset from raw device for some
2011 * reasons, please use pci_find_capability() instead.
2013 static inline int pci_pcie_cap(struct pci_dev *dev)
2015 return dev->pcie_cap;
2019 * pci_is_pcie - check if the PCI device is PCI Express capable
2022 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2024 static inline bool pci_is_pcie(struct pci_dev *dev)
2026 return pci_pcie_cap(dev);
2030 * pcie_caps_reg - get the PCIe Capabilities Register
2033 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2035 return dev->pcie_flags_reg;
2039 * pci_pcie_type - get the PCIe device/port type
2042 static inline int pci_pcie_type(const struct pci_dev *dev)
2044 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2047 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2050 if (!pci_is_pcie(dev))
2052 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2054 if (!dev->bus->self)
2056 dev = dev->bus->self;
2061 void pci_request_acs(void);
2062 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2063 bool pci_acs_path_enabled(struct pci_dev *start,
2064 struct pci_dev *end, u16 acs_flags);
2065 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2067 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2068 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2070 /* Large Resource Data Type Tag Item Names */
2071 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2072 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2073 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2075 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2076 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2077 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2079 /* Small Resource Data Type Tag Item Names */
2080 #define PCI_VPD_STIN_END 0x0f /* End */
2082 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2084 #define PCI_VPD_SRDT_TIN_MASK 0x78
2085 #define PCI_VPD_SRDT_LEN_MASK 0x07
2086 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2088 #define PCI_VPD_LRDT_TAG_SIZE 3
2089 #define PCI_VPD_SRDT_TAG_SIZE 1
2091 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2093 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2094 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2095 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2096 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2099 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2100 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2102 * Returns the extracted Large Resource Data Type length.
2104 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2106 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2110 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2111 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2113 * Returns the extracted Large Resource Data Type Tag item.
2115 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2117 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2121 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2122 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2124 * Returns the extracted Small Resource Data Type length.
2126 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2128 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2132 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2133 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2135 * Returns the extracted Small Resource Data Type Tag Item.
2137 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2139 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2143 * pci_vpd_info_field_size - Extracts the information field length
2144 * @lrdt: Pointer to the beginning of an information field header
2146 * Returns the extracted information field length.
2148 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2150 return info_field[2];
2154 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2155 * @buf: Pointer to buffered vpd data
2156 * @off: The offset into the buffer at which to begin the search
2157 * @len: The length of the vpd buffer
2158 * @rdt: The Resource Data Type to search for
2160 * Returns the index where the Resource Data Type was found or
2161 * -ENOENT otherwise.
2163 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2166 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2167 * @buf: Pointer to buffered vpd data
2168 * @off: The offset into the buffer at which to begin the search
2169 * @len: The length of the buffer area, relative to off, in which to search
2170 * @kw: The keyword to search for
2172 * Returns the index where the information field keyword was found or
2173 * -ENOENT otherwise.
2175 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2176 unsigned int len, const char *kw);
2178 /* PCI <-> OF binding helpers */
2182 void pci_set_of_node(struct pci_dev *dev);
2183 void pci_release_of_node(struct pci_dev *dev);
2184 void pci_set_bus_of_node(struct pci_bus *bus);
2185 void pci_release_bus_of_node(struct pci_bus *bus);
2186 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2187 int pci_parse_request_of_pci_ranges(struct device *dev,
2188 struct list_head *resources,
2189 struct resource **bus_range);
2191 /* Arch may override this (weak) */
2192 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2194 #else /* CONFIG_OF */
2195 static inline void pci_set_of_node(struct pci_dev *dev) { }
2196 static inline void pci_release_of_node(struct pci_dev *dev) { }
2197 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2198 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2199 static inline struct irq_domain *
2200 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2201 static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2202 struct list_head *resources,
2203 struct resource **bus_range)
2207 #endif /* CONFIG_OF */
2209 static inline struct device_node *
2210 pci_device_to_OF_node(const struct pci_dev *pdev)
2212 return pdev ? pdev->dev.of_node : NULL;
2215 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2217 return bus ? bus->dev.of_node : NULL;
2221 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2224 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2226 static inline struct irq_domain *
2227 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2231 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2233 return pdev->dev.archdata.edev;
2237 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2238 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2239 int pci_for_each_dma_alias(struct pci_dev *pdev,
2240 int (*fn)(struct pci_dev *pdev,
2241 u16 alias, void *data), void *data);
2243 /* Helper functions for operation of device flag */
2244 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2246 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2248 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2250 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2252 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2254 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2258 * pci_ari_enabled - query ARI forwarding status
2261 * Returns true if ARI forwarding is enabled.
2263 static inline bool pci_ari_enabled(struct pci_bus *bus)
2265 return bus->self && bus->self->ari_enabled;
2269 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2270 * @pdev: PCI device to check
2272 * Walk upwards from @pdev and check for each encountered bridge if it's part
2273 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2274 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2276 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2278 struct pci_dev *parent = pdev;
2280 if (pdev->is_thunderbolt)
2283 while ((parent = pci_upstream_bridge(parent)))
2284 if (parent->is_thunderbolt)
2290 #if defined(CONFIG_PCIEAER) || defined(CONFIG_EEH)
2291 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2294 /* Provide the legacy pci_dma_* API */
2295 #include <linux/pci-dma-compat.h>
2297 #define pci_printk(level, pdev, fmt, arg...) \
2298 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2300 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2301 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2302 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2303 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2304 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2305 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2306 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2307 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2309 #endif /* LINUX_PCI_H */