1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
10 #include <linux/bits.h>
11 #include <linux/types.h>
12 #include <linux/uuid.h>
14 /* NQN names in commands fields specified one size */
15 #define NVMF_NQN_FIELD_LEN 256
17 /* However the max length of a qualified name is another size */
18 #define NVMF_NQN_SIZE 223
20 #define NVMF_TRSVCID_SIZE 32
21 #define NVMF_TRADDR_SIZE 256
22 #define NVMF_TSAS_SIZE 256
23 #define NVMF_AUTH_HASH_LEN 64
25 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
27 #define NVME_RDMA_IP_PORT 4420
29 #define NVME_NSID_ALL 0xffffffff
31 enum nvme_subsys_type {
32 /* Referral to another discovery type target subsystem */
35 /* NVME type target subsystem */
38 /* Current discovery type target subsystem */
43 NVME_CTRL_IO = 1, /* I/O controller */
44 NVME_CTRL_DISC = 2, /* Discovery controller */
45 NVME_CTRL_ADMIN = 3, /* Administrative controller */
49 NVME_DCTYPE_NOT_REPORTED = 0,
50 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */
51 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */
54 /* Address Family codes for Discovery Log Page entry ADRFAM field */
56 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
57 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
58 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
59 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
60 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
61 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
65 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
67 NVMF_TRTYPE_RDMA = 1, /* RDMA */
68 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
69 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
70 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
74 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
76 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
77 NVMF_TREQ_REQUIRED = 1, /* Required */
78 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
79 #define NVME_TREQ_SECURE_CHANNEL_MASK \
80 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
82 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
85 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
89 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
90 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
93 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
97 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
98 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
99 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
100 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
101 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
104 /* RDMA Connection Management Service Type codes for Discovery Log Page
105 * entry TSAS RDMA_CMS field
108 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
111 #define NVME_AQ_DEPTH 32
112 #define NVME_NR_AEN_COMMANDS 1
113 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
116 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
117 * NVM-Express 1.2 specification, section 4.1.2.
119 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
122 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
123 NVME_REG_VS = 0x0008, /* Version */
124 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
125 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
126 NVME_REG_CC = 0x0014, /* Controller Configuration */
127 NVME_REG_CSTS = 0x001c, /* Controller Status */
128 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
129 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
130 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
131 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
132 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
133 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
134 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
135 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
136 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
139 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
142 NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */
143 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
144 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
145 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
146 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
149 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
152 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
155 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
156 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
157 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
158 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
159 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
160 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
161 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
162 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
164 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
165 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
167 #define NVME_CRTO_CRIMT(crto) ((crto) >> 16)
168 #define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff)
171 NVME_CMBSZ_SQS = 1 << 0,
172 NVME_CMBSZ_CQS = 1 << 1,
173 NVME_CMBSZ_LISTS = 1 << 2,
174 NVME_CMBSZ_RDS = 1 << 3,
175 NVME_CMBSZ_WDS = 1 << 4,
177 NVME_CMBSZ_SZ_SHIFT = 12,
178 NVME_CMBSZ_SZ_MASK = 0xfffff,
180 NVME_CMBSZ_SZU_SHIFT = 8,
181 NVME_CMBSZ_SZU_MASK = 0xf,
185 * Submission and Completion Queue Entry Sizes for the NVM command set.
186 * (In bytes and specified as a power of two (2^n)).
188 #define NVME_ADM_SQES 6
189 #define NVME_NVM_IOSQES 6
190 #define NVME_NVM_IOCQES 4
193 NVME_CC_ENABLE = 1 << 0,
194 NVME_CC_EN_SHIFT = 0,
195 NVME_CC_CSS_SHIFT = 4,
196 NVME_CC_MPS_SHIFT = 7,
197 NVME_CC_AMS_SHIFT = 11,
198 NVME_CC_SHN_SHIFT = 14,
199 NVME_CC_IOSQES_SHIFT = 16,
200 NVME_CC_IOCQES_SHIFT = 20,
201 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
202 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
203 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
204 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
205 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
206 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
207 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
208 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
209 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
210 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
211 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
212 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
213 NVME_CC_CRIME = 1 << 24,
217 NVME_CSTS_RDY = 1 << 0,
218 NVME_CSTS_CFS = 1 << 1,
219 NVME_CSTS_NSSRO = 1 << 4,
220 NVME_CSTS_PP = 1 << 5,
221 NVME_CSTS_SHST_NORMAL = 0 << 2,
222 NVME_CSTS_SHST_OCCUR = 1 << 2,
223 NVME_CSTS_SHST_CMPLT = 2 << 2,
224 NVME_CSTS_SHST_MASK = 3 << 2,
228 NVME_CMBMSC_CRE = 1 << 0,
229 NVME_CMBMSC_CMSE = 1 << 1,
233 NVME_CAP_CSS_NVM = 1 << 0,
234 NVME_CAP_CSS_CSI = 1 << 6,
238 NVME_CAP_CRMS_CRWMS = 1ULL << 59,
239 NVME_CAP_CRMS_CRIMS = 1ULL << 60,
242 struct nvme_id_power_state {
243 __le16 max_power; /* centiwatts */
246 __le32 entry_lat; /* microseconds */
247 __le32 exit_lat; /* microseconds */
256 __u8 active_work_scale;
261 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
262 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
265 enum nvme_ctrl_attr {
266 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
267 NVME_CTRL_ATTR_TBKAS = (1 << 6),
268 NVME_CTRL_ATTR_ELBAS = (1 << 15),
271 struct nvme_id_ctrl {
354 struct nvme_id_power_state psd[32];
359 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0,
360 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
361 NVME_CTRL_CMIC_ANA = 1 << 3,
362 NVME_CTRL_ONCS_COMPARE = 1 << 0,
363 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
364 NVME_CTRL_ONCS_DSM = 1 << 2,
365 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
366 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
367 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
368 NVME_CTRL_VWC_PRESENT = 1 << 0,
369 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
370 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3,
371 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
372 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
373 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
374 NVME_CTRL_CTRATT_128_ID = 1 << 0,
375 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
376 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
377 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
378 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
379 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
380 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
381 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
425 struct nvme_lbaf lbaf[64];
429 /* I/O Command Set Independent Identify Namespace Data Structure */
430 struct nvme_id_ns_cs_indep {
444 struct nvme_zns_lbafe {
450 struct nvme_id_ns_zns {
458 struct nvme_zns_lbafe lbafe[64];
462 struct nvme_id_ctrl_zns {
467 struct nvme_id_ns_nvm {
476 NVME_ID_NS_NVM_STS_MASK = 0x3f,
477 NVME_ID_NS_NVM_GUARD_SHIFT = 7,
478 NVME_ID_NS_NVM_GUARD_MASK = 0x3,
481 static inline __u8 nvme_elbaf_sts(__u32 elbaf)
483 return elbaf & NVME_ID_NS_NVM_STS_MASK;
486 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
488 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
491 struct nvme_id_ctrl_nvm {
502 NVME_ID_CNS_NS = 0x00,
503 NVME_ID_CNS_CTRL = 0x01,
504 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
505 NVME_ID_CNS_NS_DESC_LIST = 0x03,
506 NVME_ID_CNS_CS_NS = 0x05,
507 NVME_ID_CNS_CS_CTRL = 0x06,
508 NVME_ID_CNS_NS_CS_INDEP = 0x08,
509 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
510 NVME_ID_CNS_NS_PRESENT = 0x11,
511 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
512 NVME_ID_CNS_CTRL_LIST = 0x13,
513 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
514 NVME_ID_CNS_NS_GRANULARITY = 0x16,
515 NVME_ID_CNS_UUID_LIST = 0x17,
524 NVME_DIR_IDENTIFY = 0x00,
525 NVME_DIR_STREAMS = 0x01,
526 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
527 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
528 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
529 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
530 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
531 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
532 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
533 NVME_DIR_ENDIR = 0x01,
537 NVME_NS_FEAT_THIN = 1 << 0,
538 NVME_NS_FEAT_ATOMICS = 1 << 1,
539 NVME_NS_FEAT_IO_OPT = 1 << 4,
540 NVME_NS_ATTR_RO = 1 << 0,
541 NVME_NS_FLBAS_LBA_MASK = 0xf,
542 NVME_NS_FLBAS_LBA_UMASK = 0x60,
543 NVME_NS_FLBAS_LBA_SHIFT = 1,
544 NVME_NS_FLBAS_META_EXT = 0x10,
545 NVME_NS_NMIC_SHARED = 1 << 0,
546 NVME_LBAF_RP_BEST = 0,
547 NVME_LBAF_RP_BETTER = 1,
548 NVME_LBAF_RP_GOOD = 2,
549 NVME_LBAF_RP_DEGRADED = 3,
550 NVME_NS_DPC_PI_LAST = 1 << 4,
551 NVME_NS_DPC_PI_FIRST = 1 << 3,
552 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
553 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
554 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
555 NVME_NS_DPS_PI_FIRST = 1 << 3,
556 NVME_NS_DPS_PI_MASK = 0x7,
557 NVME_NS_DPS_PI_TYPE1 = 1,
558 NVME_NS_DPS_PI_TYPE2 = 2,
559 NVME_NS_DPS_PI_TYPE3 = 3,
563 NVME_NSTAT_NRDY = 1 << 0,
567 NVME_NVM_NS_16B_GUARD = 0,
568 NVME_NVM_NS_32B_GUARD = 1,
569 NVME_NVM_NS_64B_GUARD = 2,
572 static inline __u8 nvme_lbaf_index(__u8 flbas)
574 return (flbas & NVME_NS_FLBAS_LBA_MASK) |
575 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
578 /* Identify Namespace Metadata Capabilities (MC): */
580 NVME_MC_EXTENDED_LBA = (1 << 0),
581 NVME_MC_METADATA_PTR = (1 << 1),
584 struct nvme_ns_id_desc {
590 #define NVME_NIDT_EUI64_LEN 8
591 #define NVME_NIDT_NGUID_LEN 16
592 #define NVME_NIDT_UUID_LEN 16
593 #define NVME_NIDT_CSI_LEN 1
596 NVME_NIDT_EUI64 = 0x01,
597 NVME_NIDT_NGUID = 0x02,
598 NVME_NIDT_UUID = 0x03,
599 NVME_NIDT_CSI = 0x04,
602 struct nvme_smart_log {
603 __u8 critical_warning;
608 __u8 endu_grp_crit_warn_sumry;
610 __u8 data_units_read[16];
611 __u8 data_units_written[16];
613 __u8 host_writes[16];
614 __u8 ctrl_busy_time[16];
615 __u8 power_cycles[16];
616 __u8 power_on_hours[16];
617 __u8 unsafe_shutdowns[16];
618 __u8 media_errors[16];
619 __u8 num_err_log_entries[16];
620 __le32 warning_temp_time;
621 __le32 critical_comp_time;
622 __le16 temp_sensor[8];
623 __le32 thm_temp1_trans_count;
624 __le32 thm_temp2_trans_count;
625 __le32 thm_temp1_total_time;
626 __le32 thm_temp2_total_time;
630 struct nvme_fw_slot_info_log {
638 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
639 NVME_CMD_EFFECTS_LBCC = 1 << 1,
640 NVME_CMD_EFFECTS_NCC = 1 << 2,
641 NVME_CMD_EFFECTS_NIC = 1 << 3,
642 NVME_CMD_EFFECTS_CCC = 1 << 4,
643 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),
644 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
645 NVME_CMD_EFFECTS_SCOPE_MASK = GENMASK(31, 20),
648 struct nvme_effects_log {
654 enum nvme_ana_state {
655 NVME_ANA_OPTIMIZED = 0x01,
656 NVME_ANA_NONOPTIMIZED = 0x02,
657 NVME_ANA_INACCESSIBLE = 0x03,
658 NVME_ANA_PERSISTENT_LOSS = 0x04,
659 NVME_ANA_CHANGE = 0x0f,
662 struct nvme_ana_group_desc {
671 /* flag for the log specific field of the ANA log */
672 #define NVME_ANA_LOG_RGO (1 << 0)
674 struct nvme_ana_rsp_hdr {
680 struct nvme_zone_descriptor {
692 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
695 struct nvme_zone_report {
698 struct nvme_zone_descriptor entries[];
702 NVME_SMART_CRIT_SPARE = 1 << 0,
703 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
704 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
705 NVME_SMART_CRIT_MEDIA = 1 << 3,
706 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
718 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
722 NVME_AER_NOTICE_NS_CHANGED = 0x00,
723 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
724 NVME_AER_NOTICE_ANA = 0x03,
725 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
729 NVME_AEN_BIT_NS_ATTR = 8,
730 NVME_AEN_BIT_FW_ACT = 9,
731 NVME_AEN_BIT_ANA_CHANGE = 11,
732 NVME_AEN_BIT_DISC_CHANGE = 31,
736 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
737 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
738 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
739 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
742 struct nvme_lba_range_type {
753 NVME_LBART_TYPE_FS = 0x01,
754 NVME_LBART_TYPE_RAID = 0x02,
755 NVME_LBART_TYPE_CACHE = 0x03,
756 NVME_LBART_TYPE_SWAP = 0x04,
758 NVME_LBART_ATTRIB_TEMP = 1 << 0,
759 NVME_LBART_ATTRIB_HIDE = 1 << 1,
762 struct nvme_reservation_status {
778 enum nvme_async_event_type {
779 NVME_AER_TYPE_ERROR = 0,
780 NVME_AER_TYPE_SMART = 1,
781 NVME_AER_TYPE_NOTICE = 2,
787 nvme_cmd_flush = 0x00,
788 nvme_cmd_write = 0x01,
789 nvme_cmd_read = 0x02,
790 nvme_cmd_write_uncor = 0x04,
791 nvme_cmd_compare = 0x05,
792 nvme_cmd_write_zeroes = 0x08,
794 nvme_cmd_verify = 0x0c,
795 nvme_cmd_resv_register = 0x0d,
796 nvme_cmd_resv_report = 0x0e,
797 nvme_cmd_resv_acquire = 0x11,
798 nvme_cmd_resv_release = 0x15,
799 nvme_cmd_zone_mgmt_send = 0x79,
800 nvme_cmd_zone_mgmt_recv = 0x7a,
801 nvme_cmd_zone_append = 0x7d,
802 nvme_cmd_vendor_start = 0x80,
805 #define nvme_opcode_name(opcode) { opcode, #opcode }
806 #define show_nvm_opcode_name(val) \
807 __print_symbolic(val, \
808 nvme_opcode_name(nvme_cmd_flush), \
809 nvme_opcode_name(nvme_cmd_write), \
810 nvme_opcode_name(nvme_cmd_read), \
811 nvme_opcode_name(nvme_cmd_write_uncor), \
812 nvme_opcode_name(nvme_cmd_compare), \
813 nvme_opcode_name(nvme_cmd_write_zeroes), \
814 nvme_opcode_name(nvme_cmd_dsm), \
815 nvme_opcode_name(nvme_cmd_verify), \
816 nvme_opcode_name(nvme_cmd_resv_register), \
817 nvme_opcode_name(nvme_cmd_resv_report), \
818 nvme_opcode_name(nvme_cmd_resv_acquire), \
819 nvme_opcode_name(nvme_cmd_resv_release), \
820 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
821 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
822 nvme_opcode_name(nvme_cmd_zone_append))
827 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
829 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
830 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
831 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
832 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
836 NVME_SGL_FMT_ADDRESS = 0x00,
837 NVME_SGL_FMT_OFFSET = 0x01,
838 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
839 NVME_SGL_FMT_INVALIDATE = 0x0f,
843 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
845 * For struct nvme_sgl_desc:
846 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
847 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
848 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
850 * For struct nvme_keyed_sgl_desc:
851 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
853 * Transport-specific SGL types:
854 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
857 NVME_SGL_FMT_DATA_DESC = 0x00,
858 NVME_SGL_FMT_SEG_DESC = 0x02,
859 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
860 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
861 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
864 struct nvme_sgl_desc {
871 struct nvme_keyed_sgl_desc {
878 union nvme_data_ptr {
883 struct nvme_sgl_desc sgl;
884 struct nvme_keyed_sgl_desc ksgl;
888 * Lowest two bits of our flags field (FUSE field in the spec):
890 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
891 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
893 * Highest two bits in our flags field (PSDT field in the spec):
895 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
896 * If used, MPTR contains addr of single physical buffer (byte aligned).
897 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
898 * If used, MPTR contains an address of an SGL segment containing
899 * exactly 1 SGL descriptor (qword aligned).
902 NVME_CMD_FUSE_FIRST = (1 << 0),
903 NVME_CMD_FUSE_SECOND = (1 << 1),
905 NVME_CMD_SGL_METABUF = (1 << 6),
906 NVME_CMD_SGL_METASEG = (1 << 7),
907 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
910 struct nvme_common_command {
917 union nvme_data_ptr dptr;
928 struct nvme_rw_command {
936 union nvme_data_ptr dptr;
947 NVME_RW_LR = 1 << 15,
948 NVME_RW_FUA = 1 << 14,
949 NVME_RW_APPEND_PIREMAP = 1 << 9,
950 NVME_RW_DSM_FREQ_UNSPEC = 0,
951 NVME_RW_DSM_FREQ_TYPICAL = 1,
952 NVME_RW_DSM_FREQ_RARE = 2,
953 NVME_RW_DSM_FREQ_READS = 3,
954 NVME_RW_DSM_FREQ_WRITES = 4,
955 NVME_RW_DSM_FREQ_RW = 5,
956 NVME_RW_DSM_FREQ_ONCE = 6,
957 NVME_RW_DSM_FREQ_PREFETCH = 7,
958 NVME_RW_DSM_FREQ_TEMP = 8,
959 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
960 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
961 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
962 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
963 NVME_RW_DSM_SEQ_REQ = 1 << 6,
964 NVME_RW_DSM_COMPRESSED = 1 << 7,
965 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
966 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
967 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
968 NVME_RW_PRINFO_PRACT = 1 << 13,
969 NVME_RW_DTYPE_STREAMS = 1 << 4,
970 NVME_WZ_DEAC = 1 << 9,
973 struct nvme_dsm_cmd {
979 union nvme_data_ptr dptr;
986 NVME_DSMGMT_IDR = 1 << 0,
987 NVME_DSMGMT_IDW = 1 << 1,
988 NVME_DSMGMT_AD = 1 << 2,
991 #define NVME_DSM_MAX_RANGES 256
993 struct nvme_dsm_range {
999 struct nvme_write_zeroes_cmd {
1006 union nvme_data_ptr dptr;
1016 enum nvme_zone_mgmt_action {
1017 NVME_ZONE_CLOSE = 0x1,
1018 NVME_ZONE_FINISH = 0x2,
1019 NVME_ZONE_OPEN = 0x3,
1020 NVME_ZONE_RESET = 0x4,
1021 NVME_ZONE_OFFLINE = 0x5,
1022 NVME_ZONE_SET_DESC_EXT = 0x10,
1025 struct nvme_zone_mgmt_send_cmd {
1032 union nvme_data_ptr dptr;
1041 struct nvme_zone_mgmt_recv_cmd {
1047 union nvme_data_ptr dptr;
1058 NVME_ZRA_ZONE_REPORT = 0,
1059 NVME_ZRASF_ZONE_REPORT_ALL = 0,
1060 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
1061 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02,
1062 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03,
1063 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04,
1064 NVME_ZRASF_ZONE_STATE_READONLY = 0x05,
1065 NVME_ZRASF_ZONE_STATE_FULL = 0x06,
1066 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07,
1067 NVME_REPORT_ZONE_PARTIAL = 1,
1073 NVME_TEMP_THRESH_MASK = 0xffff,
1074 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
1075 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
1078 struct nvme_feat_auto_pst {
1083 NVME_HOST_MEM_ENABLE = (1 << 0),
1084 NVME_HOST_MEM_RETURN = (1 << 1),
1087 struct nvme_feat_host_behavior {
1095 NVME_ENABLE_ACRE = 1,
1096 NVME_ENABLE_LBAFEE = 1,
1099 /* Admin commands */
1101 enum nvme_admin_opcode {
1102 nvme_admin_delete_sq = 0x00,
1103 nvme_admin_create_sq = 0x01,
1104 nvme_admin_get_log_page = 0x02,
1105 nvme_admin_delete_cq = 0x04,
1106 nvme_admin_create_cq = 0x05,
1107 nvme_admin_identify = 0x06,
1108 nvme_admin_abort_cmd = 0x08,
1109 nvme_admin_set_features = 0x09,
1110 nvme_admin_get_features = 0x0a,
1111 nvme_admin_async_event = 0x0c,
1112 nvme_admin_ns_mgmt = 0x0d,
1113 nvme_admin_activate_fw = 0x10,
1114 nvme_admin_download_fw = 0x11,
1115 nvme_admin_dev_self_test = 0x14,
1116 nvme_admin_ns_attach = 0x15,
1117 nvme_admin_keep_alive = 0x18,
1118 nvme_admin_directive_send = 0x19,
1119 nvme_admin_directive_recv = 0x1a,
1120 nvme_admin_virtual_mgmt = 0x1c,
1121 nvme_admin_nvme_mi_send = 0x1d,
1122 nvme_admin_nvme_mi_recv = 0x1e,
1123 nvme_admin_dbbuf = 0x7C,
1124 nvme_admin_format_nvm = 0x80,
1125 nvme_admin_security_send = 0x81,
1126 nvme_admin_security_recv = 0x82,
1127 nvme_admin_sanitize_nvm = 0x84,
1128 nvme_admin_get_lba_status = 0x86,
1129 nvme_admin_vendor_start = 0xC0,
1132 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1133 #define show_admin_opcode_name(val) \
1134 __print_symbolic(val, \
1135 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1136 nvme_admin_opcode_name(nvme_admin_create_sq), \
1137 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1138 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1139 nvme_admin_opcode_name(nvme_admin_create_cq), \
1140 nvme_admin_opcode_name(nvme_admin_identify), \
1141 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1142 nvme_admin_opcode_name(nvme_admin_set_features), \
1143 nvme_admin_opcode_name(nvme_admin_get_features), \
1144 nvme_admin_opcode_name(nvme_admin_async_event), \
1145 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1146 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1147 nvme_admin_opcode_name(nvme_admin_download_fw), \
1148 nvme_admin_opcode_name(nvme_admin_dev_self_test), \
1149 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1150 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1151 nvme_admin_opcode_name(nvme_admin_directive_send), \
1152 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1153 nvme_admin_opcode_name(nvme_admin_virtual_mgmt), \
1154 nvme_admin_opcode_name(nvme_admin_nvme_mi_send), \
1155 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv), \
1156 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1157 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1158 nvme_admin_opcode_name(nvme_admin_security_send), \
1159 nvme_admin_opcode_name(nvme_admin_security_recv), \
1160 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1161 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1164 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1165 NVME_CQ_IRQ_ENABLED = (1 << 1),
1166 NVME_SQ_PRIO_URGENT = (0 << 1),
1167 NVME_SQ_PRIO_HIGH = (1 << 1),
1168 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1169 NVME_SQ_PRIO_LOW = (3 << 1),
1170 NVME_FEAT_ARBITRATION = 0x01,
1171 NVME_FEAT_POWER_MGMT = 0x02,
1172 NVME_FEAT_LBA_RANGE = 0x03,
1173 NVME_FEAT_TEMP_THRESH = 0x04,
1174 NVME_FEAT_ERR_RECOVERY = 0x05,
1175 NVME_FEAT_VOLATILE_WC = 0x06,
1176 NVME_FEAT_NUM_QUEUES = 0x07,
1177 NVME_FEAT_IRQ_COALESCE = 0x08,
1178 NVME_FEAT_IRQ_CONFIG = 0x09,
1179 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1180 NVME_FEAT_ASYNC_EVENT = 0x0b,
1181 NVME_FEAT_AUTO_PST = 0x0c,
1182 NVME_FEAT_HOST_MEM_BUF = 0x0d,
1183 NVME_FEAT_TIMESTAMP = 0x0e,
1184 NVME_FEAT_KATO = 0x0f,
1185 NVME_FEAT_HCTM = 0x10,
1186 NVME_FEAT_NOPSC = 0x11,
1187 NVME_FEAT_RRL = 0x12,
1188 NVME_FEAT_PLM_CONFIG = 0x13,
1189 NVME_FEAT_PLM_WINDOW = 0x14,
1190 NVME_FEAT_HOST_BEHAVIOR = 0x16,
1191 NVME_FEAT_SANITIZE = 0x17,
1192 NVME_FEAT_SW_PROGRESS = 0x80,
1193 NVME_FEAT_HOST_ID = 0x81,
1194 NVME_FEAT_RESV_MASK = 0x82,
1195 NVME_FEAT_RESV_PERSIST = 0x83,
1196 NVME_FEAT_WRITE_PROTECT = 0x84,
1197 NVME_FEAT_VENDOR_START = 0xC0,
1198 NVME_FEAT_VENDOR_END = 0xFF,
1199 NVME_LOG_ERROR = 0x01,
1200 NVME_LOG_SMART = 0x02,
1201 NVME_LOG_FW_SLOT = 0x03,
1202 NVME_LOG_CHANGED_NS = 0x04,
1203 NVME_LOG_CMD_EFFECTS = 0x05,
1204 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1205 NVME_LOG_TELEMETRY_HOST = 0x07,
1206 NVME_LOG_TELEMETRY_CTRL = 0x08,
1207 NVME_LOG_ENDURANCE_GROUP = 0x09,
1208 NVME_LOG_ANA = 0x0c,
1209 NVME_LOG_DISC = 0x70,
1210 NVME_LOG_RESERVATION = 0x80,
1211 NVME_FWACT_REPL = (0 << 3),
1212 NVME_FWACT_REPL_ACTV = (1 << 3),
1213 NVME_FWACT_ACTV = (2 << 3),
1216 /* NVMe Namespace Write Protect State */
1218 NVME_NS_NO_WRITE_PROTECT = 0,
1219 NVME_NS_WRITE_PROTECT,
1220 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1221 NVME_NS_WRITE_PROTECT_PERMANENT,
1224 #define NVME_MAX_CHANGED_NAMESPACES 1024
1226 struct nvme_identify {
1232 union nvme_data_ptr dptr;
1241 #define NVME_IDENTIFY_DATA_SIZE 4096
1243 struct nvme_features {
1249 union nvme_data_ptr dptr;
1258 struct nvme_host_mem_buf_desc {
1264 struct nvme_create_cq {
1278 struct nvme_create_sq {
1292 struct nvme_delete_queue {
1302 struct nvme_abort_cmd {
1312 struct nvme_download_firmware {
1317 union nvme_data_ptr dptr;
1323 struct nvme_format_cmd {
1333 struct nvme_get_log_page_command {
1339 union nvme_data_ptr dptr;
1341 __u8 lsp; /* upper 4 bits reserved */
1357 struct nvme_directive_cmd {
1363 union nvme_data_ptr dptr;
1376 * Fabrics subcommands.
1378 enum nvmf_fabrics_opcode {
1379 nvme_fabrics_command = 0x7f,
1382 enum nvmf_capsule_command {
1383 nvme_fabrics_type_property_set = 0x00,
1384 nvme_fabrics_type_connect = 0x01,
1385 nvme_fabrics_type_property_get = 0x04,
1386 nvme_fabrics_type_auth_send = 0x05,
1387 nvme_fabrics_type_auth_receive = 0x06,
1390 #define nvme_fabrics_type_name(type) { type, #type }
1391 #define show_fabrics_type_name(type) \
1392 __print_symbolic(type, \
1393 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1394 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1395 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1396 nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \
1397 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
1400 * If not fabrics command, fctype will be ignored.
1402 #define show_opcode_name(qid, opcode, fctype) \
1403 ((opcode) == nvme_fabrics_command ? \
1404 show_fabrics_type_name(fctype) : \
1406 show_nvm_opcode_name(opcode) : \
1407 show_admin_opcode_name(opcode)))
1409 struct nvmf_common_command {
1419 * The legal cntlid range a NVMe Target will provide.
1420 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1421 * Devices based on earlier specs did not have the subsystem concept;
1422 * therefore, those devices had their cntlid value set to 0 as a result.
1424 #define NVME_CNTLID_MIN 1
1425 #define NVME_CNTLID_MAX 0xffef
1426 #define NVME_CNTLID_DYNAMIC 0xffff
1428 #define MAX_DISC_LOGS 255
1430 /* Discovery log page entry flags (EFLAGS): */
1432 NVME_DISC_EFLAGS_EPCSD = (1 << 1),
1433 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0),
1436 /* Discovery log page entry */
1437 struct nvmf_disc_rsp_page_entry {
1447 char trsvcid[NVMF_TRSVCID_SIZE];
1449 char subnqn[NVMF_NQN_FIELD_LEN];
1450 char traddr[NVMF_TRADDR_SIZE];
1452 char common[NVMF_TSAS_SIZE];
1464 /* Discovery log page header */
1465 struct nvmf_disc_rsp_page_hdr {
1470 struct nvmf_disc_rsp_page_entry entries[];
1474 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1477 struct nvmf_connect_command {
1483 union nvme_data_ptr dptr;
1494 NVME_CONNECT_AUTHREQ_ASCR = (1U << 18),
1495 NVME_CONNECT_AUTHREQ_ATR = (1U << 17),
1498 struct nvmf_connect_data {
1502 char subsysnqn[NVMF_NQN_FIELD_LEN];
1503 char hostnqn[NVMF_NQN_FIELD_LEN];
1507 struct nvmf_property_set_command {
1520 struct nvmf_property_get_command {
1532 struct nvmf_auth_common_command {
1538 union nvme_data_ptr dptr;
1547 struct nvmf_auth_send_command {
1553 union nvme_data_ptr dptr;
1562 struct nvmf_auth_receive_command {
1568 union nvme_data_ptr dptr;
1577 /* Value for secp */
1579 NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9,
1582 /* Defined value for auth_type */
1584 NVME_AUTH_COMMON_MESSAGES = 0x00,
1585 NVME_AUTH_DHCHAP_MESSAGES = 0x01,
1588 /* Defined messages for auth_id */
1590 NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00,
1591 NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01,
1592 NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02,
1593 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03,
1594 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04,
1595 NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0,
1596 NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1,
1599 struct nvmf_auth_dhchap_protocol_descriptor {
1608 NVME_AUTH_DHCHAP_AUTH_ID = 0x01,
1611 /* Defined hash functions for DH-HMAC-CHAP authentication */
1613 NVME_AUTH_HASH_SHA256 = 0x01,
1614 NVME_AUTH_HASH_SHA384 = 0x02,
1615 NVME_AUTH_HASH_SHA512 = 0x03,
1616 NVME_AUTH_HASH_INVALID = 0xff,
1619 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1621 NVME_AUTH_DHGROUP_NULL = 0x00,
1622 NVME_AUTH_DHGROUP_2048 = 0x01,
1623 NVME_AUTH_DHGROUP_3072 = 0x02,
1624 NVME_AUTH_DHGROUP_4096 = 0x03,
1625 NVME_AUTH_DHGROUP_6144 = 0x04,
1626 NVME_AUTH_DHGROUP_8192 = 0x05,
1627 NVME_AUTH_DHGROUP_INVALID = 0xff,
1630 union nvmf_auth_protocol {
1631 struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1634 struct nvmf_auth_dhchap_negotiate_data {
1641 union nvmf_auth_protocol auth_protocol[];
1644 struct nvmf_auth_dhchap_challenge_data {
1655 /* 'hl' bytes of challenge value */
1657 /* followed by 'dhvlen' bytes of DH value */
1660 struct nvmf_auth_dhchap_reply_data {
1671 /* 'hl' bytes of response data */
1673 /* followed by 'hl' bytes of Challenge value */
1674 /* followed by 'dhvlen' bytes of DH value */
1678 NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
1681 struct nvmf_auth_dhchap_success1_data {
1690 /* 'hl' bytes of response value if 'rvalid' is set */
1694 struct nvmf_auth_dhchap_success2_data {
1702 struct nvmf_auth_dhchap_failure_data {
1712 NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01,
1716 NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01,
1717 NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02,
1718 NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03,
1719 NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04,
1720 NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05,
1721 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06,
1722 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07,
1736 struct streams_directive_params {
1748 struct nvme_command {
1750 struct nvme_common_command common;
1751 struct nvme_rw_command rw;
1752 struct nvme_identify identify;
1753 struct nvme_features features;
1754 struct nvme_create_cq create_cq;
1755 struct nvme_create_sq create_sq;
1756 struct nvme_delete_queue delete_queue;
1757 struct nvme_download_firmware dlfw;
1758 struct nvme_format_cmd format;
1759 struct nvme_dsm_cmd dsm;
1760 struct nvme_write_zeroes_cmd write_zeroes;
1761 struct nvme_zone_mgmt_send_cmd zms;
1762 struct nvme_zone_mgmt_recv_cmd zmr;
1763 struct nvme_abort_cmd abort;
1764 struct nvme_get_log_page_command get_log_page;
1765 struct nvmf_common_command fabrics;
1766 struct nvmf_connect_command connect;
1767 struct nvmf_property_set_command prop_set;
1768 struct nvmf_property_get_command prop_get;
1769 struct nvmf_auth_common_command auth_common;
1770 struct nvmf_auth_send_command auth_send;
1771 struct nvmf_auth_receive_command auth_receive;
1772 struct nvme_dbbuf dbbuf;
1773 struct nvme_directive_cmd directive;
1777 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1779 return cmd->common.opcode == nvme_fabrics_command;
1782 struct nvme_error_slot {
1786 __le16 status_field;
1787 __le16 param_error_location;
1796 static inline bool nvme_is_write(struct nvme_command *cmd)
1801 * Why can't we simply have a Fabrics In and Fabrics out command?
1803 if (unlikely(nvme_is_fabrics(cmd)))
1804 return cmd->fabrics.fctype & 1;
1805 return cmd->common.opcode & 1;
1810 * Generic Command Status:
1812 NVME_SC_SUCCESS = 0x0,
1813 NVME_SC_INVALID_OPCODE = 0x1,
1814 NVME_SC_INVALID_FIELD = 0x2,
1815 NVME_SC_CMDID_CONFLICT = 0x3,
1816 NVME_SC_DATA_XFER_ERROR = 0x4,
1817 NVME_SC_POWER_LOSS = 0x5,
1818 NVME_SC_INTERNAL = 0x6,
1819 NVME_SC_ABORT_REQ = 0x7,
1820 NVME_SC_ABORT_QUEUE = 0x8,
1821 NVME_SC_FUSED_FAIL = 0x9,
1822 NVME_SC_FUSED_MISSING = 0xa,
1823 NVME_SC_INVALID_NS = 0xb,
1824 NVME_SC_CMD_SEQ_ERROR = 0xc,
1825 NVME_SC_SGL_INVALID_LAST = 0xd,
1826 NVME_SC_SGL_INVALID_COUNT = 0xe,
1827 NVME_SC_SGL_INVALID_DATA = 0xf,
1828 NVME_SC_SGL_INVALID_METADATA = 0x10,
1829 NVME_SC_SGL_INVALID_TYPE = 0x11,
1830 NVME_SC_CMB_INVALID_USE = 0x12,
1831 NVME_SC_PRP_INVALID_OFFSET = 0x13,
1832 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
1833 NVME_SC_OP_DENIED = 0x15,
1834 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1835 NVME_SC_RESERVED = 0x17,
1836 NVME_SC_HOST_ID_INCONSIST = 0x18,
1837 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
1838 NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
1839 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
1840 NVME_SC_SANITIZE_FAILED = 0x1C,
1841 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1842 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1843 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
1844 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1845 NVME_SC_CMD_INTERRUPTED = 0x21,
1846 NVME_SC_TRANSIENT_TR_ERR = 0x22,
1847 NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
1848 NVME_SC_INVALID_IO_CMD_SET = 0x2C,
1850 NVME_SC_LBA_RANGE = 0x80,
1851 NVME_SC_CAP_EXCEEDED = 0x81,
1852 NVME_SC_NS_NOT_READY = 0x82,
1853 NVME_SC_RESERVATION_CONFLICT = 0x83,
1854 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
1857 * Command Specific Status:
1859 NVME_SC_CQ_INVALID = 0x100,
1860 NVME_SC_QID_INVALID = 0x101,
1861 NVME_SC_QUEUE_SIZE = 0x102,
1862 NVME_SC_ABORT_LIMIT = 0x103,
1863 NVME_SC_ABORT_MISSING = 0x104,
1864 NVME_SC_ASYNC_LIMIT = 0x105,
1865 NVME_SC_FIRMWARE_SLOT = 0x106,
1866 NVME_SC_FIRMWARE_IMAGE = 0x107,
1867 NVME_SC_INVALID_VECTOR = 0x108,
1868 NVME_SC_INVALID_LOG_PAGE = 0x109,
1869 NVME_SC_INVALID_FORMAT = 0x10a,
1870 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1871 NVME_SC_INVALID_QUEUE = 0x10c,
1872 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1873 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1874 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1875 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1876 NVME_SC_FW_NEEDS_RESET = 0x111,
1877 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1878 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1879 NVME_SC_OVERLAPPING_RANGE = 0x114,
1880 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1881 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1882 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1883 NVME_SC_NS_IS_PRIVATE = 0x119,
1884 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1885 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1886 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1887 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
1888 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1889 NVME_SC_CTRL_ID_INVALID = 0x11f,
1890 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
1891 NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
1892 NVME_SC_RES_ID_INVALID = 0x122,
1893 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1894 NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
1895 NVME_SC_ANA_ATTACH_FAILED = 0x125,
1898 * I/O Command Set Specific - NVM commands:
1900 NVME_SC_BAD_ATTRIBUTES = 0x180,
1901 NVME_SC_INVALID_PI = 0x181,
1902 NVME_SC_READ_ONLY = 0x182,
1903 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1906 * I/O Command Set Specific - Fabrics commands:
1908 NVME_SC_CONNECT_FORMAT = 0x180,
1909 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1910 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1911 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1912 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1914 NVME_SC_DISCOVERY_RESTART = 0x190,
1915 NVME_SC_AUTH_REQUIRED = 0x191,
1918 * I/O Command Set Specific - Zoned commands:
1920 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1921 NVME_SC_ZONE_FULL = 0x1b9,
1922 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1923 NVME_SC_ZONE_OFFLINE = 0x1bb,
1924 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1925 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1926 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1927 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1930 * Media and Data Integrity Errors:
1932 NVME_SC_WRITE_FAULT = 0x280,
1933 NVME_SC_READ_ERROR = 0x281,
1934 NVME_SC_GUARD_CHECK = 0x282,
1935 NVME_SC_APPTAG_CHECK = 0x283,
1936 NVME_SC_REFTAG_CHECK = 0x284,
1937 NVME_SC_COMPARE_FAILED = 0x285,
1938 NVME_SC_ACCESS_DENIED = 0x286,
1939 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1942 * Path-related Errors:
1944 NVME_SC_INTERNAL_PATH_ERROR = 0x300,
1945 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1946 NVME_SC_ANA_INACCESSIBLE = 0x302,
1947 NVME_SC_ANA_TRANSITION = 0x303,
1948 NVME_SC_CTRL_PATH_ERROR = 0x360,
1949 NVME_SC_HOST_PATH_ERROR = 0x370,
1950 NVME_SC_HOST_ABORTED_CMD = 0x371,
1952 NVME_SC_CRD = 0x1800,
1953 NVME_SC_MORE = 0x2000,
1954 NVME_SC_DNR = 0x4000,
1957 struct nvme_completion {
1959 * Used by Admin and Fabrics commands to return data:
1966 __le16 sq_head; /* how much of this queue may be reclaimed */
1967 __le16 sq_id; /* submission queue that generated this entry */
1968 __u16 command_id; /* of the command which completed */
1969 __le16 status; /* did the command fail, and if so, why? */
1972 #define NVME_VS(major, minor, tertiary) \
1973 (((major) << 16) | ((minor) << 8) | (tertiary))
1975 #define NVME_MAJOR(ver) ((ver) >> 16)
1976 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1977 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1979 #endif /* _LINUX_NVME_H */