2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 #include <linux/types.h>
19 #include <linux/uuid.h>
21 /* NQN names in commands fields specified one size */
22 #define NVMF_NQN_FIELD_LEN 256
24 /* However the max length of a qualified name is another size */
25 #define NVMF_NQN_SIZE 223
27 #define NVMF_TRSVCID_SIZE 32
28 #define NVMF_TRADDR_SIZE 256
29 #define NVMF_TSAS_SIZE 256
31 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
33 #define NVME_RDMA_IP_PORT 4420
35 #define NVME_NSID_ALL 0xffffffff
37 enum nvme_subsys_type {
38 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
39 NVME_NQN_NVME = 2, /* NVME type target subsystem */
42 /* Address Family codes for Discovery Log Page entry ADRFAM field */
44 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
45 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
46 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
47 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
48 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
51 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
53 NVMF_TRTYPE_RDMA = 1, /* RDMA */
54 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
55 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
56 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
60 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
62 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
63 NVMF_TREQ_REQUIRED = 1, /* Required */
64 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
65 #define NVME_TREQ_SECURE_CHANNEL_MASK \
66 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
68 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
71 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
75 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
76 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
79 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
83 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
84 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
85 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
86 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
87 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
90 /* RDMA Connection Management Service Type codes for Discovery Log Page
91 * entry TSAS RDMA_CMS field
94 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
97 #define NVME_AQ_DEPTH 32
98 #define NVME_NR_AEN_COMMANDS 1
99 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
102 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
103 * NVM-Express 1.2 specification, section 4.1.2.
105 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
108 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
109 NVME_REG_VS = 0x0008, /* Version */
110 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
111 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
112 NVME_REG_CC = 0x0014, /* Controller Configuration */
113 NVME_REG_CSTS = 0x001c, /* Controller Status */
114 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
115 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
116 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
117 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
118 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
119 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
120 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
123 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
124 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
125 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
126 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
127 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
128 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
130 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
131 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
134 NVME_CMBSZ_SQS = 1 << 0,
135 NVME_CMBSZ_CQS = 1 << 1,
136 NVME_CMBSZ_LISTS = 1 << 2,
137 NVME_CMBSZ_RDS = 1 << 3,
138 NVME_CMBSZ_WDS = 1 << 4,
140 NVME_CMBSZ_SZ_SHIFT = 12,
141 NVME_CMBSZ_SZ_MASK = 0xfffff,
143 NVME_CMBSZ_SZU_SHIFT = 8,
144 NVME_CMBSZ_SZU_MASK = 0xf,
148 * Submission and Completion Queue Entry Sizes for the NVM command set.
149 * (In bytes and specified as a power of two (2^n)).
151 #define NVME_NVM_IOSQES 6
152 #define NVME_NVM_IOCQES 4
155 NVME_CC_ENABLE = 1 << 0,
156 NVME_CC_CSS_NVM = 0 << 4,
157 NVME_CC_EN_SHIFT = 0,
158 NVME_CC_CSS_SHIFT = 4,
159 NVME_CC_MPS_SHIFT = 7,
160 NVME_CC_AMS_SHIFT = 11,
161 NVME_CC_SHN_SHIFT = 14,
162 NVME_CC_IOSQES_SHIFT = 16,
163 NVME_CC_IOCQES_SHIFT = 20,
164 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
165 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
166 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
167 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
168 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
169 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
170 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
171 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
172 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
173 NVME_CSTS_RDY = 1 << 0,
174 NVME_CSTS_CFS = 1 << 1,
175 NVME_CSTS_NSSRO = 1 << 4,
176 NVME_CSTS_PP = 1 << 5,
177 NVME_CSTS_SHST_NORMAL = 0 << 2,
178 NVME_CSTS_SHST_OCCUR = 1 << 2,
179 NVME_CSTS_SHST_CMPLT = 2 << 2,
180 NVME_CSTS_SHST_MASK = 3 << 2,
183 struct nvme_id_power_state {
184 __le16 max_power; /* centiwatts */
187 __le32 entry_lat; /* microseconds */
188 __le32 exit_lat; /* microseconds */
197 __u8 active_work_scale;
202 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
203 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
206 enum nvme_ctrl_attr {
207 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
208 NVME_CTRL_ATTR_TBKAS = (1 << 6),
211 struct nvme_id_ctrl {
290 struct nvme_id_power_state psd[32];
295 NVME_CTRL_ONCS_COMPARE = 1 << 0,
296 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
297 NVME_CTRL_ONCS_DSM = 1 << 2,
298 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
299 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
300 NVME_CTRL_VWC_PRESENT = 1 << 0,
301 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
302 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
303 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
304 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
342 struct nvme_lbaf lbaf[16];
348 NVME_ID_CNS_NS = 0x00,
349 NVME_ID_CNS_CTRL = 0x01,
350 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
351 NVME_ID_CNS_NS_DESC_LIST = 0x03,
352 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
353 NVME_ID_CNS_NS_PRESENT = 0x11,
354 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
355 NVME_ID_CNS_CTRL_LIST = 0x13,
359 NVME_DIR_IDENTIFY = 0x00,
360 NVME_DIR_STREAMS = 0x01,
361 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
362 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
363 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
364 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
365 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
366 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
367 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
368 NVME_DIR_ENDIR = 0x01,
372 NVME_NS_FEAT_THIN = 1 << 0,
373 NVME_NS_FLBAS_LBA_MASK = 0xf,
374 NVME_NS_FLBAS_META_EXT = 0x10,
375 NVME_LBAF_RP_BEST = 0,
376 NVME_LBAF_RP_BETTER = 1,
377 NVME_LBAF_RP_GOOD = 2,
378 NVME_LBAF_RP_DEGRADED = 3,
379 NVME_NS_DPC_PI_LAST = 1 << 4,
380 NVME_NS_DPC_PI_FIRST = 1 << 3,
381 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
382 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
383 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
384 NVME_NS_DPS_PI_FIRST = 1 << 3,
385 NVME_NS_DPS_PI_MASK = 0x7,
386 NVME_NS_DPS_PI_TYPE1 = 1,
387 NVME_NS_DPS_PI_TYPE2 = 2,
388 NVME_NS_DPS_PI_TYPE3 = 3,
391 struct nvme_ns_id_desc {
397 #define NVME_NIDT_EUI64_LEN 8
398 #define NVME_NIDT_NGUID_LEN 16
399 #define NVME_NIDT_UUID_LEN 16
402 NVME_NIDT_EUI64 = 0x01,
403 NVME_NIDT_NGUID = 0x02,
404 NVME_NIDT_UUID = 0x03,
407 struct nvme_smart_log {
408 __u8 critical_warning;
414 __u8 data_units_read[16];
415 __u8 data_units_written[16];
417 __u8 host_writes[16];
418 __u8 ctrl_busy_time[16];
419 __u8 power_cycles[16];
420 __u8 power_on_hours[16];
421 __u8 unsafe_shutdowns[16];
422 __u8 media_errors[16];
423 __u8 num_err_log_entries[16];
424 __le32 warning_temp_time;
425 __le32 critical_comp_time;
426 __le16 temp_sensor[8];
430 struct nvme_fw_slot_info_log {
438 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
439 NVME_CMD_EFFECTS_LBCC = 1 << 1,
440 NVME_CMD_EFFECTS_NCC = 1 << 2,
441 NVME_CMD_EFFECTS_NIC = 1 << 3,
442 NVME_CMD_EFFECTS_CCC = 1 << 4,
443 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
446 struct nvme_effects_log {
452 enum nvme_ana_state {
453 NVME_ANA_OPTIMIZED = 0x01,
454 NVME_ANA_NONOPTIMIZED = 0x02,
455 NVME_ANA_INACCESSIBLE = 0x03,
456 NVME_ANA_PERSISTENT_LOSS = 0x04,
457 NVME_ANA_CHANGE = 0x0f,
460 struct nvme_ana_group_desc {
469 /* flag for the log specific field of the ANA log */
470 #define NVME_ANA_LOG_RGO (1 << 0)
472 struct nvme_ana_rsp_hdr {
479 NVME_SMART_CRIT_SPARE = 1 << 0,
480 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
481 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
482 NVME_SMART_CRIT_MEDIA = 1 << 3,
483 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
495 NVME_AER_NOTICE_NS_CHANGED = 0x00,
496 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
497 NVME_AER_NOTICE_ANA = 0x03,
498 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
502 NVME_AEN_BIT_NS_ATTR = 8,
503 NVME_AEN_BIT_FW_ACT = 9,
504 NVME_AEN_BIT_ANA_CHANGE = 11,
505 NVME_AEN_BIT_DISC_CHANGE = 31,
509 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
510 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
511 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
512 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
515 struct nvme_lba_range_type {
526 NVME_LBART_TYPE_FS = 0x01,
527 NVME_LBART_TYPE_RAID = 0x02,
528 NVME_LBART_TYPE_CACHE = 0x03,
529 NVME_LBART_TYPE_SWAP = 0x04,
531 NVME_LBART_ATTRIB_TEMP = 1 << 0,
532 NVME_LBART_ATTRIB_HIDE = 1 << 1,
535 struct nvme_reservation_status {
551 enum nvme_async_event_type {
552 NVME_AER_TYPE_ERROR = 0,
553 NVME_AER_TYPE_SMART = 1,
554 NVME_AER_TYPE_NOTICE = 2,
560 nvme_cmd_flush = 0x00,
561 nvme_cmd_write = 0x01,
562 nvme_cmd_read = 0x02,
563 nvme_cmd_write_uncor = 0x04,
564 nvme_cmd_compare = 0x05,
565 nvme_cmd_write_zeroes = 0x08,
567 nvme_cmd_resv_register = 0x0d,
568 nvme_cmd_resv_report = 0x0e,
569 nvme_cmd_resv_acquire = 0x11,
570 nvme_cmd_resv_release = 0x15,
574 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
576 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
577 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
578 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
579 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
583 NVME_SGL_FMT_ADDRESS = 0x00,
584 NVME_SGL_FMT_OFFSET = 0x01,
585 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
586 NVME_SGL_FMT_INVALIDATE = 0x0f,
590 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
592 * For struct nvme_sgl_desc:
593 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
594 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
595 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
597 * For struct nvme_keyed_sgl_desc:
598 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
600 * Transport-specific SGL types:
601 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
604 NVME_SGL_FMT_DATA_DESC = 0x00,
605 NVME_SGL_FMT_SEG_DESC = 0x02,
606 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
607 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
608 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
611 struct nvme_sgl_desc {
618 struct nvme_keyed_sgl_desc {
625 union nvme_data_ptr {
630 struct nvme_sgl_desc sgl;
631 struct nvme_keyed_sgl_desc ksgl;
635 * Lowest two bits of our flags field (FUSE field in the spec):
637 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
638 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
640 * Highest two bits in our flags field (PSDT field in the spec):
642 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
643 * If used, MPTR contains addr of single physical buffer (byte aligned).
644 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
645 * If used, MPTR contains an address of an SGL segment containing
646 * exactly 1 SGL descriptor (qword aligned).
649 NVME_CMD_FUSE_FIRST = (1 << 0),
650 NVME_CMD_FUSE_SECOND = (1 << 1),
652 NVME_CMD_SGL_METABUF = (1 << 6),
653 NVME_CMD_SGL_METASEG = (1 << 7),
654 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
657 struct nvme_common_command {
664 union nvme_data_ptr dptr;
673 struct nvme_rw_command {
680 union nvme_data_ptr dptr;
691 NVME_RW_LR = 1 << 15,
692 NVME_RW_FUA = 1 << 14,
693 NVME_RW_DSM_FREQ_UNSPEC = 0,
694 NVME_RW_DSM_FREQ_TYPICAL = 1,
695 NVME_RW_DSM_FREQ_RARE = 2,
696 NVME_RW_DSM_FREQ_READS = 3,
697 NVME_RW_DSM_FREQ_WRITES = 4,
698 NVME_RW_DSM_FREQ_RW = 5,
699 NVME_RW_DSM_FREQ_ONCE = 6,
700 NVME_RW_DSM_FREQ_PREFETCH = 7,
701 NVME_RW_DSM_FREQ_TEMP = 8,
702 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
703 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
704 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
705 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
706 NVME_RW_DSM_SEQ_REQ = 1 << 6,
707 NVME_RW_DSM_COMPRESSED = 1 << 7,
708 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
709 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
710 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
711 NVME_RW_PRINFO_PRACT = 1 << 13,
712 NVME_RW_DTYPE_STREAMS = 1 << 4,
715 struct nvme_dsm_cmd {
721 union nvme_data_ptr dptr;
728 NVME_DSMGMT_IDR = 1 << 0,
729 NVME_DSMGMT_IDW = 1 << 1,
730 NVME_DSMGMT_AD = 1 << 2,
733 #define NVME_DSM_MAX_RANGES 256
735 struct nvme_dsm_range {
741 struct nvme_write_zeroes_cmd {
748 union nvme_data_ptr dptr;
760 struct nvme_feat_auto_pst {
765 NVME_HOST_MEM_ENABLE = (1 << 0),
766 NVME_HOST_MEM_RETURN = (1 << 1),
769 struct nvme_feat_host_behavior {
775 NVME_ENABLE_ACRE = 1,
780 enum nvme_admin_opcode {
781 nvme_admin_delete_sq = 0x00,
782 nvme_admin_create_sq = 0x01,
783 nvme_admin_get_log_page = 0x02,
784 nvme_admin_delete_cq = 0x04,
785 nvme_admin_create_cq = 0x05,
786 nvme_admin_identify = 0x06,
787 nvme_admin_abort_cmd = 0x08,
788 nvme_admin_set_features = 0x09,
789 nvme_admin_get_features = 0x0a,
790 nvme_admin_async_event = 0x0c,
791 nvme_admin_ns_mgmt = 0x0d,
792 nvme_admin_activate_fw = 0x10,
793 nvme_admin_download_fw = 0x11,
794 nvme_admin_ns_attach = 0x15,
795 nvme_admin_keep_alive = 0x18,
796 nvme_admin_directive_send = 0x19,
797 nvme_admin_directive_recv = 0x1a,
798 nvme_admin_dbbuf = 0x7C,
799 nvme_admin_format_nvm = 0x80,
800 nvme_admin_security_send = 0x81,
801 nvme_admin_security_recv = 0x82,
802 nvme_admin_sanitize_nvm = 0x84,
806 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
807 NVME_CQ_IRQ_ENABLED = (1 << 1),
808 NVME_SQ_PRIO_URGENT = (0 << 1),
809 NVME_SQ_PRIO_HIGH = (1 << 1),
810 NVME_SQ_PRIO_MEDIUM = (2 << 1),
811 NVME_SQ_PRIO_LOW = (3 << 1),
812 NVME_FEAT_ARBITRATION = 0x01,
813 NVME_FEAT_POWER_MGMT = 0x02,
814 NVME_FEAT_LBA_RANGE = 0x03,
815 NVME_FEAT_TEMP_THRESH = 0x04,
816 NVME_FEAT_ERR_RECOVERY = 0x05,
817 NVME_FEAT_VOLATILE_WC = 0x06,
818 NVME_FEAT_NUM_QUEUES = 0x07,
819 NVME_FEAT_IRQ_COALESCE = 0x08,
820 NVME_FEAT_IRQ_CONFIG = 0x09,
821 NVME_FEAT_WRITE_ATOMIC = 0x0a,
822 NVME_FEAT_ASYNC_EVENT = 0x0b,
823 NVME_FEAT_AUTO_PST = 0x0c,
824 NVME_FEAT_HOST_MEM_BUF = 0x0d,
825 NVME_FEAT_TIMESTAMP = 0x0e,
826 NVME_FEAT_KATO = 0x0f,
827 NVME_FEAT_HCTM = 0x10,
828 NVME_FEAT_NOPSC = 0x11,
829 NVME_FEAT_RRL = 0x12,
830 NVME_FEAT_PLM_CONFIG = 0x13,
831 NVME_FEAT_PLM_WINDOW = 0x14,
832 NVME_FEAT_HOST_BEHAVIOR = 0x16,
833 NVME_FEAT_SW_PROGRESS = 0x80,
834 NVME_FEAT_HOST_ID = 0x81,
835 NVME_FEAT_RESV_MASK = 0x82,
836 NVME_FEAT_RESV_PERSIST = 0x83,
837 NVME_FEAT_WRITE_PROTECT = 0x84,
838 NVME_LOG_ERROR = 0x01,
839 NVME_LOG_SMART = 0x02,
840 NVME_LOG_FW_SLOT = 0x03,
841 NVME_LOG_CHANGED_NS = 0x04,
842 NVME_LOG_CMD_EFFECTS = 0x05,
844 NVME_LOG_DISC = 0x70,
845 NVME_LOG_RESERVATION = 0x80,
846 NVME_FWACT_REPL = (0 << 3),
847 NVME_FWACT_REPL_ACTV = (1 << 3),
848 NVME_FWACT_ACTV = (2 << 3),
851 /* NVMe Namespace Write Protect State */
853 NVME_NS_NO_WRITE_PROTECT = 0,
854 NVME_NS_WRITE_PROTECT,
855 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
856 NVME_NS_WRITE_PROTECT_PERMANENT,
859 #define NVME_MAX_CHANGED_NAMESPACES 1024
861 struct nvme_identify {
867 union nvme_data_ptr dptr;
874 #define NVME_IDENTIFY_DATA_SIZE 4096
876 struct nvme_features {
882 union nvme_data_ptr dptr;
891 struct nvme_host_mem_buf_desc {
897 struct nvme_create_cq {
911 struct nvme_create_sq {
925 struct nvme_delete_queue {
935 struct nvme_abort_cmd {
945 struct nvme_download_firmware {
950 union nvme_data_ptr dptr;
956 struct nvme_format_cmd {
966 struct nvme_get_log_page_command {
972 union nvme_data_ptr dptr;
974 __u8 lsp; /* upper 4 bits reserved */
983 struct nvme_directive_cmd {
989 union nvme_data_ptr dptr;
1002 * Fabrics subcommands.
1004 enum nvmf_fabrics_opcode {
1005 nvme_fabrics_command = 0x7f,
1008 enum nvmf_capsule_command {
1009 nvme_fabrics_type_property_set = 0x00,
1010 nvme_fabrics_type_connect = 0x01,
1011 nvme_fabrics_type_property_get = 0x04,
1014 struct nvmf_common_command {
1024 * The legal cntlid range a NVMe Target will provide.
1025 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1026 * Devices based on earlier specs did not have the subsystem concept;
1027 * therefore, those devices had their cntlid value set to 0 as a result.
1029 #define NVME_CNTLID_MIN 1
1030 #define NVME_CNTLID_MAX 0xffef
1031 #define NVME_CNTLID_DYNAMIC 0xffff
1033 #define MAX_DISC_LOGS 255
1035 /* Discovery log page entry */
1036 struct nvmf_disc_rsp_page_entry {
1045 char trsvcid[NVMF_TRSVCID_SIZE];
1047 char subnqn[NVMF_NQN_FIELD_LEN];
1048 char traddr[NVMF_TRADDR_SIZE];
1050 char common[NVMF_TSAS_SIZE];
1062 /* Discovery log page header */
1063 struct nvmf_disc_rsp_page_hdr {
1068 struct nvmf_disc_rsp_page_entry entries[0];
1072 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1075 struct nvmf_connect_command {
1081 union nvme_data_ptr dptr;
1091 struct nvmf_connect_data {
1095 char subsysnqn[NVMF_NQN_FIELD_LEN];
1096 char hostnqn[NVMF_NQN_FIELD_LEN];
1100 struct nvmf_property_set_command {
1113 struct nvmf_property_get_command {
1135 struct streams_directive_params {
1147 struct nvme_command {
1149 struct nvme_common_command common;
1150 struct nvme_rw_command rw;
1151 struct nvme_identify identify;
1152 struct nvme_features features;
1153 struct nvme_create_cq create_cq;
1154 struct nvme_create_sq create_sq;
1155 struct nvme_delete_queue delete_queue;
1156 struct nvme_download_firmware dlfw;
1157 struct nvme_format_cmd format;
1158 struct nvme_dsm_cmd dsm;
1159 struct nvme_write_zeroes_cmd write_zeroes;
1160 struct nvme_abort_cmd abort;
1161 struct nvme_get_log_page_command get_log_page;
1162 struct nvmf_common_command fabrics;
1163 struct nvmf_connect_command connect;
1164 struct nvmf_property_set_command prop_set;
1165 struct nvmf_property_get_command prop_get;
1166 struct nvme_dbbuf dbbuf;
1167 struct nvme_directive_cmd directive;
1171 struct nvme_error_slot {
1175 __le16 status_field;
1176 __le16 param_error_location;
1185 static inline bool nvme_is_write(struct nvme_command *cmd)
1190 * Why can't we simply have a Fabrics In and Fabrics out command?
1192 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
1193 return cmd->fabrics.fctype & 1;
1194 return cmd->common.opcode & 1;
1199 * Generic Command Status:
1201 NVME_SC_SUCCESS = 0x0,
1202 NVME_SC_INVALID_OPCODE = 0x1,
1203 NVME_SC_INVALID_FIELD = 0x2,
1204 NVME_SC_CMDID_CONFLICT = 0x3,
1205 NVME_SC_DATA_XFER_ERROR = 0x4,
1206 NVME_SC_POWER_LOSS = 0x5,
1207 NVME_SC_INTERNAL = 0x6,
1208 NVME_SC_ABORT_REQ = 0x7,
1209 NVME_SC_ABORT_QUEUE = 0x8,
1210 NVME_SC_FUSED_FAIL = 0x9,
1211 NVME_SC_FUSED_MISSING = 0xa,
1212 NVME_SC_INVALID_NS = 0xb,
1213 NVME_SC_CMD_SEQ_ERROR = 0xc,
1214 NVME_SC_SGL_INVALID_LAST = 0xd,
1215 NVME_SC_SGL_INVALID_COUNT = 0xe,
1216 NVME_SC_SGL_INVALID_DATA = 0xf,
1217 NVME_SC_SGL_INVALID_METADATA = 0x10,
1218 NVME_SC_SGL_INVALID_TYPE = 0x11,
1220 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1221 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1223 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1225 NVME_SC_LBA_RANGE = 0x80,
1226 NVME_SC_CAP_EXCEEDED = 0x81,
1227 NVME_SC_NS_NOT_READY = 0x82,
1228 NVME_SC_RESERVATION_CONFLICT = 0x83,
1231 * Command Specific Status:
1233 NVME_SC_CQ_INVALID = 0x100,
1234 NVME_SC_QID_INVALID = 0x101,
1235 NVME_SC_QUEUE_SIZE = 0x102,
1236 NVME_SC_ABORT_LIMIT = 0x103,
1237 NVME_SC_ABORT_MISSING = 0x104,
1238 NVME_SC_ASYNC_LIMIT = 0x105,
1239 NVME_SC_FIRMWARE_SLOT = 0x106,
1240 NVME_SC_FIRMWARE_IMAGE = 0x107,
1241 NVME_SC_INVALID_VECTOR = 0x108,
1242 NVME_SC_INVALID_LOG_PAGE = 0x109,
1243 NVME_SC_INVALID_FORMAT = 0x10a,
1244 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1245 NVME_SC_INVALID_QUEUE = 0x10c,
1246 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1247 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1248 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1249 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1250 NVME_SC_FW_NEEDS_RESET = 0x111,
1251 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1252 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
1253 NVME_SC_OVERLAPPING_RANGE = 0x114,
1254 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
1255 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1256 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1257 NVME_SC_NS_IS_PRIVATE = 0x119,
1258 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1259 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1260 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1263 * I/O Command Set Specific - NVM commands:
1265 NVME_SC_BAD_ATTRIBUTES = 0x180,
1266 NVME_SC_INVALID_PI = 0x181,
1267 NVME_SC_READ_ONLY = 0x182,
1268 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1271 * I/O Command Set Specific - Fabrics commands:
1273 NVME_SC_CONNECT_FORMAT = 0x180,
1274 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1275 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1276 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1277 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1279 NVME_SC_DISCOVERY_RESTART = 0x190,
1280 NVME_SC_AUTH_REQUIRED = 0x191,
1283 * Media and Data Integrity Errors:
1285 NVME_SC_WRITE_FAULT = 0x280,
1286 NVME_SC_READ_ERROR = 0x281,
1287 NVME_SC_GUARD_CHECK = 0x282,
1288 NVME_SC_APPTAG_CHECK = 0x283,
1289 NVME_SC_REFTAG_CHECK = 0x284,
1290 NVME_SC_COMPARE_FAILED = 0x285,
1291 NVME_SC_ACCESS_DENIED = 0x286,
1292 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1295 * Path-related Errors:
1297 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1298 NVME_SC_ANA_INACCESSIBLE = 0x302,
1299 NVME_SC_ANA_TRANSITION = 0x303,
1300 NVME_SC_HOST_PATH_ERROR = 0x370,
1302 NVME_SC_CRD = 0x1800,
1303 NVME_SC_DNR = 0x4000,
1306 struct nvme_completion {
1308 * Used by Admin and Fabrics commands to return data:
1315 __le16 sq_head; /* how much of this queue may be reclaimed */
1316 __le16 sq_id; /* submission queue that generated this entry */
1317 __u16 command_id; /* of the command which completed */
1318 __le16 status; /* did the command fail, and if so, why? */
1321 #define NVME_VS(major, minor, tertiary) \
1322 (((major) << 16) | ((minor) << 8) | (tertiary))
1324 #define NVME_MAJOR(ver) ((ver) >> 16)
1325 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1326 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1328 #endif /* _LINUX_NVME_H */