include/linux/nvme.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Definitions for the NVM Express interface
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #ifndef _LINUX_NVME_H
   8 #define _LINUX_NVME_H
   9
  10 #include <linux/bits.h>
  11 #include <linux/types.h>
  12 #include <linux/uuid.h>
  13
  14 /* NQN names in commands fields specified one size */
  15 #define NVMF_NQN_FIELD_LEN      256
  16
  17 /* However the max length of a qualified name is another size */
  18 #define NVMF_NQN_SIZE           223
  19
  20 #define NVMF_TRSVCID_SIZE       32
  21 #define NVMF_TRADDR_SIZE        256
  22 #define NVMF_TSAS_SIZE          256
  23 #define NVMF_AUTH_HASH_LEN      64
  24
  25 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
  26
  27 #define NVME_RDMA_IP_PORT       4420
  28
  29 #define NVME_NSID_ALL           0xffffffff
  30
  31 enum nvme_subsys_type {
  32         /* Referral to another discovery type target subsystem */
  33         NVME_NQN_DISC   = 1,
  34
  35         /* NVME type target subsystem */
  36         NVME_NQN_NVME   = 2,
  37
  38         /* Current discovery type target subsystem */
  39         NVME_NQN_CURR   = 3,
  40 };
  41
  42 enum nvme_ctrl_type {
  43         NVME_CTRL_IO    = 1,            /* I/O controller */
  44         NVME_CTRL_DISC  = 2,            /* Discovery controller */
  45         NVME_CTRL_ADMIN = 3,            /* Administrative controller */
  46 };
  47
  48 enum nvme_dctype {
  49         NVME_DCTYPE_NOT_REPORTED        = 0,
  50         NVME_DCTYPE_DDC                 = 1, /* Direct Discovery Controller */
  51         NVME_DCTYPE_CDC                 = 2, /* Central Discovery Controller */
  52 };
  53
  54 /* Address Family codes for Discovery Log Page entry ADRFAM field */
  55 enum {
  56         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
  57         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
  58         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
  59         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
  60         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
  61         NVMF_ADDR_FAMILY_LOOP   = 254,  /* Reserved for host usage */
  62         NVMF_ADDR_FAMILY_MAX,
  63 };
  64
  65 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  66 enum {
  67         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
  68         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
  69         NVMF_TRTYPE_TCP         = 3,    /* TCP/IP */
  70         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
  71         NVMF_TRTYPE_MAX,
  72 };
  73
  74 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  75 enum {
  76         NVMF_TREQ_NOT_SPECIFIED = 0,            /* Not specified */
  77         NVMF_TREQ_REQUIRED      = 1,            /* Required */
  78         NVMF_TREQ_NOT_REQUIRED  = 2,            /* Not Required */
  79 #define NVME_TREQ_SECURE_CHANNEL_MASK \
  80         (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
  81
  82         NVMF_TREQ_DISABLE_SQFLOW = (1 << 2),    /* Supports SQ flow control disable */
  83 };
  84
  85 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  86  * RDMA_QPTYPE field
  87  */
  88 enum {
  89         NVMF_RDMA_QPTYPE_CONNECTED      = 1, /* Reliable Connected */
  90         NVMF_RDMA_QPTYPE_DATAGRAM       = 2, /* Reliable Datagram */
  91 };
  92
  93 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  94  * RDMA_QPTYPE field
  95  */
  96 enum {
  97         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
  98         NVMF_RDMA_PRTYPE_IB             = 2, /* InfiniBand */
  99         NVMF_RDMA_PRTYPE_ROCE           = 3, /* InfiniBand RoCE */
 100         NVMF_RDMA_PRTYPE_ROCEV2         = 4, /* InfiniBand RoCEV2 */
 101         NVMF_RDMA_PRTYPE_IWARP          = 5, /* IWARP */
 102 };
 103
 104 /* RDMA Connection Management Service Type codes for Discovery Log Page
 105  * entry TSAS RDMA_CMS field
 106  */
 107 enum {
 108         NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
 109 };
 110
 111 #define NVME_AQ_DEPTH           32
 112 #define NVME_NR_AEN_COMMANDS    1
 113 #define NVME_AQ_BLK_MQ_DEPTH    (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
 114
 115 /*
 116  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
 117  * NVM-Express 1.2 specification, section 4.1.2.
 118  */
 119 #define NVME_AQ_MQ_TAG_DEPTH    (NVME_AQ_BLK_MQ_DEPTH - 1)
 120
 121 enum {
 122         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
 123         NVME_REG_VS     = 0x0008,       /* Version */
 124         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
 125         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
 126         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
 127         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
 128         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
 129         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
 130         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
 131         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
 132         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
 133         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
 134         NVME_REG_BPINFO = 0x0040,       /* Boot Partition Information */
 135         NVME_REG_BPRSEL = 0x0044,       /* Boot Partition Read Select */
 136         NVME_REG_BPMBL  = 0x0048,       /* Boot Partition Memory Buffer
 137                                          * Location
 138                                          */
 139         NVME_REG_CMBMSC = 0x0050,       /* Controller Memory Buffer Memory
 140                                          * Space Control
 141                                          */
 142         NVME_REG_CRTO   = 0x0068,       /* Controller Ready Timeouts */
 143         NVME_REG_PMRCAP = 0x0e00,       /* Persistent Memory Capabilities */
 144         NVME_REG_PMRCTL = 0x0e04,       /* Persistent Memory Region Control */
 145         NVME_REG_PMRSTS = 0x0e08,       /* Persistent Memory Region Status */
 146         NVME_REG_PMREBS = 0x0e0c,       /* Persistent Memory Region Elasticity
 147                                          * Buffer Size
 148                                          */
 149         NVME_REG_PMRSWTP = 0x0e10,      /* Persistent Memory Region Sustained
 150                                          * Write Throughput
 151                                          */
 152         NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
 153 };
 154
 155 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
 156 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
 157 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
 158 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
 159 #define NVME_CAP_CSS(cap)       (((cap) >> 37) & 0xff)
 160 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
 161 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
 162 #define NVME_CAP_CMBS(cap)      (((cap) >> 57) & 0x1)
 163
 164 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
 165 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
 166
 167 #define NVME_CRTO_CRIMT(crto)   ((crto) >> 16)
 168 #define NVME_CRTO_CRWMT(crto)   ((crto) & 0xffff)
 169
 170 enum {
 171         NVME_CMBSZ_SQS          = 1 << 0,
 172         NVME_CMBSZ_CQS          = 1 << 1,
 173         NVME_CMBSZ_LISTS        = 1 << 2,
 174         NVME_CMBSZ_RDS          = 1 << 3,
 175         NVME_CMBSZ_WDS          = 1 << 4,
 176
 177         NVME_CMBSZ_SZ_SHIFT     = 12,
 178         NVME_CMBSZ_SZ_MASK      = 0xfffff,
 179
 180         NVME_CMBSZ_SZU_SHIFT    = 8,
 181         NVME_CMBSZ_SZU_MASK     = 0xf,
 182 };
 183
 184 /*
 185  * Submission and Completion Queue Entry Sizes for the NVM command set.
 186  * (In bytes and specified as a power of two (2^n)).
 187  */
 188 #define NVME_ADM_SQES       6
 189 #define NVME_NVM_IOSQES         6
 190 #define NVME_NVM_IOCQES         4
 191
 192 enum {
 193         NVME_CC_ENABLE          = 1 << 0,
 194         NVME_CC_EN_SHIFT        = 0,
 195         NVME_CC_CSS_SHIFT       = 4,
 196         NVME_CC_MPS_SHIFT       = 7,
 197         NVME_CC_AMS_SHIFT       = 11,
 198         NVME_CC_SHN_SHIFT       = 14,
 199         NVME_CC_IOSQES_SHIFT    = 16,
 200         NVME_CC_IOCQES_SHIFT    = 20,
 201         NVME_CC_CSS_NVM         = 0 << NVME_CC_CSS_SHIFT,
 202         NVME_CC_CSS_CSI         = 6 << NVME_CC_CSS_SHIFT,
 203         NVME_CC_CSS_MASK        = 7 << NVME_CC_CSS_SHIFT,
 204         NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
 205         NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
 206         NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
 207         NVME_CC_SHN_NONE        = 0 << NVME_CC_SHN_SHIFT,
 208         NVME_CC_SHN_NORMAL      = 1 << NVME_CC_SHN_SHIFT,
 209         NVME_CC_SHN_ABRUPT      = 2 << NVME_CC_SHN_SHIFT,
 210         NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
 211         NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
 212         NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
 213         NVME_CC_CRIME           = 1 << 24,
 214 };
 215
 216 enum {
 217         NVME_CSTS_RDY           = 1 << 0,
 218         NVME_CSTS_CFS           = 1 << 1,
 219         NVME_CSTS_NSSRO         = 1 << 4,
 220         NVME_CSTS_PP            = 1 << 5,
 221         NVME_CSTS_SHST_NORMAL   = 0 << 2,
 222         NVME_CSTS_SHST_OCCUR    = 1 << 2,
 223         NVME_CSTS_SHST_CMPLT    = 2 << 2,
 224         NVME_CSTS_SHST_MASK     = 3 << 2,
 225 };
 226
 227 enum {
 228         NVME_CMBMSC_CRE         = 1 << 0,
 229         NVME_CMBMSC_CMSE        = 1 << 1,
 230 };
 231
 232 enum {
 233         NVME_CAP_CSS_NVM        = 1 << 0,
 234         NVME_CAP_CSS_CSI        = 1 << 6,
 235 };
 236
 237 enum {
 238         NVME_CAP_CRMS_CRWMS     = 1ULL << 59,
 239         NVME_CAP_CRMS_CRIMS     = 1ULL << 60,
 240 };
 241
 242 struct nvme_id_power_state {
 243         __le16                  max_power;      /* centiwatts */
 244         __u8                    rsvd2;
 245         __u8                    flags;
 246         __le32                  entry_lat;      /* microseconds */
 247         __le32                  exit_lat;       /* microseconds */
 248         __u8                    read_tput;
 249         __u8                    read_lat;
 250         __u8                    write_tput;
 251         __u8                    write_lat;
 252         __le16                  idle_power;
 253         __u8                    idle_scale;
 254         __u8                    rsvd19;
 255         __le16                  active_power;
 256         __u8                    active_work_scale;
 257         __u8                    rsvd23[9];
 258 };
 259
 260 enum {
 261         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
 262         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
 263 };
 264
 265 enum nvme_ctrl_attr {
 266         NVME_CTRL_ATTR_HID_128_BIT      = (1 << 0),
 267         NVME_CTRL_ATTR_TBKAS            = (1 << 6),
 268         NVME_CTRL_ATTR_ELBAS            = (1 << 15),
 269 };
 270
 271 struct nvme_id_ctrl {
 272         __le16                  vid;
 273         __le16                  ssvid;
 274         char                    sn[20];
 275         char                    mn[40];
 276         char                    fr[8];
 277         __u8                    rab;
 278         __u8                    ieee[3];
 279         __u8                    cmic;
 280         __u8                    mdts;
 281         __le16                  cntlid;
 282         __le32                  ver;
 283         __le32                  rtd3r;
 284         __le32                  rtd3e;
 285         __le32                  oaes;
 286         __le32                  ctratt;
 287         __u8                    rsvd100[11];
 288         __u8                    cntrltype;
 289         __u8                    fguid[16];
 290         __le16                  crdt1;
 291         __le16                  crdt2;
 292         __le16                  crdt3;
 293         __u8                    rsvd134[122];
 294         __le16                  oacs;
 295         __u8                    acl;
 296         __u8                    aerl;
 297         __u8                    frmw;
 298         __u8                    lpa;
 299         __u8                    elpe;
 300         __u8                    npss;
 301         __u8                    avscc;
 302         __u8                    apsta;
 303         __le16                  wctemp;
 304         __le16                  cctemp;
 305         __le16                  mtfa;
 306         __le32                  hmpre;
 307         __le32                  hmmin;
 308         __u8                    tnvmcap[16];
 309         __u8                    unvmcap[16];
 310         __le32                  rpmbs;
 311         __le16                  edstt;
 312         __u8                    dsto;
 313         __u8                    fwug;
 314         __le16                  kas;
 315         __le16                  hctma;
 316         __le16                  mntmt;
 317         __le16                  mxtmt;
 318         __le32                  sanicap;
 319         __le32                  hmminds;
 320         __le16                  hmmaxd;
 321         __u8                    rsvd338[4];
 322         __u8                    anatt;
 323         __u8                    anacap;
 324         __le32                  anagrpmax;
 325         __le32                  nanagrpid;
 326         __u8                    rsvd352[160];
 327         __u8                    sqes;
 328         __u8                    cqes;
 329         __le16                  maxcmd;
 330         __le32                  nn;
 331         __le16                  oncs;
 332         __le16                  fuses;
 333         __u8                    fna;
 334         __u8                    vwc;
 335         __le16                  awun;
 336         __le16                  awupf;
 337         __u8                    nvscc;
 338         __u8                    nwpc;
 339         __le16                  acwu;
 340         __u8                    rsvd534[2];
 341         __le32                  sgls;
 342         __le32                  mnan;
 343         __u8                    rsvd544[224];
 344         char                    subnqn[256];
 345         __u8                    rsvd1024[768];
 346         __le32                  ioccsz;
 347         __le32                  iorcsz;
 348         __le16                  icdoff;
 349         __u8                    ctrattr;
 350         __u8                    msdbd;
 351         __u8                    rsvd1804[2];
 352         __u8                    dctype;
 353         __u8                    rsvd1807[241];
 354         struct nvme_id_power_state      psd[32];
 355         __u8                    vs[1024];
 356 };
 357
 358 enum {
 359         NVME_CTRL_CMIC_MULTI_PORT               = 1 << 0,
 360         NVME_CTRL_CMIC_MULTI_CTRL               = 1 << 1,
 361         NVME_CTRL_CMIC_ANA                      = 1 << 3,
 362         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
 363         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
 364         NVME_CTRL_ONCS_DSM                      = 1 << 2,
 365         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
 366         NVME_CTRL_ONCS_RESERVATIONS             = 1 << 5,
 367         NVME_CTRL_ONCS_TIMESTAMP                = 1 << 6,
 368         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
 369         NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
 370         NVME_CTRL_OACS_NS_MNGT_SUPP             = 1 << 3,
 371         NVME_CTRL_OACS_DIRECTIVES               = 1 << 5,
 372         NVME_CTRL_OACS_DBBUF_SUPP               = 1 << 8,
 373         NVME_CTRL_LPA_CMD_EFFECTS_LOG           = 1 << 1,
 374         NVME_CTRL_CTRATT_128_ID                 = 1 << 0,
 375         NVME_CTRL_CTRATT_NON_OP_PSP             = 1 << 1,
 376         NVME_CTRL_CTRATT_NVM_SETS               = 1 << 2,
 377         NVME_CTRL_CTRATT_READ_RECV_LVLS         = 1 << 3,
 378         NVME_CTRL_CTRATT_ENDURANCE_GROUPS       = 1 << 4,
 379         NVME_CTRL_CTRATT_PREDICTABLE_LAT        = 1 << 5,
 380         NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY  = 1 << 7,
 381         NVME_CTRL_CTRATT_UUID_LIST              = 1 << 9,
 382 };
 383
 384 struct nvme_lbaf {
 385         __le16                  ms;
 386         __u8                    ds;
 387         __u8                    rp;
 388 };
 389
 390 struct nvme_id_ns {
 391         __le64                  nsze;
 392         __le64                  ncap;
 393         __le64                  nuse;
 394         __u8                    nsfeat;
 395         __u8                    nlbaf;
 396         __u8                    flbas;
 397         __u8                    mc;
 398         __u8                    dpc;
 399         __u8                    dps;
 400         __u8                    nmic;
 401         __u8                    rescap;
 402         __u8                    fpi;
 403         __u8                    dlfeat;
 404         __le16                  nawun;
 405         __le16                  nawupf;
 406         __le16                  nacwu;
 407         __le16                  nabsn;
 408         __le16                  nabo;
 409         __le16                  nabspf;
 410         __le16                  noiob;
 411         __u8                    nvmcap[16];
 412         __le16                  npwg;
 413         __le16                  npwa;
 414         __le16                  npdg;
 415         __le16                  npda;
 416         __le16                  nows;
 417         __u8                    rsvd74[18];
 418         __le32                  anagrpid;
 419         __u8                    rsvd96[3];
 420         __u8                    nsattr;
 421         __le16                  nvmsetid;
 422         __le16                  endgid;
 423         __u8                    nguid[16];
 424         __u8                    eui64[8];
 425         struct nvme_lbaf        lbaf[64];
 426         __u8                    vs[3712];
 427 };
 428
 429 /* I/O Command Set Independent Identify Namespace Data Structure */
 430 struct nvme_id_ns_cs_indep {
 431         __u8                    nsfeat;
 432         __u8                    nmic;
 433         __u8                    rescap;
 434         __u8                    fpi;
 435         __le32                  anagrpid;
 436         __u8                    nsattr;
 437         __u8                    rsvd9;
 438         __le16                  nvmsetid;
 439         __le16                  endgid;
 440         __u8                    nstat;
 441         __u8                    rsvd15[4081];
 442 };
 443
 444 struct nvme_zns_lbafe {
 445         __le64                  zsze;
 446         __u8                    zdes;
 447         __u8                    rsvd9[7];
 448 };
 449
 450 struct nvme_id_ns_zns {
 451         __le16                  zoc;
 452         __le16                  ozcs;
 453         __le32                  mar;
 454         __le32                  mor;
 455         __le32                  rrl;
 456         __le32                  frl;
 457         __u8                    rsvd20[2796];
 458         struct nvme_zns_lbafe   lbafe[64];
 459         __u8                    vs[256];
 460 };
 461
 462 struct nvme_id_ctrl_zns {
 463         __u8    zasl;
 464         __u8    rsvd1[4095];
 465 };
 466
 467 struct nvme_id_ns_nvm {
 468         __le64  lbstm;
 469         __u8    pic;
 470         __u8    rsvd9[3];
 471         __le32  elbaf[64];
 472         __u8    rsvd268[3828];
 473 };
 474
 475 enum {
 476         NVME_ID_NS_NVM_STS_MASK         = 0x3f,
 477         NVME_ID_NS_NVM_GUARD_SHIFT      = 7,
 478         NVME_ID_NS_NVM_GUARD_MASK       = 0x3,
 479 };
 480
 481 static inline __u8 nvme_elbaf_sts(__u32 elbaf)
 482 {
 483         return elbaf & NVME_ID_NS_NVM_STS_MASK;
 484 }
 485
 486 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
 487 {
 488         return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
 489 }
 490
 491 struct nvme_id_ctrl_nvm {
 492         __u8    vsl;
 493         __u8    wzsl;
 494         __u8    wusl;
 495         __u8    dmrl;
 496         __le32  dmrsl;
 497         __le64  dmsl;
 498         __u8    rsvd16[4080];
 499 };
 500
 501 enum {
 502         NVME_ID_CNS_NS                  = 0x00,
 503         NVME_ID_CNS_CTRL                = 0x01,
 504         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
 505         NVME_ID_CNS_NS_DESC_LIST        = 0x03,
 506         NVME_ID_CNS_CS_NS               = 0x05,
 507         NVME_ID_CNS_CS_CTRL             = 0x06,
 508         NVME_ID_CNS_NS_CS_INDEP         = 0x08,
 509         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
 510         NVME_ID_CNS_NS_PRESENT          = 0x11,
 511         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
 512         NVME_ID_CNS_CTRL_LIST           = 0x13,
 513         NVME_ID_CNS_SCNDRY_CTRL_LIST    = 0x15,
 514         NVME_ID_CNS_NS_GRANULARITY      = 0x16,
 515         NVME_ID_CNS_UUID_LIST           = 0x17,
 516 };
 517
 518 enum {
 519         NVME_CSI_NVM                    = 0,
 520         NVME_CSI_ZNS                    = 2,
 521 };
 522
 523 enum {
 524         NVME_DIR_IDENTIFY               = 0x00,
 525         NVME_DIR_STREAMS                = 0x01,
 526         NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
 527         NVME_DIR_SND_ST_OP_REL_ID       = 0x01,
 528         NVME_DIR_SND_ST_OP_REL_RSC      = 0x02,
 529         NVME_DIR_RCV_ID_OP_PARAM        = 0x01,
 530         NVME_DIR_RCV_ST_OP_PARAM        = 0x01,
 531         NVME_DIR_RCV_ST_OP_STATUS       = 0x02,
 532         NVME_DIR_RCV_ST_OP_RESOURCE     = 0x03,
 533         NVME_DIR_ENDIR                  = 0x01,
 534 };
 535
 536 enum {
 537         NVME_NS_FEAT_THIN       = 1 << 0,
 538         NVME_NS_FEAT_ATOMICS    = 1 << 1,
 539         NVME_NS_FEAT_IO_OPT     = 1 << 4,
 540         NVME_NS_ATTR_RO         = 1 << 0,
 541         NVME_NS_FLBAS_LBA_MASK  = 0xf,
 542         NVME_NS_FLBAS_LBA_UMASK = 0x60,
 543         NVME_NS_FLBAS_LBA_SHIFT = 1,
 544         NVME_NS_FLBAS_META_EXT  = 0x10,
 545         NVME_NS_NMIC_SHARED     = 1 << 0,
 546         NVME_LBAF_RP_BEST       = 0,
 547         NVME_LBAF_RP_BETTER     = 1,
 548         NVME_LBAF_RP_GOOD       = 2,
 549         NVME_LBAF_RP_DEGRADED   = 3,
 550         NVME_NS_DPC_PI_LAST     = 1 << 4,
 551         NVME_NS_DPC_PI_FIRST    = 1 << 3,
 552         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
 553         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
 554         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
 555         NVME_NS_DPS_PI_FIRST    = 1 << 3,
 556         NVME_NS_DPS_PI_MASK     = 0x7,
 557         NVME_NS_DPS_PI_TYPE1    = 1,
 558         NVME_NS_DPS_PI_TYPE2    = 2,
 559         NVME_NS_DPS_PI_TYPE3    = 3,
 560 };
 561
 562 enum {
 563         NVME_NSTAT_NRDY         = 1 << 0,
 564 };
 565
 566 enum {
 567         NVME_NVM_NS_16B_GUARD   = 0,
 568         NVME_NVM_NS_32B_GUARD   = 1,
 569         NVME_NVM_NS_64B_GUARD   = 2,
 570 };
 571
 572 static inline __u8 nvme_lbaf_index(__u8 flbas)
 573 {
 574         return (flbas & NVME_NS_FLBAS_LBA_MASK) |
 575                 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
 576 }
 577
 578 /* Identify Namespace Metadata Capabilities (MC): */
 579 enum {
 580         NVME_MC_EXTENDED_LBA    = (1 << 0),
 581         NVME_MC_METADATA_PTR    = (1 << 1),
 582 };
 583
 584 struct nvme_ns_id_desc {
 585         __u8 nidt;
 586         __u8 nidl;
 587         __le16 reserved;
 588 };
 589
 590 #define NVME_NIDT_EUI64_LEN     8
 591 #define NVME_NIDT_NGUID_LEN     16
 592 #define NVME_NIDT_UUID_LEN      16
 593 #define NVME_NIDT_CSI_LEN       1
 594
 595 enum {
 596         NVME_NIDT_EUI64         = 0x01,
 597         NVME_NIDT_NGUID         = 0x02,
 598         NVME_NIDT_UUID          = 0x03,
 599         NVME_NIDT_CSI           = 0x04,
 600 };
 601
 602 struct nvme_smart_log {
 603         __u8                    critical_warning;
 604         __u8                    temperature[2];
 605         __u8                    avail_spare;
 606         __u8                    spare_thresh;
 607         __u8                    percent_used;
 608         __u8                    endu_grp_crit_warn_sumry;
 609         __u8                    rsvd7[25];
 610         __u8                    data_units_read[16];
 611         __u8                    data_units_written[16];
 612         __u8                    host_reads[16];
 613         __u8                    host_writes[16];
 614         __u8                    ctrl_busy_time[16];
 615         __u8                    power_cycles[16];
 616         __u8                    power_on_hours[16];
 617         __u8                    unsafe_shutdowns[16];
 618         __u8                    media_errors[16];
 619         __u8                    num_err_log_entries[16];
 620         __le32                  warning_temp_time;
 621         __le32                  critical_comp_time;
 622         __le16                  temp_sensor[8];
 623         __le32                  thm_temp1_trans_count;
 624         __le32                  thm_temp2_trans_count;
 625         __le32                  thm_temp1_total_time;
 626         __le32                  thm_temp2_total_time;
 627         __u8                    rsvd232[280];
 628 };
 629
 630 struct nvme_fw_slot_info_log {
 631         __u8                    afi;
 632         __u8                    rsvd1[7];
 633         __le64                  frs[7];
 634         __u8                    rsvd64[448];
 635 };
 636
 637 enum {
 638         NVME_CMD_EFFECTS_CSUPP          = 1 << 0,
 639         NVME_CMD_EFFECTS_LBCC           = 1 << 1,
 640         NVME_CMD_EFFECTS_NCC            = 1 << 2,
 641         NVME_CMD_EFFECTS_NIC            = 1 << 3,
 642         NVME_CMD_EFFECTS_CCC            = 1 << 4,
 643         NVME_CMD_EFFECTS_CSE_MASK       = GENMASK(18, 16),
 644         NVME_CMD_EFFECTS_UUID_SEL       = 1 << 19,
 645         NVME_CMD_EFFECTS_SCOPE_MASK     = GENMASK(31, 20),
 646 };
 647
 648 struct nvme_effects_log {
 649         __le32 acs[256];
 650         __le32 iocs[256];
 651         __u8   resv[2048];
 652 };
 653
 654 enum nvme_ana_state {
 655         NVME_ANA_OPTIMIZED              = 0x01,
 656         NVME_ANA_NONOPTIMIZED           = 0x02,
 657         NVME_ANA_INACCESSIBLE           = 0x03,
 658         NVME_ANA_PERSISTENT_LOSS        = 0x04,
 659         NVME_ANA_CHANGE                 = 0x0f,
 660 };
 661
 662 struct nvme_ana_group_desc {
 663         __le32  grpid;
 664         __le32  nnsids;
 665         __le64  chgcnt;
 666         __u8    state;
 667         __u8    rsvd17[15];
 668         __le32  nsids[];
 669 };
 670
 671 /* flag for the log specific field of the ANA log */
 672 #define NVME_ANA_LOG_RGO        (1 << 0)
 673
 674 struct nvme_ana_rsp_hdr {
 675         __le64  chgcnt;
 676         __le16  ngrps;
 677         __le16  rsvd10[3];
 678 };
 679
 680 struct nvme_zone_descriptor {
 681         __u8            zt;
 682         __u8            zs;
 683         __u8            za;
 684         __u8            rsvd3[5];
 685         __le64          zcap;
 686         __le64          zslba;
 687         __le64          wp;
 688         __u8            rsvd32[32];
 689 };
 690
 691 enum {
 692         NVME_ZONE_TYPE_SEQWRITE_REQ     = 0x2,
 693 };
 694
 695 struct nvme_zone_report {
 696         __le64          nr_zones;
 697         __u8            resv8[56];
 698         struct nvme_zone_descriptor entries[];
 699 };
 700
 701 enum {
 702         NVME_SMART_CRIT_SPARE           = 1 << 0,
 703         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
 704         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
 705         NVME_SMART_CRIT_MEDIA           = 1 << 3,
 706         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
 707 };
 708
 709 enum {
 710         NVME_AER_ERROR                  = 0,
 711         NVME_AER_SMART                  = 1,
 712         NVME_AER_NOTICE                 = 2,
 713         NVME_AER_CSS                    = 6,
 714         NVME_AER_VS                     = 7,
 715 };
 716
 717 enum {
 718         NVME_AER_ERROR_PERSIST_INT_ERR  = 0x03,
 719 };
 720
 721 enum {
 722         NVME_AER_NOTICE_NS_CHANGED      = 0x00,
 723         NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
 724         NVME_AER_NOTICE_ANA             = 0x03,
 725         NVME_AER_NOTICE_DISC_CHANGED    = 0xf0,
 726 };
 727
 728 enum {
 729         NVME_AEN_BIT_NS_ATTR            = 8,
 730         NVME_AEN_BIT_FW_ACT             = 9,
 731         NVME_AEN_BIT_ANA_CHANGE         = 11,
 732         NVME_AEN_BIT_DISC_CHANGE        = 31,
 733 };
 734
 735 enum {
 736         NVME_AEN_CFG_NS_ATTR            = 1 << NVME_AEN_BIT_NS_ATTR,
 737         NVME_AEN_CFG_FW_ACT             = 1 << NVME_AEN_BIT_FW_ACT,
 738         NVME_AEN_CFG_ANA_CHANGE         = 1 << NVME_AEN_BIT_ANA_CHANGE,
 739         NVME_AEN_CFG_DISC_CHANGE        = 1 << NVME_AEN_BIT_DISC_CHANGE,
 740 };
 741
 742 struct nvme_lba_range_type {
 743         __u8                    type;
 744         __u8                    attributes;
 745         __u8                    rsvd2[14];
 746         __le64                  slba;
 747         __le64                  nlb;
 748         __u8                    guid[16];
 749         __u8                    rsvd48[16];
 750 };
 751
 752 enum {
 753         NVME_LBART_TYPE_FS      = 0x01,
 754         NVME_LBART_TYPE_RAID    = 0x02,
 755         NVME_LBART_TYPE_CACHE   = 0x03,
 756         NVME_LBART_TYPE_SWAP    = 0x04,
 757
 758         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 759         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 760 };
 761
 762 struct nvme_reservation_status {
 763         __le32  gen;
 764         __u8    rtype;
 765         __u8    regctl[2];
 766         __u8    resv5[2];
 767         __u8    ptpls;
 768         __u8    resv10[13];
 769         struct {
 770                 __le16  cntlid;
 771                 __u8    rcsts;
 772                 __u8    resv3[5];
 773                 __le64  hostid;
 774                 __le64  rkey;
 775         } regctl_ds[];
 776 };
 777
 778 enum nvme_async_event_type {
 779         NVME_AER_TYPE_ERROR     = 0,
 780         NVME_AER_TYPE_SMART     = 1,
 781         NVME_AER_TYPE_NOTICE    = 2,
 782 };
 783
 784 /* I/O commands */
 785
 786 enum nvme_opcode {
 787         nvme_cmd_flush          = 0x00,
 788         nvme_cmd_write          = 0x01,
 789         nvme_cmd_read           = 0x02,
 790         nvme_cmd_write_uncor    = 0x04,
 791         nvme_cmd_compare        = 0x05,
 792         nvme_cmd_write_zeroes   = 0x08,
 793         nvme_cmd_dsm            = 0x09,
 794         nvme_cmd_verify         = 0x0c,
 795         nvme_cmd_resv_register  = 0x0d,
 796         nvme_cmd_resv_report    = 0x0e,
 797         nvme_cmd_resv_acquire   = 0x11,
 798         nvme_cmd_resv_release   = 0x15,
 799         nvme_cmd_zone_mgmt_send = 0x79,
 800         nvme_cmd_zone_mgmt_recv = 0x7a,
 801         nvme_cmd_zone_append    = 0x7d,
 802         nvme_cmd_vendor_start   = 0x80,
 803 };
 804
 805 #define nvme_opcode_name(opcode)        { opcode, #opcode }
 806 #define show_nvm_opcode_name(val)                               \
 807         __print_symbolic(val,                                   \
 808                 nvme_opcode_name(nvme_cmd_flush),               \
 809                 nvme_opcode_name(nvme_cmd_write),               \
 810                 nvme_opcode_name(nvme_cmd_read),                \
 811                 nvme_opcode_name(nvme_cmd_write_uncor),         \
 812                 nvme_opcode_name(nvme_cmd_compare),             \
 813                 nvme_opcode_name(nvme_cmd_write_zeroes),        \
 814                 nvme_opcode_name(nvme_cmd_dsm),                 \
 815                 nvme_opcode_name(nvme_cmd_verify),              \
 816                 nvme_opcode_name(nvme_cmd_resv_register),       \
 817                 nvme_opcode_name(nvme_cmd_resv_report),         \
 818                 nvme_opcode_name(nvme_cmd_resv_acquire),        \
 819                 nvme_opcode_name(nvme_cmd_resv_release),        \
 820                 nvme_opcode_name(nvme_cmd_zone_mgmt_send),      \
 821                 nvme_opcode_name(nvme_cmd_zone_mgmt_recv),      \
 822                 nvme_opcode_name(nvme_cmd_zone_append))
 823
 824
 825
 826 /*
 827  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
 828  *
 829  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
 830  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
 831  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
 832  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
 833  *                            request subtype
 834  */
 835 enum {
 836         NVME_SGL_FMT_ADDRESS            = 0x00,
 837         NVME_SGL_FMT_OFFSET             = 0x01,
 838         NVME_SGL_FMT_TRANSPORT_A        = 0x0A,
 839         NVME_SGL_FMT_INVALIDATE         = 0x0f,
 840 };
 841
 842 /*
 843  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
 844  *
 845  * For struct nvme_sgl_desc:
 846  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
 847  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
 848  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
 849  *
 850  * For struct nvme_keyed_sgl_desc:
 851  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
 852  *
 853  * Transport-specific SGL types:
 854  *   @NVME_TRANSPORT_SGL_DATA_DESC:     Transport SGL data dlock descriptor
 855  */
 856 enum {
 857         NVME_SGL_FMT_DATA_DESC          = 0x00,
 858         NVME_SGL_FMT_SEG_DESC           = 0x02,
 859         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
 860         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
 861         NVME_TRANSPORT_SGL_DATA_DESC    = 0x05,
 862 };
 863
 864 struct nvme_sgl_desc {
 865         __le64  addr;
 866         __le32  length;
 867         __u8    rsvd[3];
 868         __u8    type;
 869 };
 870
 871 struct nvme_keyed_sgl_desc {
 872         __le64  addr;
 873         __u8    length[3];
 874         __u8    key[4];
 875         __u8    type;
 876 };
 877
 878 union nvme_data_ptr {
 879         struct {
 880                 __le64  prp1;
 881                 __le64  prp2;
 882         };
 883         struct nvme_sgl_desc    sgl;
 884         struct nvme_keyed_sgl_desc ksgl;
 885 };
 886
 887 /*
 888  * Lowest two bits of our flags field (FUSE field in the spec):
 889  *
 890  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
 891  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
 892  *
 893  * Highest two bits in our flags field (PSDT field in the spec):
 894  *
 895  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
 896  *      If used, MPTR contains addr of single physical buffer (byte aligned).
 897  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
 898  *      If used, MPTR contains an address of an SGL segment containing
 899  *      exactly 1 SGL descriptor (qword aligned).
 900  */
 901 enum {
 902         NVME_CMD_FUSE_FIRST     = (1 << 0),
 903         NVME_CMD_FUSE_SECOND    = (1 << 1),
 904
 905         NVME_CMD_SGL_METABUF    = (1 << 6),
 906         NVME_CMD_SGL_METASEG    = (1 << 7),
 907         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
 908 };
 909
 910 struct nvme_common_command {
 911         __u8                    opcode;
 912         __u8                    flags;
 913         __u16                   command_id;
 914         __le32                  nsid;
 915         __le32                  cdw2[2];
 916         __le64                  metadata;
 917         union nvme_data_ptr     dptr;
 918         struct_group(cdws,
 919         __le32                  cdw10;
 920         __le32                  cdw11;
 921         __le32                  cdw12;
 922         __le32                  cdw13;
 923         __le32                  cdw14;
 924         __le32                  cdw15;
 925         );
 926 };
 927
 928 struct nvme_rw_command {
 929         __u8                    opcode;
 930         __u8                    flags;
 931         __u16                   command_id;
 932         __le32                  nsid;
 933         __le32                  cdw2;
 934         __le32                  cdw3;
 935         __le64                  metadata;
 936         union nvme_data_ptr     dptr;
 937         __le64                  slba;
 938         __le16                  length;
 939         __le16                  control;
 940         __le32                  dsmgmt;
 941         __le32                  reftag;
 942         __le16                  apptag;
 943         __le16                  appmask;
 944 };
 945
 946 enum {
 947         NVME_RW_LR                      = 1 << 15,
 948         NVME_RW_FUA                     = 1 << 14,
 949         NVME_RW_APPEND_PIREMAP          = 1 << 9,
 950         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 951         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 952         NVME_RW_DSM_FREQ_RARE           = 2,
 953         NVME_RW_DSM_FREQ_READS          = 3,
 954         NVME_RW_DSM_FREQ_WRITES         = 4,
 955         NVME_RW_DSM_FREQ_RW             = 5,
 956         NVME_RW_DSM_FREQ_ONCE           = 6,
 957         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 958         NVME_RW_DSM_FREQ_TEMP           = 8,
 959         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 960         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 961         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 962         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 963         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 964         NVME_RW_DSM_COMPRESSED          = 1 << 7,
 965         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
 966         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
 967         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
 968         NVME_RW_PRINFO_PRACT            = 1 << 13,
 969         NVME_RW_DTYPE_STREAMS           = 1 << 4,
 970         NVME_WZ_DEAC                    = 1 << 9,
 971 };
 972
 973 struct nvme_dsm_cmd {
 974         __u8                    opcode;
 975         __u8                    flags;
 976         __u16                   command_id;
 977         __le32                  nsid;
 978         __u64                   rsvd2[2];
 979         union nvme_data_ptr     dptr;
 980         __le32                  nr;
 981         __le32                  attributes;
 982         __u32                   rsvd12[4];
 983 };
 984
 985 enum {
 986         NVME_DSMGMT_IDR         = 1 << 0,
 987         NVME_DSMGMT_IDW         = 1 << 1,
 988         NVME_DSMGMT_AD          = 1 << 2,
 989 };
 990
 991 #define NVME_DSM_MAX_RANGES     256
 992
 993 struct nvme_dsm_range {
 994         __le32                  cattr;
 995         __le32                  nlb;
 996         __le64                  slba;
 997 };
 998
 999 struct nvme_write_zeroes_cmd {
1000         __u8                    opcode;
1001         __u8                    flags;
1002         __u16                   command_id;
1003         __le32                  nsid;
1004         __u64                   rsvd2;
1005         __le64                  metadata;
1006         union nvme_data_ptr     dptr;
1007         __le64                  slba;
1008         __le16                  length;
1009         __le16                  control;
1010         __le32                  dsmgmt;
1011         __le32                  reftag;
1012         __le16                  apptag;
1013         __le16                  appmask;
1014 };
1015
1016 enum nvme_zone_mgmt_action {
1017         NVME_ZONE_CLOSE         = 0x1,
1018         NVME_ZONE_FINISH        = 0x2,
1019         NVME_ZONE_OPEN          = 0x3,
1020         NVME_ZONE_RESET         = 0x4,
1021         NVME_ZONE_OFFLINE       = 0x5,
1022         NVME_ZONE_SET_DESC_EXT  = 0x10,
1023 };
1024
1025 struct nvme_zone_mgmt_send_cmd {
1026         __u8                    opcode;
1027         __u8                    flags;
1028         __u16                   command_id;
1029         __le32                  nsid;
1030         __le32                  cdw2[2];
1031         __le64                  metadata;
1032         union nvme_data_ptr     dptr;
1033         __le64                  slba;
1034         __le32                  cdw12;
1035         __u8                    zsa;
1036         __u8                    select_all;
1037         __u8                    rsvd13[2];
1038         __le32                  cdw14[2];
1039 };
1040
1041 struct nvme_zone_mgmt_recv_cmd {
1042         __u8                    opcode;
1043         __u8                    flags;
1044         __u16                   command_id;
1045         __le32                  nsid;
1046         __le64                  rsvd2[2];
1047         union nvme_data_ptr     dptr;
1048         __le64                  slba;
1049         __le32                  numd;
1050         __u8                    zra;
1051         __u8                    zrasf;
1052         __u8                    pr;
1053         __u8                    rsvd13;
1054         __le32                  cdw14[2];
1055 };
1056
1057 enum {
1058         NVME_ZRA_ZONE_REPORT            = 0,
1059         NVME_ZRASF_ZONE_REPORT_ALL      = 0,
1060         NVME_ZRASF_ZONE_STATE_EMPTY     = 0x01,
1061         NVME_ZRASF_ZONE_STATE_IMP_OPEN  = 0x02,
1062         NVME_ZRASF_ZONE_STATE_EXP_OPEN  = 0x03,
1063         NVME_ZRASF_ZONE_STATE_CLOSED    = 0x04,
1064         NVME_ZRASF_ZONE_STATE_READONLY  = 0x05,
1065         NVME_ZRASF_ZONE_STATE_FULL      = 0x06,
1066         NVME_ZRASF_ZONE_STATE_OFFLINE   = 0x07,
1067         NVME_REPORT_ZONE_PARTIAL        = 1,
1068 };
1069
1070 /* Features */
1071
1072 enum {
1073         NVME_TEMP_THRESH_MASK           = 0xffff,
1074         NVME_TEMP_THRESH_SELECT_SHIFT   = 16,
1075         NVME_TEMP_THRESH_TYPE_UNDER     = 0x100000,
1076 };
1077
1078 struct nvme_feat_auto_pst {
1079         __le64 entries[32];
1080 };
1081
1082 enum {
1083         NVME_HOST_MEM_ENABLE    = (1 << 0),
1084         NVME_HOST_MEM_RETURN    = (1 << 1),
1085 };
1086
1087 struct nvme_feat_host_behavior {
1088         __u8 acre;
1089         __u8 etdas;
1090         __u8 lbafee;
1091         __u8 resv1[509];
1092 };
1093
1094 enum {
1095         NVME_ENABLE_ACRE        = 1,
1096         NVME_ENABLE_LBAFEE      = 1,
1097 };
1098
1099 /* Admin commands */
1100
1101 enum nvme_admin_opcode {
1102         nvme_admin_delete_sq            = 0x00,
1103         nvme_admin_create_sq            = 0x01,
1104         nvme_admin_get_log_page         = 0x02,
1105         nvme_admin_delete_cq            = 0x04,
1106         nvme_admin_create_cq            = 0x05,
1107         nvme_admin_identify             = 0x06,
1108         nvme_admin_abort_cmd            = 0x08,
1109         nvme_admin_set_features         = 0x09,
1110         nvme_admin_get_features         = 0x0a,
1111         nvme_admin_async_event          = 0x0c,
1112         nvme_admin_ns_mgmt              = 0x0d,
1113         nvme_admin_activate_fw          = 0x10,
1114         nvme_admin_download_fw          = 0x11,
1115         nvme_admin_dev_self_test        = 0x14,
1116         nvme_admin_ns_attach            = 0x15,
1117         nvme_admin_keep_alive           = 0x18,
1118         nvme_admin_directive_send       = 0x19,
1119         nvme_admin_directive_recv       = 0x1a,
1120         nvme_admin_virtual_mgmt         = 0x1c,
1121         nvme_admin_nvme_mi_send         = 0x1d,
1122         nvme_admin_nvme_mi_recv         = 0x1e,
1123         nvme_admin_dbbuf                = 0x7C,
1124         nvme_admin_format_nvm           = 0x80,
1125         nvme_admin_security_send        = 0x81,
1126         nvme_admin_security_recv        = 0x82,
1127         nvme_admin_sanitize_nvm         = 0x84,
1128         nvme_admin_get_lba_status       = 0x86,
1129         nvme_admin_vendor_start         = 0xC0,
1130 };
1131
1132 #define nvme_admin_opcode_name(opcode)  { opcode, #opcode }
1133 #define show_admin_opcode_name(val)                                     \
1134         __print_symbolic(val,                                           \
1135                 nvme_admin_opcode_name(nvme_admin_delete_sq),           \
1136                 nvme_admin_opcode_name(nvme_admin_create_sq),           \
1137                 nvme_admin_opcode_name(nvme_admin_get_log_page),        \
1138                 nvme_admin_opcode_name(nvme_admin_delete_cq),           \
1139                 nvme_admin_opcode_name(nvme_admin_create_cq),           \
1140                 nvme_admin_opcode_name(nvme_admin_identify),            \
1141                 nvme_admin_opcode_name(nvme_admin_abort_cmd),           \
1142                 nvme_admin_opcode_name(nvme_admin_set_features),        \
1143                 nvme_admin_opcode_name(nvme_admin_get_features),        \
1144                 nvme_admin_opcode_name(nvme_admin_async_event),         \
1145                 nvme_admin_opcode_name(nvme_admin_ns_mgmt),             \
1146                 nvme_admin_opcode_name(nvme_admin_activate_fw),         \
1147                 nvme_admin_opcode_name(nvme_admin_download_fw),         \
1148                 nvme_admin_opcode_name(nvme_admin_dev_self_test),       \
1149                 nvme_admin_opcode_name(nvme_admin_ns_attach),           \
1150                 nvme_admin_opcode_name(nvme_admin_keep_alive),          \
1151                 nvme_admin_opcode_name(nvme_admin_directive_send),      \
1152                 nvme_admin_opcode_name(nvme_admin_directive_recv),      \
1153                 nvme_admin_opcode_name(nvme_admin_virtual_mgmt),        \
1154                 nvme_admin_opcode_name(nvme_admin_nvme_mi_send),        \
1155                 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv),        \
1156                 nvme_admin_opcode_name(nvme_admin_dbbuf),               \
1157                 nvme_admin_opcode_name(nvme_admin_format_nvm),          \
1158                 nvme_admin_opcode_name(nvme_admin_security_send),       \
1159                 nvme_admin_opcode_name(nvme_admin_security_recv),       \
1160                 nvme_admin_opcode_name(nvme_admin_sanitize_nvm),        \
1161                 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1162
1163 enum {
1164         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
1165         NVME_CQ_IRQ_ENABLED     = (1 << 1),
1166         NVME_SQ_PRIO_URGENT     = (0 << 1),
1167         NVME_SQ_PRIO_HIGH       = (1 << 1),
1168         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
1169         NVME_SQ_PRIO_LOW        = (3 << 1),
1170         NVME_FEAT_ARBITRATION   = 0x01,
1171         NVME_FEAT_POWER_MGMT    = 0x02,
1172         NVME_FEAT_LBA_RANGE     = 0x03,
1173         NVME_FEAT_TEMP_THRESH   = 0x04,
1174         NVME_FEAT_ERR_RECOVERY  = 0x05,
1175         NVME_FEAT_VOLATILE_WC   = 0x06,
1176         NVME_FEAT_NUM_QUEUES    = 0x07,
1177         NVME_FEAT_IRQ_COALESCE  = 0x08,
1178         NVME_FEAT_IRQ_CONFIG    = 0x09,
1179         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
1180         NVME_FEAT_ASYNC_EVENT   = 0x0b,
1181         NVME_FEAT_AUTO_PST      = 0x0c,
1182         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
1183         NVME_FEAT_TIMESTAMP     = 0x0e,
1184         NVME_FEAT_KATO          = 0x0f,
1185         NVME_FEAT_HCTM          = 0x10,
1186         NVME_FEAT_NOPSC         = 0x11,
1187         NVME_FEAT_RRL           = 0x12,
1188         NVME_FEAT_PLM_CONFIG    = 0x13,
1189         NVME_FEAT_PLM_WINDOW    = 0x14,
1190         NVME_FEAT_HOST_BEHAVIOR = 0x16,
1191         NVME_FEAT_SANITIZE      = 0x17,
1192         NVME_FEAT_SW_PROGRESS   = 0x80,
1193         NVME_FEAT_HOST_ID       = 0x81,
1194         NVME_FEAT_RESV_MASK     = 0x82,
1195         NVME_FEAT_RESV_PERSIST  = 0x83,
1196         NVME_FEAT_WRITE_PROTECT = 0x84,
1197         NVME_FEAT_VENDOR_START  = 0xC0,
1198         NVME_FEAT_VENDOR_END    = 0xFF,
1199         NVME_LOG_ERROR          = 0x01,
1200         NVME_LOG_SMART          = 0x02,
1201         NVME_LOG_FW_SLOT        = 0x03,
1202         NVME_LOG_CHANGED_NS     = 0x04,
1203         NVME_LOG_CMD_EFFECTS    = 0x05,
1204         NVME_LOG_DEVICE_SELF_TEST = 0x06,
1205         NVME_LOG_TELEMETRY_HOST = 0x07,
1206         NVME_LOG_TELEMETRY_CTRL = 0x08,
1207         NVME_LOG_ENDURANCE_GROUP = 0x09,
1208         NVME_LOG_ANA            = 0x0c,
1209         NVME_LOG_DISC           = 0x70,
1210         NVME_LOG_RESERVATION    = 0x80,
1211         NVME_FWACT_REPL         = (0 << 3),
1212         NVME_FWACT_REPL_ACTV    = (1 << 3),
1213         NVME_FWACT_ACTV         = (2 << 3),
1214 };
1215
1216 /* NVMe Namespace Write Protect State */
1217 enum {
1218         NVME_NS_NO_WRITE_PROTECT = 0,
1219         NVME_NS_WRITE_PROTECT,
1220         NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1221         NVME_NS_WRITE_PROTECT_PERMANENT,
1222 };
1223
1224 #define NVME_MAX_CHANGED_NAMESPACES     1024
1225
1226 struct nvme_identify {
1227         __u8                    opcode;
1228         __u8                    flags;
1229         __u16                   command_id;
1230         __le32                  nsid;
1231         __u64                   rsvd2[2];
1232         union nvme_data_ptr     dptr;
1233         __u8                    cns;
1234         __u8                    rsvd3;
1235         __le16                  ctrlid;
1236         __u8                    rsvd11[3];
1237         __u8                    csi;
1238         __u32                   rsvd12[4];
1239 };
1240
1241 #define NVME_IDENTIFY_DATA_SIZE 4096
1242
1243 struct nvme_features {
1244         __u8                    opcode;
1245         __u8                    flags;
1246         __u16                   command_id;
1247         __le32                  nsid;
1248         __u64                   rsvd2[2];
1249         union nvme_data_ptr     dptr;
1250         __le32                  fid;
1251         __le32                  dword11;
1252         __le32                  dword12;
1253         __le32                  dword13;
1254         __le32                  dword14;
1255         __le32                  dword15;
1256 };
1257
1258 struct nvme_host_mem_buf_desc {
1259         __le64                  addr;
1260         __le32                  size;
1261         __u32                   rsvd;
1262 };
1263
1264 struct nvme_create_cq {
1265         __u8                    opcode;
1266         __u8                    flags;
1267         __u16                   command_id;
1268         __u32                   rsvd1[5];
1269         __le64                  prp1;
1270         __u64                   rsvd8;
1271         __le16                  cqid;
1272         __le16                  qsize;
1273         __le16                  cq_flags;
1274         __le16                  irq_vector;
1275         __u32                   rsvd12[4];
1276 };
1277
1278 struct nvme_create_sq {
1279         __u8                    opcode;
1280         __u8                    flags;
1281         __u16                   command_id;
1282         __u32                   rsvd1[5];
1283         __le64                  prp1;
1284         __u64                   rsvd8;
1285         __le16                  sqid;
1286         __le16                  qsize;
1287         __le16                  sq_flags;
1288         __le16                  cqid;
1289         __u32                   rsvd12[4];
1290 };
1291
1292 struct nvme_delete_queue {
1293         __u8                    opcode;
1294         __u8                    flags;
1295         __u16                   command_id;
1296         __u32                   rsvd1[9];
1297         __le16                  qid;
1298         __u16                   rsvd10;
1299         __u32                   rsvd11[5];
1300 };
1301
1302 struct nvme_abort_cmd {
1303         __u8                    opcode;
1304         __u8                    flags;
1305         __u16                   command_id;
1306         __u32                   rsvd1[9];
1307         __le16                  sqid;
1308         __u16                   cid;
1309         __u32                   rsvd11[5];
1310 };
1311
1312 struct nvme_download_firmware {
1313         __u8                    opcode;
1314         __u8                    flags;
1315         __u16                   command_id;
1316         __u32                   rsvd1[5];
1317         union nvme_data_ptr     dptr;
1318         __le32                  numd;
1319         __le32                  offset;
1320         __u32                   rsvd12[4];
1321 };
1322
1323 struct nvme_format_cmd {
1324         __u8                    opcode;
1325         __u8                    flags;
1326         __u16                   command_id;
1327         __le32                  nsid;
1328         __u64                   rsvd2[4];
1329         __le32                  cdw10;
1330         __u32                   rsvd11[5];
1331 };
1332
1333 struct nvme_get_log_page_command {
1334         __u8                    opcode;
1335         __u8                    flags;
1336         __u16                   command_id;
1337         __le32                  nsid;
1338         __u64                   rsvd2[2];
1339         union nvme_data_ptr     dptr;
1340         __u8                    lid;
1341         __u8                    lsp; /* upper 4 bits reserved */
1342         __le16                  numdl;
1343         __le16                  numdu;
1344         __u16                   rsvd11;
1345         union {
1346                 struct {
1347                         __le32 lpol;
1348                         __le32 lpou;
1349                 };
1350                 __le64 lpo;
1351         };
1352         __u8                    rsvd14[3];
1353         __u8                    csi;
1354         __u32                   rsvd15;
1355 };
1356
1357 struct nvme_directive_cmd {
1358         __u8                    opcode;
1359         __u8                    flags;
1360         __u16                   command_id;
1361         __le32                  nsid;
1362         __u64                   rsvd2[2];
1363         union nvme_data_ptr     dptr;
1364         __le32                  numd;
1365         __u8                    doper;
1366         __u8                    dtype;
1367         __le16                  dspec;
1368         __u8                    endir;
1369         __u8                    tdtype;
1370         __u16                   rsvd15;
1371
1372         __u32                   rsvd16[3];
1373 };
1374
1375 /*
1376  * Fabrics subcommands.
1377  */
1378 enum nvmf_fabrics_opcode {
1379         nvme_fabrics_command            = 0x7f,
1380 };
1381
1382 enum nvmf_capsule_command {
1383         nvme_fabrics_type_property_set  = 0x00,
1384         nvme_fabrics_type_connect       = 0x01,
1385         nvme_fabrics_type_property_get  = 0x04,
1386         nvme_fabrics_type_auth_send     = 0x05,
1387         nvme_fabrics_type_auth_receive  = 0x06,
1388 };
1389
1390 #define nvme_fabrics_type_name(type)   { type, #type }
1391 #define show_fabrics_type_name(type)                                    \
1392         __print_symbolic(type,                                          \
1393                 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1394                 nvme_fabrics_type_name(nvme_fabrics_type_connect),      \
1395                 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1396                 nvme_fabrics_type_name(nvme_fabrics_type_auth_send),    \
1397                 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
1398
1399 /*
1400  * If not fabrics command, fctype will be ignored.
1401  */
1402 #define show_opcode_name(qid, opcode, fctype)                   \
1403         ((opcode) == nvme_fabrics_command ?                     \
1404          show_fabrics_type_name(fctype) :                       \
1405         ((qid) ?                                                \
1406          show_nvm_opcode_name(opcode) :                         \
1407          show_admin_opcode_name(opcode)))
1408
1409 struct nvmf_common_command {
1410         __u8    opcode;
1411         __u8    resv1;
1412         __u16   command_id;
1413         __u8    fctype;
1414         __u8    resv2[35];
1415         __u8    ts[24];
1416 };
1417
1418 /*
1419  * The legal cntlid range a NVMe Target will provide.
1420  * Note that cntlid of value 0 is considered illegal in the fabrics world.
1421  * Devices based on earlier specs did not have the subsystem concept;
1422  * therefore, those devices had their cntlid value set to 0 as a result.
1423  */
1424 #define NVME_CNTLID_MIN         1
1425 #define NVME_CNTLID_MAX         0xffef
1426 #define NVME_CNTLID_DYNAMIC     0xffff
1427
1428 #define MAX_DISC_LOGS   255
1429
1430 /* Discovery log page entry flags (EFLAGS): */
1431 enum {
1432         NVME_DISC_EFLAGS_EPCSD          = (1 << 1),
1433         NVME_DISC_EFLAGS_DUPRETINFO     = (1 << 0),
1434 };
1435
1436 /* Discovery log page entry */
1437 struct nvmf_disc_rsp_page_entry {
1438         __u8            trtype;
1439         __u8            adrfam;
1440         __u8            subtype;
1441         __u8            treq;
1442         __le16          portid;
1443         __le16          cntlid;
1444         __le16          asqsz;
1445         __le16          eflags;
1446         __u8            resv10[20];
1447         char            trsvcid[NVMF_TRSVCID_SIZE];
1448         __u8            resv64[192];
1449         char            subnqn[NVMF_NQN_FIELD_LEN];
1450         char            traddr[NVMF_TRADDR_SIZE];
1451         union tsas {
1452                 char            common[NVMF_TSAS_SIZE];
1453                 struct rdma {
1454                         __u8    qptype;
1455                         __u8    prtype;
1456                         __u8    cms;
1457                         __u8    resv3[5];
1458                         __u16   pkey;
1459                         __u8    resv10[246];
1460                 } rdma;
1461         } tsas;
1462 };
1463
1464 /* Discovery log page header */
1465 struct nvmf_disc_rsp_page_hdr {
1466         __le64          genctr;
1467         __le64          numrec;
1468         __le16          recfmt;
1469         __u8            resv14[1006];
1470         struct nvmf_disc_rsp_page_entry entries[];
1471 };
1472
1473 enum {
1474         NVME_CONNECT_DISABLE_SQFLOW     = (1 << 2),
1475 };
1476
1477 struct nvmf_connect_command {
1478         __u8            opcode;
1479         __u8            resv1;
1480         __u16           command_id;
1481         __u8            fctype;
1482         __u8            resv2[19];
1483         union nvme_data_ptr dptr;
1484         __le16          recfmt;
1485         __le16          qid;
1486         __le16          sqsize;
1487         __u8            cattr;
1488         __u8            resv3;
1489         __le32          kato;
1490         __u8            resv4[12];
1491 };
1492
1493 enum {
1494         NVME_CONNECT_AUTHREQ_ASCR       = (1U << 18),
1495         NVME_CONNECT_AUTHREQ_ATR        = (1U << 17),
1496 };
1497
1498 struct nvmf_connect_data {
1499         uuid_t          hostid;
1500         __le16          cntlid;
1501         char            resv4[238];
1502         char            subsysnqn[NVMF_NQN_FIELD_LEN];
1503         char            hostnqn[NVMF_NQN_FIELD_LEN];
1504         char            resv5[256];
1505 };
1506
1507 struct nvmf_property_set_command {
1508         __u8            opcode;
1509         __u8            resv1;
1510         __u16           command_id;
1511         __u8            fctype;
1512         __u8            resv2[35];
1513         __u8            attrib;
1514         __u8            resv3[3];
1515         __le32          offset;
1516         __le64          value;
1517         __u8            resv4[8];
1518 };
1519
1520 struct nvmf_property_get_command {
1521         __u8            opcode;
1522         __u8            resv1;
1523         __u16           command_id;
1524         __u8            fctype;
1525         __u8            resv2[35];
1526         __u8            attrib;
1527         __u8            resv3[3];
1528         __le32          offset;
1529         __u8            resv4[16];
1530 };
1531
1532 struct nvmf_auth_common_command {
1533         __u8            opcode;
1534         __u8            resv1;
1535         __u16           command_id;
1536         __u8            fctype;
1537         __u8            resv2[19];
1538         union nvme_data_ptr dptr;
1539         __u8            resv3;
1540         __u8            spsp0;
1541         __u8            spsp1;
1542         __u8            secp;
1543         __le32          al_tl;
1544         __u8            resv4[16];
1545 };
1546
1547 struct nvmf_auth_send_command {
1548         __u8            opcode;
1549         __u8            resv1;
1550         __u16           command_id;
1551         __u8            fctype;
1552         __u8            resv2[19];
1553         union nvme_data_ptr dptr;
1554         __u8            resv3;
1555         __u8            spsp0;
1556         __u8            spsp1;
1557         __u8            secp;
1558         __le32          tl;
1559         __u8            resv4[16];
1560 };
1561
1562 struct nvmf_auth_receive_command {
1563         __u8            opcode;
1564         __u8            resv1;
1565         __u16           command_id;
1566         __u8            fctype;
1567         __u8            resv2[19];
1568         union nvme_data_ptr dptr;
1569         __u8            resv3;
1570         __u8            spsp0;
1571         __u8            spsp1;
1572         __u8            secp;
1573         __le32          al;
1574         __u8            resv4[16];
1575 };
1576
1577 /* Value for secp */
1578 enum {
1579         NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER    = 0xe9,
1580 };
1581
1582 /* Defined value for auth_type */
1583 enum {
1584         NVME_AUTH_COMMON_MESSAGES       = 0x00,
1585         NVME_AUTH_DHCHAP_MESSAGES       = 0x01,
1586 };
1587
1588 /* Defined messages for auth_id */
1589 enum {
1590         NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE      = 0x00,
1591         NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE      = 0x01,
1592         NVME_AUTH_DHCHAP_MESSAGE_REPLY          = 0x02,
1593         NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1       = 0x03,
1594         NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2       = 0x04,
1595         NVME_AUTH_DHCHAP_MESSAGE_FAILURE2       = 0xf0,
1596         NVME_AUTH_DHCHAP_MESSAGE_FAILURE1       = 0xf1,
1597 };
1598
1599 struct nvmf_auth_dhchap_protocol_descriptor {
1600         __u8            authid;
1601         __u8            rsvd;
1602         __u8            halen;
1603         __u8            dhlen;
1604         __u8            idlist[60];
1605 };
1606
1607 enum {
1608         NVME_AUTH_DHCHAP_AUTH_ID        = 0x01,
1609 };
1610
1611 /* Defined hash functions for DH-HMAC-CHAP authentication */
1612 enum {
1613         NVME_AUTH_HASH_SHA256   = 0x01,
1614         NVME_AUTH_HASH_SHA384   = 0x02,
1615         NVME_AUTH_HASH_SHA512   = 0x03,
1616         NVME_AUTH_HASH_INVALID  = 0xff,
1617 };
1618
1619 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1620 enum {
1621         NVME_AUTH_DHGROUP_NULL          = 0x00,
1622         NVME_AUTH_DHGROUP_2048          = 0x01,
1623         NVME_AUTH_DHGROUP_3072          = 0x02,
1624         NVME_AUTH_DHGROUP_4096          = 0x03,
1625         NVME_AUTH_DHGROUP_6144          = 0x04,
1626         NVME_AUTH_DHGROUP_8192          = 0x05,
1627         NVME_AUTH_DHGROUP_INVALID       = 0xff,
1628 };
1629
1630 union nvmf_auth_protocol {
1631         struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1632 };
1633
1634 struct nvmf_auth_dhchap_negotiate_data {
1635         __u8            auth_type;
1636         __u8            auth_id;
1637         __le16          rsvd;
1638         __le16          t_id;
1639         __u8            sc_c;
1640         __u8            napd;
1641         union nvmf_auth_protocol auth_protocol[];
1642 };
1643
1644 struct nvmf_auth_dhchap_challenge_data {
1645         __u8            auth_type;
1646         __u8            auth_id;
1647         __u16           rsvd1;
1648         __le16          t_id;
1649         __u8            hl;
1650         __u8            rsvd2;
1651         __u8            hashid;
1652         __u8            dhgid;
1653         __le16          dhvlen;
1654         __le32          seqnum;
1655         /* 'hl' bytes of challenge value */
1656         __u8            cval[];
1657         /* followed by 'dhvlen' bytes of DH value */
1658 };
1659
1660 struct nvmf_auth_dhchap_reply_data {
1661         __u8            auth_type;
1662         __u8            auth_id;
1663         __le16          rsvd1;
1664         __le16          t_id;
1665         __u8            hl;
1666         __u8            rsvd2;
1667         __u8            cvalid;
1668         __u8            rsvd3;
1669         __le16          dhvlen;
1670         __le32          seqnum;
1671         /* 'hl' bytes of response data */
1672         __u8            rval[];
1673         /* followed by 'hl' bytes of Challenge value */
1674         /* followed by 'dhvlen' bytes of DH value */
1675 };
1676
1677 enum {
1678         NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
1679 };
1680
1681 struct nvmf_auth_dhchap_success1_data {
1682         __u8            auth_type;
1683         __u8            auth_id;
1684         __le16          rsvd1;
1685         __le16          t_id;
1686         __u8            hl;
1687         __u8            rsvd2;
1688         __u8            rvalid;
1689         __u8            rsvd3[7];
1690         /* 'hl' bytes of response value if 'rvalid' is set */
1691         __u8            rval[];
1692 };
1693
1694 struct nvmf_auth_dhchap_success2_data {
1695         __u8            auth_type;
1696         __u8            auth_id;
1697         __le16          rsvd1;
1698         __le16          t_id;
1699         __u8            rsvd2[10];
1700 };
1701
1702 struct nvmf_auth_dhchap_failure_data {
1703         __u8            auth_type;
1704         __u8            auth_id;
1705         __le16          rsvd1;
1706         __le16          t_id;
1707         __u8            rescode;
1708         __u8            rescode_exp;
1709 };
1710
1711 enum {
1712         NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED  = 0x01,
1713 };
1714
1715 enum {
1716         NVME_AUTH_DHCHAP_FAILURE_FAILED                 = 0x01,
1717         NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE             = 0x02,
1718         NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH        = 0x03,
1719         NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE          = 0x04,
1720         NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE       = 0x05,
1721         NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD      = 0x06,
1722         NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE      = 0x07,
1723 };
1724
1725
1726 struct nvme_dbbuf {
1727         __u8                    opcode;
1728         __u8                    flags;
1729         __u16                   command_id;
1730         __u32                   rsvd1[5];
1731         __le64                  prp1;
1732         __le64                  prp2;
1733         __u32                   rsvd12[6];
1734 };
1735
1736 struct streams_directive_params {
1737         __le16  msl;
1738         __le16  nssa;
1739         __le16  nsso;
1740         __u8    rsvd[10];
1741         __le32  sws;
1742         __le16  sgs;
1743         __le16  nsa;
1744         __le16  nso;
1745         __u8    rsvd2[6];
1746 };
1747
1748 struct nvme_command {
1749         union {
1750                 struct nvme_common_command common;
1751                 struct nvme_rw_command rw;
1752                 struct nvme_identify identify;
1753                 struct nvme_features features;
1754                 struct nvme_create_cq create_cq;
1755                 struct nvme_create_sq create_sq;
1756                 struct nvme_delete_queue delete_queue;
1757                 struct nvme_download_firmware dlfw;
1758                 struct nvme_format_cmd format;
1759                 struct nvme_dsm_cmd dsm;
1760                 struct nvme_write_zeroes_cmd write_zeroes;
1761                 struct nvme_zone_mgmt_send_cmd zms;
1762                 struct nvme_zone_mgmt_recv_cmd zmr;
1763                 struct nvme_abort_cmd abort;
1764                 struct nvme_get_log_page_command get_log_page;
1765                 struct nvmf_common_command fabrics;
1766                 struct nvmf_connect_command connect;
1767                 struct nvmf_property_set_command prop_set;
1768                 struct nvmf_property_get_command prop_get;
1769                 struct nvmf_auth_common_command auth_common;
1770                 struct nvmf_auth_send_command auth_send;
1771                 struct nvmf_auth_receive_command auth_receive;
1772                 struct nvme_dbbuf dbbuf;
1773                 struct nvme_directive_cmd directive;
1774         };
1775 };
1776
1777 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1778 {
1779         return cmd->common.opcode == nvme_fabrics_command;
1780 }
1781
1782 struct nvme_error_slot {
1783         __le64          error_count;
1784         __le16          sqid;
1785         __le16          cmdid;
1786         __le16          status_field;
1787         __le16          param_error_location;
1788         __le64          lba;
1789         __le32          nsid;
1790         __u8            vs;
1791         __u8            resv[3];
1792         __le64          cs;
1793         __u8            resv2[24];
1794 };
1795
1796 static inline bool nvme_is_write(struct nvme_command *cmd)
1797 {
1798         /*
1799          * What a mess...
1800          *
1801          * Why can't we simply have a Fabrics In and Fabrics out command?
1802          */
1803         if (unlikely(nvme_is_fabrics(cmd)))
1804                 return cmd->fabrics.fctype & 1;
1805         return cmd->common.opcode & 1;
1806 }
1807
1808 enum {
1809         /*
1810          * Generic Command Status:
1811          */
1812         NVME_SC_SUCCESS                 = 0x0,
1813         NVME_SC_INVALID_OPCODE          = 0x1,
1814         NVME_SC_INVALID_FIELD           = 0x2,
1815         NVME_SC_CMDID_CONFLICT          = 0x3,
1816         NVME_SC_DATA_XFER_ERROR         = 0x4,
1817         NVME_SC_POWER_LOSS              = 0x5,
1818         NVME_SC_INTERNAL                = 0x6,
1819         NVME_SC_ABORT_REQ               = 0x7,
1820         NVME_SC_ABORT_QUEUE             = 0x8,
1821         NVME_SC_FUSED_FAIL              = 0x9,
1822         NVME_SC_FUSED_MISSING           = 0xa,
1823         NVME_SC_INVALID_NS              = 0xb,
1824         NVME_SC_CMD_SEQ_ERROR           = 0xc,
1825         NVME_SC_SGL_INVALID_LAST        = 0xd,
1826         NVME_SC_SGL_INVALID_COUNT       = 0xe,
1827         NVME_SC_SGL_INVALID_DATA        = 0xf,
1828         NVME_SC_SGL_INVALID_METADATA    = 0x10,
1829         NVME_SC_SGL_INVALID_TYPE        = 0x11,
1830         NVME_SC_CMB_INVALID_USE         = 0x12,
1831         NVME_SC_PRP_INVALID_OFFSET      = 0x13,
1832         NVME_SC_ATOMIC_WU_EXCEEDED      = 0x14,
1833         NVME_SC_OP_DENIED               = 0x15,
1834         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
1835         NVME_SC_RESERVED                = 0x17,
1836         NVME_SC_HOST_ID_INCONSIST       = 0x18,
1837         NVME_SC_KA_TIMEOUT_EXPIRED      = 0x19,
1838         NVME_SC_KA_TIMEOUT_INVALID      = 0x1A,
1839         NVME_SC_ABORTED_PREEMPT_ABORT   = 0x1B,
1840         NVME_SC_SANITIZE_FAILED         = 0x1C,
1841         NVME_SC_SANITIZE_IN_PROGRESS    = 0x1D,
1842         NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1843         NVME_SC_CMD_NOT_SUP_CMB_QUEUE   = 0x1F,
1844         NVME_SC_NS_WRITE_PROTECTED      = 0x20,
1845         NVME_SC_CMD_INTERRUPTED         = 0x21,
1846         NVME_SC_TRANSIENT_TR_ERR        = 0x22,
1847         NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
1848         NVME_SC_INVALID_IO_CMD_SET      = 0x2C,
1849
1850         NVME_SC_LBA_RANGE               = 0x80,
1851         NVME_SC_CAP_EXCEEDED            = 0x81,
1852         NVME_SC_NS_NOT_READY            = 0x82,
1853         NVME_SC_RESERVATION_CONFLICT    = 0x83,
1854         NVME_SC_FORMAT_IN_PROGRESS      = 0x84,
1855
1856         /*
1857          * Command Specific Status:
1858          */
1859         NVME_SC_CQ_INVALID              = 0x100,
1860         NVME_SC_QID_INVALID             = 0x101,
1861         NVME_SC_QUEUE_SIZE              = 0x102,
1862         NVME_SC_ABORT_LIMIT             = 0x103,
1863         NVME_SC_ABORT_MISSING           = 0x104,
1864         NVME_SC_ASYNC_LIMIT             = 0x105,
1865         NVME_SC_FIRMWARE_SLOT           = 0x106,
1866         NVME_SC_FIRMWARE_IMAGE          = 0x107,
1867         NVME_SC_INVALID_VECTOR          = 0x108,
1868         NVME_SC_INVALID_LOG_PAGE        = 0x109,
1869         NVME_SC_INVALID_FORMAT          = 0x10a,
1870         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
1871         NVME_SC_INVALID_QUEUE           = 0x10c,
1872         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1873         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1874         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
1875         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1876         NVME_SC_FW_NEEDS_RESET          = 0x111,
1877         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
1878         NVME_SC_FW_ACTIVATE_PROHIBITED  = 0x113,
1879         NVME_SC_OVERLAPPING_RANGE       = 0x114,
1880         NVME_SC_NS_INSUFFICIENT_CAP     = 0x115,
1881         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
1882         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
1883         NVME_SC_NS_IS_PRIVATE           = 0x119,
1884         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
1885         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
1886         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
1887         NVME_SC_SELT_TEST_IN_PROGRESS   = 0x11d,
1888         NVME_SC_BP_WRITE_PROHIBITED     = 0x11e,
1889         NVME_SC_CTRL_ID_INVALID         = 0x11f,
1890         NVME_SC_SEC_CTRL_STATE_INVALID  = 0x120,
1891         NVME_SC_CTRL_RES_NUM_INVALID    = 0x121,
1892         NVME_SC_RES_ID_INVALID          = 0x122,
1893         NVME_SC_PMR_SAN_PROHIBITED      = 0x123,
1894         NVME_SC_ANA_GROUP_ID_INVALID    = 0x124,
1895         NVME_SC_ANA_ATTACH_FAILED       = 0x125,
1896
1897         /*
1898          * I/O Command Set Specific - NVM commands:
1899          */
1900         NVME_SC_BAD_ATTRIBUTES          = 0x180,
1901         NVME_SC_INVALID_PI              = 0x181,
1902         NVME_SC_READ_ONLY               = 0x182,
1903         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
1904
1905         /*
1906          * I/O Command Set Specific - Fabrics commands:
1907          */
1908         NVME_SC_CONNECT_FORMAT          = 0x180,
1909         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
1910         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1911         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1912         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1913
1914         NVME_SC_DISCOVERY_RESTART       = 0x190,
1915         NVME_SC_AUTH_REQUIRED           = 0x191,
1916
1917         /*
1918          * I/O Command Set Specific - Zoned commands:
1919          */
1920         NVME_SC_ZONE_BOUNDARY_ERROR     = 0x1b8,
1921         NVME_SC_ZONE_FULL               = 0x1b9,
1922         NVME_SC_ZONE_READ_ONLY          = 0x1ba,
1923         NVME_SC_ZONE_OFFLINE            = 0x1bb,
1924         NVME_SC_ZONE_INVALID_WRITE      = 0x1bc,
1925         NVME_SC_ZONE_TOO_MANY_ACTIVE    = 0x1bd,
1926         NVME_SC_ZONE_TOO_MANY_OPEN      = 0x1be,
1927         NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1928
1929         /*
1930          * Media and Data Integrity Errors:
1931          */
1932         NVME_SC_WRITE_FAULT             = 0x280,
1933         NVME_SC_READ_ERROR              = 0x281,
1934         NVME_SC_GUARD_CHECK             = 0x282,
1935         NVME_SC_APPTAG_CHECK            = 0x283,
1936         NVME_SC_REFTAG_CHECK            = 0x284,
1937         NVME_SC_COMPARE_FAILED          = 0x285,
1938         NVME_SC_ACCESS_DENIED           = 0x286,
1939         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
1940
1941         /*
1942          * Path-related Errors:
1943          */
1944         NVME_SC_INTERNAL_PATH_ERROR     = 0x300,
1945         NVME_SC_ANA_PERSISTENT_LOSS     = 0x301,
1946         NVME_SC_ANA_INACCESSIBLE        = 0x302,
1947         NVME_SC_ANA_TRANSITION          = 0x303,
1948         NVME_SC_CTRL_PATH_ERROR         = 0x360,
1949         NVME_SC_HOST_PATH_ERROR         = 0x370,
1950         NVME_SC_HOST_ABORTED_CMD        = 0x371,
1951
1952         NVME_SC_CRD                     = 0x1800,
1953         NVME_SC_MORE                    = 0x2000,
1954         NVME_SC_DNR                     = 0x4000,
1955 };
1956
1957 struct nvme_completion {
1958         /*
1959          * Used by Admin and Fabrics commands to return data:
1960          */
1961         union nvme_result {
1962                 __le16  u16;
1963                 __le32  u32;
1964                 __le64  u64;
1965         } result;
1966         __le16  sq_head;        /* how much of this queue may be reclaimed */
1967         __le16  sq_id;          /* submission queue that generated this entry */
1968         __u16   command_id;     /* of the command which completed */
1969         __le16  status;         /* did the command fail, and if so, why? */
1970 };
1971
1972 #define NVME_VS(major, minor, tertiary) \
1973         (((major) << 16) | ((minor) << 8) | (tertiary))
1974
1975 #define NVME_MAJOR(ver)         ((ver) >> 16)
1976 #define NVME_MINOR(ver)         (((ver) >> 8) & 0xff)
1977 #define NVME_TERTIARY(ver)      ((ver) & 0xff)
1978
1979 #endif /* _LINUX_NVME_H */