2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 #include <linux/types.h>
19 #include <linux/uuid.h>
21 /* NQN names in commands fields specified one size */
22 #define NVMF_NQN_FIELD_LEN 256
24 /* However the max length of a qualified name is another size */
25 #define NVMF_NQN_SIZE 223
27 #define NVMF_TRSVCID_SIZE 32
28 #define NVMF_TRADDR_SIZE 256
29 #define NVMF_TSAS_SIZE 256
31 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
33 #define NVME_RDMA_IP_PORT 4420
35 #define NVME_NSID_ALL 0xffffffff
37 enum nvme_subsys_type {
38 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
39 NVME_NQN_NVME = 2, /* NVME type target subsystem */
42 /* Address Family codes for Discovery Log Page entry ADRFAM field */
44 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
45 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
46 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
47 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
48 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
51 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
53 NVMF_TRTYPE_RDMA = 1, /* RDMA */
54 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
55 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
59 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
61 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
62 NVMF_TREQ_REQUIRED = 1, /* Required */
63 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
66 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
70 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
71 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
74 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
78 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
79 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
80 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
81 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
82 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
85 /* RDMA Connection Management Service Type codes for Discovery Log Page
86 * entry TSAS RDMA_CMS field
89 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
92 #define NVME_AQ_DEPTH 32
93 #define NVME_NR_AEN_COMMANDS 1
94 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
97 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
98 * NVM-Express 1.2 specification, section 4.1.2.
100 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
103 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
104 NVME_REG_VS = 0x0008, /* Version */
105 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
106 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
107 NVME_REG_CC = 0x0014, /* Controller Configuration */
108 NVME_REG_CSTS = 0x001c, /* Controller Status */
109 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
110 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
111 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
112 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
113 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
114 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
115 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
118 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
119 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
120 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
121 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
122 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
123 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
125 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
126 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
129 NVME_CMBSZ_SQS = 1 << 0,
130 NVME_CMBSZ_CQS = 1 << 1,
131 NVME_CMBSZ_LISTS = 1 << 2,
132 NVME_CMBSZ_RDS = 1 << 3,
133 NVME_CMBSZ_WDS = 1 << 4,
135 NVME_CMBSZ_SZ_SHIFT = 12,
136 NVME_CMBSZ_SZ_MASK = 0xfffff,
138 NVME_CMBSZ_SZU_SHIFT = 8,
139 NVME_CMBSZ_SZU_MASK = 0xf,
143 * Submission and Completion Queue Entry Sizes for the NVM command set.
144 * (In bytes and specified as a power of two (2^n)).
146 #define NVME_NVM_IOSQES 6
147 #define NVME_NVM_IOCQES 4
150 NVME_CC_ENABLE = 1 << 0,
151 NVME_CC_CSS_NVM = 0 << 4,
152 NVME_CC_EN_SHIFT = 0,
153 NVME_CC_CSS_SHIFT = 4,
154 NVME_CC_MPS_SHIFT = 7,
155 NVME_CC_AMS_SHIFT = 11,
156 NVME_CC_SHN_SHIFT = 14,
157 NVME_CC_IOSQES_SHIFT = 16,
158 NVME_CC_IOCQES_SHIFT = 20,
159 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
160 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
161 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
162 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
163 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
164 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
165 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
166 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
167 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
168 NVME_CSTS_RDY = 1 << 0,
169 NVME_CSTS_CFS = 1 << 1,
170 NVME_CSTS_NSSRO = 1 << 4,
171 NVME_CSTS_PP = 1 << 5,
172 NVME_CSTS_SHST_NORMAL = 0 << 2,
173 NVME_CSTS_SHST_OCCUR = 1 << 2,
174 NVME_CSTS_SHST_CMPLT = 2 << 2,
175 NVME_CSTS_SHST_MASK = 3 << 2,
178 struct nvme_id_power_state {
179 __le16 max_power; /* centiwatts */
182 __le32 entry_lat; /* microseconds */
183 __le32 exit_lat; /* microseconds */
192 __u8 active_work_scale;
197 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
198 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
201 struct nvme_id_ctrl {
276 struct nvme_id_power_state psd[32];
281 NVME_CTRL_ONCS_COMPARE = 1 << 0,
282 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
283 NVME_CTRL_ONCS_DSM = 1 << 2,
284 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
285 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
286 NVME_CTRL_VWC_PRESENT = 1 << 0,
287 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
288 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
289 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
290 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
328 struct nvme_lbaf lbaf[16];
334 NVME_ID_CNS_NS = 0x00,
335 NVME_ID_CNS_CTRL = 0x01,
336 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
337 NVME_ID_CNS_NS_DESC_LIST = 0x03,
338 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
339 NVME_ID_CNS_NS_PRESENT = 0x11,
340 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
341 NVME_ID_CNS_CTRL_LIST = 0x13,
345 NVME_DIR_IDENTIFY = 0x00,
346 NVME_DIR_STREAMS = 0x01,
347 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
348 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
349 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
350 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
351 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
352 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
353 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
354 NVME_DIR_ENDIR = 0x01,
358 NVME_NS_FEAT_THIN = 1 << 0,
359 NVME_NS_FLBAS_LBA_MASK = 0xf,
360 NVME_NS_FLBAS_META_EXT = 0x10,
361 NVME_LBAF_RP_BEST = 0,
362 NVME_LBAF_RP_BETTER = 1,
363 NVME_LBAF_RP_GOOD = 2,
364 NVME_LBAF_RP_DEGRADED = 3,
365 NVME_NS_DPC_PI_LAST = 1 << 4,
366 NVME_NS_DPC_PI_FIRST = 1 << 3,
367 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
368 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
369 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
370 NVME_NS_DPS_PI_FIRST = 1 << 3,
371 NVME_NS_DPS_PI_MASK = 0x7,
372 NVME_NS_DPS_PI_TYPE1 = 1,
373 NVME_NS_DPS_PI_TYPE2 = 2,
374 NVME_NS_DPS_PI_TYPE3 = 3,
377 struct nvme_ns_id_desc {
383 #define NVME_NIDT_EUI64_LEN 8
384 #define NVME_NIDT_NGUID_LEN 16
385 #define NVME_NIDT_UUID_LEN 16
388 NVME_NIDT_EUI64 = 0x01,
389 NVME_NIDT_NGUID = 0x02,
390 NVME_NIDT_UUID = 0x03,
393 struct nvme_smart_log {
394 __u8 critical_warning;
400 __u8 data_units_read[16];
401 __u8 data_units_written[16];
403 __u8 host_writes[16];
404 __u8 ctrl_busy_time[16];
405 __u8 power_cycles[16];
406 __u8 power_on_hours[16];
407 __u8 unsafe_shutdowns[16];
408 __u8 media_errors[16];
409 __u8 num_err_log_entries[16];
410 __le32 warning_temp_time;
411 __le32 critical_comp_time;
412 __le16 temp_sensor[8];
416 struct nvme_fw_slot_info_log {
424 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
425 NVME_CMD_EFFECTS_LBCC = 1 << 1,
426 NVME_CMD_EFFECTS_NCC = 1 << 2,
427 NVME_CMD_EFFECTS_NIC = 1 << 3,
428 NVME_CMD_EFFECTS_CCC = 1 << 4,
429 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
432 struct nvme_effects_log {
438 enum nvme_ana_state {
439 NVME_ANA_OPTIMIZED = 0x01,
440 NVME_ANA_NONOPTIMIZED = 0x02,
441 NVME_ANA_INACCESSIBLE = 0x03,
442 NVME_ANA_PERSISTENT_LOSS = 0x04,
443 NVME_ANA_CHANGE = 0x0f,
446 struct nvme_ana_group_desc {
455 /* flag for the log specific field of the ANA log */
456 #define NVME_ANA_LOG_RGO (1 << 0)
458 struct nvme_ana_rsp_hdr {
465 NVME_SMART_CRIT_SPARE = 1 << 0,
466 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
467 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
468 NVME_SMART_CRIT_MEDIA = 1 << 3,
469 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
481 NVME_AER_NOTICE_NS_CHANGED = 0x00,
482 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
483 NVME_AER_NOTICE_ANA = 0x03,
487 NVME_AEN_CFG_NS_ATTR = 1 << 8,
488 NVME_AEN_CFG_FW_ACT = 1 << 9,
489 NVME_AEN_CFG_ANA_CHANGE = 1 << 11,
492 struct nvme_lba_range_type {
503 NVME_LBART_TYPE_FS = 0x01,
504 NVME_LBART_TYPE_RAID = 0x02,
505 NVME_LBART_TYPE_CACHE = 0x03,
506 NVME_LBART_TYPE_SWAP = 0x04,
508 NVME_LBART_ATTRIB_TEMP = 1 << 0,
509 NVME_LBART_ATTRIB_HIDE = 1 << 1,
512 struct nvme_reservation_status {
528 enum nvme_async_event_type {
529 NVME_AER_TYPE_ERROR = 0,
530 NVME_AER_TYPE_SMART = 1,
531 NVME_AER_TYPE_NOTICE = 2,
537 nvme_cmd_flush = 0x00,
538 nvme_cmd_write = 0x01,
539 nvme_cmd_read = 0x02,
540 nvme_cmd_write_uncor = 0x04,
541 nvme_cmd_compare = 0x05,
542 nvme_cmd_write_zeroes = 0x08,
544 nvme_cmd_resv_register = 0x0d,
545 nvme_cmd_resv_report = 0x0e,
546 nvme_cmd_resv_acquire = 0x11,
547 nvme_cmd_resv_release = 0x15,
551 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
553 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
554 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
555 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
556 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
560 NVME_SGL_FMT_ADDRESS = 0x00,
561 NVME_SGL_FMT_OFFSET = 0x01,
562 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
563 NVME_SGL_FMT_INVALIDATE = 0x0f,
567 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
569 * For struct nvme_sgl_desc:
570 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
571 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
572 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
574 * For struct nvme_keyed_sgl_desc:
575 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
577 * Transport-specific SGL types:
578 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
581 NVME_SGL_FMT_DATA_DESC = 0x00,
582 NVME_SGL_FMT_SEG_DESC = 0x02,
583 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
584 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
585 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
588 struct nvme_sgl_desc {
595 struct nvme_keyed_sgl_desc {
602 union nvme_data_ptr {
607 struct nvme_sgl_desc sgl;
608 struct nvme_keyed_sgl_desc ksgl;
612 * Lowest two bits of our flags field (FUSE field in the spec):
614 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
615 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
617 * Highest two bits in our flags field (PSDT field in the spec):
619 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
620 * If used, MPTR contains addr of single physical buffer (byte aligned).
621 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
622 * If used, MPTR contains an address of an SGL segment containing
623 * exactly 1 SGL descriptor (qword aligned).
626 NVME_CMD_FUSE_FIRST = (1 << 0),
627 NVME_CMD_FUSE_SECOND = (1 << 1),
629 NVME_CMD_SGL_METABUF = (1 << 6),
630 NVME_CMD_SGL_METASEG = (1 << 7),
631 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
634 struct nvme_common_command {
641 union nvme_data_ptr dptr;
645 struct nvme_rw_command {
652 union nvme_data_ptr dptr;
663 NVME_RW_LR = 1 << 15,
664 NVME_RW_FUA = 1 << 14,
665 NVME_RW_DSM_FREQ_UNSPEC = 0,
666 NVME_RW_DSM_FREQ_TYPICAL = 1,
667 NVME_RW_DSM_FREQ_RARE = 2,
668 NVME_RW_DSM_FREQ_READS = 3,
669 NVME_RW_DSM_FREQ_WRITES = 4,
670 NVME_RW_DSM_FREQ_RW = 5,
671 NVME_RW_DSM_FREQ_ONCE = 6,
672 NVME_RW_DSM_FREQ_PREFETCH = 7,
673 NVME_RW_DSM_FREQ_TEMP = 8,
674 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
675 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
676 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
677 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
678 NVME_RW_DSM_SEQ_REQ = 1 << 6,
679 NVME_RW_DSM_COMPRESSED = 1 << 7,
680 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
681 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
682 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
683 NVME_RW_PRINFO_PRACT = 1 << 13,
684 NVME_RW_DTYPE_STREAMS = 1 << 4,
687 struct nvme_dsm_cmd {
693 union nvme_data_ptr dptr;
700 NVME_DSMGMT_IDR = 1 << 0,
701 NVME_DSMGMT_IDW = 1 << 1,
702 NVME_DSMGMT_AD = 1 << 2,
705 #define NVME_DSM_MAX_RANGES 256
707 struct nvme_dsm_range {
713 struct nvme_write_zeroes_cmd {
720 union nvme_data_ptr dptr;
732 struct nvme_feat_auto_pst {
737 NVME_HOST_MEM_ENABLE = (1 << 0),
738 NVME_HOST_MEM_RETURN = (1 << 1),
743 enum nvme_admin_opcode {
744 nvme_admin_delete_sq = 0x00,
745 nvme_admin_create_sq = 0x01,
746 nvme_admin_get_log_page = 0x02,
747 nvme_admin_delete_cq = 0x04,
748 nvme_admin_create_cq = 0x05,
749 nvme_admin_identify = 0x06,
750 nvme_admin_abort_cmd = 0x08,
751 nvme_admin_set_features = 0x09,
752 nvme_admin_get_features = 0x0a,
753 nvme_admin_async_event = 0x0c,
754 nvme_admin_ns_mgmt = 0x0d,
755 nvme_admin_activate_fw = 0x10,
756 nvme_admin_download_fw = 0x11,
757 nvme_admin_ns_attach = 0x15,
758 nvme_admin_keep_alive = 0x18,
759 nvme_admin_directive_send = 0x19,
760 nvme_admin_directive_recv = 0x1a,
761 nvme_admin_dbbuf = 0x7C,
762 nvme_admin_format_nvm = 0x80,
763 nvme_admin_security_send = 0x81,
764 nvme_admin_security_recv = 0x82,
765 nvme_admin_sanitize_nvm = 0x84,
769 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
770 NVME_CQ_IRQ_ENABLED = (1 << 1),
771 NVME_SQ_PRIO_URGENT = (0 << 1),
772 NVME_SQ_PRIO_HIGH = (1 << 1),
773 NVME_SQ_PRIO_MEDIUM = (2 << 1),
774 NVME_SQ_PRIO_LOW = (3 << 1),
775 NVME_FEAT_ARBITRATION = 0x01,
776 NVME_FEAT_POWER_MGMT = 0x02,
777 NVME_FEAT_LBA_RANGE = 0x03,
778 NVME_FEAT_TEMP_THRESH = 0x04,
779 NVME_FEAT_ERR_RECOVERY = 0x05,
780 NVME_FEAT_VOLATILE_WC = 0x06,
781 NVME_FEAT_NUM_QUEUES = 0x07,
782 NVME_FEAT_IRQ_COALESCE = 0x08,
783 NVME_FEAT_IRQ_CONFIG = 0x09,
784 NVME_FEAT_WRITE_ATOMIC = 0x0a,
785 NVME_FEAT_ASYNC_EVENT = 0x0b,
786 NVME_FEAT_AUTO_PST = 0x0c,
787 NVME_FEAT_HOST_MEM_BUF = 0x0d,
788 NVME_FEAT_TIMESTAMP = 0x0e,
789 NVME_FEAT_KATO = 0x0f,
790 NVME_FEAT_HCTM = 0x10,
791 NVME_FEAT_NOPSC = 0x11,
792 NVME_FEAT_RRL = 0x12,
793 NVME_FEAT_PLM_CONFIG = 0x13,
794 NVME_FEAT_PLM_WINDOW = 0x14,
795 NVME_FEAT_SW_PROGRESS = 0x80,
796 NVME_FEAT_HOST_ID = 0x81,
797 NVME_FEAT_RESV_MASK = 0x82,
798 NVME_FEAT_RESV_PERSIST = 0x83,
799 NVME_FEAT_WRITE_PROTECT = 0x84,
800 NVME_LOG_ERROR = 0x01,
801 NVME_LOG_SMART = 0x02,
802 NVME_LOG_FW_SLOT = 0x03,
803 NVME_LOG_CHANGED_NS = 0x04,
804 NVME_LOG_CMD_EFFECTS = 0x05,
806 NVME_LOG_DISC = 0x70,
807 NVME_LOG_RESERVATION = 0x80,
808 NVME_FWACT_REPL = (0 << 3),
809 NVME_FWACT_REPL_ACTV = (1 << 3),
810 NVME_FWACT_ACTV = (2 << 3),
813 /* NVMe Namespace Write Protect State */
815 NVME_NS_NO_WRITE_PROTECT = 0,
816 NVME_NS_WRITE_PROTECT,
817 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
818 NVME_NS_WRITE_PROTECT_PERMANENT,
821 #define NVME_MAX_CHANGED_NAMESPACES 1024
823 struct nvme_identify {
829 union nvme_data_ptr dptr;
836 #define NVME_IDENTIFY_DATA_SIZE 4096
838 struct nvme_features {
844 union nvme_data_ptr dptr;
853 struct nvme_host_mem_buf_desc {
859 struct nvme_create_cq {
873 struct nvme_create_sq {
887 struct nvme_delete_queue {
897 struct nvme_abort_cmd {
907 struct nvme_download_firmware {
912 union nvme_data_ptr dptr;
918 struct nvme_format_cmd {
928 struct nvme_get_log_page_command {
934 union nvme_data_ptr dptr;
936 __u8 lsp; /* upper 4 bits reserved */
945 struct nvme_directive_cmd {
951 union nvme_data_ptr dptr;
964 * Fabrics subcommands.
966 enum nvmf_fabrics_opcode {
967 nvme_fabrics_command = 0x7f,
970 enum nvmf_capsule_command {
971 nvme_fabrics_type_property_set = 0x00,
972 nvme_fabrics_type_connect = 0x01,
973 nvme_fabrics_type_property_get = 0x04,
976 struct nvmf_common_command {
986 * The legal cntlid range a NVMe Target will provide.
987 * Note that cntlid of value 0 is considered illegal in the fabrics world.
988 * Devices based on earlier specs did not have the subsystem concept;
989 * therefore, those devices had their cntlid value set to 0 as a result.
991 #define NVME_CNTLID_MIN 1
992 #define NVME_CNTLID_MAX 0xffef
993 #define NVME_CNTLID_DYNAMIC 0xffff
995 #define MAX_DISC_LOGS 255
997 /* Discovery log page entry */
998 struct nvmf_disc_rsp_page_entry {
1007 char trsvcid[NVMF_TRSVCID_SIZE];
1009 char subnqn[NVMF_NQN_FIELD_LEN];
1010 char traddr[NVMF_TRADDR_SIZE];
1012 char common[NVMF_TSAS_SIZE];
1024 /* Discovery log page header */
1025 struct nvmf_disc_rsp_page_hdr {
1030 struct nvmf_disc_rsp_page_entry entries[0];
1033 struct nvmf_connect_command {
1039 union nvme_data_ptr dptr;
1049 struct nvmf_connect_data {
1053 char subsysnqn[NVMF_NQN_FIELD_LEN];
1054 char hostnqn[NVMF_NQN_FIELD_LEN];
1058 struct nvmf_property_set_command {
1071 struct nvmf_property_get_command {
1093 struct streams_directive_params {
1105 struct nvme_command {
1107 struct nvme_common_command common;
1108 struct nvme_rw_command rw;
1109 struct nvme_identify identify;
1110 struct nvme_features features;
1111 struct nvme_create_cq create_cq;
1112 struct nvme_create_sq create_sq;
1113 struct nvme_delete_queue delete_queue;
1114 struct nvme_download_firmware dlfw;
1115 struct nvme_format_cmd format;
1116 struct nvme_dsm_cmd dsm;
1117 struct nvme_write_zeroes_cmd write_zeroes;
1118 struct nvme_abort_cmd abort;
1119 struct nvme_get_log_page_command get_log_page;
1120 struct nvmf_common_command fabrics;
1121 struct nvmf_connect_command connect;
1122 struct nvmf_property_set_command prop_set;
1123 struct nvmf_property_get_command prop_get;
1124 struct nvme_dbbuf dbbuf;
1125 struct nvme_directive_cmd directive;
1129 static inline bool nvme_is_write(struct nvme_command *cmd)
1134 * Why can't we simply have a Fabrics In and Fabrics out command?
1136 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
1137 return cmd->fabrics.fctype & 1;
1138 return cmd->common.opcode & 1;
1143 * Generic Command Status:
1145 NVME_SC_SUCCESS = 0x0,
1146 NVME_SC_INVALID_OPCODE = 0x1,
1147 NVME_SC_INVALID_FIELD = 0x2,
1148 NVME_SC_CMDID_CONFLICT = 0x3,
1149 NVME_SC_DATA_XFER_ERROR = 0x4,
1150 NVME_SC_POWER_LOSS = 0x5,
1151 NVME_SC_INTERNAL = 0x6,
1152 NVME_SC_ABORT_REQ = 0x7,
1153 NVME_SC_ABORT_QUEUE = 0x8,
1154 NVME_SC_FUSED_FAIL = 0x9,
1155 NVME_SC_FUSED_MISSING = 0xa,
1156 NVME_SC_INVALID_NS = 0xb,
1157 NVME_SC_CMD_SEQ_ERROR = 0xc,
1158 NVME_SC_SGL_INVALID_LAST = 0xd,
1159 NVME_SC_SGL_INVALID_COUNT = 0xe,
1160 NVME_SC_SGL_INVALID_DATA = 0xf,
1161 NVME_SC_SGL_INVALID_METADATA = 0x10,
1162 NVME_SC_SGL_INVALID_TYPE = 0x11,
1164 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1165 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1167 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1169 NVME_SC_LBA_RANGE = 0x80,
1170 NVME_SC_CAP_EXCEEDED = 0x81,
1171 NVME_SC_NS_NOT_READY = 0x82,
1172 NVME_SC_RESERVATION_CONFLICT = 0x83,
1175 * Command Specific Status:
1177 NVME_SC_CQ_INVALID = 0x100,
1178 NVME_SC_QID_INVALID = 0x101,
1179 NVME_SC_QUEUE_SIZE = 0x102,
1180 NVME_SC_ABORT_LIMIT = 0x103,
1181 NVME_SC_ABORT_MISSING = 0x104,
1182 NVME_SC_ASYNC_LIMIT = 0x105,
1183 NVME_SC_FIRMWARE_SLOT = 0x106,
1184 NVME_SC_FIRMWARE_IMAGE = 0x107,
1185 NVME_SC_INVALID_VECTOR = 0x108,
1186 NVME_SC_INVALID_LOG_PAGE = 0x109,
1187 NVME_SC_INVALID_FORMAT = 0x10a,
1188 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1189 NVME_SC_INVALID_QUEUE = 0x10c,
1190 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1191 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1192 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1193 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1194 NVME_SC_FW_NEEDS_RESET = 0x111,
1195 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1196 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
1197 NVME_SC_OVERLAPPING_RANGE = 0x114,
1198 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
1199 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1200 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1201 NVME_SC_NS_IS_PRIVATE = 0x119,
1202 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1203 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1204 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1207 * I/O Command Set Specific - NVM commands:
1209 NVME_SC_BAD_ATTRIBUTES = 0x180,
1210 NVME_SC_INVALID_PI = 0x181,
1211 NVME_SC_READ_ONLY = 0x182,
1212 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1215 * I/O Command Set Specific - Fabrics commands:
1217 NVME_SC_CONNECT_FORMAT = 0x180,
1218 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1219 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1220 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1221 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1223 NVME_SC_DISCOVERY_RESTART = 0x190,
1224 NVME_SC_AUTH_REQUIRED = 0x191,
1227 * Media and Data Integrity Errors:
1229 NVME_SC_WRITE_FAULT = 0x280,
1230 NVME_SC_READ_ERROR = 0x281,
1231 NVME_SC_GUARD_CHECK = 0x282,
1232 NVME_SC_APPTAG_CHECK = 0x283,
1233 NVME_SC_REFTAG_CHECK = 0x284,
1234 NVME_SC_COMPARE_FAILED = 0x285,
1235 NVME_SC_ACCESS_DENIED = 0x286,
1236 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1239 * Path-related Errors:
1241 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1242 NVME_SC_ANA_INACCESSIBLE = 0x302,
1243 NVME_SC_ANA_TRANSITION = 0x303,
1245 NVME_SC_DNR = 0x4000,
1248 struct nvme_completion {
1250 * Used by Admin and Fabrics commands to return data:
1257 __le16 sq_head; /* how much of this queue may be reclaimed */
1258 __le16 sq_id; /* submission queue that generated this entry */
1259 __u16 command_id; /* of the command which completed */
1260 __le16 status; /* did the command fail, and if so, why? */
1263 #define NVME_VS(major, minor, tertiary) \
1264 (((major) << 16) | ((minor) << 8) | (tertiary))
1266 #define NVME_MAJOR(ver) ((ver) >> 16)
1267 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1268 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1270 #endif /* _LINUX_NVME_H */