2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #ifndef LINUX_MMC_DW_MMC_H
15 #define LINUX_MMC_DW_MMC_H
17 #include <linux/scatterlist.h>
18 #include <linux/mmc/core.h>
19 #include <linux/dmaengine.h>
20 #include <linux/reset.h>
22 #define MAX_MCI_SLOTS 2
32 STATE_WAITING_CMD11_DONE,
36 EVENT_CMD_COMPLETE = 0,
50 struct dw_mci_dma_slave {
52 enum dma_transfer_direction direction;
56 * struct dw_mci - MMC controller state shared between all slots
57 * @lock: Spinlock protecting the queue and associated data.
58 * @irq_lock: Spinlock protecting the INTMASK setting.
59 * @regs: Pointer to MMIO registers.
60 * @fifo_reg: Pointer to MMIO registers for data FIFO
61 * @sg: Scatterlist entry currently being processed by PIO code, if any.
62 * @sg_miter: PIO mapping scatterlist iterator.
63 * @cur_slot: The slot which is currently using the controller.
64 * @mrq: The request currently being processed on @cur_slot,
65 * or NULL if the controller is idle.
66 * @cmd: The command currently being sent to the card, or NULL.
67 * @data: The data currently being transferred, or NULL if no data
68 * transfer is in progress.
69 * @stop_abort: The command currently prepared for stoping transfer.
70 * @prev_blksz: The former transfer blksz record.
71 * @timing: Record of current ios timing.
72 * @use_dma: Whether DMA channel is initialized or not.
73 * @using_dma: Whether DMA is in use for the current transfer.
74 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
75 * @sg_dma: Bus address of DMA buffer.
76 * @sg_cpu: Virtual address of DMA buffer.
77 * @dma_ops: Pointer to platform-specific DMA callbacks.
78 * @cmd_status: Snapshot of SR taken upon completion of the current
79 * @ring_size: Buffer size for idma descriptors.
80 * command. Only valid when EVENT_CMD_COMPLETE is pending.
81 * @dms: structure of slave-dma private data.
82 * @phy_regs: physical address of controller's register map
83 * @data_status: Snapshot of SR taken upon completion of the current
84 * data transfer. Only valid when EVENT_DATA_COMPLETE or
85 * EVENT_DATA_ERROR is pending.
86 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
88 * @dir_status: Direction of current transfer.
89 * @tasklet: Tasklet running the request state machine.
90 * @pending_events: Bitmask of events flagged by the interrupt handler
91 * to be processed by the tasklet.
92 * @completed_events: Bitmask of events which the state machine has
94 * @state: Tasklet state.
95 * @queue: List of slots waiting for access to the controller.
96 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
97 * rate and timeout calculations.
98 * @current_speed: Configured rate of the controller.
99 * @num_slots: Number of slots available.
100 * @fifoth_val: The value of FIFOTH register.
101 * @verid: Denote Version ID.
102 * @dev: Device associated with the MMC controller.
103 * @pdata: Platform data associated with the MMC controller.
104 * @drv_data: Driver specific data for identified variant of the controller
105 * @priv: Implementation defined private data.
106 * @biu_clk: Pointer to bus interface unit clock instance.
107 * @ciu_clk: Pointer to card interface unit clock instance.
108 * @slot: Slots sharing this MMC controller.
109 * @fifo_depth: depth of FIFO.
110 * @data_shift: log2 of FIFO item size.
111 * @part_buf_start: Start index in part_buf.
112 * @part_buf_count: Bytes of partial data in part_buf.
113 * @part_buf: Simple buffer for partial fifo reads/writes.
114 * @push_data: Pointer to FIFO push function.
115 * @pull_data: Pointer to FIFO pull function.
116 * @vqmmc_enabled: Status of vqmmc, should be true or false.
117 * @irq_flags: The flags to be passed to request_irq.
118 * @irq: The irq value to be passed to request_irq.
119 * @sdio_id0: Number of slot0 in the SDIO interrupt registers.
120 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
121 * @dto_timer: Timer for broken data transfer over scheme.
126 * @lock is a softirq-safe spinlock protecting @queue as well as
127 * @cur_slot, @mrq and @state. These must always be updated
128 * at the same time while holding @lock.
130 * @irq_lock is an irq-safe spinlock protecting the INTMASK register
131 * to allow the interrupt handler to modify it directly. Held for only long
132 * enough to read-modify-write INTMASK and no other locks are grabbed when
135 * The @mrq field of struct dw_mci_slot is also protected by @lock,
136 * and must always be written at the same time as the slot is added to
139 * @pending_events and @completed_events are accessed using atomic bit
140 * operations, so they don't need any locking.
142 * None of the fields touched by the interrupt handler need any
143 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
144 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
145 * interrupts must be disabled and @data_status updated with a
146 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
147 * CMDRDY interrupt must be disabled and @cmd_status updated with a
148 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
149 * bytes_xfered field of @data must be written. This is ensured by
156 void __iomem *fifo_reg;
158 struct scatterlist *sg;
159 struct sg_mapping_iter sg_miter;
161 struct dw_mci_slot *cur_slot;
162 struct mmc_request *mrq;
163 struct mmc_command *cmd;
164 struct mmc_data *data;
165 struct mmc_command stop_abort;
166 unsigned int prev_blksz;
167 unsigned char timing;
169 /* DMA interface members*/
172 int dma_64bit_address;
176 const struct dw_mci_dma_ops *dma_ops;
178 unsigned int ring_size;
181 struct dw_mci_dma_slave *dms;
182 /* Registers's physical base address */
183 resource_size_t phy_regs;
189 struct tasklet_struct tasklet;
190 unsigned long pending_events;
191 unsigned long completed_events;
192 enum dw_mci_state state;
193 struct list_head queue;
201 struct dw_mci_board *pdata;
202 const struct dw_mci_drv_data *drv_data;
206 struct dw_mci_slot *slot[MAX_MCI_SLOTS];
208 /* FIFO push and pull */
218 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
219 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
222 unsigned long irq_flags; /* IRQ flags */
227 struct timer_list cmd11_timer;
228 struct timer_list dto_timer;
231 /* DMA ops for Internal/External DMAC interface */
232 struct dw_mci_dma_ops {
234 int (*init)(struct dw_mci *host);
235 int (*start)(struct dw_mci *host, unsigned int sg_len);
236 void (*complete)(void *host);
237 void (*stop)(struct dw_mci *host);
238 void (*cleanup)(struct dw_mci *host);
239 void (*exit)(struct dw_mci *host);
244 /* Board platform data */
245 struct dw_mci_board {
248 unsigned int bus_hz; /* Clock speed at the cclk_in pad */
250 u32 caps; /* Capabilities */
251 u32 caps2; /* More capabilities */
252 u32 pm_caps; /* PM capabilities */
254 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
255 * but note that this may not be reliable after a bootloader has used
258 unsigned int fifo_depth;
260 /* delay in mS before detecting cards after interrupt */
263 struct reset_control *rstc;
264 struct dw_mci_dma_ops *dma_ops;
265 struct dma_pdata *data;
268 #endif /* LINUX_MMC_DW_MMC_H */