2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h>
39 #define MLX5_INVALID_LKEY 0x100
40 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
41 #define MLX5_DIF_SIZE 8
42 #define MLX5_STRIDE_BLOCK_OP 0x400
43 #define MLX5_CPY_GRD_MASK 0xc0
44 #define MLX5_CPY_APP_MASK 0x30
45 #define MLX5_CPY_REF_MASK 0x0f
46 #define MLX5_BSF_INC_REFTAG (1 << 6)
47 #define MLX5_BSF_INL_VALID (1 << 15)
48 #define MLX5_BSF_REFRESH_DIF (1 << 14)
49 #define MLX5_BSF_REPEAT_BLOCK (1 << 7)
50 #define MLX5_BSF_APPTAG_ESCAPE 0x1
51 #define MLX5_BSF_APPREF_ESCAPE 0x2
53 #define MLX5_QPN_BITS 24
54 #define MLX5_QPN_MASK ((1 << MLX5_QPN_BITS) - 1)
57 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
58 MLX5_QP_OPTPAR_RRE = 1 << 1,
59 MLX5_QP_OPTPAR_RAE = 1 << 2,
60 MLX5_QP_OPTPAR_RWE = 1 << 3,
61 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
62 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
63 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
64 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
65 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
66 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
67 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
68 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
69 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
70 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
71 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
72 MLX5_QP_OPTPAR_SRQN = 1 << 18,
73 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
74 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
75 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
79 MLX5_QP_STATE_RST = 0,
80 MLX5_QP_STATE_INIT = 1,
81 MLX5_QP_STATE_RTR = 2,
82 MLX5_QP_STATE_RTS = 3,
83 MLX5_QP_STATE_SQER = 4,
84 MLX5_QP_STATE_SQD = 5,
85 MLX5_QP_STATE_ERR = 6,
86 MLX5_QP_STATE_SQ_DRAINING = 7,
87 MLX5_QP_STATE_SUSPENDED = 9,
94 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1,
95 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1,
96 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1,
97 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1,
104 MLX5_QP_ST_XRC = 0x3,
105 MLX5_QP_ST_MLX = 0x4,
106 MLX5_QP_ST_DCI = 0x5,
107 MLX5_QP_ST_DCT = 0x6,
108 MLX5_QP_ST_QP0 = 0x7,
109 MLX5_QP_ST_QP1 = 0x8,
110 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
111 MLX5_QP_ST_RAW_IPV6 = 0xa,
112 MLX5_QP_ST_SNIFFER = 0xb,
113 MLX5_QP_ST_SYNC_UMR = 0xe,
114 MLX5_QP_ST_PTP_1588 = 0xd,
115 MLX5_QP_ST_REG_UMR = 0xc,
120 MLX5_QP_PM_MIGRATED = 0x3,
121 MLX5_QP_PM_ARMED = 0x0,
122 MLX5_QP_PM_REARM = 0x1
126 MLX5_NON_ZERO_RQ = 0 << 24,
127 MLX5_SRQ_RQ = 1 << 24,
128 MLX5_CRQ_RQ = 2 << 24,
129 MLX5_ZERO_LEN_RQ = 3 << 24
134 MLX5_QP_BIT_SRE = 1 << 15,
135 MLX5_QP_BIT_SWE = 1 << 14,
136 MLX5_QP_BIT_SAE = 1 << 13,
138 MLX5_QP_BIT_RRE = 1 << 15,
139 MLX5_QP_BIT_RWE = 1 << 14,
140 MLX5_QP_BIT_RAE = 1 << 13,
141 MLX5_QP_BIT_RIC = 1 << 4,
142 MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2,
143 MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1,
144 MLX5_QP_BIT_CC_MASTER = 1 << 0
148 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
149 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
150 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
154 MLX5_SEND_WQE_DS = 16,
155 MLX5_SEND_WQE_BB = 64,
158 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
161 MLX5_SEND_WQE_MAX_WQEBBS = 16,
165 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
166 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
167 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
168 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
169 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
173 MLX5_FENCE_MODE_NONE = 0 << 5,
174 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
175 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
176 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
180 MLX5_QP_LAT_SENSITIVE = 1 << 28,
181 MLX5_QP_BLOCK_MCAST = 1 << 30,
182 MLX5_QP_ENABLE_SIG = 1 << 31,
191 MLX5_FLAGS_INLINE = 1<<7,
192 MLX5_FLAGS_CHECK_FREE = 1<<5,
195 struct mlx5_wqe_fmr_seg {
206 struct mlx5_wqe_ctrl_seg {
207 __be32 opmod_idx_opcode;
215 #define MLX5_WQE_CTRL_DS_MASK 0x3f
216 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
217 #define MLX5_WQE_CTRL_QPN_SHIFT 8
218 #define MLX5_WQE_DS_UNITS 16
219 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff
220 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
221 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
224 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
225 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
226 MLX5_ETH_WQE_L3_CSUM = 1 << 6,
227 MLX5_ETH_WQE_L4_CSUM = 1 << 7,
230 struct mlx5_wqe_eth_seg {
236 __be16 inline_hdr_sz;
237 u8 inline_hdr_start[2];
240 struct mlx5_wqe_xrc_seg {
245 struct mlx5_wqe_masked_atomic_seg {
248 __be64 swap_add_mask;
275 struct mlx5_wqe_datagram_seg {
279 struct mlx5_wqe_raddr_seg {
285 struct mlx5_wqe_atomic_seg {
290 struct mlx5_wqe_data_seg {
296 struct mlx5_wqe_umr_ctrl_seg {
299 __be16 klm_octowords;
300 __be16 bsf_octowords;
305 struct mlx5_seg_set_psv {
309 __be32 transient_sig;
313 struct mlx5_seg_get_psv {
321 struct mlx5_seg_check_psv {
323 __be16 err_coalescing_op;
327 __be16 xport_err_mask;
335 struct mlx5_rwqe_sig {
341 struct mlx5_wqe_signature_seg {
347 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
349 struct mlx5_wqe_inline_seg {
358 struct mlx5_bsf_inl {
365 u8 dif_inc_ref_guard_check;
366 __be16 dif_app_bitmask_check;
370 struct mlx5_bsf_basic {
382 __be32 raw_data_size;
386 struct mlx5_bsf_ext {
387 __be32 t_init_gen_pro_size;
388 __be32 rsvd_epi_size;
392 struct mlx5_bsf_inl w_inl;
393 struct mlx5_bsf_inl m_inl;
402 struct mlx5_stride_block_entry {
409 struct mlx5_stride_block_ctrl_seg {
410 __be32 bcount_per_cycle;
417 enum mlx5_pagefault_flags {
418 MLX5_PFAULT_REQUESTOR = 1 << 0,
419 MLX5_PFAULT_WRITE = 1 << 1,
420 MLX5_PFAULT_RDMA = 1 << 2,
423 /* Contains the details of a pagefault. */
424 struct mlx5_pagefault {
427 enum mlx5_pagefault_flags flags;
429 /* Initiator or send message responder pagefault details. */
431 /* Received packet size, only valid for responders. */
434 * WQE index. Refers to either the send queue or
435 * receive queue, according to event_subtype.
439 /* RDMA responder pagefault details */
443 * Received packet size, minimal size page fault
444 * resolution required for forward progress.
453 struct mlx5_core_qp {
454 struct mlx5_core_rsc_common common; /* must be first */
455 void (*event) (struct mlx5_core_qp *, int);
456 void (*pfault_handler)(struct mlx5_core_qp *, struct mlx5_pagefault *);
458 struct mlx5_rsc_debug *dbg;
462 struct mlx5_qp_path {
474 __be32 tclass_flowlabel;
487 struct mlx5_qp_context {
493 __be32 qp_counter_set_usr_page;
495 __be32 log_pg_sz_remote_qpn;
496 struct mlx5_qp_path pri_path;
497 struct mlx5_qp_path alt_path;
500 __be32 next_send_psn;
504 __be32 last_acked_psn;
507 __be32 rnr_nextrecvpsn;
514 __be16 hw_sq_wqe_counter;
515 __be16 sw_sq_wqe_counter;
516 __be16 hw_rcyclic_byte_counter;
517 __be16 hw_rq_counter;
518 __be16 sw_rcyclic_byte_counter;
519 __be16 sw_rq_counter;
524 __be64 dc_access_key;
528 struct mlx5_create_qp_mbox_in {
529 struct mlx5_inbox_hdr hdr;
532 __be32 opt_param_mask;
534 struct mlx5_qp_context ctx;
539 struct mlx5_create_qp_mbox_out {
540 struct mlx5_outbox_hdr hdr;
545 struct mlx5_destroy_qp_mbox_in {
546 struct mlx5_inbox_hdr hdr;
551 struct mlx5_destroy_qp_mbox_out {
552 struct mlx5_outbox_hdr hdr;
556 struct mlx5_modify_qp_mbox_in {
557 struct mlx5_inbox_hdr hdr;
562 struct mlx5_qp_context ctx;
565 struct mlx5_modify_qp_mbox_out {
566 struct mlx5_outbox_hdr hdr;
570 struct mlx5_query_qp_mbox_in {
571 struct mlx5_inbox_hdr hdr;
576 struct mlx5_query_qp_mbox_out {
577 struct mlx5_outbox_hdr hdr;
581 struct mlx5_qp_context ctx;
586 struct mlx5_conf_sqp_mbox_in {
587 struct mlx5_inbox_hdr hdr;
593 struct mlx5_conf_sqp_mbox_out {
594 struct mlx5_outbox_hdr hdr;
598 struct mlx5_alloc_xrcd_mbox_in {
599 struct mlx5_inbox_hdr hdr;
603 struct mlx5_alloc_xrcd_mbox_out {
604 struct mlx5_outbox_hdr hdr;
609 struct mlx5_dealloc_xrcd_mbox_in {
610 struct mlx5_inbox_hdr hdr;
615 struct mlx5_dealloc_xrcd_mbox_out {
616 struct mlx5_outbox_hdr hdr;
620 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
622 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
625 static inline struct mlx5_core_mkey *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
627 return radix_tree_lookup(&dev->priv.mkey_table.tree, key);
630 struct mlx5_page_fault_resume_mbox_in {
631 struct mlx5_inbox_hdr hdr;
636 struct mlx5_page_fault_resume_mbox_out {
637 struct mlx5_outbox_hdr hdr;
641 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
642 struct mlx5_core_qp *qp,
643 struct mlx5_create_qp_mbox_in *in,
645 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 operation,
646 struct mlx5_modify_qp_mbox_in *in, int sqd_event,
647 struct mlx5_core_qp *qp);
648 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
649 struct mlx5_core_qp *qp);
650 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
651 struct mlx5_query_qp_mbox_out *out, int outlen);
653 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
654 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
655 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
656 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
657 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
658 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
659 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
660 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 qpn,
661 u8 context, int error);
663 int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
664 struct mlx5_core_qp *rq);
665 void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev,
666 struct mlx5_core_qp *rq);
667 int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
668 struct mlx5_core_qp *sq);
669 void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev,
670 struct mlx5_core_qp *sq);
672 static inline const char *mlx5_qp_type_str(int type)
675 case MLX5_QP_ST_RC: return "RC";
676 case MLX5_QP_ST_UC: return "C";
677 case MLX5_QP_ST_UD: return "UD";
678 case MLX5_QP_ST_XRC: return "XRC";
679 case MLX5_QP_ST_MLX: return "MLX";
680 case MLX5_QP_ST_QP0: return "QP0";
681 case MLX5_QP_ST_QP1: return "QP1";
682 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
683 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
684 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
685 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
686 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
687 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
688 default: return "Invalid transport type";
692 static inline const char *mlx5_qp_state_str(int state)
695 case MLX5_QP_STATE_RST:
697 case MLX5_QP_STATE_INIT:
699 case MLX5_QP_STATE_RTR:
701 case MLX5_QP_STATE_RTS:
703 case MLX5_QP_STATE_SQER:
705 case MLX5_QP_STATE_SQD:
707 case MLX5_QP_STATE_ERR:
709 case MLX5_QP_STATE_SQ_DRAINING:
710 return "SQ_DRAINING";
711 case MLX5_QP_STATE_SUSPENDED:
713 default: return "Invalid QP state";
717 #endif /* MLX5_QP_H */