2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h>
39 #define MLX5_TERMINATE_SCATTER_LIST_LKEY cpu_to_be32(0x100)
40 /* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV (mem) + PSV (wire) */
41 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 8)
42 #define MLX5_DIF_SIZE 8
43 #define MLX5_STRIDE_BLOCK_OP 0x400
44 #define MLX5_CPY_GRD_MASK 0xc0
45 #define MLX5_CPY_APP_MASK 0x30
46 #define MLX5_CPY_REF_MASK 0x0f
47 #define MLX5_BSF_INC_REFTAG (1 << 6)
48 #define MLX5_BSF_INL_VALID (1 << 15)
49 #define MLX5_BSF_REFRESH_DIF (1 << 14)
50 #define MLX5_BSF_REPEAT_BLOCK (1 << 7)
51 #define MLX5_BSF_APPTAG_ESCAPE 0x1
52 #define MLX5_BSF_APPREF_ESCAPE 0x2
55 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
56 MLX5_QP_OPTPAR_RRE = 1 << 1,
57 MLX5_QP_OPTPAR_RAE = 1 << 2,
58 MLX5_QP_OPTPAR_RWE = 1 << 3,
59 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
60 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
61 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
62 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
63 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
64 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
65 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
66 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
67 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
68 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
69 MLX5_QP_OPTPAR_LAG_TX_AFF = 1 << 15,
70 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
71 MLX5_QP_OPTPAR_SRQN = 1 << 18,
72 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
73 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
74 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
75 MLX5_QP_OPTPAR_COUNTER_SET_ID = 1 << 25,
79 MLX5_QP_STATE_RST = 0,
80 MLX5_QP_STATE_INIT = 1,
81 MLX5_QP_STATE_RTR = 2,
82 MLX5_QP_STATE_RTS = 3,
83 MLX5_QP_STATE_SQER = 4,
84 MLX5_QP_STATE_SQD = 5,
85 MLX5_QP_STATE_ERR = 6,
86 MLX5_QP_STATE_SQ_DRAINING = 7,
87 MLX5_QP_STATE_SUSPENDED = 9,
94 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1,
95 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1,
96 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1,
97 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1,
104 MLX5_QP_ST_XRC = 0x3,
105 MLX5_QP_ST_MLX = 0x4,
106 MLX5_QP_ST_DCI = 0x5,
107 MLX5_QP_ST_DCT = 0x6,
108 MLX5_QP_ST_QP0 = 0x7,
109 MLX5_QP_ST_QP1 = 0x8,
110 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
111 MLX5_QP_ST_RAW_IPV6 = 0xa,
112 MLX5_QP_ST_SNIFFER = 0xb,
113 MLX5_QP_ST_SYNC_UMR = 0xe,
114 MLX5_QP_ST_PTP_1588 = 0xd,
115 MLX5_QP_ST_REG_UMR = 0xc,
120 MLX5_QP_PM_MIGRATED = 0x3,
121 MLX5_QP_PM_ARMED = 0x0,
122 MLX5_QP_PM_REARM = 0x1
126 MLX5_NON_ZERO_RQ = 0x0,
129 MLX5_ZERO_LEN_RQ = 0x3
135 MLX5_QP_BIT_SRE = 1 << 15,
136 MLX5_QP_BIT_SWE = 1 << 14,
137 MLX5_QP_BIT_SAE = 1 << 13,
139 MLX5_QP_BIT_RRE = 1 << 15,
140 MLX5_QP_BIT_RWE = 1 << 14,
141 MLX5_QP_BIT_RAE = 1 << 13,
142 MLX5_QP_BIT_RIC = 1 << 4,
143 MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2,
144 MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1,
145 MLX5_QP_BIT_CC_MASTER = 1 << 0
149 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
150 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
151 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
155 MLX5_SEND_WQE_DS = 16,
156 MLX5_SEND_WQE_BB = 64,
159 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
162 MLX5_SEND_WQE_MAX_WQEBBS = 16,
165 #define MLX5_SEND_WQE_MAX_SIZE (MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQE_BB)
168 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
169 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
170 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
171 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
172 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
176 MLX5_FENCE_MODE_NONE = 0 << 5,
177 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
178 MLX5_FENCE_MODE_FENCE = 2 << 5,
179 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
180 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
189 MLX5_FLAGS_INLINE = 1<<7,
190 MLX5_FLAGS_CHECK_FREE = 1<<5,
193 struct mlx5_wqe_fmr_seg {
204 struct mlx5_wqe_ctrl_seg {
205 __be32 opmod_idx_opcode;
208 struct_group(trailer,
220 ); /* end of trailer group */
223 #define MLX5_WQE_CTRL_DS_MASK 0x3f
224 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
225 #define MLX5_WQE_CTRL_QPN_SHIFT 8
226 #define MLX5_WQE_DS_UNITS 16
227 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff
228 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
229 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
232 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
233 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
234 MLX5_ETH_WQE_L3_CSUM = 1 << 6,
235 MLX5_ETH_WQE_L4_CSUM = 1 << 7,
239 MLX5_ETH_WQE_SVLAN = 1 << 0,
240 MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSOC = 1 << 26,
241 MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSOC = 1 << 27,
242 MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSOC = 3 << 26,
243 MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSOC = 1 << 28,
244 MLX5_ETH_WQE_INSERT_TRAILER = 1 << 30,
245 MLX5_ETH_WQE_INSERT_VLAN = 1 << 15,
249 MLX5_ETH_WQE_SWP_INNER_L3_IPV6 = 1 << 0,
250 MLX5_ETH_WQE_SWP_INNER_L4_UDP = 1 << 1,
251 MLX5_ETH_WQE_SWP_OUTER_L3_IPV6 = 1 << 4,
252 MLX5_ETH_WQE_SWP_OUTER_L4_UDP = 1 << 5,
256 MLX5_ETH_WQE_FT_META_IPSEC = BIT(0),
257 MLX5_ETH_WQE_FT_META_MACSEC = BIT(1),
260 struct mlx5_wqe_eth_seg {
261 u8 swp_outer_l4_offset;
262 u8 swp_outer_l3_offset;
263 u8 swp_inner_l4_offset;
264 u8 swp_inner_l3_offset;
268 __be32 flow_table_metadata;
282 struct mlx5_wqe_xrc_seg {
287 struct mlx5_wqe_masked_atomic_seg {
290 __be64 swap_add_mask;
294 struct mlx5_base_av {
340 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
342 return container_of(ibah, struct mlx5_ib_ah, ibah);
345 struct mlx5_wqe_datagram_seg {
349 struct mlx5_wqe_raddr_seg {
355 struct mlx5_wqe_atomic_seg {
360 struct mlx5_wqe_data_seg {
366 struct mlx5_wqe_umr_ctrl_seg {
369 __be16 xlt_octowords;
372 __be16 bsf_octowords;
375 __be32 xlt_offset_47_16;
379 struct mlx5_seg_set_psv {
383 __be32 transient_sig;
387 struct mlx5_seg_get_psv {
395 struct mlx5_seg_check_psv {
397 __be16 err_coalescing_op;
401 __be16 xport_err_mask;
409 struct mlx5_rwqe_sig {
415 struct mlx5_wqe_signature_seg {
421 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
423 struct mlx5_wqe_inline_seg {
433 struct mlx5_bsf_inl {
440 u8 dif_inc_ref_guard_check;
441 __be16 dif_app_bitmask_check;
445 struct mlx5_bsf_basic {
457 __be32 raw_data_size;
461 struct mlx5_bsf_ext {
462 __be32 t_init_gen_pro_size;
463 __be32 rsvd_epi_size;
467 struct mlx5_bsf_inl w_inl;
468 struct mlx5_bsf_inl m_inl;
487 struct mlx5_stride_block_entry {
494 struct mlx5_stride_block_ctrl_seg {
495 __be32 bcount_per_cycle;
502 struct mlx5_wqe_flow_update_ctrl_seg {
503 __be32 flow_idx_update;
508 struct mlx5_wqe_header_modify_argument_update_seg {
509 u8 argument_list[64];
512 struct mlx5_core_qp {
513 struct mlx5_core_rsc_common common; /* must be first */
514 void (*event) (struct mlx5_core_qp *, int);
516 struct mlx5_rsc_debug *dbg;
521 struct mlx5_core_dct {
522 struct mlx5_core_qp mqp;
523 struct completion drained;
526 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
527 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
529 static inline const char *mlx5_qp_type_str(int type)
532 case MLX5_QP_ST_RC: return "RC";
533 case MLX5_QP_ST_UC: return "C";
534 case MLX5_QP_ST_UD: return "UD";
535 case MLX5_QP_ST_XRC: return "XRC";
536 case MLX5_QP_ST_MLX: return "MLX";
537 case MLX5_QP_ST_QP0: return "QP0";
538 case MLX5_QP_ST_QP1: return "QP1";
539 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
540 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
541 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
542 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
543 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
544 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
545 default: return "Invalid transport type";
549 static inline const char *mlx5_qp_state_str(int state)
552 case MLX5_QP_STATE_RST:
554 case MLX5_QP_STATE_INIT:
556 case MLX5_QP_STATE_RTR:
558 case MLX5_QP_STATE_RTS:
560 case MLX5_QP_STATE_SQER:
562 case MLX5_QP_STATE_SQD:
564 case MLX5_QP_STATE_ERR:
566 case MLX5_QP_STATE_SQ_DRAINING:
567 return "SQ_DRAINING";
568 case MLX5_QP_STATE_SUSPENDED:
570 default: return "Invalid QP state";
574 static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
576 return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
577 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING :
578 MLX5_TIMESTAMP_FORMAT_DEFAULT;
581 #endif /* MLX5_QP_H */