include/linux/mlx5/mlx5_ifc_fpga.h

   1 /*
   2  * Copyright (c) 2017, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef MLX5_IFC_FPGA_H
  33 #define MLX5_IFC_FPGA_H
  34
  35 struct mlx5_ifc_fpga_shell_caps_bits {
  36         u8         max_num_qps[0x10];
  37         u8         reserved_at_10[0x8];
  38         u8         total_rcv_credits[0x8];
  39
  40         u8         reserved_at_20[0xe];
  41         u8         qp_type[0x2];
  42         u8         reserved_at_30[0x5];
  43         u8         rae[0x1];
  44         u8         rwe[0x1];
  45         u8         rre[0x1];
  46         u8         reserved_at_38[0x4];
  47         u8         dc[0x1];
  48         u8         ud[0x1];
  49         u8         uc[0x1];
  50         u8         rc[0x1];
  51
  52         u8         reserved_at_40[0x1a];
  53         u8         log_ddr_size[0x6];
  54
  55         u8         max_fpga_qp_msg_size[0x20];
  56
  57         u8         reserved_at_80[0x180];
  58 };
  59
  60 struct mlx5_ifc_fpga_cap_bits {
  61         u8         fpga_id[0x8];
  62         u8         fpga_device[0x18];
  63
  64         u8         register_file_ver[0x20];
  65
  66         u8         fpga_ctrl_modify[0x1];
  67         u8         reserved_at_41[0x5];
  68         u8         access_reg_query_mode[0x2];
  69         u8         reserved_at_48[0x6];
  70         u8         access_reg_modify_mode[0x2];
  71         u8         reserved_at_50[0x10];
  72
  73         u8         reserved_at_60[0x20];
  74
  75         u8         image_version[0x20];
  76
  77         u8         image_date[0x20];
  78
  79         u8         image_time[0x20];
  80
  81         u8         shell_version[0x20];
  82
  83         u8         reserved_at_100[0x80];
  84
  85         struct mlx5_ifc_fpga_shell_caps_bits shell_caps;
  86
  87         u8         reserved_at_380[0x8];
  88         u8         ieee_vendor_id[0x18];
  89
  90         u8         sandbox_product_version[0x10];
  91         u8         sandbox_product_id[0x10];
  92
  93         u8         sandbox_basic_caps[0x20];
  94
  95         u8         reserved_at_3e0[0x10];
  96         u8         sandbox_extended_caps_len[0x10];
  97
  98         u8         sandbox_extended_caps_addr[0x40];
  99
 100         u8         fpga_ddr_start_addr[0x40];
 101
 102         u8         fpga_cr_space_start_addr[0x40];
 103
 104         u8         fpga_ddr_size[0x20];
 105
 106         u8         fpga_cr_space_size[0x20];
 107
 108         u8         reserved_at_500[0x300];
 109 };
 110
 111 enum {
 112         MLX5_FPGA_CTRL_OPERATION_LOAD                = 0x1,
 113         MLX5_FPGA_CTRL_OPERATION_RESET               = 0x2,
 114         MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT        = 0x3,
 115         MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON   = 0x4,
 116         MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF  = 0x5,
 117         MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX       = 0x6,
 118 };
 119
 120 struct mlx5_ifc_fpga_ctrl_bits {
 121         u8         reserved_at_0[0x8];
 122         u8         operation[0x8];
 123         u8         reserved_at_10[0x8];
 124         u8         status[0x8];
 125
 126         u8         reserved_at_20[0x8];
 127         u8         flash_select_admin[0x8];
 128         u8         reserved_at_30[0x8];
 129         u8         flash_select_oper[0x8];
 130
 131         u8         reserved_at_40[0x40];
 132 };
 133
 134 enum {
 135         MLX5_FPGA_ERROR_EVENT_SYNDROME_CORRUPTED_DDR        = 0x1,
 136         MLX5_FPGA_ERROR_EVENT_SYNDROME_FLASH_TIMEOUT        = 0x2,
 137         MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR  = 0x3,
 138         MLX5_FPGA_ERROR_EVENT_SYNDROME_WATCHDOG_FAILURE     = 0x4,
 139         MLX5_FPGA_ERROR_EVENT_SYNDROME_I2C_FAILURE          = 0x5,
 140         MLX5_FPGA_ERROR_EVENT_SYNDROME_IMAGE_CHANGED        = 0x6,
 141         MLX5_FPGA_ERROR_EVENT_SYNDROME_TEMPERATURE_CRITICAL = 0x7,
 142 };
 143
 144 struct mlx5_ifc_fpga_error_event_bits {
 145         u8         reserved_at_0[0x40];
 146
 147         u8         reserved_at_40[0x18];
 148         u8         syndrome[0x8];
 149
 150         u8         reserved_at_60[0x80];
 151 };
 152
 153 #define MLX5_FPGA_ACCESS_REG_SIZE_MAX 64
 154
 155 struct mlx5_ifc_fpga_access_reg_bits {
 156         u8         reserved_at_0[0x20];
 157
 158         u8         reserved_at_20[0x10];
 159         u8         size[0x10];
 160
 161         u8         address[0x40];
 162
 163         u8         data[0][0x8];
 164 };
 165
 166 enum mlx5_ifc_fpga_qp_state {
 167         MLX5_FPGA_QPC_STATE_INIT    = 0x0,
 168         MLX5_FPGA_QPC_STATE_ACTIVE  = 0x1,
 169         MLX5_FPGA_QPC_STATE_ERROR   = 0x2,
 170 };
 171
 172 enum mlx5_ifc_fpga_qp_type {
 173         MLX5_FPGA_QPC_QP_TYPE_SHELL_QP    = 0x0,
 174         MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP  = 0x1,
 175 };
 176
 177 enum mlx5_ifc_fpga_qp_service_type {
 178         MLX5_FPGA_QPC_ST_RC  = 0x0,
 179 };
 180
 181 struct mlx5_ifc_fpga_qpc_bits {
 182         u8         state[0x4];
 183         u8         reserved_at_4[0x1b];
 184         u8         qp_type[0x1];
 185
 186         u8         reserved_at_20[0x4];
 187         u8         st[0x4];
 188         u8         reserved_at_28[0x10];
 189         u8         traffic_class[0x8];
 190
 191         u8         ether_type[0x10];
 192         u8         prio[0x3];
 193         u8         dei[0x1];
 194         u8         vid[0xc];
 195
 196         u8         reserved_at_60[0x20];
 197
 198         u8         reserved_at_80[0x8];
 199         u8         next_rcv_psn[0x18];
 200
 201         u8         reserved_at_a0[0x8];
 202         u8         next_send_psn[0x18];
 203
 204         u8         reserved_at_c0[0x10];
 205         u8         pkey[0x10];
 206
 207         u8         reserved_at_e0[0x8];
 208         u8         remote_qpn[0x18];
 209
 210         u8         reserved_at_100[0x15];
 211         u8         rnr_retry[0x3];
 212         u8         reserved_at_118[0x5];
 213         u8         retry_count[0x3];
 214
 215         u8         reserved_at_120[0x20];
 216
 217         u8         reserved_at_140[0x10];
 218         u8         remote_mac_47_32[0x10];
 219
 220         u8         remote_mac_31_0[0x20];
 221
 222         u8         remote_ip[16][0x8];
 223
 224         u8         reserved_at_200[0x40];
 225
 226         u8         reserved_at_240[0x10];
 227         u8         fpga_mac_47_32[0x10];
 228
 229         u8         fpga_mac_31_0[0x20];
 230
 231         u8         fpga_ip[16][0x8];
 232 };
 233
 234 struct mlx5_ifc_fpga_create_qp_in_bits {
 235         u8         opcode[0x10];
 236         u8         reserved_at_10[0x10];
 237
 238         u8         reserved_at_20[0x10];
 239         u8         op_mod[0x10];
 240
 241         u8         reserved_at_40[0x40];
 242
 243         struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
 244 };
 245
 246 struct mlx5_ifc_fpga_create_qp_out_bits {
 247         u8         status[0x8];
 248         u8         reserved_at_8[0x18];
 249
 250         u8         syndrome[0x20];
 251
 252         u8         reserved_at_40[0x8];
 253         u8         fpga_qpn[0x18];
 254
 255         u8         reserved_at_60[0x20];
 256
 257         struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
 258 };
 259
 260 struct mlx5_ifc_fpga_modify_qp_in_bits {
 261         u8         opcode[0x10];
 262         u8         reserved_at_10[0x10];
 263
 264         u8         reserved_at_20[0x10];
 265         u8         op_mod[0x10];
 266
 267         u8         reserved_at_40[0x8];
 268         u8         fpga_qpn[0x18];
 269
 270         u8         field_select[0x20];
 271
 272         struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
 273 };
 274
 275 struct mlx5_ifc_fpga_modify_qp_out_bits {
 276         u8         status[0x8];
 277         u8         reserved_at_8[0x18];
 278
 279         u8         syndrome[0x20];
 280
 281         u8         reserved_at_40[0x40];
 282 };
 283
 284 struct mlx5_ifc_fpga_query_qp_in_bits {
 285         u8         opcode[0x10];
 286         u8         reserved_at_10[0x10];
 287
 288         u8         reserved_at_20[0x10];
 289         u8         op_mod[0x10];
 290
 291         u8         reserved_at_40[0x8];
 292         u8         fpga_qpn[0x18];
 293
 294         u8         reserved_at_60[0x20];
 295 };
 296
 297 struct mlx5_ifc_fpga_query_qp_out_bits {
 298         u8         status[0x8];
 299         u8         reserved_at_8[0x18];
 300
 301         u8         syndrome[0x20];
 302
 303         u8         reserved_at_40[0x40];
 304
 305         struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
 306 };
 307
 308 struct mlx5_ifc_fpga_query_qp_counters_in_bits {
 309         u8         opcode[0x10];
 310         u8         reserved_at_10[0x10];
 311
 312         u8         reserved_at_20[0x10];
 313         u8         op_mod[0x10];
 314
 315         u8         clear[0x1];
 316         u8         reserved_at_41[0x7];
 317         u8         fpga_qpn[0x18];
 318
 319         u8         reserved_at_60[0x20];
 320 };
 321
 322 struct mlx5_ifc_fpga_query_qp_counters_out_bits {
 323         u8         status[0x8];
 324         u8         reserved_at_8[0x18];
 325
 326         u8         syndrome[0x20];
 327
 328         u8         reserved_at_40[0x40];
 329
 330         u8         rx_ack_packets[0x40];
 331
 332         u8         rx_send_packets[0x40];
 333
 334         u8         tx_ack_packets[0x40];
 335
 336         u8         tx_send_packets[0x40];
 337
 338         u8         rx_total_drop[0x40];
 339
 340         u8         reserved_at_1c0[0x1c0];
 341 };
 342
 343 struct mlx5_ifc_fpga_destroy_qp_in_bits {
 344         u8         opcode[0x10];
 345         u8         reserved_at_10[0x10];
 346
 347         u8         reserved_at_20[0x10];
 348         u8         op_mod[0x10];
 349
 350         u8         reserved_at_40[0x8];
 351         u8         fpga_qpn[0x18];
 352
 353         u8         reserved_at_60[0x20];
 354 };
 355
 356 struct mlx5_ifc_fpga_destroy_qp_out_bits {
 357         u8         status[0x8];
 358         u8         reserved_at_8[0x18];
 359
 360         u8         syndrome[0x20];
 361
 362         u8         reserved_at_40[0x40];
 363 };
 364
 365 enum {
 366         MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RETRY_COUNTER_EXPIRED  = 0x1,
 367         MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RNR_EXPIRED            = 0x2,
 368 };
 369
 370 struct mlx5_ifc_fpga_qp_error_event_bits {
 371         u8         reserved_at_0[0x40];
 372
 373         u8         reserved_at_40[0x18];
 374         u8         syndrome[0x8];
 375
 376         u8         reserved_at_60[0x60];
 377
 378         u8         reserved_at_c0[0x8];
 379         u8         fpga_qpn[0x18];
 380 };
 381 #endif /* MLX5_IFC_FPGA_H */