2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
87 MLX5_CMD_OP_CREATE_MKEY = 0x200,
88 MLX5_CMD_OP_QUERY_MKEY = 0x201,
89 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
92 MLX5_CMD_OP_CREATE_EQ = 0x301,
93 MLX5_CMD_OP_DESTROY_EQ = 0x302,
94 MLX5_CMD_OP_QUERY_EQ = 0x303,
95 MLX5_CMD_OP_GEN_EQE = 0x304,
96 MLX5_CMD_OP_CREATE_CQ = 0x400,
97 MLX5_CMD_OP_DESTROY_CQ = 0x401,
98 MLX5_CMD_OP_QUERY_CQ = 0x402,
99 MLX5_CMD_OP_MODIFY_CQ = 0x403,
100 MLX5_CMD_OP_CREATE_QP = 0x500,
101 MLX5_CMD_OP_DESTROY_QP = 0x501,
102 MLX5_CMD_OP_RST2INIT_QP = 0x502,
103 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
104 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
105 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
107 MLX5_CMD_OP_2ERR_QP = 0x507,
108 MLX5_CMD_OP_2RST_QP = 0x50a,
109 MLX5_CMD_OP_QUERY_QP = 0x50b,
110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
112 MLX5_CMD_OP_CREATE_PSV = 0x600,
113 MLX5_CMD_OP_DESTROY_PSV = 0x601,
114 MLX5_CMD_OP_CREATE_SRQ = 0x700,
115 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
116 MLX5_CMD_OP_QUERY_SRQ = 0x702,
117 MLX5_CMD_OP_ARM_RQ = 0x703,
118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
122 MLX5_CMD_OP_CREATE_DCT = 0x710,
123 MLX5_CMD_OP_DESTROY_DCT = 0x711,
124 MLX5_CMD_OP_DRAIN_DCT = 0x712,
125 MLX5_CMD_OP_QUERY_DCT = 0x713,
126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
127 MLX5_CMD_OP_CREATE_XRQ = 0x717,
128 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
129 MLX5_CMD_OP_QUERY_XRQ = 0x719,
130 MLX5_CMD_OP_ARM_XRQ = 0x71a,
131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
155 MLX5_CMD_OP_ALLOC_PD = 0x800,
156 MLX5_CMD_OP_DEALLOC_PD = 0x801,
157 MLX5_CMD_OP_ALLOC_UAR = 0x802,
158 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
160 MLX5_CMD_OP_ACCESS_REG = 0x805,
161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
164 MLX5_CMD_OP_MAD_IFC = 0x50d,
165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
167 MLX5_CMD_OP_NOP = 0x80d,
168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
182 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
184 MLX5_CMD_OP_CREATE_LAG = 0x840,
185 MLX5_CMD_OP_MODIFY_LAG = 0x841,
186 MLX5_CMD_OP_QUERY_LAG = 0x842,
187 MLX5_CMD_OP_DESTROY_LAG = 0x843,
188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
190 MLX5_CMD_OP_CREATE_TIR = 0x900,
191 MLX5_CMD_OP_MODIFY_TIR = 0x901,
192 MLX5_CMD_OP_DESTROY_TIR = 0x902,
193 MLX5_CMD_OP_QUERY_TIR = 0x903,
194 MLX5_CMD_OP_CREATE_SQ = 0x904,
195 MLX5_CMD_OP_MODIFY_SQ = 0x905,
196 MLX5_CMD_OP_DESTROY_SQ = 0x906,
197 MLX5_CMD_OP_QUERY_SQ = 0x907,
198 MLX5_CMD_OP_CREATE_RQ = 0x908,
199 MLX5_CMD_OP_MODIFY_RQ = 0x909,
200 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
201 MLX5_CMD_OP_QUERY_RQ = 0x90b,
202 MLX5_CMD_OP_CREATE_RMP = 0x90c,
203 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
204 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
205 MLX5_CMD_OP_QUERY_RMP = 0x90f,
206 MLX5_CMD_OP_CREATE_TIS = 0x912,
207 MLX5_CMD_OP_MODIFY_TIS = 0x913,
208 MLX5_CMD_OP_DESTROY_TIS = 0x914,
209 MLX5_CMD_OP_QUERY_TIS = 0x915,
210 MLX5_CMD_OP_CREATE_RQT = 0x916,
211 MLX5_CMD_OP_MODIFY_RQT = 0x917,
212 MLX5_CMD_OP_DESTROY_RQT = 0x918,
213 MLX5_CMD_OP_QUERY_RQT = 0x919,
214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
230 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
231 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
235 struct mlx5_ifc_flow_table_fields_supported_bits {
238 u8 outer_ether_type[0x1];
239 u8 outer_ip_version[0x1];
240 u8 outer_first_prio[0x1];
241 u8 outer_first_cfi[0x1];
242 u8 outer_first_vid[0x1];
243 u8 reserved_at_7[0x1];
244 u8 outer_second_prio[0x1];
245 u8 outer_second_cfi[0x1];
246 u8 outer_second_vid[0x1];
247 u8 reserved_at_b[0x1];
251 u8 outer_ip_protocol[0x1];
252 u8 outer_ip_ecn[0x1];
253 u8 outer_ip_dscp[0x1];
254 u8 outer_udp_sport[0x1];
255 u8 outer_udp_dport[0x1];
256 u8 outer_tcp_sport[0x1];
257 u8 outer_tcp_dport[0x1];
258 u8 outer_tcp_flags[0x1];
259 u8 outer_gre_protocol[0x1];
260 u8 outer_gre_key[0x1];
261 u8 outer_vxlan_vni[0x1];
262 u8 reserved_at_1a[0x5];
263 u8 source_eswitch_port[0x1];
267 u8 inner_ether_type[0x1];
268 u8 inner_ip_version[0x1];
269 u8 inner_first_prio[0x1];
270 u8 inner_first_cfi[0x1];
271 u8 inner_first_vid[0x1];
272 u8 reserved_at_27[0x1];
273 u8 inner_second_prio[0x1];
274 u8 inner_second_cfi[0x1];
275 u8 inner_second_vid[0x1];
276 u8 reserved_at_2b[0x1];
280 u8 inner_ip_protocol[0x1];
281 u8 inner_ip_ecn[0x1];
282 u8 inner_ip_dscp[0x1];
283 u8 inner_udp_sport[0x1];
284 u8 inner_udp_dport[0x1];
285 u8 inner_tcp_sport[0x1];
286 u8 inner_tcp_dport[0x1];
287 u8 inner_tcp_flags[0x1];
288 u8 reserved_at_37[0x9];
290 u8 reserved_at_40[0x40];
293 struct mlx5_ifc_flow_table_prop_layout_bits {
295 u8 reserved_at_1[0x1];
296 u8 flow_counter[0x1];
297 u8 flow_modify_en[0x1];
299 u8 identified_miss_table_mode[0x1];
300 u8 flow_table_modify[0x1];
303 u8 reserved_at_9[0x17];
305 u8 reserved_at_20[0x2];
306 u8 log_max_ft_size[0x6];
307 u8 log_max_modify_header_context[0x8];
308 u8 max_modify_header_actions[0x8];
309 u8 max_ft_level[0x8];
311 u8 reserved_at_40[0x20];
313 u8 reserved_at_60[0x18];
314 u8 log_max_ft_num[0x8];
316 u8 reserved_at_80[0x18];
317 u8 log_max_destination[0x8];
319 u8 reserved_at_a0[0x18];
320 u8 log_max_flow[0x8];
322 u8 reserved_at_c0[0x40];
324 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
326 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
329 struct mlx5_ifc_odp_per_transport_service_cap_bits {
336 u8 reserved_at_6[0x1a];
339 struct mlx5_ifc_ipv4_layout_bits {
340 u8 reserved_at_0[0x60];
345 struct mlx5_ifc_ipv6_layout_bits {
349 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
350 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
351 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
352 u8 reserved_at_0[0x80];
355 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
380 u8 reserved_at_c0[0x20];
385 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
387 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
390 struct mlx5_ifc_fte_match_set_misc_bits {
391 u8 reserved_at_0[0x8];
394 u8 reserved_at_20[0x10];
395 u8 source_port[0x10];
397 u8 outer_second_prio[0x3];
398 u8 outer_second_cfi[0x1];
399 u8 outer_second_vid[0xc];
400 u8 inner_second_prio[0x3];
401 u8 inner_second_cfi[0x1];
402 u8 inner_second_vid[0xc];
404 u8 outer_second_cvlan_tag[0x1];
405 u8 inner_second_cvlan_tag[0x1];
406 u8 outer_second_svlan_tag[0x1];
407 u8 inner_second_svlan_tag[0x1];
408 u8 reserved_at_64[0xc];
409 u8 gre_protocol[0x10];
415 u8 reserved_at_b8[0x8];
417 u8 reserved_at_c0[0x20];
419 u8 reserved_at_e0[0xc];
420 u8 outer_ipv6_flow_label[0x14];
422 u8 reserved_at_100[0xc];
423 u8 inner_ipv6_flow_label[0x14];
425 u8 reserved_at_120[0xe0];
428 struct mlx5_ifc_cmd_pas_bits {
432 u8 reserved_at_34[0xc];
435 struct mlx5_ifc_uint64_bits {
442 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
443 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
444 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
445 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
446 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
447 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
448 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
449 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
450 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
451 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
454 struct mlx5_ifc_ads_bits {
457 u8 reserved_at_2[0xe];
460 u8 reserved_at_20[0x8];
466 u8 reserved_at_45[0x3];
467 u8 src_addr_index[0x8];
468 u8 reserved_at_50[0x4];
472 u8 reserved_at_60[0x4];
476 u8 rgid_rip[16][0x8];
478 u8 reserved_at_100[0x4];
481 u8 reserved_at_106[0x1];
496 struct mlx5_ifc_flow_table_nic_cap_bits {
497 u8 nic_rx_multi_path_tirs[0x1];
498 u8 nic_rx_multi_path_tirs_fts[0x1];
499 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
500 u8 reserved_at_3[0x1fd];
502 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
504 u8 reserved_at_400[0x200];
506 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
508 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
510 u8 reserved_at_a00[0x200];
512 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
514 u8 reserved_at_e00[0x7200];
517 struct mlx5_ifc_flow_table_eswitch_cap_bits {
518 u8 reserved_at_0[0x200];
520 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
522 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
524 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
526 u8 reserved_at_800[0x7800];
529 struct mlx5_ifc_e_switch_cap_bits {
530 u8 vport_svlan_strip[0x1];
531 u8 vport_cvlan_strip[0x1];
532 u8 vport_svlan_insert[0x1];
533 u8 vport_cvlan_insert_if_not_exist[0x1];
534 u8 vport_cvlan_insert_overwrite[0x1];
535 u8 reserved_at_5[0x19];
536 u8 nic_vport_node_guid_modify[0x1];
537 u8 nic_vport_port_guid_modify[0x1];
539 u8 vxlan_encap_decap[0x1];
540 u8 nvgre_encap_decap[0x1];
541 u8 reserved_at_22[0x9];
542 u8 log_max_encap_headers[0x5];
544 u8 max_encap_header_size[0xa];
546 u8 reserved_40[0x7c0];
550 struct mlx5_ifc_qos_cap_bits {
551 u8 packet_pacing[0x1];
552 u8 esw_scheduling[0x1];
553 u8 esw_bw_share[0x1];
554 u8 esw_rate_limit[0x1];
555 u8 reserved_at_4[0x1c];
557 u8 reserved_at_20[0x20];
559 u8 packet_pacing_max_rate[0x20];
561 u8 packet_pacing_min_rate[0x20];
563 u8 reserved_at_80[0x10];
564 u8 packet_pacing_rate_table_size[0x10];
566 u8 esw_element_type[0x10];
567 u8 esw_tsar_type[0x10];
569 u8 reserved_at_c0[0x10];
570 u8 max_qos_para_vport[0x10];
572 u8 max_tsar_bw_share[0x20];
574 u8 reserved_at_100[0x700];
577 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
581 u8 lro_psh_flag[0x1];
582 u8 lro_time_stamp[0x1];
583 u8 reserved_at_5[0x2];
584 u8 wqe_vlan_insert[0x1];
585 u8 self_lb_en_modifiable[0x1];
586 u8 reserved_at_9[0x2];
588 u8 multi_pkt_send_wqe[0x2];
589 u8 wqe_inline_mode[0x2];
590 u8 rss_ind_tbl_cap[0x4];
593 u8 reserved_at_1a[0x1];
594 u8 tunnel_lso_const_out_ip_id[0x1];
595 u8 reserved_at_1c[0x2];
596 u8 tunnel_statless_gre[0x1];
597 u8 tunnel_stateless_vxlan[0x1];
599 u8 reserved_at_20[0x20];
601 u8 reserved_at_40[0x10];
602 u8 lro_min_mss_size[0x10];
604 u8 reserved_at_60[0x120];
606 u8 lro_timer_supported_periods[4][0x20];
608 u8 reserved_at_200[0x600];
611 struct mlx5_ifc_roce_cap_bits {
613 u8 reserved_at_1[0x1f];
615 u8 reserved_at_20[0x60];
617 u8 reserved_at_80[0xc];
619 u8 reserved_at_90[0x8];
620 u8 roce_version[0x8];
622 u8 reserved_at_a0[0x10];
623 u8 r_roce_dest_udp_port[0x10];
625 u8 r_roce_max_src_udp_port[0x10];
626 u8 r_roce_min_src_udp_port[0x10];
628 u8 reserved_at_e0[0x10];
629 u8 roce_address_table_size[0x10];
631 u8 reserved_at_100[0x700];
635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
636 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
637 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
638 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
648 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
649 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
650 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
651 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
652 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
653 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
654 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
658 struct mlx5_ifc_atomic_caps_bits {
659 u8 reserved_at_0[0x40];
661 u8 atomic_req_8B_endianess_mode[0x2];
662 u8 reserved_at_42[0x4];
663 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
665 u8 reserved_at_47[0x19];
667 u8 reserved_at_60[0x20];
669 u8 reserved_at_80[0x10];
670 u8 atomic_operations[0x10];
672 u8 reserved_at_a0[0x10];
673 u8 atomic_size_qp[0x10];
675 u8 reserved_at_c0[0x10];
676 u8 atomic_size_dc[0x10];
678 u8 reserved_at_e0[0x720];
681 struct mlx5_ifc_odp_cap_bits {
682 u8 reserved_at_0[0x40];
685 u8 reserved_at_41[0x1f];
687 u8 reserved_at_60[0x20];
689 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
691 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
693 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
695 u8 reserved_at_e0[0x720];
698 struct mlx5_ifc_calc_op {
699 u8 reserved_at_0[0x10];
700 u8 reserved_at_10[0x9];
701 u8 op_swap_endianness[0x1];
710 struct mlx5_ifc_vector_calc_cap_bits {
712 u8 reserved_at_1[0x1f];
713 u8 reserved_at_20[0x8];
714 u8 max_vec_count[0x8];
715 u8 reserved_at_30[0xd];
716 u8 max_chunk_size[0x3];
717 struct mlx5_ifc_calc_op calc0;
718 struct mlx5_ifc_calc_op calc1;
719 struct mlx5_ifc_calc_op calc2;
720 struct mlx5_ifc_calc_op calc3;
722 u8 reserved_at_e0[0x720];
726 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
727 MLX5_WQ_TYPE_CYCLIC = 0x1,
728 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
732 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
733 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
737 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
738 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
739 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
740 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
741 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
745 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
746 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
747 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
748 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
749 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
750 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
754 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
755 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
759 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
760 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
761 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
765 MLX5_CAP_PORT_TYPE_IB = 0x0,
766 MLX5_CAP_PORT_TYPE_ETH = 0x1,
770 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
771 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
772 MLX5_CAP_UMR_FENCE_NONE = 0x2,
775 struct mlx5_ifc_cmd_hca_cap_bits {
776 u8 reserved_at_0[0x80];
778 u8 log_max_srq_sz[0x8];
779 u8 log_max_qp_sz[0x8];
780 u8 reserved_at_90[0xb];
783 u8 reserved_at_a0[0xb];
785 u8 reserved_at_b0[0x10];
787 u8 reserved_at_c0[0x8];
788 u8 log_max_cq_sz[0x8];
789 u8 reserved_at_d0[0xb];
792 u8 log_max_eq_sz[0x8];
793 u8 reserved_at_e8[0x2];
794 u8 log_max_mkey[0x6];
795 u8 reserved_at_f0[0xc];
798 u8 max_indirection[0x8];
799 u8 fixed_buffer_size[0x1];
800 u8 log_max_mrw_sz[0x7];
801 u8 reserved_at_110[0x2];
802 u8 log_max_bsf_list_size[0x6];
803 u8 umr_extended_translation_offset[0x1];
805 u8 log_max_klm_list_size[0x6];
807 u8 reserved_at_120[0xa];
808 u8 log_max_ra_req_dc[0x6];
809 u8 reserved_at_130[0xa];
810 u8 log_max_ra_res_dc[0x6];
812 u8 reserved_at_140[0xa];
813 u8 log_max_ra_req_qp[0x6];
814 u8 reserved_at_150[0xa];
815 u8 log_max_ra_res_qp[0x6];
818 u8 cc_query_allowed[0x1];
819 u8 cc_modify_allowed[0x1];
821 u8 cache_line_128byte[0x1];
822 u8 reserved_at_163[0xb];
823 u8 gid_table_size[0x10];
825 u8 out_of_seq_cnt[0x1];
826 u8 vport_counters[0x1];
827 u8 retransmission_q_counters[0x1];
828 u8 reserved_at_183[0x1];
829 u8 modify_rq_counter_set_id[0x1];
830 u8 reserved_at_185[0x1];
832 u8 pkey_table_size[0x10];
834 u8 vport_group_manager[0x1];
835 u8 vhca_group_manager[0x1];
838 u8 reserved_at_1a4[0x1];
840 u8 nic_flow_table[0x1];
841 u8 eswitch_flow_table[0x1];
842 u8 early_vf_enable[0x1];
845 u8 local_ca_ack_delay[0x5];
846 u8 port_module_event[0x1];
847 u8 reserved_at_1b1[0x1];
849 u8 reserved_at_1b3[0x1];
850 u8 disable_link_up[0x1];
855 u8 reserved_at_1c0[0x1];
859 u8 reserved_at_1c8[0x4];
861 u8 reserved_at_1d0[0x1];
863 u8 reserved_at_1d2[0x4];
866 u8 reserved_at_1d8[0x1];
875 u8 stat_rate_support[0x10];
876 u8 reserved_at_1f0[0xc];
879 u8 compact_address_vector[0x1];
881 u8 reserved_at_202[0x1];
882 u8 ipoib_enhanced_offloads[0x1];
883 u8 ipoib_basic_offloads[0x1];
884 u8 reserved_at_205[0x5];
886 u8 reserved_at_20c[0x3];
887 u8 drain_sigerr[0x1];
888 u8 cmdif_checksum[0x2];
890 u8 reserved_at_213[0x1];
891 u8 wq_signature[0x1];
892 u8 sctr_data_cqe[0x1];
893 u8 reserved_at_216[0x1];
899 u8 eth_net_offloads[0x1];
902 u8 reserved_at_21f[0x1];
906 u8 cq_moderation[0x1];
907 u8 reserved_at_223[0x3];
911 u8 reserved_at_229[0x1];
912 u8 scqe_break_moderation[0x1];
913 u8 cq_period_start_from_cqe[0x1];
915 u8 reserved_at_22d[0x1];
918 u8 umr_ptr_rlky[0x1];
920 u8 reserved_at_232[0x4];
923 u8 set_deth_sqpn[0x1];
924 u8 reserved_at_239[0x3];
931 u8 reserved_at_241[0x9];
933 u8 reserved_at_250[0x8];
937 u8 driver_version[0x1];
938 u8 pad_tx_eth_packet[0x1];
939 u8 reserved_at_263[0x8];
940 u8 log_bf_reg_size[0x5];
942 u8 reserved_at_270[0xb];
944 u8 num_lag_ports[0x4];
946 u8 reserved_at_280[0x10];
947 u8 max_wqe_sz_sq[0x10];
949 u8 reserved_at_2a0[0x10];
950 u8 max_wqe_sz_rq[0x10];
952 u8 reserved_at_2c0[0x10];
953 u8 max_wqe_sz_sq_dc[0x10];
955 u8 reserved_at_2e0[0x7];
958 u8 reserved_at_300[0x18];
961 u8 reserved_at_320[0x3];
962 u8 log_max_transport_domain[0x5];
963 u8 reserved_at_328[0x3];
965 u8 reserved_at_330[0xb];
966 u8 log_max_xrcd[0x5];
968 u8 reserved_at_340[0x8];
969 u8 log_max_flow_counter_bulk[0x8];
970 u8 max_flow_counter[0x10];
973 u8 reserved_at_360[0x3];
975 u8 reserved_at_368[0x3];
977 u8 reserved_at_370[0x3];
979 u8 reserved_at_378[0x3];
982 u8 basic_cyclic_rcv_wqe[0x1];
983 u8 reserved_at_381[0x2];
985 u8 reserved_at_388[0x3];
987 u8 reserved_at_390[0x3];
988 u8 log_max_rqt_size[0x5];
989 u8 reserved_at_398[0x3];
990 u8 log_max_tis_per_sq[0x5];
992 u8 reserved_at_3a0[0x3];
993 u8 log_max_stride_sz_rq[0x5];
994 u8 reserved_at_3a8[0x3];
995 u8 log_min_stride_sz_rq[0x5];
996 u8 reserved_at_3b0[0x3];
997 u8 log_max_stride_sz_sq[0x5];
998 u8 reserved_at_3b8[0x3];
999 u8 log_min_stride_sz_sq[0x5];
1001 u8 reserved_at_3c0[0x1b];
1002 u8 log_max_wq_sz[0x5];
1004 u8 nic_vport_change_event[0x1];
1005 u8 reserved_at_3e1[0xa];
1006 u8 log_max_vlan_list[0x5];
1007 u8 reserved_at_3f0[0x3];
1008 u8 log_max_current_mc_list[0x5];
1009 u8 reserved_at_3f8[0x3];
1010 u8 log_max_current_uc_list[0x5];
1012 u8 reserved_at_400[0x80];
1014 u8 reserved_at_480[0x3];
1015 u8 log_max_l2_table[0x5];
1016 u8 reserved_at_488[0x8];
1017 u8 log_uar_page_sz[0x10];
1019 u8 reserved_at_4a0[0x20];
1020 u8 device_frequency_mhz[0x20];
1021 u8 device_frequency_khz[0x20];
1023 u8 reserved_at_500[0x20];
1024 u8 num_of_uars_per_page[0x20];
1025 u8 reserved_at_540[0x40];
1027 u8 reserved_at_580[0x3f];
1028 u8 cqe_compression[0x1];
1030 u8 cqe_compression_timeout[0x10];
1031 u8 cqe_compression_max_num[0x10];
1033 u8 reserved_at_5e0[0x10];
1034 u8 tag_matching[0x1];
1035 u8 rndv_offload_rc[0x1];
1036 u8 rndv_offload_dc[0x1];
1037 u8 log_tag_matching_list_sz[0x5];
1038 u8 reserved_at_5f8[0x3];
1039 u8 log_max_xrq[0x5];
1041 u8 reserved_at_600[0x200];
1044 enum mlx5_flow_destination_type {
1045 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1046 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1047 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1049 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1052 struct mlx5_ifc_dest_format_struct_bits {
1053 u8 destination_type[0x8];
1054 u8 destination_id[0x18];
1056 u8 reserved_at_20[0x20];
1059 struct mlx5_ifc_flow_counter_list_bits {
1061 u8 num_of_counters[0xf];
1062 u8 flow_counter_id[0x10];
1064 u8 reserved_at_20[0x20];
1067 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1068 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1069 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1070 u8 reserved_at_0[0x40];
1073 struct mlx5_ifc_fte_match_param_bits {
1074 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1076 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1078 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1080 u8 reserved_at_600[0xa00];
1084 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1085 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1086 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1087 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1088 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1091 struct mlx5_ifc_rx_hash_field_select_bits {
1092 u8 l3_prot_type[0x1];
1093 u8 l4_prot_type[0x1];
1094 u8 selected_fields[0x1e];
1098 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1099 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1103 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1104 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1107 struct mlx5_ifc_wq_bits {
1109 u8 wq_signature[0x1];
1110 u8 end_padding_mode[0x2];
1112 u8 reserved_at_8[0x18];
1114 u8 hds_skip_first_sge[0x1];
1115 u8 log2_hds_buf_size[0x3];
1116 u8 reserved_at_24[0x7];
1117 u8 page_offset[0x5];
1120 u8 reserved_at_40[0x8];
1123 u8 reserved_at_60[0x8];
1128 u8 hw_counter[0x20];
1130 u8 sw_counter[0x20];
1132 u8 reserved_at_100[0xc];
1133 u8 log_wq_stride[0x4];
1134 u8 reserved_at_110[0x3];
1135 u8 log_wq_pg_sz[0x5];
1136 u8 reserved_at_118[0x3];
1139 u8 reserved_at_120[0x15];
1140 u8 log_wqe_num_of_strides[0x3];
1141 u8 two_byte_shift_en[0x1];
1142 u8 reserved_at_139[0x4];
1143 u8 log_wqe_stride_size[0x3];
1145 u8 reserved_at_140[0x4c0];
1147 struct mlx5_ifc_cmd_pas_bits pas[0];
1150 struct mlx5_ifc_rq_num_bits {
1151 u8 reserved_at_0[0x8];
1155 struct mlx5_ifc_mac_address_layout_bits {
1156 u8 reserved_at_0[0x10];
1157 u8 mac_addr_47_32[0x10];
1159 u8 mac_addr_31_0[0x20];
1162 struct mlx5_ifc_vlan_layout_bits {
1163 u8 reserved_at_0[0x14];
1166 u8 reserved_at_20[0x20];
1169 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1170 u8 reserved_at_0[0xa0];
1172 u8 min_time_between_cnps[0x20];
1174 u8 reserved_at_c0[0x12];
1176 u8 reserved_at_d8[0x5];
1177 u8 cnp_802p_prio[0x3];
1179 u8 reserved_at_e0[0x720];
1182 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1183 u8 reserved_at_0[0x60];
1185 u8 reserved_at_60[0x4];
1186 u8 clamp_tgt_rate[0x1];
1187 u8 reserved_at_65[0x3];
1188 u8 clamp_tgt_rate_after_time_inc[0x1];
1189 u8 reserved_at_69[0x17];
1191 u8 reserved_at_80[0x20];
1193 u8 rpg_time_reset[0x20];
1195 u8 rpg_byte_reset[0x20];
1197 u8 rpg_threshold[0x20];
1199 u8 rpg_max_rate[0x20];
1201 u8 rpg_ai_rate[0x20];
1203 u8 rpg_hai_rate[0x20];
1207 u8 rpg_min_dec_fac[0x20];
1209 u8 rpg_min_rate[0x20];
1211 u8 reserved_at_1c0[0xe0];
1213 u8 rate_to_set_on_first_cnp[0x20];
1217 u8 dce_tcp_rtt[0x20];
1219 u8 rate_reduce_monitor_period[0x20];
1221 u8 reserved_at_320[0x20];
1223 u8 initial_alpha_value[0x20];
1225 u8 reserved_at_360[0x4a0];
1228 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1229 u8 reserved_at_0[0x80];
1231 u8 rppp_max_rps[0x20];
1233 u8 rpg_time_reset[0x20];
1235 u8 rpg_byte_reset[0x20];
1237 u8 rpg_threshold[0x20];
1239 u8 rpg_max_rate[0x20];
1241 u8 rpg_ai_rate[0x20];
1243 u8 rpg_hai_rate[0x20];
1247 u8 rpg_min_dec_fac[0x20];
1249 u8 rpg_min_rate[0x20];
1251 u8 reserved_at_1c0[0x640];
1255 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1256 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1257 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1260 struct mlx5_ifc_resize_field_select_bits {
1261 u8 resize_field_select[0x20];
1265 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1266 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1267 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1268 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1271 struct mlx5_ifc_modify_field_select_bits {
1272 u8 modify_field_select[0x20];
1275 struct mlx5_ifc_field_select_r_roce_np_bits {
1276 u8 field_select_r_roce_np[0x20];
1279 struct mlx5_ifc_field_select_r_roce_rp_bits {
1280 u8 field_select_r_roce_rp[0x20];
1284 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1285 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1286 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1287 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1288 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1289 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1290 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1291 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1292 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1293 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1296 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1297 u8 field_select_8021qaurp[0x20];
1300 struct mlx5_ifc_phys_layer_cntrs_bits {
1301 u8 time_since_last_clear_high[0x20];
1303 u8 time_since_last_clear_low[0x20];
1305 u8 symbol_errors_high[0x20];
1307 u8 symbol_errors_low[0x20];
1309 u8 sync_headers_errors_high[0x20];
1311 u8 sync_headers_errors_low[0x20];
1313 u8 edpl_bip_errors_lane0_high[0x20];
1315 u8 edpl_bip_errors_lane0_low[0x20];
1317 u8 edpl_bip_errors_lane1_high[0x20];
1319 u8 edpl_bip_errors_lane1_low[0x20];
1321 u8 edpl_bip_errors_lane2_high[0x20];
1323 u8 edpl_bip_errors_lane2_low[0x20];
1325 u8 edpl_bip_errors_lane3_high[0x20];
1327 u8 edpl_bip_errors_lane3_low[0x20];
1329 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1331 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1333 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1335 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1337 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1339 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1341 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1343 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1345 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1347 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1349 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1351 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1353 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1355 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1357 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1359 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1361 u8 rs_fec_corrected_blocks_high[0x20];
1363 u8 rs_fec_corrected_blocks_low[0x20];
1365 u8 rs_fec_uncorrectable_blocks_high[0x20];
1367 u8 rs_fec_uncorrectable_blocks_low[0x20];
1369 u8 rs_fec_no_errors_blocks_high[0x20];
1371 u8 rs_fec_no_errors_blocks_low[0x20];
1373 u8 rs_fec_single_error_blocks_high[0x20];
1375 u8 rs_fec_single_error_blocks_low[0x20];
1377 u8 rs_fec_corrected_symbols_total_high[0x20];
1379 u8 rs_fec_corrected_symbols_total_low[0x20];
1381 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1383 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1385 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1387 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1389 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1391 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1393 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1395 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1397 u8 link_down_events[0x20];
1399 u8 successful_recovery_events[0x20];
1401 u8 reserved_at_640[0x180];
1404 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1405 u8 time_since_last_clear_high[0x20];
1407 u8 time_since_last_clear_low[0x20];
1409 u8 phy_received_bits_high[0x20];
1411 u8 phy_received_bits_low[0x20];
1413 u8 phy_symbol_errors_high[0x20];
1415 u8 phy_symbol_errors_low[0x20];
1417 u8 phy_corrected_bits_high[0x20];
1419 u8 phy_corrected_bits_low[0x20];
1421 u8 phy_corrected_bits_lane0_high[0x20];
1423 u8 phy_corrected_bits_lane0_low[0x20];
1425 u8 phy_corrected_bits_lane1_high[0x20];
1427 u8 phy_corrected_bits_lane1_low[0x20];
1429 u8 phy_corrected_bits_lane2_high[0x20];
1431 u8 phy_corrected_bits_lane2_low[0x20];
1433 u8 phy_corrected_bits_lane3_high[0x20];
1435 u8 phy_corrected_bits_lane3_low[0x20];
1437 u8 reserved_at_200[0x5c0];
1440 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1441 u8 symbol_error_counter[0x10];
1443 u8 link_error_recovery_counter[0x8];
1445 u8 link_downed_counter[0x8];
1447 u8 port_rcv_errors[0x10];
1449 u8 port_rcv_remote_physical_errors[0x10];
1451 u8 port_rcv_switch_relay_errors[0x10];
1453 u8 port_xmit_discards[0x10];
1455 u8 port_xmit_constraint_errors[0x8];
1457 u8 port_rcv_constraint_errors[0x8];
1459 u8 reserved_at_70[0x8];
1461 u8 link_overrun_errors[0x8];
1463 u8 reserved_at_80[0x10];
1465 u8 vl_15_dropped[0x10];
1467 u8 reserved_at_a0[0x80];
1469 u8 port_xmit_wait[0x20];
1472 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1473 u8 transmit_queue_high[0x20];
1475 u8 transmit_queue_low[0x20];
1477 u8 reserved_at_40[0x780];
1480 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1481 u8 rx_octets_high[0x20];
1483 u8 rx_octets_low[0x20];
1485 u8 reserved_at_40[0xc0];
1487 u8 rx_frames_high[0x20];
1489 u8 rx_frames_low[0x20];
1491 u8 tx_octets_high[0x20];
1493 u8 tx_octets_low[0x20];
1495 u8 reserved_at_180[0xc0];
1497 u8 tx_frames_high[0x20];
1499 u8 tx_frames_low[0x20];
1501 u8 rx_pause_high[0x20];
1503 u8 rx_pause_low[0x20];
1505 u8 rx_pause_duration_high[0x20];
1507 u8 rx_pause_duration_low[0x20];
1509 u8 tx_pause_high[0x20];
1511 u8 tx_pause_low[0x20];
1513 u8 tx_pause_duration_high[0x20];
1515 u8 tx_pause_duration_low[0x20];
1517 u8 rx_pause_transition_high[0x20];
1519 u8 rx_pause_transition_low[0x20];
1521 u8 reserved_at_3c0[0x400];
1524 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1525 u8 port_transmit_wait_high[0x20];
1527 u8 port_transmit_wait_low[0x20];
1529 u8 reserved_at_40[0x780];
1532 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1533 u8 dot3stats_alignment_errors_high[0x20];
1535 u8 dot3stats_alignment_errors_low[0x20];
1537 u8 dot3stats_fcs_errors_high[0x20];
1539 u8 dot3stats_fcs_errors_low[0x20];
1541 u8 dot3stats_single_collision_frames_high[0x20];
1543 u8 dot3stats_single_collision_frames_low[0x20];
1545 u8 dot3stats_multiple_collision_frames_high[0x20];
1547 u8 dot3stats_multiple_collision_frames_low[0x20];
1549 u8 dot3stats_sqe_test_errors_high[0x20];
1551 u8 dot3stats_sqe_test_errors_low[0x20];
1553 u8 dot3stats_deferred_transmissions_high[0x20];
1555 u8 dot3stats_deferred_transmissions_low[0x20];
1557 u8 dot3stats_late_collisions_high[0x20];
1559 u8 dot3stats_late_collisions_low[0x20];
1561 u8 dot3stats_excessive_collisions_high[0x20];
1563 u8 dot3stats_excessive_collisions_low[0x20];
1565 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1567 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1569 u8 dot3stats_carrier_sense_errors_high[0x20];
1571 u8 dot3stats_carrier_sense_errors_low[0x20];
1573 u8 dot3stats_frame_too_longs_high[0x20];
1575 u8 dot3stats_frame_too_longs_low[0x20];
1577 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1579 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1581 u8 dot3stats_symbol_errors_high[0x20];
1583 u8 dot3stats_symbol_errors_low[0x20];
1585 u8 dot3control_in_unknown_opcodes_high[0x20];
1587 u8 dot3control_in_unknown_opcodes_low[0x20];
1589 u8 dot3in_pause_frames_high[0x20];
1591 u8 dot3in_pause_frames_low[0x20];
1593 u8 dot3out_pause_frames_high[0x20];
1595 u8 dot3out_pause_frames_low[0x20];
1597 u8 reserved_at_400[0x3c0];
1600 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1601 u8 ether_stats_drop_events_high[0x20];
1603 u8 ether_stats_drop_events_low[0x20];
1605 u8 ether_stats_octets_high[0x20];
1607 u8 ether_stats_octets_low[0x20];
1609 u8 ether_stats_pkts_high[0x20];
1611 u8 ether_stats_pkts_low[0x20];
1613 u8 ether_stats_broadcast_pkts_high[0x20];
1615 u8 ether_stats_broadcast_pkts_low[0x20];
1617 u8 ether_stats_multicast_pkts_high[0x20];
1619 u8 ether_stats_multicast_pkts_low[0x20];
1621 u8 ether_stats_crc_align_errors_high[0x20];
1623 u8 ether_stats_crc_align_errors_low[0x20];
1625 u8 ether_stats_undersize_pkts_high[0x20];
1627 u8 ether_stats_undersize_pkts_low[0x20];
1629 u8 ether_stats_oversize_pkts_high[0x20];
1631 u8 ether_stats_oversize_pkts_low[0x20];
1633 u8 ether_stats_fragments_high[0x20];
1635 u8 ether_stats_fragments_low[0x20];
1637 u8 ether_stats_jabbers_high[0x20];
1639 u8 ether_stats_jabbers_low[0x20];
1641 u8 ether_stats_collisions_high[0x20];
1643 u8 ether_stats_collisions_low[0x20];
1645 u8 ether_stats_pkts64octets_high[0x20];
1647 u8 ether_stats_pkts64octets_low[0x20];
1649 u8 ether_stats_pkts65to127octets_high[0x20];
1651 u8 ether_stats_pkts65to127octets_low[0x20];
1653 u8 ether_stats_pkts128to255octets_high[0x20];
1655 u8 ether_stats_pkts128to255octets_low[0x20];
1657 u8 ether_stats_pkts256to511octets_high[0x20];
1659 u8 ether_stats_pkts256to511octets_low[0x20];
1661 u8 ether_stats_pkts512to1023octets_high[0x20];
1663 u8 ether_stats_pkts512to1023octets_low[0x20];
1665 u8 ether_stats_pkts1024to1518octets_high[0x20];
1667 u8 ether_stats_pkts1024to1518octets_low[0x20];
1669 u8 ether_stats_pkts1519to2047octets_high[0x20];
1671 u8 ether_stats_pkts1519to2047octets_low[0x20];
1673 u8 ether_stats_pkts2048to4095octets_high[0x20];
1675 u8 ether_stats_pkts2048to4095octets_low[0x20];
1677 u8 ether_stats_pkts4096to8191octets_high[0x20];
1679 u8 ether_stats_pkts4096to8191octets_low[0x20];
1681 u8 ether_stats_pkts8192to10239octets_high[0x20];
1683 u8 ether_stats_pkts8192to10239octets_low[0x20];
1685 u8 reserved_at_540[0x280];
1688 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1689 u8 if_in_octets_high[0x20];
1691 u8 if_in_octets_low[0x20];
1693 u8 if_in_ucast_pkts_high[0x20];
1695 u8 if_in_ucast_pkts_low[0x20];
1697 u8 if_in_discards_high[0x20];
1699 u8 if_in_discards_low[0x20];
1701 u8 if_in_errors_high[0x20];
1703 u8 if_in_errors_low[0x20];
1705 u8 if_in_unknown_protos_high[0x20];
1707 u8 if_in_unknown_protos_low[0x20];
1709 u8 if_out_octets_high[0x20];
1711 u8 if_out_octets_low[0x20];
1713 u8 if_out_ucast_pkts_high[0x20];
1715 u8 if_out_ucast_pkts_low[0x20];
1717 u8 if_out_discards_high[0x20];
1719 u8 if_out_discards_low[0x20];
1721 u8 if_out_errors_high[0x20];
1723 u8 if_out_errors_low[0x20];
1725 u8 if_in_multicast_pkts_high[0x20];
1727 u8 if_in_multicast_pkts_low[0x20];
1729 u8 if_in_broadcast_pkts_high[0x20];
1731 u8 if_in_broadcast_pkts_low[0x20];
1733 u8 if_out_multicast_pkts_high[0x20];
1735 u8 if_out_multicast_pkts_low[0x20];
1737 u8 if_out_broadcast_pkts_high[0x20];
1739 u8 if_out_broadcast_pkts_low[0x20];
1741 u8 reserved_at_340[0x480];
1744 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1745 u8 a_frames_transmitted_ok_high[0x20];
1747 u8 a_frames_transmitted_ok_low[0x20];
1749 u8 a_frames_received_ok_high[0x20];
1751 u8 a_frames_received_ok_low[0x20];
1753 u8 a_frame_check_sequence_errors_high[0x20];
1755 u8 a_frame_check_sequence_errors_low[0x20];
1757 u8 a_alignment_errors_high[0x20];
1759 u8 a_alignment_errors_low[0x20];
1761 u8 a_octets_transmitted_ok_high[0x20];
1763 u8 a_octets_transmitted_ok_low[0x20];
1765 u8 a_octets_received_ok_high[0x20];
1767 u8 a_octets_received_ok_low[0x20];
1769 u8 a_multicast_frames_xmitted_ok_high[0x20];
1771 u8 a_multicast_frames_xmitted_ok_low[0x20];
1773 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1775 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1777 u8 a_multicast_frames_received_ok_high[0x20];
1779 u8 a_multicast_frames_received_ok_low[0x20];
1781 u8 a_broadcast_frames_received_ok_high[0x20];
1783 u8 a_broadcast_frames_received_ok_low[0x20];
1785 u8 a_in_range_length_errors_high[0x20];
1787 u8 a_in_range_length_errors_low[0x20];
1789 u8 a_out_of_range_length_field_high[0x20];
1791 u8 a_out_of_range_length_field_low[0x20];
1793 u8 a_frame_too_long_errors_high[0x20];
1795 u8 a_frame_too_long_errors_low[0x20];
1797 u8 a_symbol_error_during_carrier_high[0x20];
1799 u8 a_symbol_error_during_carrier_low[0x20];
1801 u8 a_mac_control_frames_transmitted_high[0x20];
1803 u8 a_mac_control_frames_transmitted_low[0x20];
1805 u8 a_mac_control_frames_received_high[0x20];
1807 u8 a_mac_control_frames_received_low[0x20];
1809 u8 a_unsupported_opcodes_received_high[0x20];
1811 u8 a_unsupported_opcodes_received_low[0x20];
1813 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1815 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1817 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1819 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1821 u8 reserved_at_4c0[0x300];
1824 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1825 u8 life_time_counter_high[0x20];
1827 u8 life_time_counter_low[0x20];
1833 u8 l0_to_recovery_eieos[0x20];
1835 u8 l0_to_recovery_ts[0x20];
1837 u8 l0_to_recovery_framing[0x20];
1839 u8 l0_to_recovery_retrain[0x20];
1841 u8 crc_error_dllp[0x20];
1843 u8 crc_error_tlp[0x20];
1845 u8 reserved_at_140[0x680];
1848 struct mlx5_ifc_cmd_inter_comp_event_bits {
1849 u8 command_completion_vector[0x20];
1851 u8 reserved_at_20[0xc0];
1854 struct mlx5_ifc_stall_vl_event_bits {
1855 u8 reserved_at_0[0x18];
1857 u8 reserved_at_19[0x3];
1860 u8 reserved_at_20[0xa0];
1863 struct mlx5_ifc_db_bf_congestion_event_bits {
1864 u8 event_subtype[0x8];
1865 u8 reserved_at_8[0x8];
1866 u8 congestion_level[0x8];
1867 u8 reserved_at_18[0x8];
1869 u8 reserved_at_20[0xa0];
1872 struct mlx5_ifc_gpio_event_bits {
1873 u8 reserved_at_0[0x60];
1875 u8 gpio_event_hi[0x20];
1877 u8 gpio_event_lo[0x20];
1879 u8 reserved_at_a0[0x40];
1882 struct mlx5_ifc_port_state_change_event_bits {
1883 u8 reserved_at_0[0x40];
1886 u8 reserved_at_44[0x1c];
1888 u8 reserved_at_60[0x80];
1891 struct mlx5_ifc_dropped_packet_logged_bits {
1892 u8 reserved_at_0[0xe0];
1896 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1897 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1900 struct mlx5_ifc_cq_error_bits {
1901 u8 reserved_at_0[0x8];
1904 u8 reserved_at_20[0x20];
1906 u8 reserved_at_40[0x18];
1909 u8 reserved_at_60[0x80];
1912 struct mlx5_ifc_rdma_page_fault_event_bits {
1913 u8 bytes_committed[0x20];
1917 u8 reserved_at_40[0x10];
1918 u8 packet_len[0x10];
1920 u8 rdma_op_len[0x20];
1924 u8 reserved_at_c0[0x5];
1931 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1932 u8 bytes_committed[0x20];
1934 u8 reserved_at_20[0x10];
1937 u8 reserved_at_40[0x10];
1940 u8 reserved_at_60[0x60];
1942 u8 reserved_at_c0[0x5];
1949 struct mlx5_ifc_qp_events_bits {
1950 u8 reserved_at_0[0xa0];
1953 u8 reserved_at_a8[0x18];
1955 u8 reserved_at_c0[0x8];
1956 u8 qpn_rqn_sqn[0x18];
1959 struct mlx5_ifc_dct_events_bits {
1960 u8 reserved_at_0[0xc0];
1962 u8 reserved_at_c0[0x8];
1963 u8 dct_number[0x18];
1966 struct mlx5_ifc_comp_event_bits {
1967 u8 reserved_at_0[0xc0];
1969 u8 reserved_at_c0[0x8];
1974 MLX5_QPC_STATE_RST = 0x0,
1975 MLX5_QPC_STATE_INIT = 0x1,
1976 MLX5_QPC_STATE_RTR = 0x2,
1977 MLX5_QPC_STATE_RTS = 0x3,
1978 MLX5_QPC_STATE_SQER = 0x4,
1979 MLX5_QPC_STATE_ERR = 0x6,
1980 MLX5_QPC_STATE_SQD = 0x7,
1981 MLX5_QPC_STATE_SUSPENDED = 0x9,
1985 MLX5_QPC_ST_RC = 0x0,
1986 MLX5_QPC_ST_UC = 0x1,
1987 MLX5_QPC_ST_UD = 0x2,
1988 MLX5_QPC_ST_XRC = 0x3,
1989 MLX5_QPC_ST_DCI = 0x5,
1990 MLX5_QPC_ST_QP0 = 0x7,
1991 MLX5_QPC_ST_QP1 = 0x8,
1992 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1993 MLX5_QPC_ST_REG_UMR = 0xc,
1997 MLX5_QPC_PM_STATE_ARMED = 0x0,
1998 MLX5_QPC_PM_STATE_REARM = 0x1,
1999 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2000 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2004 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2005 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2009 MLX5_QPC_MTU_256_BYTES = 0x1,
2010 MLX5_QPC_MTU_512_BYTES = 0x2,
2011 MLX5_QPC_MTU_1K_BYTES = 0x3,
2012 MLX5_QPC_MTU_2K_BYTES = 0x4,
2013 MLX5_QPC_MTU_4K_BYTES = 0x5,
2014 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2018 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2019 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2020 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2021 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2022 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2023 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2024 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2025 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2029 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2030 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2031 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2035 MLX5_QPC_CS_RES_DISABLE = 0x0,
2036 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2037 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2040 struct mlx5_ifc_qpc_bits {
2042 u8 lag_tx_port_affinity[0x4];
2044 u8 reserved_at_10[0x3];
2046 u8 reserved_at_15[0x7];
2047 u8 end_padding_mode[0x2];
2048 u8 reserved_at_1e[0x2];
2050 u8 wq_signature[0x1];
2051 u8 block_lb_mc[0x1];
2052 u8 atomic_like_write_en[0x1];
2053 u8 latency_sensitive[0x1];
2054 u8 reserved_at_24[0x1];
2055 u8 drain_sigerr[0x1];
2056 u8 reserved_at_26[0x2];
2060 u8 log_msg_max[0x5];
2061 u8 reserved_at_48[0x1];
2062 u8 log_rq_size[0x4];
2063 u8 log_rq_stride[0x3];
2065 u8 log_sq_size[0x4];
2066 u8 reserved_at_55[0x6];
2068 u8 ulp_stateless_offload_mode[0x4];
2070 u8 counter_set_id[0x8];
2073 u8 reserved_at_80[0x8];
2074 u8 user_index[0x18];
2076 u8 reserved_at_a0[0x3];
2077 u8 log_page_size[0x5];
2078 u8 remote_qpn[0x18];
2080 struct mlx5_ifc_ads_bits primary_address_path;
2082 struct mlx5_ifc_ads_bits secondary_address_path;
2084 u8 log_ack_req_freq[0x4];
2085 u8 reserved_at_384[0x4];
2086 u8 log_sra_max[0x3];
2087 u8 reserved_at_38b[0x2];
2088 u8 retry_count[0x3];
2090 u8 reserved_at_393[0x1];
2092 u8 cur_rnr_retry[0x3];
2093 u8 cur_retry_count[0x3];
2094 u8 reserved_at_39b[0x5];
2096 u8 reserved_at_3a0[0x20];
2098 u8 reserved_at_3c0[0x8];
2099 u8 next_send_psn[0x18];
2101 u8 reserved_at_3e0[0x8];
2104 u8 reserved_at_400[0x8];
2107 u8 reserved_at_420[0x20];
2109 u8 reserved_at_440[0x8];
2110 u8 last_acked_psn[0x18];
2112 u8 reserved_at_460[0x8];
2115 u8 reserved_at_480[0x8];
2116 u8 log_rra_max[0x3];
2117 u8 reserved_at_48b[0x1];
2118 u8 atomic_mode[0x4];
2122 u8 reserved_at_493[0x1];
2123 u8 page_offset[0x6];
2124 u8 reserved_at_49a[0x3];
2125 u8 cd_slave_receive[0x1];
2126 u8 cd_slave_send[0x1];
2129 u8 reserved_at_4a0[0x3];
2130 u8 min_rnr_nak[0x5];
2131 u8 next_rcv_psn[0x18];
2133 u8 reserved_at_4c0[0x8];
2136 u8 reserved_at_4e0[0x8];
2143 u8 reserved_at_560[0x5];
2145 u8 srqn_rmpn_xrqn[0x18];
2147 u8 reserved_at_580[0x8];
2150 u8 hw_sq_wqebb_counter[0x10];
2151 u8 sw_sq_wqebb_counter[0x10];
2153 u8 hw_rq_counter[0x20];
2155 u8 sw_rq_counter[0x20];
2157 u8 reserved_at_600[0x20];
2159 u8 reserved_at_620[0xf];
2164 u8 dc_access_key[0x40];
2166 u8 reserved_at_680[0xc0];
2169 struct mlx5_ifc_roce_addr_layout_bits {
2170 u8 source_l3_address[16][0x8];
2172 u8 reserved_at_80[0x3];
2175 u8 source_mac_47_32[0x10];
2177 u8 source_mac_31_0[0x20];
2179 u8 reserved_at_c0[0x14];
2180 u8 roce_l3_type[0x4];
2181 u8 roce_version[0x8];
2183 u8 reserved_at_e0[0x20];
2186 union mlx5_ifc_hca_cap_union_bits {
2187 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2188 struct mlx5_ifc_odp_cap_bits odp_cap;
2189 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2190 struct mlx5_ifc_roce_cap_bits roce_cap;
2191 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2192 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2193 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2194 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2195 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2196 struct mlx5_ifc_qos_cap_bits qos_cap;
2197 u8 reserved_at_0[0x8000];
2201 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2202 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2203 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2204 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2205 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2206 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2207 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2210 struct mlx5_ifc_flow_context_bits {
2211 u8 reserved_at_0[0x20];
2215 u8 reserved_at_40[0x8];
2218 u8 reserved_at_60[0x10];
2221 u8 reserved_at_80[0x8];
2222 u8 destination_list_size[0x18];
2224 u8 reserved_at_a0[0x8];
2225 u8 flow_counter_list_size[0x18];
2229 u8 modify_header_id[0x20];
2231 u8 reserved_at_100[0x100];
2233 struct mlx5_ifc_fte_match_param_bits match_value;
2235 u8 reserved_at_1200[0x600];
2237 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2241 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2242 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2245 struct mlx5_ifc_xrc_srqc_bits {
2247 u8 log_xrc_srq_size[0x4];
2248 u8 reserved_at_8[0x18];
2250 u8 wq_signature[0x1];
2252 u8 reserved_at_22[0x1];
2254 u8 basic_cyclic_rcv_wqe[0x1];
2255 u8 log_rq_stride[0x3];
2258 u8 page_offset[0x6];
2259 u8 reserved_at_46[0x2];
2262 u8 reserved_at_60[0x20];
2264 u8 user_index_equal_xrc_srqn[0x1];
2265 u8 reserved_at_81[0x1];
2266 u8 log_page_size[0x6];
2267 u8 user_index[0x18];
2269 u8 reserved_at_a0[0x20];
2271 u8 reserved_at_c0[0x8];
2277 u8 reserved_at_100[0x40];
2279 u8 db_record_addr_h[0x20];
2281 u8 db_record_addr_l[0x1e];
2282 u8 reserved_at_17e[0x2];
2284 u8 reserved_at_180[0x80];
2287 struct mlx5_ifc_traffic_counter_bits {
2293 struct mlx5_ifc_tisc_bits {
2294 u8 strict_lag_tx_port_affinity[0x1];
2295 u8 reserved_at_1[0x3];
2296 u8 lag_tx_port_affinity[0x04];
2298 u8 reserved_at_8[0x4];
2300 u8 reserved_at_10[0x10];
2302 u8 reserved_at_20[0x100];
2304 u8 reserved_at_120[0x8];
2305 u8 transport_domain[0x18];
2307 u8 reserved_at_140[0x8];
2308 u8 underlay_qpn[0x18];
2309 u8 reserved_at_160[0x3a0];
2313 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2314 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2318 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2319 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2323 MLX5_RX_HASH_FN_NONE = 0x0,
2324 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2325 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2329 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2330 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2333 struct mlx5_ifc_tirc_bits {
2334 u8 reserved_at_0[0x20];
2337 u8 reserved_at_24[0x1c];
2339 u8 reserved_at_40[0x40];
2341 u8 reserved_at_80[0x4];
2342 u8 lro_timeout_period_usecs[0x10];
2343 u8 lro_enable_mask[0x4];
2344 u8 lro_max_ip_payload_size[0x8];
2346 u8 reserved_at_a0[0x40];
2348 u8 reserved_at_e0[0x8];
2349 u8 inline_rqn[0x18];
2351 u8 rx_hash_symmetric[0x1];
2352 u8 reserved_at_101[0x1];
2353 u8 tunneled_offload_en[0x1];
2354 u8 reserved_at_103[0x5];
2355 u8 indirect_table[0x18];
2358 u8 reserved_at_124[0x2];
2359 u8 self_lb_block[0x2];
2360 u8 transport_domain[0x18];
2362 u8 rx_hash_toeplitz_key[10][0x20];
2364 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2366 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2368 u8 reserved_at_2c0[0x4c0];
2372 MLX5_SRQC_STATE_GOOD = 0x0,
2373 MLX5_SRQC_STATE_ERROR = 0x1,
2376 struct mlx5_ifc_srqc_bits {
2378 u8 log_srq_size[0x4];
2379 u8 reserved_at_8[0x18];
2381 u8 wq_signature[0x1];
2383 u8 reserved_at_22[0x1];
2385 u8 reserved_at_24[0x1];
2386 u8 log_rq_stride[0x3];
2389 u8 page_offset[0x6];
2390 u8 reserved_at_46[0x2];
2393 u8 reserved_at_60[0x20];
2395 u8 reserved_at_80[0x2];
2396 u8 log_page_size[0x6];
2397 u8 reserved_at_88[0x18];
2399 u8 reserved_at_a0[0x20];
2401 u8 reserved_at_c0[0x8];
2407 u8 reserved_at_100[0x40];
2411 u8 reserved_at_180[0x80];
2415 MLX5_SQC_STATE_RST = 0x0,
2416 MLX5_SQC_STATE_RDY = 0x1,
2417 MLX5_SQC_STATE_ERR = 0x3,
2420 struct mlx5_ifc_sqc_bits {
2424 u8 flush_in_error_en[0x1];
2425 u8 reserved_at_4[0x1];
2426 u8 min_wqe_inline_mode[0x3];
2429 u8 reserved_at_d[0x13];
2431 u8 reserved_at_20[0x8];
2432 u8 user_index[0x18];
2434 u8 reserved_at_40[0x8];
2437 u8 reserved_at_60[0x90];
2439 u8 packet_pacing_rate_limit_index[0x10];
2440 u8 tis_lst_sz[0x10];
2441 u8 reserved_at_110[0x10];
2443 u8 reserved_at_120[0x40];
2445 u8 reserved_at_160[0x8];
2448 struct mlx5_ifc_wq_bits wq;
2452 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2453 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2454 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2455 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2458 struct mlx5_ifc_scheduling_context_bits {
2459 u8 element_type[0x8];
2460 u8 reserved_at_8[0x18];
2462 u8 element_attributes[0x20];
2464 u8 parent_element_id[0x20];
2466 u8 reserved_at_60[0x40];
2470 u8 max_average_bw[0x20];
2472 u8 reserved_at_e0[0x120];
2475 struct mlx5_ifc_rqtc_bits {
2476 u8 reserved_at_0[0xa0];
2478 u8 reserved_at_a0[0x10];
2479 u8 rqt_max_size[0x10];
2481 u8 reserved_at_c0[0x10];
2482 u8 rqt_actual_size[0x10];
2484 u8 reserved_at_e0[0x6a0];
2486 struct mlx5_ifc_rq_num_bits rq_num[0];
2490 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2491 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2495 MLX5_RQC_STATE_RST = 0x0,
2496 MLX5_RQC_STATE_RDY = 0x1,
2497 MLX5_RQC_STATE_ERR = 0x3,
2500 struct mlx5_ifc_rqc_bits {
2502 u8 reserved_at_1[0x1];
2503 u8 scatter_fcs[0x1];
2505 u8 mem_rq_type[0x4];
2507 u8 reserved_at_c[0x1];
2508 u8 flush_in_error_en[0x1];
2509 u8 reserved_at_e[0x12];
2511 u8 reserved_at_20[0x8];
2512 u8 user_index[0x18];
2514 u8 reserved_at_40[0x8];
2517 u8 counter_set_id[0x8];
2518 u8 reserved_at_68[0x18];
2520 u8 reserved_at_80[0x8];
2523 u8 reserved_at_a0[0xe0];
2525 struct mlx5_ifc_wq_bits wq;
2529 MLX5_RMPC_STATE_RDY = 0x1,
2530 MLX5_RMPC_STATE_ERR = 0x3,
2533 struct mlx5_ifc_rmpc_bits {
2534 u8 reserved_at_0[0x8];
2536 u8 reserved_at_c[0x14];
2538 u8 basic_cyclic_rcv_wqe[0x1];
2539 u8 reserved_at_21[0x1f];
2541 u8 reserved_at_40[0x140];
2543 struct mlx5_ifc_wq_bits wq;
2546 struct mlx5_ifc_nic_vport_context_bits {
2547 u8 reserved_at_0[0x5];
2548 u8 min_wqe_inline_mode[0x3];
2549 u8 reserved_at_8[0x17];
2552 u8 arm_change_event[0x1];
2553 u8 reserved_at_21[0x1a];
2554 u8 event_on_mtu[0x1];
2555 u8 event_on_promisc_change[0x1];
2556 u8 event_on_vlan_change[0x1];
2557 u8 event_on_mc_address_change[0x1];
2558 u8 event_on_uc_address_change[0x1];
2560 u8 reserved_at_40[0xf0];
2564 u8 system_image_guid[0x40];
2568 u8 reserved_at_200[0x140];
2569 u8 qkey_violation_counter[0x10];
2570 u8 reserved_at_350[0x430];
2574 u8 promisc_all[0x1];
2575 u8 reserved_at_783[0x2];
2576 u8 allowed_list_type[0x3];
2577 u8 reserved_at_788[0xc];
2578 u8 allowed_list_size[0xc];
2580 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2582 u8 reserved_at_7e0[0x20];
2584 u8 current_uc_mac_address[0][0x40];
2588 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2589 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2590 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2591 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2594 struct mlx5_ifc_mkc_bits {
2595 u8 reserved_at_0[0x1];
2597 u8 reserved_at_2[0xd];
2598 u8 small_fence_on_rdma_read_response[0x1];
2605 u8 access_mode[0x2];
2606 u8 reserved_at_18[0x8];
2611 u8 reserved_at_40[0x20];
2616 u8 reserved_at_63[0x2];
2617 u8 expected_sigerr_count[0x1];
2618 u8 reserved_at_66[0x1];
2622 u8 start_addr[0x40];
2626 u8 bsf_octword_size[0x20];
2628 u8 reserved_at_120[0x80];
2630 u8 translations_octword_size[0x20];
2632 u8 reserved_at_1c0[0x1b];
2633 u8 log_page_size[0x5];
2635 u8 reserved_at_1e0[0x20];
2638 struct mlx5_ifc_pkey_bits {
2639 u8 reserved_at_0[0x10];
2643 struct mlx5_ifc_array128_auto_bits {
2644 u8 array128_auto[16][0x8];
2647 struct mlx5_ifc_hca_vport_context_bits {
2648 u8 field_select[0x20];
2650 u8 reserved_at_20[0xe0];
2652 u8 sm_virt_aware[0x1];
2655 u8 grh_required[0x1];
2656 u8 reserved_at_104[0xc];
2657 u8 port_physical_state[0x4];
2658 u8 vport_state_policy[0x4];
2660 u8 vport_state[0x4];
2662 u8 reserved_at_120[0x20];
2664 u8 system_image_guid[0x40];
2672 u8 cap_mask1_field_select[0x20];
2676 u8 cap_mask2_field_select[0x20];
2678 u8 reserved_at_280[0x80];
2681 u8 reserved_at_310[0x4];
2682 u8 init_type_reply[0x4];
2684 u8 subnet_timeout[0x5];
2688 u8 reserved_at_334[0xc];
2690 u8 qkey_violation_counter[0x10];
2691 u8 pkey_violation_counter[0x10];
2693 u8 reserved_at_360[0xca0];
2696 struct mlx5_ifc_esw_vport_context_bits {
2697 u8 reserved_at_0[0x3];
2698 u8 vport_svlan_strip[0x1];
2699 u8 vport_cvlan_strip[0x1];
2700 u8 vport_svlan_insert[0x1];
2701 u8 vport_cvlan_insert[0x2];
2702 u8 reserved_at_8[0x18];
2704 u8 reserved_at_20[0x20];
2713 u8 reserved_at_60[0x7a0];
2717 MLX5_EQC_STATUS_OK = 0x0,
2718 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2722 MLX5_EQC_ST_ARMED = 0x9,
2723 MLX5_EQC_ST_FIRED = 0xa,
2726 struct mlx5_ifc_eqc_bits {
2728 u8 reserved_at_4[0x9];
2731 u8 reserved_at_f[0x5];
2733 u8 reserved_at_18[0x8];
2735 u8 reserved_at_20[0x20];
2737 u8 reserved_at_40[0x14];
2738 u8 page_offset[0x6];
2739 u8 reserved_at_5a[0x6];
2741 u8 reserved_at_60[0x3];
2742 u8 log_eq_size[0x5];
2745 u8 reserved_at_80[0x20];
2747 u8 reserved_at_a0[0x18];
2750 u8 reserved_at_c0[0x3];
2751 u8 log_page_size[0x5];
2752 u8 reserved_at_c8[0x18];
2754 u8 reserved_at_e0[0x60];
2756 u8 reserved_at_140[0x8];
2757 u8 consumer_counter[0x18];
2759 u8 reserved_at_160[0x8];
2760 u8 producer_counter[0x18];
2762 u8 reserved_at_180[0x80];
2766 MLX5_DCTC_STATE_ACTIVE = 0x0,
2767 MLX5_DCTC_STATE_DRAINING = 0x1,
2768 MLX5_DCTC_STATE_DRAINED = 0x2,
2772 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2773 MLX5_DCTC_CS_RES_NA = 0x1,
2774 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2778 MLX5_DCTC_MTU_256_BYTES = 0x1,
2779 MLX5_DCTC_MTU_512_BYTES = 0x2,
2780 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2781 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2782 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2785 struct mlx5_ifc_dctc_bits {
2786 u8 reserved_at_0[0x4];
2788 u8 reserved_at_8[0x18];
2790 u8 reserved_at_20[0x8];
2791 u8 user_index[0x18];
2793 u8 reserved_at_40[0x8];
2796 u8 counter_set_id[0x8];
2797 u8 atomic_mode[0x4];
2801 u8 atomic_like_write_en[0x1];
2802 u8 latency_sensitive[0x1];
2805 u8 reserved_at_73[0xd];
2807 u8 reserved_at_80[0x8];
2809 u8 reserved_at_90[0x3];
2810 u8 min_rnr_nak[0x5];
2811 u8 reserved_at_98[0x8];
2813 u8 reserved_at_a0[0x8];
2816 u8 reserved_at_c0[0x8];
2820 u8 reserved_at_e8[0x4];
2821 u8 flow_label[0x14];
2823 u8 dc_access_key[0x40];
2825 u8 reserved_at_140[0x5];
2828 u8 pkey_index[0x10];
2830 u8 reserved_at_160[0x8];
2831 u8 my_addr_index[0x8];
2832 u8 reserved_at_170[0x8];
2835 u8 dc_access_key_violation_count[0x20];
2837 u8 reserved_at_1a0[0x14];
2843 u8 reserved_at_1c0[0x40];
2847 MLX5_CQC_STATUS_OK = 0x0,
2848 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2849 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2853 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2854 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2858 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2859 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2860 MLX5_CQC_ST_FIRED = 0xa,
2864 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2865 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2866 MLX5_CQ_PERIOD_NUM_MODES
2869 struct mlx5_ifc_cqc_bits {
2871 u8 reserved_at_4[0x4];
2874 u8 reserved_at_c[0x1];
2875 u8 scqe_break_moderation_en[0x1];
2877 u8 cq_period_mode[0x2];
2878 u8 cqe_comp_en[0x1];
2879 u8 mini_cqe_res_format[0x2];
2881 u8 reserved_at_18[0x8];
2883 u8 reserved_at_20[0x20];
2885 u8 reserved_at_40[0x14];
2886 u8 page_offset[0x6];
2887 u8 reserved_at_5a[0x6];
2889 u8 reserved_at_60[0x3];
2890 u8 log_cq_size[0x5];
2893 u8 reserved_at_80[0x4];
2895 u8 cq_max_count[0x10];
2897 u8 reserved_at_a0[0x18];
2900 u8 reserved_at_c0[0x3];
2901 u8 log_page_size[0x5];
2902 u8 reserved_at_c8[0x18];
2904 u8 reserved_at_e0[0x20];
2906 u8 reserved_at_100[0x8];
2907 u8 last_notified_index[0x18];
2909 u8 reserved_at_120[0x8];
2910 u8 last_solicit_index[0x18];
2912 u8 reserved_at_140[0x8];
2913 u8 consumer_counter[0x18];
2915 u8 reserved_at_160[0x8];
2916 u8 producer_counter[0x18];
2918 u8 reserved_at_180[0x40];
2923 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2924 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2925 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2926 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2927 u8 reserved_at_0[0x800];
2930 struct mlx5_ifc_query_adapter_param_block_bits {
2931 u8 reserved_at_0[0xc0];
2933 u8 reserved_at_c0[0x8];
2934 u8 ieee_vendor_id[0x18];
2936 u8 reserved_at_e0[0x10];
2937 u8 vsd_vendor_id[0x10];
2941 u8 vsd_contd_psid[16][0x8];
2945 MLX5_XRQC_STATE_GOOD = 0x0,
2946 MLX5_XRQC_STATE_ERROR = 0x1,
2950 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2951 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2955 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2958 struct mlx5_ifc_tag_matching_topology_context_bits {
2959 u8 log_matching_list_sz[0x4];
2960 u8 reserved_at_4[0xc];
2961 u8 append_next_index[0x10];
2963 u8 sw_phase_cnt[0x10];
2964 u8 hw_phase_cnt[0x10];
2966 u8 reserved_at_40[0x40];
2969 struct mlx5_ifc_xrqc_bits {
2972 u8 reserved_at_5[0xf];
2974 u8 reserved_at_18[0x4];
2977 u8 reserved_at_20[0x8];
2978 u8 user_index[0x18];
2980 u8 reserved_at_40[0x8];
2983 u8 reserved_at_60[0xa0];
2985 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2987 u8 reserved_at_180[0x880];
2989 struct mlx5_ifc_wq_bits wq;
2992 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2993 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2994 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2995 u8 reserved_at_0[0x20];
2998 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2999 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3000 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3001 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3002 u8 reserved_at_0[0x20];
3005 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3006 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3007 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3008 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3009 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3010 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3011 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3012 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3013 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3014 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3015 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3016 u8 reserved_at_0[0x7c0];
3019 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3020 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3021 u8 reserved_at_0[0x7c0];
3024 union mlx5_ifc_event_auto_bits {
3025 struct mlx5_ifc_comp_event_bits comp_event;
3026 struct mlx5_ifc_dct_events_bits dct_events;
3027 struct mlx5_ifc_qp_events_bits qp_events;
3028 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3029 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3030 struct mlx5_ifc_cq_error_bits cq_error;
3031 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3032 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3033 struct mlx5_ifc_gpio_event_bits gpio_event;
3034 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3035 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3036 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3037 u8 reserved_at_0[0xe0];
3040 struct mlx5_ifc_health_buffer_bits {
3041 u8 reserved_at_0[0x100];
3043 u8 assert_existptr[0x20];
3045 u8 assert_callra[0x20];
3047 u8 reserved_at_140[0x40];
3049 u8 fw_version[0x20];
3053 u8 reserved_at_1c0[0x20];
3055 u8 irisc_index[0x8];
3060 struct mlx5_ifc_register_loopback_control_bits {
3062 u8 reserved_at_1[0x7];
3064 u8 reserved_at_10[0x10];
3066 u8 reserved_at_20[0x60];
3069 struct mlx5_ifc_vport_tc_element_bits {
3070 u8 traffic_class[0x4];
3071 u8 reserved_at_4[0xc];
3072 u8 vport_number[0x10];
3075 struct mlx5_ifc_vport_element_bits {
3076 u8 reserved_at_0[0x10];
3077 u8 vport_number[0x10];
3081 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3082 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3083 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3086 struct mlx5_ifc_tsar_element_bits {
3087 u8 reserved_at_0[0x8];
3089 u8 reserved_at_10[0x10];
3092 struct mlx5_ifc_teardown_hca_out_bits {
3094 u8 reserved_at_8[0x18];
3098 u8 reserved_at_40[0x40];
3102 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3103 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
3106 struct mlx5_ifc_teardown_hca_in_bits {
3108 u8 reserved_at_10[0x10];
3110 u8 reserved_at_20[0x10];
3113 u8 reserved_at_40[0x10];
3116 u8 reserved_at_60[0x20];
3119 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3121 u8 reserved_at_8[0x18];
3125 u8 reserved_at_40[0x40];
3128 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3130 u8 reserved_at_10[0x10];
3132 u8 reserved_at_20[0x10];
3135 u8 reserved_at_40[0x8];
3138 u8 reserved_at_60[0x20];
3140 u8 opt_param_mask[0x20];
3142 u8 reserved_at_a0[0x20];
3144 struct mlx5_ifc_qpc_bits qpc;
3146 u8 reserved_at_800[0x80];
3149 struct mlx5_ifc_sqd2rts_qp_out_bits {
3151 u8 reserved_at_8[0x18];
3155 u8 reserved_at_40[0x40];
3158 struct mlx5_ifc_sqd2rts_qp_in_bits {
3160 u8 reserved_at_10[0x10];
3162 u8 reserved_at_20[0x10];
3165 u8 reserved_at_40[0x8];
3168 u8 reserved_at_60[0x20];
3170 u8 opt_param_mask[0x20];
3172 u8 reserved_at_a0[0x20];
3174 struct mlx5_ifc_qpc_bits qpc;
3176 u8 reserved_at_800[0x80];
3179 struct mlx5_ifc_set_roce_address_out_bits {
3181 u8 reserved_at_8[0x18];
3185 u8 reserved_at_40[0x40];
3188 struct mlx5_ifc_set_roce_address_in_bits {
3190 u8 reserved_at_10[0x10];
3192 u8 reserved_at_20[0x10];
3195 u8 roce_address_index[0x10];
3196 u8 reserved_at_50[0x10];
3198 u8 reserved_at_60[0x20];
3200 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3203 struct mlx5_ifc_set_mad_demux_out_bits {
3205 u8 reserved_at_8[0x18];
3209 u8 reserved_at_40[0x40];
3213 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3214 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3217 struct mlx5_ifc_set_mad_demux_in_bits {
3219 u8 reserved_at_10[0x10];
3221 u8 reserved_at_20[0x10];
3224 u8 reserved_at_40[0x20];
3226 u8 reserved_at_60[0x6];
3228 u8 reserved_at_68[0x18];
3231 struct mlx5_ifc_set_l2_table_entry_out_bits {
3233 u8 reserved_at_8[0x18];
3237 u8 reserved_at_40[0x40];
3240 struct mlx5_ifc_set_l2_table_entry_in_bits {
3242 u8 reserved_at_10[0x10];
3244 u8 reserved_at_20[0x10];
3247 u8 reserved_at_40[0x60];
3249 u8 reserved_at_a0[0x8];
3250 u8 table_index[0x18];
3252 u8 reserved_at_c0[0x20];
3254 u8 reserved_at_e0[0x13];
3258 struct mlx5_ifc_mac_address_layout_bits mac_address;
3260 u8 reserved_at_140[0xc0];
3263 struct mlx5_ifc_set_issi_out_bits {
3265 u8 reserved_at_8[0x18];
3269 u8 reserved_at_40[0x40];
3272 struct mlx5_ifc_set_issi_in_bits {
3274 u8 reserved_at_10[0x10];
3276 u8 reserved_at_20[0x10];
3279 u8 reserved_at_40[0x10];
3280 u8 current_issi[0x10];
3282 u8 reserved_at_60[0x20];
3285 struct mlx5_ifc_set_hca_cap_out_bits {
3287 u8 reserved_at_8[0x18];
3291 u8 reserved_at_40[0x40];
3294 struct mlx5_ifc_set_hca_cap_in_bits {
3296 u8 reserved_at_10[0x10];
3298 u8 reserved_at_20[0x10];
3301 u8 reserved_at_40[0x40];
3303 union mlx5_ifc_hca_cap_union_bits capability;
3307 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3308 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3309 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3310 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3313 struct mlx5_ifc_set_fte_out_bits {
3315 u8 reserved_at_8[0x18];
3319 u8 reserved_at_40[0x40];
3322 struct mlx5_ifc_set_fte_in_bits {
3324 u8 reserved_at_10[0x10];
3326 u8 reserved_at_20[0x10];
3329 u8 other_vport[0x1];
3330 u8 reserved_at_41[0xf];
3331 u8 vport_number[0x10];
3333 u8 reserved_at_60[0x20];
3336 u8 reserved_at_88[0x18];
3338 u8 reserved_at_a0[0x8];
3341 u8 reserved_at_c0[0x18];
3342 u8 modify_enable_mask[0x8];
3344 u8 reserved_at_e0[0x20];
3346 u8 flow_index[0x20];
3348 u8 reserved_at_120[0xe0];
3350 struct mlx5_ifc_flow_context_bits flow_context;
3353 struct mlx5_ifc_rts2rts_qp_out_bits {
3355 u8 reserved_at_8[0x18];
3359 u8 reserved_at_40[0x40];
3362 struct mlx5_ifc_rts2rts_qp_in_bits {
3364 u8 reserved_at_10[0x10];
3366 u8 reserved_at_20[0x10];
3369 u8 reserved_at_40[0x8];
3372 u8 reserved_at_60[0x20];
3374 u8 opt_param_mask[0x20];
3376 u8 reserved_at_a0[0x20];
3378 struct mlx5_ifc_qpc_bits qpc;
3380 u8 reserved_at_800[0x80];
3383 struct mlx5_ifc_rtr2rts_qp_out_bits {
3385 u8 reserved_at_8[0x18];
3389 u8 reserved_at_40[0x40];
3392 struct mlx5_ifc_rtr2rts_qp_in_bits {
3394 u8 reserved_at_10[0x10];
3396 u8 reserved_at_20[0x10];
3399 u8 reserved_at_40[0x8];
3402 u8 reserved_at_60[0x20];
3404 u8 opt_param_mask[0x20];
3406 u8 reserved_at_a0[0x20];
3408 struct mlx5_ifc_qpc_bits qpc;
3410 u8 reserved_at_800[0x80];
3413 struct mlx5_ifc_rst2init_qp_out_bits {
3415 u8 reserved_at_8[0x18];
3419 u8 reserved_at_40[0x40];
3422 struct mlx5_ifc_rst2init_qp_in_bits {
3424 u8 reserved_at_10[0x10];
3426 u8 reserved_at_20[0x10];
3429 u8 reserved_at_40[0x8];
3432 u8 reserved_at_60[0x20];
3434 u8 opt_param_mask[0x20];
3436 u8 reserved_at_a0[0x20];
3438 struct mlx5_ifc_qpc_bits qpc;
3440 u8 reserved_at_800[0x80];
3443 struct mlx5_ifc_query_xrq_out_bits {
3445 u8 reserved_at_8[0x18];
3449 u8 reserved_at_40[0x40];
3451 struct mlx5_ifc_xrqc_bits xrq_context;
3454 struct mlx5_ifc_query_xrq_in_bits {
3456 u8 reserved_at_10[0x10];
3458 u8 reserved_at_20[0x10];
3461 u8 reserved_at_40[0x8];
3464 u8 reserved_at_60[0x20];
3467 struct mlx5_ifc_query_xrc_srq_out_bits {
3469 u8 reserved_at_8[0x18];
3473 u8 reserved_at_40[0x40];
3475 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3477 u8 reserved_at_280[0x600];
3482 struct mlx5_ifc_query_xrc_srq_in_bits {
3484 u8 reserved_at_10[0x10];
3486 u8 reserved_at_20[0x10];
3489 u8 reserved_at_40[0x8];
3492 u8 reserved_at_60[0x20];
3496 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3497 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3500 struct mlx5_ifc_query_vport_state_out_bits {
3502 u8 reserved_at_8[0x18];
3506 u8 reserved_at_40[0x20];
3508 u8 reserved_at_60[0x18];
3509 u8 admin_state[0x4];
3514 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3515 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3518 struct mlx5_ifc_query_vport_state_in_bits {
3520 u8 reserved_at_10[0x10];
3522 u8 reserved_at_20[0x10];
3525 u8 other_vport[0x1];
3526 u8 reserved_at_41[0xf];
3527 u8 vport_number[0x10];
3529 u8 reserved_at_60[0x20];
3532 struct mlx5_ifc_query_vport_counter_out_bits {
3534 u8 reserved_at_8[0x18];
3538 u8 reserved_at_40[0x40];
3540 struct mlx5_ifc_traffic_counter_bits received_errors;
3542 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3544 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3546 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3548 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3550 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3552 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3554 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3556 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3558 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3560 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3562 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3564 u8 reserved_at_680[0xa00];
3568 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3571 struct mlx5_ifc_query_vport_counter_in_bits {
3573 u8 reserved_at_10[0x10];
3575 u8 reserved_at_20[0x10];
3578 u8 other_vport[0x1];
3579 u8 reserved_at_41[0xb];
3581 u8 vport_number[0x10];
3583 u8 reserved_at_60[0x60];
3586 u8 reserved_at_c1[0x1f];
3588 u8 reserved_at_e0[0x20];
3591 struct mlx5_ifc_query_tis_out_bits {
3593 u8 reserved_at_8[0x18];
3597 u8 reserved_at_40[0x40];
3599 struct mlx5_ifc_tisc_bits tis_context;
3602 struct mlx5_ifc_query_tis_in_bits {
3604 u8 reserved_at_10[0x10];
3606 u8 reserved_at_20[0x10];
3609 u8 reserved_at_40[0x8];
3612 u8 reserved_at_60[0x20];
3615 struct mlx5_ifc_query_tir_out_bits {
3617 u8 reserved_at_8[0x18];
3621 u8 reserved_at_40[0xc0];
3623 struct mlx5_ifc_tirc_bits tir_context;
3626 struct mlx5_ifc_query_tir_in_bits {
3628 u8 reserved_at_10[0x10];
3630 u8 reserved_at_20[0x10];
3633 u8 reserved_at_40[0x8];
3636 u8 reserved_at_60[0x20];
3639 struct mlx5_ifc_query_srq_out_bits {
3641 u8 reserved_at_8[0x18];
3645 u8 reserved_at_40[0x40];
3647 struct mlx5_ifc_srqc_bits srq_context_entry;
3649 u8 reserved_at_280[0x600];
3654 struct mlx5_ifc_query_srq_in_bits {
3656 u8 reserved_at_10[0x10];
3658 u8 reserved_at_20[0x10];
3661 u8 reserved_at_40[0x8];
3664 u8 reserved_at_60[0x20];
3667 struct mlx5_ifc_query_sq_out_bits {
3669 u8 reserved_at_8[0x18];
3673 u8 reserved_at_40[0xc0];
3675 struct mlx5_ifc_sqc_bits sq_context;
3678 struct mlx5_ifc_query_sq_in_bits {
3680 u8 reserved_at_10[0x10];
3682 u8 reserved_at_20[0x10];
3685 u8 reserved_at_40[0x8];
3688 u8 reserved_at_60[0x20];
3691 struct mlx5_ifc_query_special_contexts_out_bits {
3693 u8 reserved_at_8[0x18];
3697 u8 dump_fill_mkey[0x20];
3703 u8 reserved_at_a0[0x60];
3706 struct mlx5_ifc_query_special_contexts_in_bits {
3708 u8 reserved_at_10[0x10];
3710 u8 reserved_at_20[0x10];
3713 u8 reserved_at_40[0x40];
3716 struct mlx5_ifc_query_scheduling_element_out_bits {
3718 u8 reserved_at_10[0x10];
3720 u8 reserved_at_20[0x10];
3723 u8 reserved_at_40[0xc0];
3725 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3727 u8 reserved_at_300[0x100];
3731 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3734 struct mlx5_ifc_query_scheduling_element_in_bits {
3736 u8 reserved_at_10[0x10];
3738 u8 reserved_at_20[0x10];
3741 u8 scheduling_hierarchy[0x8];
3742 u8 reserved_at_48[0x18];
3744 u8 scheduling_element_id[0x20];
3746 u8 reserved_at_80[0x180];
3749 struct mlx5_ifc_query_rqt_out_bits {
3751 u8 reserved_at_8[0x18];
3755 u8 reserved_at_40[0xc0];
3757 struct mlx5_ifc_rqtc_bits rqt_context;
3760 struct mlx5_ifc_query_rqt_in_bits {
3762 u8 reserved_at_10[0x10];
3764 u8 reserved_at_20[0x10];
3767 u8 reserved_at_40[0x8];
3770 u8 reserved_at_60[0x20];
3773 struct mlx5_ifc_query_rq_out_bits {
3775 u8 reserved_at_8[0x18];
3779 u8 reserved_at_40[0xc0];
3781 struct mlx5_ifc_rqc_bits rq_context;
3784 struct mlx5_ifc_query_rq_in_bits {
3786 u8 reserved_at_10[0x10];
3788 u8 reserved_at_20[0x10];
3791 u8 reserved_at_40[0x8];
3794 u8 reserved_at_60[0x20];
3797 struct mlx5_ifc_query_roce_address_out_bits {
3799 u8 reserved_at_8[0x18];
3803 u8 reserved_at_40[0x40];
3805 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3808 struct mlx5_ifc_query_roce_address_in_bits {
3810 u8 reserved_at_10[0x10];
3812 u8 reserved_at_20[0x10];
3815 u8 roce_address_index[0x10];
3816 u8 reserved_at_50[0x10];
3818 u8 reserved_at_60[0x20];
3821 struct mlx5_ifc_query_rmp_out_bits {
3823 u8 reserved_at_8[0x18];
3827 u8 reserved_at_40[0xc0];
3829 struct mlx5_ifc_rmpc_bits rmp_context;
3832 struct mlx5_ifc_query_rmp_in_bits {
3834 u8 reserved_at_10[0x10];
3836 u8 reserved_at_20[0x10];
3839 u8 reserved_at_40[0x8];
3842 u8 reserved_at_60[0x20];
3845 struct mlx5_ifc_query_qp_out_bits {
3847 u8 reserved_at_8[0x18];
3851 u8 reserved_at_40[0x40];
3853 u8 opt_param_mask[0x20];
3855 u8 reserved_at_a0[0x20];
3857 struct mlx5_ifc_qpc_bits qpc;
3859 u8 reserved_at_800[0x80];
3864 struct mlx5_ifc_query_qp_in_bits {
3866 u8 reserved_at_10[0x10];
3868 u8 reserved_at_20[0x10];
3871 u8 reserved_at_40[0x8];
3874 u8 reserved_at_60[0x20];
3877 struct mlx5_ifc_query_q_counter_out_bits {
3879 u8 reserved_at_8[0x18];
3883 u8 reserved_at_40[0x40];
3885 u8 rx_write_requests[0x20];
3887 u8 reserved_at_a0[0x20];
3889 u8 rx_read_requests[0x20];
3891 u8 reserved_at_e0[0x20];
3893 u8 rx_atomic_requests[0x20];
3895 u8 reserved_at_120[0x20];
3897 u8 rx_dct_connect[0x20];
3899 u8 reserved_at_160[0x20];
3901 u8 out_of_buffer[0x20];
3903 u8 reserved_at_1a0[0x20];
3905 u8 out_of_sequence[0x20];
3907 u8 reserved_at_1e0[0x20];
3909 u8 duplicate_request[0x20];
3911 u8 reserved_at_220[0x20];
3913 u8 rnr_nak_retry_err[0x20];
3915 u8 reserved_at_260[0x20];
3917 u8 packet_seq_err[0x20];
3919 u8 reserved_at_2a0[0x20];
3921 u8 implied_nak_seq_err[0x20];
3923 u8 reserved_at_2e0[0x20];
3925 u8 local_ack_timeout_err[0x20];
3927 u8 reserved_at_320[0x4e0];
3930 struct mlx5_ifc_query_q_counter_in_bits {
3932 u8 reserved_at_10[0x10];
3934 u8 reserved_at_20[0x10];
3937 u8 reserved_at_40[0x80];
3940 u8 reserved_at_c1[0x1f];
3942 u8 reserved_at_e0[0x18];
3943 u8 counter_set_id[0x8];
3946 struct mlx5_ifc_query_pages_out_bits {
3948 u8 reserved_at_8[0x18];
3952 u8 reserved_at_40[0x10];
3953 u8 function_id[0x10];
3959 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3960 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3961 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3964 struct mlx5_ifc_query_pages_in_bits {
3966 u8 reserved_at_10[0x10];
3968 u8 reserved_at_20[0x10];
3971 u8 reserved_at_40[0x10];
3972 u8 function_id[0x10];
3974 u8 reserved_at_60[0x20];
3977 struct mlx5_ifc_query_nic_vport_context_out_bits {
3979 u8 reserved_at_8[0x18];
3983 u8 reserved_at_40[0x40];
3985 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3988 struct mlx5_ifc_query_nic_vport_context_in_bits {
3990 u8 reserved_at_10[0x10];
3992 u8 reserved_at_20[0x10];
3995 u8 other_vport[0x1];
3996 u8 reserved_at_41[0xf];
3997 u8 vport_number[0x10];
3999 u8 reserved_at_60[0x5];
4000 u8 allowed_list_type[0x3];
4001 u8 reserved_at_68[0x18];
4004 struct mlx5_ifc_query_mkey_out_bits {
4006 u8 reserved_at_8[0x18];
4010 u8 reserved_at_40[0x40];
4012 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4014 u8 reserved_at_280[0x600];
4016 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4018 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4021 struct mlx5_ifc_query_mkey_in_bits {
4023 u8 reserved_at_10[0x10];
4025 u8 reserved_at_20[0x10];
4028 u8 reserved_at_40[0x8];
4029 u8 mkey_index[0x18];
4032 u8 reserved_at_61[0x1f];
4035 struct mlx5_ifc_query_mad_demux_out_bits {
4037 u8 reserved_at_8[0x18];
4041 u8 reserved_at_40[0x40];
4043 u8 mad_dumux_parameters_block[0x20];
4046 struct mlx5_ifc_query_mad_demux_in_bits {
4048 u8 reserved_at_10[0x10];
4050 u8 reserved_at_20[0x10];
4053 u8 reserved_at_40[0x40];
4056 struct mlx5_ifc_query_l2_table_entry_out_bits {
4058 u8 reserved_at_8[0x18];
4062 u8 reserved_at_40[0xa0];
4064 u8 reserved_at_e0[0x13];
4068 struct mlx5_ifc_mac_address_layout_bits mac_address;
4070 u8 reserved_at_140[0xc0];
4073 struct mlx5_ifc_query_l2_table_entry_in_bits {
4075 u8 reserved_at_10[0x10];
4077 u8 reserved_at_20[0x10];
4080 u8 reserved_at_40[0x60];
4082 u8 reserved_at_a0[0x8];
4083 u8 table_index[0x18];
4085 u8 reserved_at_c0[0x140];
4088 struct mlx5_ifc_query_issi_out_bits {
4090 u8 reserved_at_8[0x18];
4094 u8 reserved_at_40[0x10];
4095 u8 current_issi[0x10];
4097 u8 reserved_at_60[0xa0];
4099 u8 reserved_at_100[76][0x8];
4100 u8 supported_issi_dw0[0x20];
4103 struct mlx5_ifc_query_issi_in_bits {
4105 u8 reserved_at_10[0x10];
4107 u8 reserved_at_20[0x10];
4110 u8 reserved_at_40[0x40];
4113 struct mlx5_ifc_set_driver_version_out_bits {
4115 u8 reserved_0[0x18];
4118 u8 reserved_1[0x40];
4121 struct mlx5_ifc_set_driver_version_in_bits {
4123 u8 reserved_0[0x10];
4125 u8 reserved_1[0x10];
4128 u8 reserved_2[0x40];
4129 u8 driver_version[64][0x8];
4132 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4134 u8 reserved_at_8[0x18];
4138 u8 reserved_at_40[0x40];
4140 struct mlx5_ifc_pkey_bits pkey[0];
4143 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4145 u8 reserved_at_10[0x10];
4147 u8 reserved_at_20[0x10];
4150 u8 other_vport[0x1];
4151 u8 reserved_at_41[0xb];
4153 u8 vport_number[0x10];
4155 u8 reserved_at_60[0x10];
4156 u8 pkey_index[0x10];
4160 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4161 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4162 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4165 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4167 u8 reserved_at_8[0x18];
4171 u8 reserved_at_40[0x20];
4174 u8 reserved_at_70[0x10];
4176 struct mlx5_ifc_array128_auto_bits gid[0];
4179 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4181 u8 reserved_at_10[0x10];
4183 u8 reserved_at_20[0x10];
4186 u8 other_vport[0x1];
4187 u8 reserved_at_41[0xb];
4189 u8 vport_number[0x10];
4191 u8 reserved_at_60[0x10];
4195 struct mlx5_ifc_query_hca_vport_context_out_bits {
4197 u8 reserved_at_8[0x18];
4201 u8 reserved_at_40[0x40];
4203 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4206 struct mlx5_ifc_query_hca_vport_context_in_bits {
4208 u8 reserved_at_10[0x10];
4210 u8 reserved_at_20[0x10];
4213 u8 other_vport[0x1];
4214 u8 reserved_at_41[0xb];
4216 u8 vport_number[0x10];
4218 u8 reserved_at_60[0x20];
4221 struct mlx5_ifc_query_hca_cap_out_bits {
4223 u8 reserved_at_8[0x18];
4227 u8 reserved_at_40[0x40];
4229 union mlx5_ifc_hca_cap_union_bits capability;
4232 struct mlx5_ifc_query_hca_cap_in_bits {
4234 u8 reserved_at_10[0x10];
4236 u8 reserved_at_20[0x10];
4239 u8 reserved_at_40[0x40];
4242 struct mlx5_ifc_query_flow_table_out_bits {
4244 u8 reserved_at_8[0x18];
4248 u8 reserved_at_40[0x80];
4250 u8 reserved_at_c0[0x8];
4252 u8 reserved_at_d0[0x8];
4255 u8 reserved_at_e0[0x120];
4258 struct mlx5_ifc_query_flow_table_in_bits {
4260 u8 reserved_at_10[0x10];
4262 u8 reserved_at_20[0x10];
4265 u8 reserved_at_40[0x40];
4268 u8 reserved_at_88[0x18];
4270 u8 reserved_at_a0[0x8];
4273 u8 reserved_at_c0[0x140];
4276 struct mlx5_ifc_query_fte_out_bits {
4278 u8 reserved_at_8[0x18];
4282 u8 reserved_at_40[0x1c0];
4284 struct mlx5_ifc_flow_context_bits flow_context;
4287 struct mlx5_ifc_query_fte_in_bits {
4289 u8 reserved_at_10[0x10];
4291 u8 reserved_at_20[0x10];
4294 u8 reserved_at_40[0x40];
4297 u8 reserved_at_88[0x18];
4299 u8 reserved_at_a0[0x8];
4302 u8 reserved_at_c0[0x40];
4304 u8 flow_index[0x20];
4306 u8 reserved_at_120[0xe0];
4310 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4311 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4312 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4315 struct mlx5_ifc_query_flow_group_out_bits {
4317 u8 reserved_at_8[0x18];
4321 u8 reserved_at_40[0xa0];
4323 u8 start_flow_index[0x20];
4325 u8 reserved_at_100[0x20];
4327 u8 end_flow_index[0x20];
4329 u8 reserved_at_140[0xa0];
4331 u8 reserved_at_1e0[0x18];
4332 u8 match_criteria_enable[0x8];
4334 struct mlx5_ifc_fte_match_param_bits match_criteria;
4336 u8 reserved_at_1200[0xe00];
4339 struct mlx5_ifc_query_flow_group_in_bits {
4341 u8 reserved_at_10[0x10];
4343 u8 reserved_at_20[0x10];
4346 u8 reserved_at_40[0x40];
4349 u8 reserved_at_88[0x18];
4351 u8 reserved_at_a0[0x8];
4356 u8 reserved_at_e0[0x120];
4359 struct mlx5_ifc_query_flow_counter_out_bits {
4361 u8 reserved_at_8[0x18];
4365 u8 reserved_at_40[0x40];
4367 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4370 struct mlx5_ifc_query_flow_counter_in_bits {
4372 u8 reserved_at_10[0x10];
4374 u8 reserved_at_20[0x10];
4377 u8 reserved_at_40[0x80];
4380 u8 reserved_at_c1[0xf];
4381 u8 num_of_counters[0x10];
4383 u8 reserved_at_e0[0x10];
4384 u8 flow_counter_id[0x10];
4387 struct mlx5_ifc_query_esw_vport_context_out_bits {
4389 u8 reserved_at_8[0x18];
4393 u8 reserved_at_40[0x40];
4395 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4398 struct mlx5_ifc_query_esw_vport_context_in_bits {
4400 u8 reserved_at_10[0x10];
4402 u8 reserved_at_20[0x10];
4405 u8 other_vport[0x1];
4406 u8 reserved_at_41[0xf];
4407 u8 vport_number[0x10];
4409 u8 reserved_at_60[0x20];
4412 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4414 u8 reserved_at_8[0x18];
4418 u8 reserved_at_40[0x40];
4421 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4422 u8 reserved_at_0[0x1c];
4423 u8 vport_cvlan_insert[0x1];
4424 u8 vport_svlan_insert[0x1];
4425 u8 vport_cvlan_strip[0x1];
4426 u8 vport_svlan_strip[0x1];
4429 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4431 u8 reserved_at_10[0x10];
4433 u8 reserved_at_20[0x10];
4436 u8 other_vport[0x1];
4437 u8 reserved_at_41[0xf];
4438 u8 vport_number[0x10];
4440 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4442 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4445 struct mlx5_ifc_query_eq_out_bits {
4447 u8 reserved_at_8[0x18];
4451 u8 reserved_at_40[0x40];
4453 struct mlx5_ifc_eqc_bits eq_context_entry;
4455 u8 reserved_at_280[0x40];
4457 u8 event_bitmask[0x40];
4459 u8 reserved_at_300[0x580];
4464 struct mlx5_ifc_query_eq_in_bits {
4466 u8 reserved_at_10[0x10];
4468 u8 reserved_at_20[0x10];
4471 u8 reserved_at_40[0x18];
4474 u8 reserved_at_60[0x20];
4477 struct mlx5_ifc_encap_header_in_bits {
4478 u8 reserved_at_0[0x5];
4479 u8 header_type[0x3];
4480 u8 reserved_at_8[0xe];
4481 u8 encap_header_size[0xa];
4483 u8 reserved_at_20[0x10];
4484 u8 encap_header[2][0x8];
4486 u8 more_encap_header[0][0x8];
4489 struct mlx5_ifc_query_encap_header_out_bits {
4491 u8 reserved_at_8[0x18];
4495 u8 reserved_at_40[0xa0];
4497 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4500 struct mlx5_ifc_query_encap_header_in_bits {
4502 u8 reserved_at_10[0x10];
4504 u8 reserved_at_20[0x10];
4509 u8 reserved_at_60[0xa0];
4512 struct mlx5_ifc_alloc_encap_header_out_bits {
4514 u8 reserved_at_8[0x18];
4520 u8 reserved_at_60[0x20];
4523 struct mlx5_ifc_alloc_encap_header_in_bits {
4525 u8 reserved_at_10[0x10];
4527 u8 reserved_at_20[0x10];
4530 u8 reserved_at_40[0xa0];
4532 struct mlx5_ifc_encap_header_in_bits encap_header;
4535 struct mlx5_ifc_dealloc_encap_header_out_bits {
4537 u8 reserved_at_8[0x18];
4541 u8 reserved_at_40[0x40];
4544 struct mlx5_ifc_dealloc_encap_header_in_bits {
4546 u8 reserved_at_10[0x10];
4548 u8 reserved_20[0x10];
4553 u8 reserved_60[0x20];
4556 struct mlx5_ifc_set_action_in_bits {
4557 u8 action_type[0x4];
4559 u8 reserved_at_10[0x3];
4561 u8 reserved_at_18[0x3];
4567 struct mlx5_ifc_add_action_in_bits {
4568 u8 action_type[0x4];
4570 u8 reserved_at_10[0x10];
4575 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4576 struct mlx5_ifc_set_action_in_bits set_action_in;
4577 struct mlx5_ifc_add_action_in_bits add_action_in;
4578 u8 reserved_at_0[0x40];
4582 MLX5_ACTION_TYPE_SET = 0x1,
4583 MLX5_ACTION_TYPE_ADD = 0x2,
4587 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4588 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4589 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4590 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4591 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4592 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4593 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4594 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4595 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4596 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4597 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4598 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4599 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4600 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4601 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4602 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4603 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4604 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4605 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4606 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4607 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4608 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4611 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4613 u8 reserved_at_8[0x18];
4617 u8 modify_header_id[0x20];
4619 u8 reserved_at_60[0x20];
4622 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4624 u8 reserved_at_10[0x10];
4626 u8 reserved_at_20[0x10];
4629 u8 reserved_at_40[0x20];
4632 u8 reserved_at_68[0x10];
4633 u8 num_of_actions[0x8];
4635 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4638 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4640 u8 reserved_at_8[0x18];
4644 u8 reserved_at_40[0x40];
4647 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4649 u8 reserved_at_10[0x10];
4651 u8 reserved_at_20[0x10];
4654 u8 modify_header_id[0x20];
4656 u8 reserved_at_60[0x20];
4659 struct mlx5_ifc_query_dct_out_bits {
4661 u8 reserved_at_8[0x18];
4665 u8 reserved_at_40[0x40];
4667 struct mlx5_ifc_dctc_bits dct_context_entry;
4669 u8 reserved_at_280[0x180];
4672 struct mlx5_ifc_query_dct_in_bits {
4674 u8 reserved_at_10[0x10];
4676 u8 reserved_at_20[0x10];
4679 u8 reserved_at_40[0x8];
4682 u8 reserved_at_60[0x20];
4685 struct mlx5_ifc_query_cq_out_bits {
4687 u8 reserved_at_8[0x18];
4691 u8 reserved_at_40[0x40];
4693 struct mlx5_ifc_cqc_bits cq_context;
4695 u8 reserved_at_280[0x600];
4700 struct mlx5_ifc_query_cq_in_bits {
4702 u8 reserved_at_10[0x10];
4704 u8 reserved_at_20[0x10];
4707 u8 reserved_at_40[0x8];
4710 u8 reserved_at_60[0x20];
4713 struct mlx5_ifc_query_cong_status_out_bits {
4715 u8 reserved_at_8[0x18];
4719 u8 reserved_at_40[0x20];
4723 u8 reserved_at_62[0x1e];
4726 struct mlx5_ifc_query_cong_status_in_bits {
4728 u8 reserved_at_10[0x10];
4730 u8 reserved_at_20[0x10];
4733 u8 reserved_at_40[0x18];
4735 u8 cong_protocol[0x4];
4737 u8 reserved_at_60[0x20];
4740 struct mlx5_ifc_query_cong_statistics_out_bits {
4742 u8 reserved_at_8[0x18];
4746 u8 reserved_at_40[0x40];
4748 u8 rp_cur_flows[0x20];
4752 u8 rp_cnp_ignored_high[0x20];
4754 u8 rp_cnp_ignored_low[0x20];
4756 u8 rp_cnp_handled_high[0x20];
4758 u8 rp_cnp_handled_low[0x20];
4760 u8 reserved_at_140[0x100];
4762 u8 time_stamp_high[0x20];
4764 u8 time_stamp_low[0x20];
4766 u8 accumulators_period[0x20];
4768 u8 np_ecn_marked_roce_packets_high[0x20];
4770 u8 np_ecn_marked_roce_packets_low[0x20];
4772 u8 np_cnp_sent_high[0x20];
4774 u8 np_cnp_sent_low[0x20];
4776 u8 reserved_at_320[0x560];
4779 struct mlx5_ifc_query_cong_statistics_in_bits {
4781 u8 reserved_at_10[0x10];
4783 u8 reserved_at_20[0x10];
4787 u8 reserved_at_41[0x1f];
4789 u8 reserved_at_60[0x20];
4792 struct mlx5_ifc_query_cong_params_out_bits {
4794 u8 reserved_at_8[0x18];
4798 u8 reserved_at_40[0x40];
4800 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4803 struct mlx5_ifc_query_cong_params_in_bits {
4805 u8 reserved_at_10[0x10];
4807 u8 reserved_at_20[0x10];
4810 u8 reserved_at_40[0x1c];
4811 u8 cong_protocol[0x4];
4813 u8 reserved_at_60[0x20];
4816 struct mlx5_ifc_query_adapter_out_bits {
4818 u8 reserved_at_8[0x18];
4822 u8 reserved_at_40[0x40];
4824 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4827 struct mlx5_ifc_query_adapter_in_bits {
4829 u8 reserved_at_10[0x10];
4831 u8 reserved_at_20[0x10];
4834 u8 reserved_at_40[0x40];
4837 struct mlx5_ifc_qp_2rst_out_bits {
4839 u8 reserved_at_8[0x18];
4843 u8 reserved_at_40[0x40];
4846 struct mlx5_ifc_qp_2rst_in_bits {
4848 u8 reserved_at_10[0x10];
4850 u8 reserved_at_20[0x10];
4853 u8 reserved_at_40[0x8];
4856 u8 reserved_at_60[0x20];
4859 struct mlx5_ifc_qp_2err_out_bits {
4861 u8 reserved_at_8[0x18];
4865 u8 reserved_at_40[0x40];
4868 struct mlx5_ifc_qp_2err_in_bits {
4870 u8 reserved_at_10[0x10];
4872 u8 reserved_at_20[0x10];
4875 u8 reserved_at_40[0x8];
4878 u8 reserved_at_60[0x20];
4881 struct mlx5_ifc_page_fault_resume_out_bits {
4883 u8 reserved_at_8[0x18];
4887 u8 reserved_at_40[0x40];
4890 struct mlx5_ifc_page_fault_resume_in_bits {
4892 u8 reserved_at_10[0x10];
4894 u8 reserved_at_20[0x10];
4898 u8 reserved_at_41[0x4];
4899 u8 page_fault_type[0x3];
4902 u8 reserved_at_60[0x8];
4906 struct mlx5_ifc_nop_out_bits {
4908 u8 reserved_at_8[0x18];
4912 u8 reserved_at_40[0x40];
4915 struct mlx5_ifc_nop_in_bits {
4917 u8 reserved_at_10[0x10];
4919 u8 reserved_at_20[0x10];
4922 u8 reserved_at_40[0x40];
4925 struct mlx5_ifc_modify_vport_state_out_bits {
4927 u8 reserved_at_8[0x18];
4931 u8 reserved_at_40[0x40];
4934 struct mlx5_ifc_modify_vport_state_in_bits {
4936 u8 reserved_at_10[0x10];
4938 u8 reserved_at_20[0x10];
4941 u8 other_vport[0x1];
4942 u8 reserved_at_41[0xf];
4943 u8 vport_number[0x10];
4945 u8 reserved_at_60[0x18];
4946 u8 admin_state[0x4];
4947 u8 reserved_at_7c[0x4];
4950 struct mlx5_ifc_modify_tis_out_bits {
4952 u8 reserved_at_8[0x18];
4956 u8 reserved_at_40[0x40];
4959 struct mlx5_ifc_modify_tis_bitmask_bits {
4960 u8 reserved_at_0[0x20];
4962 u8 reserved_at_20[0x1d];
4963 u8 lag_tx_port_affinity[0x1];
4964 u8 strict_lag_tx_port_affinity[0x1];
4968 struct mlx5_ifc_modify_tis_in_bits {
4970 u8 reserved_at_10[0x10];
4972 u8 reserved_at_20[0x10];
4975 u8 reserved_at_40[0x8];
4978 u8 reserved_at_60[0x20];
4980 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4982 u8 reserved_at_c0[0x40];
4984 struct mlx5_ifc_tisc_bits ctx;
4987 struct mlx5_ifc_modify_tir_bitmask_bits {
4988 u8 reserved_at_0[0x20];
4990 u8 reserved_at_20[0x1b];
4992 u8 reserved_at_3c[0x1];
4994 u8 reserved_at_3e[0x1];
4998 struct mlx5_ifc_modify_tir_out_bits {
5000 u8 reserved_at_8[0x18];
5004 u8 reserved_at_40[0x40];
5007 struct mlx5_ifc_modify_tir_in_bits {
5009 u8 reserved_at_10[0x10];
5011 u8 reserved_at_20[0x10];
5014 u8 reserved_at_40[0x8];
5017 u8 reserved_at_60[0x20];
5019 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5021 u8 reserved_at_c0[0x40];
5023 struct mlx5_ifc_tirc_bits ctx;
5026 struct mlx5_ifc_modify_sq_out_bits {
5028 u8 reserved_at_8[0x18];
5032 u8 reserved_at_40[0x40];
5035 struct mlx5_ifc_modify_sq_in_bits {
5037 u8 reserved_at_10[0x10];
5039 u8 reserved_at_20[0x10];
5043 u8 reserved_at_44[0x4];
5046 u8 reserved_at_60[0x20];
5048 u8 modify_bitmask[0x40];
5050 u8 reserved_at_c0[0x40];
5052 struct mlx5_ifc_sqc_bits ctx;
5055 struct mlx5_ifc_modify_scheduling_element_out_bits {
5057 u8 reserved_at_8[0x18];
5061 u8 reserved_at_40[0x1c0];
5065 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5066 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5069 struct mlx5_ifc_modify_scheduling_element_in_bits {
5071 u8 reserved_at_10[0x10];
5073 u8 reserved_at_20[0x10];
5076 u8 scheduling_hierarchy[0x8];
5077 u8 reserved_at_48[0x18];
5079 u8 scheduling_element_id[0x20];
5081 u8 reserved_at_80[0x20];
5083 u8 modify_bitmask[0x20];
5085 u8 reserved_at_c0[0x40];
5087 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5089 u8 reserved_at_300[0x100];
5092 struct mlx5_ifc_modify_rqt_out_bits {
5094 u8 reserved_at_8[0x18];
5098 u8 reserved_at_40[0x40];
5101 struct mlx5_ifc_rqt_bitmask_bits {
5102 u8 reserved_at_0[0x20];
5104 u8 reserved_at_20[0x1f];
5108 struct mlx5_ifc_modify_rqt_in_bits {
5110 u8 reserved_at_10[0x10];
5112 u8 reserved_at_20[0x10];
5115 u8 reserved_at_40[0x8];
5118 u8 reserved_at_60[0x20];
5120 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5122 u8 reserved_at_c0[0x40];
5124 struct mlx5_ifc_rqtc_bits ctx;
5127 struct mlx5_ifc_modify_rq_out_bits {
5129 u8 reserved_at_8[0x18];
5133 u8 reserved_at_40[0x40];
5137 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5138 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5139 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5142 struct mlx5_ifc_modify_rq_in_bits {
5144 u8 reserved_at_10[0x10];
5146 u8 reserved_at_20[0x10];
5150 u8 reserved_at_44[0x4];
5153 u8 reserved_at_60[0x20];
5155 u8 modify_bitmask[0x40];
5157 u8 reserved_at_c0[0x40];
5159 struct mlx5_ifc_rqc_bits ctx;
5162 struct mlx5_ifc_modify_rmp_out_bits {
5164 u8 reserved_at_8[0x18];
5168 u8 reserved_at_40[0x40];
5171 struct mlx5_ifc_rmp_bitmask_bits {
5172 u8 reserved_at_0[0x20];
5174 u8 reserved_at_20[0x1f];
5178 struct mlx5_ifc_modify_rmp_in_bits {
5180 u8 reserved_at_10[0x10];
5182 u8 reserved_at_20[0x10];
5186 u8 reserved_at_44[0x4];
5189 u8 reserved_at_60[0x20];
5191 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5193 u8 reserved_at_c0[0x40];
5195 struct mlx5_ifc_rmpc_bits ctx;
5198 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5200 u8 reserved_at_8[0x18];
5204 u8 reserved_at_40[0x40];
5207 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5208 u8 reserved_at_0[0x16];
5213 u8 change_event[0x1];
5215 u8 permanent_address[0x1];
5216 u8 addresses_list[0x1];
5218 u8 reserved_at_1f[0x1];
5221 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5223 u8 reserved_at_10[0x10];
5225 u8 reserved_at_20[0x10];
5228 u8 other_vport[0x1];
5229 u8 reserved_at_41[0xf];
5230 u8 vport_number[0x10];
5232 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5234 u8 reserved_at_80[0x780];
5236 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5239 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5241 u8 reserved_at_8[0x18];
5245 u8 reserved_at_40[0x40];
5248 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5250 u8 reserved_at_10[0x10];
5252 u8 reserved_at_20[0x10];
5255 u8 other_vport[0x1];
5256 u8 reserved_at_41[0xb];
5258 u8 vport_number[0x10];
5260 u8 reserved_at_60[0x20];
5262 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5265 struct mlx5_ifc_modify_cq_out_bits {
5267 u8 reserved_at_8[0x18];
5271 u8 reserved_at_40[0x40];
5275 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5276 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5279 struct mlx5_ifc_modify_cq_in_bits {
5281 u8 reserved_at_10[0x10];
5283 u8 reserved_at_20[0x10];
5286 u8 reserved_at_40[0x8];
5289 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5291 struct mlx5_ifc_cqc_bits cq_context;
5293 u8 reserved_at_280[0x600];
5298 struct mlx5_ifc_modify_cong_status_out_bits {
5300 u8 reserved_at_8[0x18];
5304 u8 reserved_at_40[0x40];
5307 struct mlx5_ifc_modify_cong_status_in_bits {
5309 u8 reserved_at_10[0x10];
5311 u8 reserved_at_20[0x10];
5314 u8 reserved_at_40[0x18];
5316 u8 cong_protocol[0x4];
5320 u8 reserved_at_62[0x1e];
5323 struct mlx5_ifc_modify_cong_params_out_bits {
5325 u8 reserved_at_8[0x18];
5329 u8 reserved_at_40[0x40];
5332 struct mlx5_ifc_modify_cong_params_in_bits {
5334 u8 reserved_at_10[0x10];
5336 u8 reserved_at_20[0x10];
5339 u8 reserved_at_40[0x1c];
5340 u8 cong_protocol[0x4];
5342 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5344 u8 reserved_at_80[0x80];
5346 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5349 struct mlx5_ifc_manage_pages_out_bits {
5351 u8 reserved_at_8[0x18];
5355 u8 output_num_entries[0x20];
5357 u8 reserved_at_60[0x20];
5363 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5364 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5365 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5368 struct mlx5_ifc_manage_pages_in_bits {
5370 u8 reserved_at_10[0x10];
5372 u8 reserved_at_20[0x10];
5375 u8 reserved_at_40[0x10];
5376 u8 function_id[0x10];
5378 u8 input_num_entries[0x20];
5383 struct mlx5_ifc_mad_ifc_out_bits {
5385 u8 reserved_at_8[0x18];
5389 u8 reserved_at_40[0x40];
5391 u8 response_mad_packet[256][0x8];
5394 struct mlx5_ifc_mad_ifc_in_bits {
5396 u8 reserved_at_10[0x10];
5398 u8 reserved_at_20[0x10];
5401 u8 remote_lid[0x10];
5402 u8 reserved_at_50[0x8];
5405 u8 reserved_at_60[0x20];
5410 struct mlx5_ifc_init_hca_out_bits {
5412 u8 reserved_at_8[0x18];
5416 u8 reserved_at_40[0x40];
5419 struct mlx5_ifc_init_hca_in_bits {
5421 u8 reserved_at_10[0x10];
5423 u8 reserved_at_20[0x10];
5426 u8 reserved_at_40[0x40];
5429 struct mlx5_ifc_init2rtr_qp_out_bits {
5431 u8 reserved_at_8[0x18];
5435 u8 reserved_at_40[0x40];
5438 struct mlx5_ifc_init2rtr_qp_in_bits {
5440 u8 reserved_at_10[0x10];
5442 u8 reserved_at_20[0x10];
5445 u8 reserved_at_40[0x8];
5448 u8 reserved_at_60[0x20];
5450 u8 opt_param_mask[0x20];
5452 u8 reserved_at_a0[0x20];
5454 struct mlx5_ifc_qpc_bits qpc;
5456 u8 reserved_at_800[0x80];
5459 struct mlx5_ifc_init2init_qp_out_bits {
5461 u8 reserved_at_8[0x18];
5465 u8 reserved_at_40[0x40];
5468 struct mlx5_ifc_init2init_qp_in_bits {
5470 u8 reserved_at_10[0x10];
5472 u8 reserved_at_20[0x10];
5475 u8 reserved_at_40[0x8];
5478 u8 reserved_at_60[0x20];
5480 u8 opt_param_mask[0x20];
5482 u8 reserved_at_a0[0x20];
5484 struct mlx5_ifc_qpc_bits qpc;
5486 u8 reserved_at_800[0x80];
5489 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5491 u8 reserved_at_8[0x18];
5495 u8 reserved_at_40[0x40];
5497 u8 packet_headers_log[128][0x8];
5499 u8 packet_syndrome[64][0x8];
5502 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5504 u8 reserved_at_10[0x10];
5506 u8 reserved_at_20[0x10];
5509 u8 reserved_at_40[0x40];
5512 struct mlx5_ifc_gen_eqe_in_bits {
5514 u8 reserved_at_10[0x10];
5516 u8 reserved_at_20[0x10];
5519 u8 reserved_at_40[0x18];
5522 u8 reserved_at_60[0x20];
5527 struct mlx5_ifc_gen_eq_out_bits {
5529 u8 reserved_at_8[0x18];
5533 u8 reserved_at_40[0x40];
5536 struct mlx5_ifc_enable_hca_out_bits {
5538 u8 reserved_at_8[0x18];
5542 u8 reserved_at_40[0x20];
5545 struct mlx5_ifc_enable_hca_in_bits {
5547 u8 reserved_at_10[0x10];
5549 u8 reserved_at_20[0x10];
5552 u8 reserved_at_40[0x10];
5553 u8 function_id[0x10];
5555 u8 reserved_at_60[0x20];
5558 struct mlx5_ifc_drain_dct_out_bits {
5560 u8 reserved_at_8[0x18];
5564 u8 reserved_at_40[0x40];
5567 struct mlx5_ifc_drain_dct_in_bits {
5569 u8 reserved_at_10[0x10];
5571 u8 reserved_at_20[0x10];
5574 u8 reserved_at_40[0x8];
5577 u8 reserved_at_60[0x20];
5580 struct mlx5_ifc_disable_hca_out_bits {
5582 u8 reserved_at_8[0x18];
5586 u8 reserved_at_40[0x20];
5589 struct mlx5_ifc_disable_hca_in_bits {
5591 u8 reserved_at_10[0x10];
5593 u8 reserved_at_20[0x10];
5596 u8 reserved_at_40[0x10];
5597 u8 function_id[0x10];
5599 u8 reserved_at_60[0x20];
5602 struct mlx5_ifc_detach_from_mcg_out_bits {
5604 u8 reserved_at_8[0x18];
5608 u8 reserved_at_40[0x40];
5611 struct mlx5_ifc_detach_from_mcg_in_bits {
5613 u8 reserved_at_10[0x10];
5615 u8 reserved_at_20[0x10];
5618 u8 reserved_at_40[0x8];
5621 u8 reserved_at_60[0x20];
5623 u8 multicast_gid[16][0x8];
5626 struct mlx5_ifc_destroy_xrq_out_bits {
5628 u8 reserved_at_8[0x18];
5632 u8 reserved_at_40[0x40];
5635 struct mlx5_ifc_destroy_xrq_in_bits {
5637 u8 reserved_at_10[0x10];
5639 u8 reserved_at_20[0x10];
5642 u8 reserved_at_40[0x8];
5645 u8 reserved_at_60[0x20];
5648 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5650 u8 reserved_at_8[0x18];
5654 u8 reserved_at_40[0x40];
5657 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5659 u8 reserved_at_10[0x10];
5661 u8 reserved_at_20[0x10];
5664 u8 reserved_at_40[0x8];
5667 u8 reserved_at_60[0x20];
5670 struct mlx5_ifc_destroy_tis_out_bits {
5672 u8 reserved_at_8[0x18];
5676 u8 reserved_at_40[0x40];
5679 struct mlx5_ifc_destroy_tis_in_bits {
5681 u8 reserved_at_10[0x10];
5683 u8 reserved_at_20[0x10];
5686 u8 reserved_at_40[0x8];
5689 u8 reserved_at_60[0x20];
5692 struct mlx5_ifc_destroy_tir_out_bits {
5694 u8 reserved_at_8[0x18];
5698 u8 reserved_at_40[0x40];
5701 struct mlx5_ifc_destroy_tir_in_bits {
5703 u8 reserved_at_10[0x10];
5705 u8 reserved_at_20[0x10];
5708 u8 reserved_at_40[0x8];
5711 u8 reserved_at_60[0x20];
5714 struct mlx5_ifc_destroy_srq_out_bits {
5716 u8 reserved_at_8[0x18];
5720 u8 reserved_at_40[0x40];
5723 struct mlx5_ifc_destroy_srq_in_bits {
5725 u8 reserved_at_10[0x10];
5727 u8 reserved_at_20[0x10];
5730 u8 reserved_at_40[0x8];
5733 u8 reserved_at_60[0x20];
5736 struct mlx5_ifc_destroy_sq_out_bits {
5738 u8 reserved_at_8[0x18];
5742 u8 reserved_at_40[0x40];
5745 struct mlx5_ifc_destroy_sq_in_bits {
5747 u8 reserved_at_10[0x10];
5749 u8 reserved_at_20[0x10];
5752 u8 reserved_at_40[0x8];
5755 u8 reserved_at_60[0x20];
5758 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5760 u8 reserved_at_8[0x18];
5764 u8 reserved_at_40[0x1c0];
5767 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5769 u8 reserved_at_10[0x10];
5771 u8 reserved_at_20[0x10];
5774 u8 scheduling_hierarchy[0x8];
5775 u8 reserved_at_48[0x18];
5777 u8 scheduling_element_id[0x20];
5779 u8 reserved_at_80[0x180];
5782 struct mlx5_ifc_destroy_rqt_out_bits {
5784 u8 reserved_at_8[0x18];
5788 u8 reserved_at_40[0x40];
5791 struct mlx5_ifc_destroy_rqt_in_bits {
5793 u8 reserved_at_10[0x10];
5795 u8 reserved_at_20[0x10];
5798 u8 reserved_at_40[0x8];
5801 u8 reserved_at_60[0x20];
5804 struct mlx5_ifc_destroy_rq_out_bits {
5806 u8 reserved_at_8[0x18];
5810 u8 reserved_at_40[0x40];
5813 struct mlx5_ifc_destroy_rq_in_bits {
5815 u8 reserved_at_10[0x10];
5817 u8 reserved_at_20[0x10];
5820 u8 reserved_at_40[0x8];
5823 u8 reserved_at_60[0x20];
5826 struct mlx5_ifc_destroy_rmp_out_bits {
5828 u8 reserved_at_8[0x18];
5832 u8 reserved_at_40[0x40];
5835 struct mlx5_ifc_destroy_rmp_in_bits {
5837 u8 reserved_at_10[0x10];
5839 u8 reserved_at_20[0x10];
5842 u8 reserved_at_40[0x8];
5845 u8 reserved_at_60[0x20];
5848 struct mlx5_ifc_destroy_qp_out_bits {
5850 u8 reserved_at_8[0x18];
5854 u8 reserved_at_40[0x40];
5857 struct mlx5_ifc_destroy_qp_in_bits {
5859 u8 reserved_at_10[0x10];
5861 u8 reserved_at_20[0x10];
5864 u8 reserved_at_40[0x8];
5867 u8 reserved_at_60[0x20];
5870 struct mlx5_ifc_destroy_psv_out_bits {
5872 u8 reserved_at_8[0x18];
5876 u8 reserved_at_40[0x40];
5879 struct mlx5_ifc_destroy_psv_in_bits {
5881 u8 reserved_at_10[0x10];
5883 u8 reserved_at_20[0x10];
5886 u8 reserved_at_40[0x8];
5889 u8 reserved_at_60[0x20];
5892 struct mlx5_ifc_destroy_mkey_out_bits {
5894 u8 reserved_at_8[0x18];
5898 u8 reserved_at_40[0x40];
5901 struct mlx5_ifc_destroy_mkey_in_bits {
5903 u8 reserved_at_10[0x10];
5905 u8 reserved_at_20[0x10];
5908 u8 reserved_at_40[0x8];
5909 u8 mkey_index[0x18];
5911 u8 reserved_at_60[0x20];
5914 struct mlx5_ifc_destroy_flow_table_out_bits {
5916 u8 reserved_at_8[0x18];
5920 u8 reserved_at_40[0x40];
5923 struct mlx5_ifc_destroy_flow_table_in_bits {
5925 u8 reserved_at_10[0x10];
5927 u8 reserved_at_20[0x10];
5930 u8 other_vport[0x1];
5931 u8 reserved_at_41[0xf];
5932 u8 vport_number[0x10];
5934 u8 reserved_at_60[0x20];
5937 u8 reserved_at_88[0x18];
5939 u8 reserved_at_a0[0x8];
5942 u8 reserved_at_c0[0x140];
5945 struct mlx5_ifc_destroy_flow_group_out_bits {
5947 u8 reserved_at_8[0x18];
5951 u8 reserved_at_40[0x40];
5954 struct mlx5_ifc_destroy_flow_group_in_bits {
5956 u8 reserved_at_10[0x10];
5958 u8 reserved_at_20[0x10];
5961 u8 other_vport[0x1];
5962 u8 reserved_at_41[0xf];
5963 u8 vport_number[0x10];
5965 u8 reserved_at_60[0x20];
5968 u8 reserved_at_88[0x18];
5970 u8 reserved_at_a0[0x8];
5975 u8 reserved_at_e0[0x120];
5978 struct mlx5_ifc_destroy_eq_out_bits {
5980 u8 reserved_at_8[0x18];
5984 u8 reserved_at_40[0x40];
5987 struct mlx5_ifc_destroy_eq_in_bits {
5989 u8 reserved_at_10[0x10];
5991 u8 reserved_at_20[0x10];
5994 u8 reserved_at_40[0x18];
5997 u8 reserved_at_60[0x20];
6000 struct mlx5_ifc_destroy_dct_out_bits {
6002 u8 reserved_at_8[0x18];
6006 u8 reserved_at_40[0x40];
6009 struct mlx5_ifc_destroy_dct_in_bits {
6011 u8 reserved_at_10[0x10];
6013 u8 reserved_at_20[0x10];
6016 u8 reserved_at_40[0x8];
6019 u8 reserved_at_60[0x20];
6022 struct mlx5_ifc_destroy_cq_out_bits {
6024 u8 reserved_at_8[0x18];
6028 u8 reserved_at_40[0x40];
6031 struct mlx5_ifc_destroy_cq_in_bits {
6033 u8 reserved_at_10[0x10];
6035 u8 reserved_at_20[0x10];
6038 u8 reserved_at_40[0x8];
6041 u8 reserved_at_60[0x20];
6044 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6046 u8 reserved_at_8[0x18];
6050 u8 reserved_at_40[0x40];
6053 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6055 u8 reserved_at_10[0x10];
6057 u8 reserved_at_20[0x10];
6060 u8 reserved_at_40[0x20];
6062 u8 reserved_at_60[0x10];
6063 u8 vxlan_udp_port[0x10];
6066 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6068 u8 reserved_at_8[0x18];
6072 u8 reserved_at_40[0x40];
6075 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6077 u8 reserved_at_10[0x10];
6079 u8 reserved_at_20[0x10];
6082 u8 reserved_at_40[0x60];
6084 u8 reserved_at_a0[0x8];
6085 u8 table_index[0x18];
6087 u8 reserved_at_c0[0x140];
6090 struct mlx5_ifc_delete_fte_out_bits {
6092 u8 reserved_at_8[0x18];
6096 u8 reserved_at_40[0x40];
6099 struct mlx5_ifc_delete_fte_in_bits {
6101 u8 reserved_at_10[0x10];
6103 u8 reserved_at_20[0x10];
6106 u8 other_vport[0x1];
6107 u8 reserved_at_41[0xf];
6108 u8 vport_number[0x10];
6110 u8 reserved_at_60[0x20];
6113 u8 reserved_at_88[0x18];
6115 u8 reserved_at_a0[0x8];
6118 u8 reserved_at_c0[0x40];
6120 u8 flow_index[0x20];
6122 u8 reserved_at_120[0xe0];
6125 struct mlx5_ifc_dealloc_xrcd_out_bits {
6127 u8 reserved_at_8[0x18];
6131 u8 reserved_at_40[0x40];
6134 struct mlx5_ifc_dealloc_xrcd_in_bits {
6136 u8 reserved_at_10[0x10];
6138 u8 reserved_at_20[0x10];
6141 u8 reserved_at_40[0x8];
6144 u8 reserved_at_60[0x20];
6147 struct mlx5_ifc_dealloc_uar_out_bits {
6149 u8 reserved_at_8[0x18];
6153 u8 reserved_at_40[0x40];
6156 struct mlx5_ifc_dealloc_uar_in_bits {
6158 u8 reserved_at_10[0x10];
6160 u8 reserved_at_20[0x10];
6163 u8 reserved_at_40[0x8];
6166 u8 reserved_at_60[0x20];
6169 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6171 u8 reserved_at_8[0x18];
6175 u8 reserved_at_40[0x40];
6178 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6180 u8 reserved_at_10[0x10];
6182 u8 reserved_at_20[0x10];
6185 u8 reserved_at_40[0x8];
6186 u8 transport_domain[0x18];
6188 u8 reserved_at_60[0x20];
6191 struct mlx5_ifc_dealloc_q_counter_out_bits {
6193 u8 reserved_at_8[0x18];
6197 u8 reserved_at_40[0x40];
6200 struct mlx5_ifc_dealloc_q_counter_in_bits {
6202 u8 reserved_at_10[0x10];
6204 u8 reserved_at_20[0x10];
6207 u8 reserved_at_40[0x18];
6208 u8 counter_set_id[0x8];
6210 u8 reserved_at_60[0x20];
6213 struct mlx5_ifc_dealloc_pd_out_bits {
6215 u8 reserved_at_8[0x18];
6219 u8 reserved_at_40[0x40];
6222 struct mlx5_ifc_dealloc_pd_in_bits {
6224 u8 reserved_at_10[0x10];
6226 u8 reserved_at_20[0x10];
6229 u8 reserved_at_40[0x8];
6232 u8 reserved_at_60[0x20];
6235 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6237 u8 reserved_at_8[0x18];
6241 u8 reserved_at_40[0x40];
6244 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6246 u8 reserved_at_10[0x10];
6248 u8 reserved_at_20[0x10];
6251 u8 reserved_at_40[0x10];
6252 u8 flow_counter_id[0x10];
6254 u8 reserved_at_60[0x20];
6257 struct mlx5_ifc_create_xrq_out_bits {
6259 u8 reserved_at_8[0x18];
6263 u8 reserved_at_40[0x8];
6266 u8 reserved_at_60[0x20];
6269 struct mlx5_ifc_create_xrq_in_bits {
6271 u8 reserved_at_10[0x10];
6273 u8 reserved_at_20[0x10];
6276 u8 reserved_at_40[0x40];
6278 struct mlx5_ifc_xrqc_bits xrq_context;
6281 struct mlx5_ifc_create_xrc_srq_out_bits {
6283 u8 reserved_at_8[0x18];
6287 u8 reserved_at_40[0x8];
6290 u8 reserved_at_60[0x20];
6293 struct mlx5_ifc_create_xrc_srq_in_bits {
6295 u8 reserved_at_10[0x10];
6297 u8 reserved_at_20[0x10];
6300 u8 reserved_at_40[0x40];
6302 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6304 u8 reserved_at_280[0x600];
6309 struct mlx5_ifc_create_tis_out_bits {
6311 u8 reserved_at_8[0x18];
6315 u8 reserved_at_40[0x8];
6318 u8 reserved_at_60[0x20];
6321 struct mlx5_ifc_create_tis_in_bits {
6323 u8 reserved_at_10[0x10];
6325 u8 reserved_at_20[0x10];
6328 u8 reserved_at_40[0xc0];
6330 struct mlx5_ifc_tisc_bits ctx;
6333 struct mlx5_ifc_create_tir_out_bits {
6335 u8 reserved_at_8[0x18];
6339 u8 reserved_at_40[0x8];
6342 u8 reserved_at_60[0x20];
6345 struct mlx5_ifc_create_tir_in_bits {
6347 u8 reserved_at_10[0x10];
6349 u8 reserved_at_20[0x10];
6352 u8 reserved_at_40[0xc0];
6354 struct mlx5_ifc_tirc_bits ctx;
6357 struct mlx5_ifc_create_srq_out_bits {
6359 u8 reserved_at_8[0x18];
6363 u8 reserved_at_40[0x8];
6366 u8 reserved_at_60[0x20];
6369 struct mlx5_ifc_create_srq_in_bits {
6371 u8 reserved_at_10[0x10];
6373 u8 reserved_at_20[0x10];
6376 u8 reserved_at_40[0x40];
6378 struct mlx5_ifc_srqc_bits srq_context_entry;
6380 u8 reserved_at_280[0x600];
6385 struct mlx5_ifc_create_sq_out_bits {
6387 u8 reserved_at_8[0x18];
6391 u8 reserved_at_40[0x8];
6394 u8 reserved_at_60[0x20];
6397 struct mlx5_ifc_create_sq_in_bits {
6399 u8 reserved_at_10[0x10];
6401 u8 reserved_at_20[0x10];
6404 u8 reserved_at_40[0xc0];
6406 struct mlx5_ifc_sqc_bits ctx;
6409 struct mlx5_ifc_create_scheduling_element_out_bits {
6411 u8 reserved_at_8[0x18];
6415 u8 reserved_at_40[0x40];
6417 u8 scheduling_element_id[0x20];
6419 u8 reserved_at_a0[0x160];
6422 struct mlx5_ifc_create_scheduling_element_in_bits {
6424 u8 reserved_at_10[0x10];
6426 u8 reserved_at_20[0x10];
6429 u8 scheduling_hierarchy[0x8];
6430 u8 reserved_at_48[0x18];
6432 u8 reserved_at_60[0xa0];
6434 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6436 u8 reserved_at_300[0x100];
6439 struct mlx5_ifc_create_rqt_out_bits {
6441 u8 reserved_at_8[0x18];
6445 u8 reserved_at_40[0x8];
6448 u8 reserved_at_60[0x20];
6451 struct mlx5_ifc_create_rqt_in_bits {
6453 u8 reserved_at_10[0x10];
6455 u8 reserved_at_20[0x10];
6458 u8 reserved_at_40[0xc0];
6460 struct mlx5_ifc_rqtc_bits rqt_context;
6463 struct mlx5_ifc_create_rq_out_bits {
6465 u8 reserved_at_8[0x18];
6469 u8 reserved_at_40[0x8];
6472 u8 reserved_at_60[0x20];
6475 struct mlx5_ifc_create_rq_in_bits {
6477 u8 reserved_at_10[0x10];
6479 u8 reserved_at_20[0x10];
6482 u8 reserved_at_40[0xc0];
6484 struct mlx5_ifc_rqc_bits ctx;
6487 struct mlx5_ifc_create_rmp_out_bits {
6489 u8 reserved_at_8[0x18];
6493 u8 reserved_at_40[0x8];
6496 u8 reserved_at_60[0x20];
6499 struct mlx5_ifc_create_rmp_in_bits {
6501 u8 reserved_at_10[0x10];
6503 u8 reserved_at_20[0x10];
6506 u8 reserved_at_40[0xc0];
6508 struct mlx5_ifc_rmpc_bits ctx;
6511 struct mlx5_ifc_create_qp_out_bits {
6513 u8 reserved_at_8[0x18];
6517 u8 reserved_at_40[0x8];
6520 u8 reserved_at_60[0x20];
6523 struct mlx5_ifc_create_qp_in_bits {
6525 u8 reserved_at_10[0x10];
6527 u8 reserved_at_20[0x10];
6530 u8 reserved_at_40[0x40];
6532 u8 opt_param_mask[0x20];
6534 u8 reserved_at_a0[0x20];
6536 struct mlx5_ifc_qpc_bits qpc;
6538 u8 reserved_at_800[0x80];
6543 struct mlx5_ifc_create_psv_out_bits {
6545 u8 reserved_at_8[0x18];
6549 u8 reserved_at_40[0x40];
6551 u8 reserved_at_80[0x8];
6552 u8 psv0_index[0x18];
6554 u8 reserved_at_a0[0x8];
6555 u8 psv1_index[0x18];
6557 u8 reserved_at_c0[0x8];
6558 u8 psv2_index[0x18];
6560 u8 reserved_at_e0[0x8];
6561 u8 psv3_index[0x18];
6564 struct mlx5_ifc_create_psv_in_bits {
6566 u8 reserved_at_10[0x10];
6568 u8 reserved_at_20[0x10];
6572 u8 reserved_at_44[0x4];
6575 u8 reserved_at_60[0x20];
6578 struct mlx5_ifc_create_mkey_out_bits {
6580 u8 reserved_at_8[0x18];
6584 u8 reserved_at_40[0x8];
6585 u8 mkey_index[0x18];
6587 u8 reserved_at_60[0x20];
6590 struct mlx5_ifc_create_mkey_in_bits {
6592 u8 reserved_at_10[0x10];
6594 u8 reserved_at_20[0x10];
6597 u8 reserved_at_40[0x20];
6600 u8 reserved_at_61[0x1f];
6602 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6604 u8 reserved_at_280[0x80];
6606 u8 translations_octword_actual_size[0x20];
6608 u8 reserved_at_320[0x560];
6610 u8 klm_pas_mtt[0][0x20];
6613 struct mlx5_ifc_create_flow_table_out_bits {
6615 u8 reserved_at_8[0x18];
6619 u8 reserved_at_40[0x8];
6622 u8 reserved_at_60[0x20];
6625 struct mlx5_ifc_create_flow_table_in_bits {
6627 u8 reserved_at_10[0x10];
6629 u8 reserved_at_20[0x10];
6632 u8 other_vport[0x1];
6633 u8 reserved_at_41[0xf];
6634 u8 vport_number[0x10];
6636 u8 reserved_at_60[0x20];
6639 u8 reserved_at_88[0x18];
6641 u8 reserved_at_a0[0x20];
6645 u8 reserved_at_c2[0x2];
6646 u8 table_miss_mode[0x4];
6648 u8 reserved_at_d0[0x8];
6651 u8 reserved_at_e0[0x8];
6652 u8 table_miss_id[0x18];
6654 u8 reserved_at_100[0x8];
6655 u8 lag_master_next_table_id[0x18];
6657 u8 reserved_at_120[0x80];
6660 struct mlx5_ifc_create_flow_group_out_bits {
6662 u8 reserved_at_8[0x18];
6666 u8 reserved_at_40[0x8];
6669 u8 reserved_at_60[0x20];
6673 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6674 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6675 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6678 struct mlx5_ifc_create_flow_group_in_bits {
6680 u8 reserved_at_10[0x10];
6682 u8 reserved_at_20[0x10];
6685 u8 other_vport[0x1];
6686 u8 reserved_at_41[0xf];
6687 u8 vport_number[0x10];
6689 u8 reserved_at_60[0x20];
6692 u8 reserved_at_88[0x18];
6694 u8 reserved_at_a0[0x8];
6697 u8 reserved_at_c0[0x20];
6699 u8 start_flow_index[0x20];
6701 u8 reserved_at_100[0x20];
6703 u8 end_flow_index[0x20];
6705 u8 reserved_at_140[0xa0];
6707 u8 reserved_at_1e0[0x18];
6708 u8 match_criteria_enable[0x8];
6710 struct mlx5_ifc_fte_match_param_bits match_criteria;
6712 u8 reserved_at_1200[0xe00];
6715 struct mlx5_ifc_create_eq_out_bits {
6717 u8 reserved_at_8[0x18];
6721 u8 reserved_at_40[0x18];
6724 u8 reserved_at_60[0x20];
6727 struct mlx5_ifc_create_eq_in_bits {
6729 u8 reserved_at_10[0x10];
6731 u8 reserved_at_20[0x10];
6734 u8 reserved_at_40[0x40];
6736 struct mlx5_ifc_eqc_bits eq_context_entry;
6738 u8 reserved_at_280[0x40];
6740 u8 event_bitmask[0x40];
6742 u8 reserved_at_300[0x580];
6747 struct mlx5_ifc_create_dct_out_bits {
6749 u8 reserved_at_8[0x18];
6753 u8 reserved_at_40[0x8];
6756 u8 reserved_at_60[0x20];
6759 struct mlx5_ifc_create_dct_in_bits {
6761 u8 reserved_at_10[0x10];
6763 u8 reserved_at_20[0x10];
6766 u8 reserved_at_40[0x40];
6768 struct mlx5_ifc_dctc_bits dct_context_entry;
6770 u8 reserved_at_280[0x180];
6773 struct mlx5_ifc_create_cq_out_bits {
6775 u8 reserved_at_8[0x18];
6779 u8 reserved_at_40[0x8];
6782 u8 reserved_at_60[0x20];
6785 struct mlx5_ifc_create_cq_in_bits {
6787 u8 reserved_at_10[0x10];
6789 u8 reserved_at_20[0x10];
6792 u8 reserved_at_40[0x40];
6794 struct mlx5_ifc_cqc_bits cq_context;
6796 u8 reserved_at_280[0x600];
6801 struct mlx5_ifc_config_int_moderation_out_bits {
6803 u8 reserved_at_8[0x18];
6807 u8 reserved_at_40[0x4];
6809 u8 int_vector[0x10];
6811 u8 reserved_at_60[0x20];
6815 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6816 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6819 struct mlx5_ifc_config_int_moderation_in_bits {
6821 u8 reserved_at_10[0x10];
6823 u8 reserved_at_20[0x10];
6826 u8 reserved_at_40[0x4];
6828 u8 int_vector[0x10];
6830 u8 reserved_at_60[0x20];
6833 struct mlx5_ifc_attach_to_mcg_out_bits {
6835 u8 reserved_at_8[0x18];
6839 u8 reserved_at_40[0x40];
6842 struct mlx5_ifc_attach_to_mcg_in_bits {
6844 u8 reserved_at_10[0x10];
6846 u8 reserved_at_20[0x10];
6849 u8 reserved_at_40[0x8];
6852 u8 reserved_at_60[0x20];
6854 u8 multicast_gid[16][0x8];
6857 struct mlx5_ifc_arm_xrq_out_bits {
6859 u8 reserved_at_8[0x18];
6863 u8 reserved_at_40[0x40];
6866 struct mlx5_ifc_arm_xrq_in_bits {
6868 u8 reserved_at_10[0x10];
6870 u8 reserved_at_20[0x10];
6873 u8 reserved_at_40[0x8];
6876 u8 reserved_at_60[0x10];
6880 struct mlx5_ifc_arm_xrc_srq_out_bits {
6882 u8 reserved_at_8[0x18];
6886 u8 reserved_at_40[0x40];
6890 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6893 struct mlx5_ifc_arm_xrc_srq_in_bits {
6895 u8 reserved_at_10[0x10];
6897 u8 reserved_at_20[0x10];
6900 u8 reserved_at_40[0x8];
6903 u8 reserved_at_60[0x10];
6907 struct mlx5_ifc_arm_rq_out_bits {
6909 u8 reserved_at_8[0x18];
6913 u8 reserved_at_40[0x40];
6917 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6918 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6921 struct mlx5_ifc_arm_rq_in_bits {
6923 u8 reserved_at_10[0x10];
6925 u8 reserved_at_20[0x10];
6928 u8 reserved_at_40[0x8];
6929 u8 srq_number[0x18];
6931 u8 reserved_at_60[0x10];
6935 struct mlx5_ifc_arm_dct_out_bits {
6937 u8 reserved_at_8[0x18];
6941 u8 reserved_at_40[0x40];
6944 struct mlx5_ifc_arm_dct_in_bits {
6946 u8 reserved_at_10[0x10];
6948 u8 reserved_at_20[0x10];
6951 u8 reserved_at_40[0x8];
6952 u8 dct_number[0x18];
6954 u8 reserved_at_60[0x20];
6957 struct mlx5_ifc_alloc_xrcd_out_bits {
6959 u8 reserved_at_8[0x18];
6963 u8 reserved_at_40[0x8];
6966 u8 reserved_at_60[0x20];
6969 struct mlx5_ifc_alloc_xrcd_in_bits {
6971 u8 reserved_at_10[0x10];
6973 u8 reserved_at_20[0x10];
6976 u8 reserved_at_40[0x40];
6979 struct mlx5_ifc_alloc_uar_out_bits {
6981 u8 reserved_at_8[0x18];
6985 u8 reserved_at_40[0x8];
6988 u8 reserved_at_60[0x20];
6991 struct mlx5_ifc_alloc_uar_in_bits {
6993 u8 reserved_at_10[0x10];
6995 u8 reserved_at_20[0x10];
6998 u8 reserved_at_40[0x40];
7001 struct mlx5_ifc_alloc_transport_domain_out_bits {
7003 u8 reserved_at_8[0x18];
7007 u8 reserved_at_40[0x8];
7008 u8 transport_domain[0x18];
7010 u8 reserved_at_60[0x20];
7013 struct mlx5_ifc_alloc_transport_domain_in_bits {
7015 u8 reserved_at_10[0x10];
7017 u8 reserved_at_20[0x10];
7020 u8 reserved_at_40[0x40];
7023 struct mlx5_ifc_alloc_q_counter_out_bits {
7025 u8 reserved_at_8[0x18];
7029 u8 reserved_at_40[0x18];
7030 u8 counter_set_id[0x8];
7032 u8 reserved_at_60[0x20];
7035 struct mlx5_ifc_alloc_q_counter_in_bits {
7037 u8 reserved_at_10[0x10];
7039 u8 reserved_at_20[0x10];
7042 u8 reserved_at_40[0x40];
7045 struct mlx5_ifc_alloc_pd_out_bits {
7047 u8 reserved_at_8[0x18];
7051 u8 reserved_at_40[0x8];
7054 u8 reserved_at_60[0x20];
7057 struct mlx5_ifc_alloc_pd_in_bits {
7059 u8 reserved_at_10[0x10];
7061 u8 reserved_at_20[0x10];
7064 u8 reserved_at_40[0x40];
7067 struct mlx5_ifc_alloc_flow_counter_out_bits {
7069 u8 reserved_at_8[0x18];
7073 u8 reserved_at_40[0x10];
7074 u8 flow_counter_id[0x10];
7076 u8 reserved_at_60[0x20];
7079 struct mlx5_ifc_alloc_flow_counter_in_bits {
7081 u8 reserved_at_10[0x10];
7083 u8 reserved_at_20[0x10];
7086 u8 reserved_at_40[0x40];
7089 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7091 u8 reserved_at_8[0x18];
7095 u8 reserved_at_40[0x40];
7098 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7100 u8 reserved_at_10[0x10];
7102 u8 reserved_at_20[0x10];
7105 u8 reserved_at_40[0x20];
7107 u8 reserved_at_60[0x10];
7108 u8 vxlan_udp_port[0x10];
7111 struct mlx5_ifc_set_rate_limit_out_bits {
7113 u8 reserved_at_8[0x18];
7117 u8 reserved_at_40[0x40];
7120 struct mlx5_ifc_set_rate_limit_in_bits {
7122 u8 reserved_at_10[0x10];
7124 u8 reserved_at_20[0x10];
7127 u8 reserved_at_40[0x10];
7128 u8 rate_limit_index[0x10];
7130 u8 reserved_at_60[0x20];
7132 u8 rate_limit[0x20];
7135 struct mlx5_ifc_access_register_out_bits {
7137 u8 reserved_at_8[0x18];
7141 u8 reserved_at_40[0x40];
7143 u8 register_data[0][0x20];
7147 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7148 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7151 struct mlx5_ifc_access_register_in_bits {
7153 u8 reserved_at_10[0x10];
7155 u8 reserved_at_20[0x10];
7158 u8 reserved_at_40[0x10];
7159 u8 register_id[0x10];
7163 u8 register_data[0][0x20];
7166 struct mlx5_ifc_sltp_reg_bits {
7171 u8 reserved_at_12[0x2];
7173 u8 reserved_at_18[0x8];
7175 u8 reserved_at_20[0x20];
7177 u8 reserved_at_40[0x7];
7183 u8 reserved_at_60[0xc];
7184 u8 ob_preemp_mode[0x4];
7188 u8 reserved_at_80[0x20];
7191 struct mlx5_ifc_slrg_reg_bits {
7196 u8 reserved_at_12[0x2];
7198 u8 reserved_at_18[0x8];
7200 u8 time_to_link_up[0x10];
7201 u8 reserved_at_30[0xc];
7202 u8 grade_lane_speed[0x4];
7204 u8 grade_version[0x8];
7207 u8 reserved_at_60[0x4];
7208 u8 height_grade_type[0x4];
7209 u8 height_grade[0x18];
7214 u8 reserved_at_a0[0x10];
7215 u8 height_sigma[0x10];
7217 u8 reserved_at_c0[0x20];
7219 u8 reserved_at_e0[0x4];
7220 u8 phase_grade_type[0x4];
7221 u8 phase_grade[0x18];
7223 u8 reserved_at_100[0x8];
7224 u8 phase_eo_pos[0x8];
7225 u8 reserved_at_110[0x8];
7226 u8 phase_eo_neg[0x8];
7228 u8 ffe_set_tested[0x10];
7229 u8 test_errors_per_lane[0x10];
7232 struct mlx5_ifc_pvlc_reg_bits {
7233 u8 reserved_at_0[0x8];
7235 u8 reserved_at_10[0x10];
7237 u8 reserved_at_20[0x1c];
7240 u8 reserved_at_40[0x1c];
7243 u8 reserved_at_60[0x1c];
7244 u8 vl_operational[0x4];
7247 struct mlx5_ifc_pude_reg_bits {
7250 u8 reserved_at_10[0x4];
7251 u8 admin_status[0x4];
7252 u8 reserved_at_18[0x4];
7253 u8 oper_status[0x4];
7255 u8 reserved_at_20[0x60];
7258 struct mlx5_ifc_ptys_reg_bits {
7259 u8 reserved_at_0[0x1];
7260 u8 an_disable_admin[0x1];
7261 u8 an_disable_cap[0x1];
7262 u8 reserved_at_3[0x5];
7264 u8 reserved_at_10[0xd];
7268 u8 reserved_at_24[0x3c];
7270 u8 eth_proto_capability[0x20];
7272 u8 ib_link_width_capability[0x10];
7273 u8 ib_proto_capability[0x10];
7275 u8 reserved_at_a0[0x20];
7277 u8 eth_proto_admin[0x20];
7279 u8 ib_link_width_admin[0x10];
7280 u8 ib_proto_admin[0x10];
7282 u8 reserved_at_100[0x20];
7284 u8 eth_proto_oper[0x20];
7286 u8 ib_link_width_oper[0x10];
7287 u8 ib_proto_oper[0x10];
7289 u8 reserved_at_160[0x20];
7291 u8 eth_proto_lp_advertise[0x20];
7293 u8 reserved_at_1a0[0x60];
7296 struct mlx5_ifc_mlcr_reg_bits {
7297 u8 reserved_at_0[0x8];
7299 u8 reserved_at_10[0x20];
7301 u8 beacon_duration[0x10];
7302 u8 reserved_at_40[0x10];
7304 u8 beacon_remain[0x10];
7307 struct mlx5_ifc_ptas_reg_bits {
7308 u8 reserved_at_0[0x20];
7310 u8 algorithm_options[0x10];
7311 u8 reserved_at_30[0x4];
7312 u8 repetitions_mode[0x4];
7313 u8 num_of_repetitions[0x8];
7315 u8 grade_version[0x8];
7316 u8 height_grade_type[0x4];
7317 u8 phase_grade_type[0x4];
7318 u8 height_grade_weight[0x8];
7319 u8 phase_grade_weight[0x8];
7321 u8 gisim_measure_bits[0x10];
7322 u8 adaptive_tap_measure_bits[0x10];
7324 u8 ber_bath_high_error_threshold[0x10];
7325 u8 ber_bath_mid_error_threshold[0x10];
7327 u8 ber_bath_low_error_threshold[0x10];
7328 u8 one_ratio_high_threshold[0x10];
7330 u8 one_ratio_high_mid_threshold[0x10];
7331 u8 one_ratio_low_mid_threshold[0x10];
7333 u8 one_ratio_low_threshold[0x10];
7334 u8 ndeo_error_threshold[0x10];
7336 u8 mixer_offset_step_size[0x10];
7337 u8 reserved_at_110[0x8];
7338 u8 mix90_phase_for_voltage_bath[0x8];
7340 u8 mixer_offset_start[0x10];
7341 u8 mixer_offset_end[0x10];
7343 u8 reserved_at_140[0x15];
7344 u8 ber_test_time[0xb];
7347 struct mlx5_ifc_pspa_reg_bits {
7351 u8 reserved_at_18[0x8];
7353 u8 reserved_at_20[0x20];
7356 struct mlx5_ifc_pqdr_reg_bits {
7357 u8 reserved_at_0[0x8];
7359 u8 reserved_at_10[0x5];
7361 u8 reserved_at_18[0x6];
7364 u8 reserved_at_20[0x20];
7366 u8 reserved_at_40[0x10];
7367 u8 min_threshold[0x10];
7369 u8 reserved_at_60[0x10];
7370 u8 max_threshold[0x10];
7372 u8 reserved_at_80[0x10];
7373 u8 mark_probability_denominator[0x10];
7375 u8 reserved_at_a0[0x60];
7378 struct mlx5_ifc_ppsc_reg_bits {
7379 u8 reserved_at_0[0x8];
7381 u8 reserved_at_10[0x10];
7383 u8 reserved_at_20[0x60];
7385 u8 reserved_at_80[0x1c];
7388 u8 reserved_at_a0[0x1c];
7389 u8 wrps_status[0x4];
7391 u8 reserved_at_c0[0x8];
7392 u8 up_threshold[0x8];
7393 u8 reserved_at_d0[0x8];
7394 u8 down_threshold[0x8];
7396 u8 reserved_at_e0[0x20];
7398 u8 reserved_at_100[0x1c];
7401 u8 reserved_at_120[0x1c];
7402 u8 srps_status[0x4];
7404 u8 reserved_at_140[0x40];
7407 struct mlx5_ifc_pplr_reg_bits {
7408 u8 reserved_at_0[0x8];
7410 u8 reserved_at_10[0x10];
7412 u8 reserved_at_20[0x8];
7414 u8 reserved_at_30[0x8];
7418 struct mlx5_ifc_pplm_reg_bits {
7419 u8 reserved_at_0[0x8];
7421 u8 reserved_at_10[0x10];
7423 u8 reserved_at_20[0x20];
7425 u8 port_profile_mode[0x8];
7426 u8 static_port_profile[0x8];
7427 u8 active_port_profile[0x8];
7428 u8 reserved_at_58[0x8];
7430 u8 retransmission_active[0x8];
7431 u8 fec_mode_active[0x18];
7433 u8 reserved_at_80[0x20];
7436 struct mlx5_ifc_ppcnt_reg_bits {
7440 u8 reserved_at_12[0x8];
7444 u8 reserved_at_21[0x1c];
7447 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7450 struct mlx5_ifc_mpcnt_reg_bits {
7451 u8 reserved_at_0[0x8];
7453 u8 reserved_at_10[0xa];
7457 u8 reserved_at_21[0x1f];
7459 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7462 struct mlx5_ifc_ppad_reg_bits {
7463 u8 reserved_at_0[0x3];
7465 u8 reserved_at_4[0x4];
7471 u8 reserved_at_40[0x40];
7474 struct mlx5_ifc_pmtu_reg_bits {
7475 u8 reserved_at_0[0x8];
7477 u8 reserved_at_10[0x10];
7480 u8 reserved_at_30[0x10];
7483 u8 reserved_at_50[0x10];
7486 u8 reserved_at_70[0x10];
7489 struct mlx5_ifc_pmpr_reg_bits {
7490 u8 reserved_at_0[0x8];
7492 u8 reserved_at_10[0x10];
7494 u8 reserved_at_20[0x18];
7495 u8 attenuation_5g[0x8];
7497 u8 reserved_at_40[0x18];
7498 u8 attenuation_7g[0x8];
7500 u8 reserved_at_60[0x18];
7501 u8 attenuation_12g[0x8];
7504 struct mlx5_ifc_pmpe_reg_bits {
7505 u8 reserved_at_0[0x8];
7507 u8 reserved_at_10[0xc];
7508 u8 module_status[0x4];
7510 u8 reserved_at_20[0x60];
7513 struct mlx5_ifc_pmpc_reg_bits {
7514 u8 module_state_updated[32][0x8];
7517 struct mlx5_ifc_pmlpn_reg_bits {
7518 u8 reserved_at_0[0x4];
7519 u8 mlpn_status[0x4];
7521 u8 reserved_at_10[0x10];
7524 u8 reserved_at_21[0x1f];
7527 struct mlx5_ifc_pmlp_reg_bits {
7529 u8 reserved_at_1[0x7];
7531 u8 reserved_at_10[0x8];
7534 u8 lane0_module_mapping[0x20];
7536 u8 lane1_module_mapping[0x20];
7538 u8 lane2_module_mapping[0x20];
7540 u8 lane3_module_mapping[0x20];
7542 u8 reserved_at_a0[0x160];
7545 struct mlx5_ifc_pmaos_reg_bits {
7546 u8 reserved_at_0[0x8];
7548 u8 reserved_at_10[0x4];
7549 u8 admin_status[0x4];
7550 u8 reserved_at_18[0x4];
7551 u8 oper_status[0x4];
7555 u8 reserved_at_22[0x1c];
7558 u8 reserved_at_40[0x40];
7561 struct mlx5_ifc_plpc_reg_bits {
7562 u8 reserved_at_0[0x4];
7564 u8 reserved_at_10[0x4];
7566 u8 reserved_at_18[0x8];
7568 u8 reserved_at_20[0x10];
7569 u8 lane_speed[0x10];
7571 u8 reserved_at_40[0x17];
7573 u8 fec_mode_policy[0x8];
7575 u8 retransmission_capability[0x8];
7576 u8 fec_mode_capability[0x18];
7578 u8 retransmission_support_admin[0x8];
7579 u8 fec_mode_support_admin[0x18];
7581 u8 retransmission_request_admin[0x8];
7582 u8 fec_mode_request_admin[0x18];
7584 u8 reserved_at_c0[0x80];
7587 struct mlx5_ifc_plib_reg_bits {
7588 u8 reserved_at_0[0x8];
7590 u8 reserved_at_10[0x8];
7593 u8 reserved_at_20[0x60];
7596 struct mlx5_ifc_plbf_reg_bits {
7597 u8 reserved_at_0[0x8];
7599 u8 reserved_at_10[0xd];
7602 u8 reserved_at_20[0x20];
7605 struct mlx5_ifc_pipg_reg_bits {
7606 u8 reserved_at_0[0x8];
7608 u8 reserved_at_10[0x10];
7611 u8 reserved_at_21[0x19];
7613 u8 reserved_at_3e[0x2];
7616 struct mlx5_ifc_pifr_reg_bits {
7617 u8 reserved_at_0[0x8];
7619 u8 reserved_at_10[0x10];
7621 u8 reserved_at_20[0xe0];
7623 u8 port_filter[8][0x20];
7625 u8 port_filter_update_en[8][0x20];
7628 struct mlx5_ifc_pfcc_reg_bits {
7629 u8 reserved_at_0[0x8];
7631 u8 reserved_at_10[0x10];
7634 u8 reserved_at_24[0x4];
7635 u8 prio_mask_tx[0x8];
7636 u8 reserved_at_30[0x8];
7637 u8 prio_mask_rx[0x8];
7641 u8 reserved_at_42[0x6];
7643 u8 reserved_at_50[0x10];
7647 u8 reserved_at_62[0x6];
7649 u8 reserved_at_70[0x10];
7651 u8 reserved_at_80[0x80];
7654 struct mlx5_ifc_pelc_reg_bits {
7656 u8 reserved_at_4[0x4];
7658 u8 reserved_at_10[0x10];
7661 u8 op_capability[0x8];
7667 u8 capability[0x40];
7673 u8 reserved_at_140[0x80];
7676 struct mlx5_ifc_peir_reg_bits {
7677 u8 reserved_at_0[0x8];
7679 u8 reserved_at_10[0x10];
7681 u8 reserved_at_20[0xc];
7682 u8 error_count[0x4];
7683 u8 reserved_at_30[0x10];
7685 u8 reserved_at_40[0xc];
7687 u8 reserved_at_50[0x8];
7691 struct mlx5_ifc_pcam_enhanced_features_bits {
7692 u8 reserved_at_0[0x7e];
7694 u8 ppcnt_discard_group[0x1];
7695 u8 ppcnt_statistical_group[0x1];
7698 struct mlx5_ifc_pcam_reg_bits {
7699 u8 reserved_at_0[0x8];
7700 u8 feature_group[0x8];
7701 u8 reserved_at_10[0x8];
7702 u8 access_reg_group[0x8];
7704 u8 reserved_at_20[0x20];
7707 u8 reserved_at_0[0x80];
7708 } port_access_reg_cap_mask;
7710 u8 reserved_at_c0[0x80];
7713 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7714 u8 reserved_at_0[0x80];
7717 u8 reserved_at_1c0[0xc0];
7720 struct mlx5_ifc_mcam_enhanced_features_bits {
7721 u8 reserved_at_0[0x7f];
7723 u8 pcie_performance_group[0x1];
7726 struct mlx5_ifc_mcam_reg_bits {
7727 u8 reserved_at_0[0x8];
7728 u8 feature_group[0x8];
7729 u8 reserved_at_10[0x8];
7730 u8 access_reg_group[0x8];
7732 u8 reserved_at_20[0x20];
7735 u8 reserved_at_0[0x80];
7736 } mng_access_reg_cap_mask;
7738 u8 reserved_at_c0[0x80];
7741 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7742 u8 reserved_at_0[0x80];
7743 } mng_feature_cap_mask;
7745 u8 reserved_at_1c0[0x80];
7748 struct mlx5_ifc_pcap_reg_bits {
7749 u8 reserved_at_0[0x8];
7751 u8 reserved_at_10[0x10];
7753 u8 port_capability_mask[4][0x20];
7756 struct mlx5_ifc_paos_reg_bits {
7759 u8 reserved_at_10[0x4];
7760 u8 admin_status[0x4];
7761 u8 reserved_at_18[0x4];
7762 u8 oper_status[0x4];
7766 u8 reserved_at_22[0x1c];
7769 u8 reserved_at_40[0x40];
7772 struct mlx5_ifc_pamp_reg_bits {
7773 u8 reserved_at_0[0x8];
7774 u8 opamp_group[0x8];
7775 u8 reserved_at_10[0xc];
7776 u8 opamp_group_type[0x4];
7778 u8 start_index[0x10];
7779 u8 reserved_at_30[0x4];
7780 u8 num_of_indices[0xc];
7782 u8 index_data[18][0x10];
7785 struct mlx5_ifc_pcmr_reg_bits {
7786 u8 reserved_at_0[0x8];
7788 u8 reserved_at_10[0x2e];
7790 u8 reserved_at_3f[0x1f];
7792 u8 reserved_at_5f[0x1];
7795 struct mlx5_ifc_lane_2_module_mapping_bits {
7796 u8 reserved_at_0[0x6];
7798 u8 reserved_at_8[0x6];
7800 u8 reserved_at_10[0x8];
7804 struct mlx5_ifc_bufferx_reg_bits {
7805 u8 reserved_at_0[0x6];
7808 u8 reserved_at_8[0xc];
7811 u8 xoff_threshold[0x10];
7812 u8 xon_threshold[0x10];
7815 struct mlx5_ifc_set_node_in_bits {
7816 u8 node_description[64][0x8];
7819 struct mlx5_ifc_register_power_settings_bits {
7820 u8 reserved_at_0[0x18];
7821 u8 power_settings_level[0x8];
7823 u8 reserved_at_20[0x60];
7826 struct mlx5_ifc_register_host_endianness_bits {
7828 u8 reserved_at_1[0x1f];
7830 u8 reserved_at_20[0x60];
7833 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7834 u8 reserved_at_0[0x20];
7838 u8 addressh_63_32[0x20];
7840 u8 addressl_31_0[0x20];
7843 struct mlx5_ifc_ud_adrs_vector_bits {
7847 u8 reserved_at_41[0x7];
7848 u8 destination_qp_dct[0x18];
7850 u8 static_rate[0x4];
7851 u8 sl_eth_prio[0x4];
7854 u8 rlid_udp_sport[0x10];
7856 u8 reserved_at_80[0x20];
7858 u8 rmac_47_16[0x20];
7864 u8 reserved_at_e0[0x1];
7866 u8 reserved_at_e2[0x2];
7867 u8 src_addr_index[0x8];
7868 u8 flow_label[0x14];
7870 u8 rgid_rip[16][0x8];
7873 struct mlx5_ifc_pages_req_event_bits {
7874 u8 reserved_at_0[0x10];
7875 u8 function_id[0x10];
7879 u8 reserved_at_40[0xa0];
7882 struct mlx5_ifc_eqe_bits {
7883 u8 reserved_at_0[0x8];
7885 u8 reserved_at_10[0x8];
7886 u8 event_sub_type[0x8];
7888 u8 reserved_at_20[0xe0];
7890 union mlx5_ifc_event_auto_bits event_data;
7892 u8 reserved_at_1e0[0x10];
7894 u8 reserved_at_1f8[0x7];
7899 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7902 struct mlx5_ifc_cmd_queue_entry_bits {
7904 u8 reserved_at_8[0x18];
7906 u8 input_length[0x20];
7908 u8 input_mailbox_pointer_63_32[0x20];
7910 u8 input_mailbox_pointer_31_9[0x17];
7911 u8 reserved_at_77[0x9];
7913 u8 command_input_inline_data[16][0x8];
7915 u8 command_output_inline_data[16][0x8];
7917 u8 output_mailbox_pointer_63_32[0x20];
7919 u8 output_mailbox_pointer_31_9[0x17];
7920 u8 reserved_at_1b7[0x9];
7922 u8 output_length[0x20];
7926 u8 reserved_at_1f0[0x8];
7931 struct mlx5_ifc_cmd_out_bits {
7933 u8 reserved_at_8[0x18];
7937 u8 command_output[0x20];
7940 struct mlx5_ifc_cmd_in_bits {
7942 u8 reserved_at_10[0x10];
7944 u8 reserved_at_20[0x10];
7947 u8 command[0][0x20];
7950 struct mlx5_ifc_cmd_if_box_bits {
7951 u8 mailbox_data[512][0x8];
7953 u8 reserved_at_1000[0x180];
7955 u8 next_pointer_63_32[0x20];
7957 u8 next_pointer_31_10[0x16];
7958 u8 reserved_at_11b6[0xa];
7960 u8 block_number[0x20];
7962 u8 reserved_at_11e0[0x8];
7964 u8 ctrl_signature[0x8];
7968 struct mlx5_ifc_mtt_bits {
7969 u8 ptag_63_32[0x20];
7972 u8 reserved_at_38[0x6];
7977 struct mlx5_ifc_query_wol_rol_out_bits {
7979 u8 reserved_at_8[0x18];
7983 u8 reserved_at_40[0x10];
7987 u8 reserved_at_60[0x20];
7990 struct mlx5_ifc_query_wol_rol_in_bits {
7992 u8 reserved_at_10[0x10];
7994 u8 reserved_at_20[0x10];
7997 u8 reserved_at_40[0x40];
8000 struct mlx5_ifc_set_wol_rol_out_bits {
8002 u8 reserved_at_8[0x18];
8006 u8 reserved_at_40[0x40];
8009 struct mlx5_ifc_set_wol_rol_in_bits {
8011 u8 reserved_at_10[0x10];
8013 u8 reserved_at_20[0x10];
8016 u8 rol_mode_valid[0x1];
8017 u8 wol_mode_valid[0x1];
8018 u8 reserved_at_42[0xe];
8022 u8 reserved_at_60[0x20];
8026 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8027 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8028 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8032 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8033 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8034 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8038 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8039 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8040 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8041 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8042 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8043 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8044 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8045 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8046 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8047 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8048 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8051 struct mlx5_ifc_initial_seg_bits {
8052 u8 fw_rev_minor[0x10];
8053 u8 fw_rev_major[0x10];
8055 u8 cmd_interface_rev[0x10];
8056 u8 fw_rev_subminor[0x10];
8058 u8 reserved_at_40[0x40];
8060 u8 cmdq_phy_addr_63_32[0x20];
8062 u8 cmdq_phy_addr_31_12[0x14];
8063 u8 reserved_at_b4[0x2];
8064 u8 nic_interface[0x2];
8065 u8 log_cmdq_size[0x4];
8066 u8 log_cmdq_stride[0x4];
8068 u8 command_doorbell_vector[0x20];
8070 u8 reserved_at_e0[0xf00];
8072 u8 initializing[0x1];
8073 u8 reserved_at_fe1[0x4];
8074 u8 nic_interface_supported[0x3];
8075 u8 reserved_at_fe8[0x18];
8077 struct mlx5_ifc_health_buffer_bits health_buffer;
8079 u8 no_dram_nic_offset[0x20];
8081 u8 reserved_at_1220[0x6e40];
8083 u8 reserved_at_8060[0x1f];
8086 u8 health_syndrome[0x8];
8087 u8 health_counter[0x18];
8089 u8 reserved_at_80a0[0x17fc0];
8092 struct mlx5_ifc_mtpps_reg_bits {
8093 u8 reserved_at_0[0xc];
8094 u8 cap_number_of_pps_pins[0x4];
8095 u8 reserved_at_10[0x4];
8096 u8 cap_max_num_of_pps_in_pins[0x4];
8097 u8 reserved_at_18[0x4];
8098 u8 cap_max_num_of_pps_out_pins[0x4];
8100 u8 reserved_at_20[0x24];
8101 u8 cap_pin_3_mode[0x4];
8102 u8 reserved_at_48[0x4];
8103 u8 cap_pin_2_mode[0x4];
8104 u8 reserved_at_50[0x4];
8105 u8 cap_pin_1_mode[0x4];
8106 u8 reserved_at_58[0x4];
8107 u8 cap_pin_0_mode[0x4];
8109 u8 reserved_at_60[0x4];
8110 u8 cap_pin_7_mode[0x4];
8111 u8 reserved_at_68[0x4];
8112 u8 cap_pin_6_mode[0x4];
8113 u8 reserved_at_70[0x4];
8114 u8 cap_pin_5_mode[0x4];
8115 u8 reserved_at_78[0x4];
8116 u8 cap_pin_4_mode[0x4];
8118 u8 reserved_at_80[0x80];
8121 u8 reserved_at_101[0xb];
8123 u8 reserved_at_110[0x4];
8127 u8 reserved_at_120[0x20];
8129 u8 time_stamp[0x40];
8131 u8 out_pulse_duration[0x10];
8132 u8 out_periodic_adjustment[0x10];
8134 u8 reserved_at_1a0[0x60];
8137 struct mlx5_ifc_mtppse_reg_bits {
8138 u8 reserved_at_0[0x18];
8141 u8 reserved_at_21[0x1b];
8142 u8 event_generation_mode[0x4];
8143 u8 reserved_at_40[0x40];
8146 union mlx5_ifc_ports_control_registers_document_bits {
8147 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8148 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8149 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8150 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8151 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8152 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8153 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8154 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8155 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8156 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8157 struct mlx5_ifc_paos_reg_bits paos_reg;
8158 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8159 struct mlx5_ifc_peir_reg_bits peir_reg;
8160 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8161 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8162 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8163 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8164 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8165 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8166 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8167 struct mlx5_ifc_plib_reg_bits plib_reg;
8168 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8169 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8170 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8171 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8172 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8173 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8174 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8175 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8176 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8177 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8178 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8179 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8180 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8181 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8182 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8183 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8184 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8185 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8186 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8187 struct mlx5_ifc_pude_reg_bits pude_reg;
8188 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8189 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8190 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8191 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8192 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8193 u8 reserved_at_0[0x60e0];
8196 union mlx5_ifc_debug_enhancements_document_bits {
8197 struct mlx5_ifc_health_buffer_bits health_buffer;
8198 u8 reserved_at_0[0x200];
8201 union mlx5_ifc_uplink_pci_interface_document_bits {
8202 struct mlx5_ifc_initial_seg_bits initial_seg;
8203 u8 reserved_at_0[0x20060];
8206 struct mlx5_ifc_set_flow_table_root_out_bits {
8208 u8 reserved_at_8[0x18];
8212 u8 reserved_at_40[0x40];
8215 struct mlx5_ifc_set_flow_table_root_in_bits {
8217 u8 reserved_at_10[0x10];
8219 u8 reserved_at_20[0x10];
8222 u8 other_vport[0x1];
8223 u8 reserved_at_41[0xf];
8224 u8 vport_number[0x10];
8226 u8 reserved_at_60[0x20];
8229 u8 reserved_at_88[0x18];
8231 u8 reserved_at_a0[0x8];
8234 u8 reserved_at_c0[0x8];
8235 u8 underlay_qpn[0x18];
8236 u8 reserved_at_e0[0x120];
8240 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8241 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8244 struct mlx5_ifc_modify_flow_table_out_bits {
8246 u8 reserved_at_8[0x18];
8250 u8 reserved_at_40[0x40];
8253 struct mlx5_ifc_modify_flow_table_in_bits {
8255 u8 reserved_at_10[0x10];
8257 u8 reserved_at_20[0x10];
8260 u8 other_vport[0x1];
8261 u8 reserved_at_41[0xf];
8262 u8 vport_number[0x10];
8264 u8 reserved_at_60[0x10];
8265 u8 modify_field_select[0x10];
8268 u8 reserved_at_88[0x18];
8270 u8 reserved_at_a0[0x8];
8273 u8 reserved_at_c0[0x4];
8274 u8 table_miss_mode[0x4];
8275 u8 reserved_at_c8[0x18];
8277 u8 reserved_at_e0[0x8];
8278 u8 table_miss_id[0x18];
8280 u8 reserved_at_100[0x8];
8281 u8 lag_master_next_table_id[0x18];
8283 u8 reserved_at_120[0x80];
8286 struct mlx5_ifc_ets_tcn_config_reg_bits {
8290 u8 reserved_at_3[0x9];
8292 u8 reserved_at_10[0x9];
8293 u8 bw_allocation[0x7];
8295 u8 reserved_at_20[0xc];
8296 u8 max_bw_units[0x4];
8297 u8 reserved_at_30[0x8];
8298 u8 max_bw_value[0x8];
8301 struct mlx5_ifc_ets_global_config_reg_bits {
8302 u8 reserved_at_0[0x2];
8304 u8 reserved_at_3[0x1d];
8306 u8 reserved_at_20[0xc];
8307 u8 max_bw_units[0x4];
8308 u8 reserved_at_30[0x8];
8309 u8 max_bw_value[0x8];
8312 struct mlx5_ifc_qetc_reg_bits {
8313 u8 reserved_at_0[0x8];
8314 u8 port_number[0x8];
8315 u8 reserved_at_10[0x30];
8317 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8318 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8321 struct mlx5_ifc_qtct_reg_bits {
8322 u8 reserved_at_0[0x8];
8323 u8 port_number[0x8];
8324 u8 reserved_at_10[0xd];
8327 u8 reserved_at_20[0x1d];
8331 struct mlx5_ifc_mcia_reg_bits {
8333 u8 reserved_at_1[0x7];
8335 u8 reserved_at_10[0x8];
8338 u8 i2c_device_address[0x8];
8339 u8 page_number[0x8];
8340 u8 device_address[0x10];
8342 u8 reserved_at_40[0x10];
8345 u8 reserved_at_60[0x20];
8361 struct mlx5_ifc_dcbx_param_bits {
8362 u8 dcbx_cee_cap[0x1];
8363 u8 dcbx_ieee_cap[0x1];
8364 u8 dcbx_standby_cap[0x1];
8365 u8 reserved_at_0[0x5];
8366 u8 port_number[0x8];
8367 u8 reserved_at_10[0xa];
8368 u8 max_application_table_size[6];
8369 u8 reserved_at_20[0x15];
8370 u8 version_oper[0x3];
8371 u8 reserved_at_38[5];
8372 u8 version_admin[0x3];
8373 u8 willing_admin[0x1];
8374 u8 reserved_at_41[0x3];
8375 u8 pfc_cap_oper[0x4];
8376 u8 reserved_at_48[0x4];
8377 u8 pfc_cap_admin[0x4];
8378 u8 reserved_at_50[0x4];
8379 u8 num_of_tc_oper[0x4];
8380 u8 reserved_at_58[0x4];
8381 u8 num_of_tc_admin[0x4];
8382 u8 remote_willing[0x1];
8383 u8 reserved_at_61[3];
8384 u8 remote_pfc_cap[4];
8385 u8 reserved_at_68[0x14];
8386 u8 remote_num_of_tc[0x4];
8387 u8 reserved_at_80[0x18];
8389 u8 reserved_at_a0[0x160];
8392 struct mlx5_ifc_lagc_bits {
8393 u8 reserved_at_0[0x1d];
8396 u8 reserved_at_20[0x14];
8397 u8 tx_remap_affinity_2[0x4];
8398 u8 reserved_at_38[0x4];
8399 u8 tx_remap_affinity_1[0x4];
8402 struct mlx5_ifc_create_lag_out_bits {
8404 u8 reserved_at_8[0x18];
8408 u8 reserved_at_40[0x40];
8411 struct mlx5_ifc_create_lag_in_bits {
8413 u8 reserved_at_10[0x10];
8415 u8 reserved_at_20[0x10];
8418 struct mlx5_ifc_lagc_bits ctx;
8421 struct mlx5_ifc_modify_lag_out_bits {
8423 u8 reserved_at_8[0x18];
8427 u8 reserved_at_40[0x40];
8430 struct mlx5_ifc_modify_lag_in_bits {
8432 u8 reserved_at_10[0x10];
8434 u8 reserved_at_20[0x10];
8437 u8 reserved_at_40[0x20];
8438 u8 field_select[0x20];
8440 struct mlx5_ifc_lagc_bits ctx;
8443 struct mlx5_ifc_query_lag_out_bits {
8445 u8 reserved_at_8[0x18];
8449 u8 reserved_at_40[0x40];
8451 struct mlx5_ifc_lagc_bits ctx;
8454 struct mlx5_ifc_query_lag_in_bits {
8456 u8 reserved_at_10[0x10];
8458 u8 reserved_at_20[0x10];
8461 u8 reserved_at_40[0x40];
8464 struct mlx5_ifc_destroy_lag_out_bits {
8466 u8 reserved_at_8[0x18];
8470 u8 reserved_at_40[0x40];
8473 struct mlx5_ifc_destroy_lag_in_bits {
8475 u8 reserved_at_10[0x10];
8477 u8 reserved_at_20[0x10];
8480 u8 reserved_at_40[0x40];
8483 struct mlx5_ifc_create_vport_lag_out_bits {
8485 u8 reserved_at_8[0x18];
8489 u8 reserved_at_40[0x40];
8492 struct mlx5_ifc_create_vport_lag_in_bits {
8494 u8 reserved_at_10[0x10];
8496 u8 reserved_at_20[0x10];
8499 u8 reserved_at_40[0x40];
8502 struct mlx5_ifc_destroy_vport_lag_out_bits {
8504 u8 reserved_at_8[0x18];
8508 u8 reserved_at_40[0x40];
8511 struct mlx5_ifc_destroy_vport_lag_in_bits {
8513 u8 reserved_at_10[0x10];
8515 u8 reserved_at_20[0x10];
8518 u8 reserved_at_40[0x40];
8521 #endif /* MLX5_IFC_H */