include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  71         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  72         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  73         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  74         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  75         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  76         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  77         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  78         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  79         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  80         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  81         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  82         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  83         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  84         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  85         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  86         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  87         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  88         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  89         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  90         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  91         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  92         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  93         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  94         MLX5_CMD_OP_CREATE_QP                     = 0x500,
  95         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
  96         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
  97         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
  98         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
  99         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 100         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 101         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 102         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 103         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 104         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 105         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 106         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 107         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 108         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 109         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 110         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 111         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 112         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 113         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 114         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 115         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 116         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 117         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 118         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 119         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 120         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 121         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 122         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 123         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 124         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 125         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 126         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 127         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 128         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 129         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 130         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 131         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 132         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 133         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 134         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 135         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 136         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 137         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 138         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 139         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 140         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 141         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 142         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 143         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 144         MLX5_CMD_OP_DETTACH_FROM_MCG              = 0x807,
 145         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 146         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 147         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 148         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 149         MLX5_CMD_OP_NOP                           = 0x80d,
 150         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 151         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 152         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 153         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 154         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 155         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 156         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 157         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 158         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 159         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 160         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 161         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 162         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 163         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 164         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 165         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 166         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 167         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 168         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 169         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 170         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 171         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 172         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 173         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 174         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 175         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 176         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 177         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 178         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 179         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 180         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 181         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 182         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 183         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 184         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 185         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 186         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 187         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 188         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 189         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 190         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 191         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 192         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 193         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 194         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 195         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 196         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938
 197 };
 198
 199 struct mlx5_ifc_flow_table_fields_supported_bits {
 200         u8         outer_dmac[0x1];
 201         u8         outer_smac[0x1];
 202         u8         outer_ether_type[0x1];
 203         u8         reserved_0[0x1];
 204         u8         outer_first_prio[0x1];
 205         u8         outer_first_cfi[0x1];
 206         u8         outer_first_vid[0x1];
 207         u8         reserved_1[0x1];
 208         u8         outer_second_prio[0x1];
 209         u8         outer_second_cfi[0x1];
 210         u8         outer_second_vid[0x1];
 211         u8         reserved_2[0x1];
 212         u8         outer_sip[0x1];
 213         u8         outer_dip[0x1];
 214         u8         outer_frag[0x1];
 215         u8         outer_ip_protocol[0x1];
 216         u8         outer_ip_ecn[0x1];
 217         u8         outer_ip_dscp[0x1];
 218         u8         outer_udp_sport[0x1];
 219         u8         outer_udp_dport[0x1];
 220         u8         outer_tcp_sport[0x1];
 221         u8         outer_tcp_dport[0x1];
 222         u8         outer_tcp_flags[0x1];
 223         u8         outer_gre_protocol[0x1];
 224         u8         outer_gre_key[0x1];
 225         u8         outer_vxlan_vni[0x1];
 226         u8         reserved_3[0x5];
 227         u8         source_eswitch_port[0x1];
 228
 229         u8         inner_dmac[0x1];
 230         u8         inner_smac[0x1];
 231         u8         inner_ether_type[0x1];
 232         u8         reserved_4[0x1];
 233         u8         inner_first_prio[0x1];
 234         u8         inner_first_cfi[0x1];
 235         u8         inner_first_vid[0x1];
 236         u8         reserved_5[0x1];
 237         u8         inner_second_prio[0x1];
 238         u8         inner_second_cfi[0x1];
 239         u8         inner_second_vid[0x1];
 240         u8         reserved_6[0x1];
 241         u8         inner_sip[0x1];
 242         u8         inner_dip[0x1];
 243         u8         inner_frag[0x1];
 244         u8         inner_ip_protocol[0x1];
 245         u8         inner_ip_ecn[0x1];
 246         u8         inner_ip_dscp[0x1];
 247         u8         inner_udp_sport[0x1];
 248         u8         inner_udp_dport[0x1];
 249         u8         inner_tcp_sport[0x1];
 250         u8         inner_tcp_dport[0x1];
 251         u8         inner_tcp_flags[0x1];
 252         u8         reserved_7[0x9];
 253
 254         u8         reserved_8[0x40];
 255 };
 256
 257 struct mlx5_ifc_flow_table_prop_layout_bits {
 258         u8         ft_support[0x1];
 259         u8         reserved_0[0x1f];
 260
 261         u8         reserved_1[0x2];
 262         u8         log_max_ft_size[0x6];
 263         u8         reserved_2[0x10];
 264         u8         max_ft_level[0x8];
 265
 266         u8         reserved_3[0x20];
 267
 268         u8         reserved_4[0x18];
 269         u8         log_max_ft_num[0x8];
 270
 271         u8         reserved_5[0x18];
 272         u8         log_max_destination[0x8];
 273
 274         u8         reserved_6[0x18];
 275         u8         log_max_flow[0x8];
 276
 277         u8         reserved_7[0x40];
 278
 279         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 280
 281         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 282 };
 283
 284 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 285         u8         send[0x1];
 286         u8         receive[0x1];
 287         u8         write[0x1];
 288         u8         read[0x1];
 289         u8         reserved_0[0x1];
 290         u8         srq_receive[0x1];
 291         u8         reserved_1[0x1a];
 292 };
 293
 294 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 295         u8         smac_47_16[0x20];
 296
 297         u8         smac_15_0[0x10];
 298         u8         ethertype[0x10];
 299
 300         u8         dmac_47_16[0x20];
 301
 302         u8         dmac_15_0[0x10];
 303         u8         first_prio[0x3];
 304         u8         first_cfi[0x1];
 305         u8         first_vid[0xc];
 306
 307         u8         ip_protocol[0x8];
 308         u8         ip_dscp[0x6];
 309         u8         ip_ecn[0x2];
 310         u8         vlan_tag[0x1];
 311         u8         reserved_0[0x1];
 312         u8         frag[0x1];
 313         u8         reserved_1[0x4];
 314         u8         tcp_flags[0x9];
 315
 316         u8         tcp_sport[0x10];
 317         u8         tcp_dport[0x10];
 318
 319         u8         reserved_2[0x20];
 320
 321         u8         udp_sport[0x10];
 322         u8         udp_dport[0x10];
 323
 324         u8         src_ip[4][0x20];
 325
 326         u8         dst_ip[4][0x20];
 327 };
 328
 329 struct mlx5_ifc_fte_match_set_misc_bits {
 330         u8         reserved_0[0x20];
 331
 332         u8         reserved_1[0x10];
 333         u8         source_port[0x10];
 334
 335         u8         outer_second_prio[0x3];
 336         u8         outer_second_cfi[0x1];
 337         u8         outer_second_vid[0xc];
 338         u8         inner_second_prio[0x3];
 339         u8         inner_second_cfi[0x1];
 340         u8         inner_second_vid[0xc];
 341
 342         u8         outer_second_vlan_tag[0x1];
 343         u8         inner_second_vlan_tag[0x1];
 344         u8         reserved_2[0xe];
 345         u8         gre_protocol[0x10];
 346
 347         u8         gre_key_h[0x18];
 348         u8         gre_key_l[0x8];
 349
 350         u8         vxlan_vni[0x18];
 351         u8         reserved_3[0x8];
 352
 353         u8         reserved_4[0x20];
 354
 355         u8         reserved_5[0xc];
 356         u8         outer_ipv6_flow_label[0x14];
 357
 358         u8         reserved_6[0xc];
 359         u8         inner_ipv6_flow_label[0x14];
 360
 361         u8         reserved_7[0xe0];
 362 };
 363
 364 struct mlx5_ifc_cmd_pas_bits {
 365         u8         pa_h[0x20];
 366
 367         u8         pa_l[0x14];
 368         u8         reserved_0[0xc];
 369 };
 370
 371 struct mlx5_ifc_uint64_bits {
 372         u8         hi[0x20];
 373
 374         u8         lo[0x20];
 375 };
 376
 377 enum {
 378         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 379         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 380         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 381         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 382         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 383         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 384         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 385         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 386         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 387         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 388 };
 389
 390 struct mlx5_ifc_ads_bits {
 391         u8         fl[0x1];
 392         u8         free_ar[0x1];
 393         u8         reserved_0[0xe];
 394         u8         pkey_index[0x10];
 395
 396         u8         reserved_1[0x8];
 397         u8         grh[0x1];
 398         u8         mlid[0x7];
 399         u8         rlid[0x10];
 400
 401         u8         ack_timeout[0x5];
 402         u8         reserved_2[0x3];
 403         u8         src_addr_index[0x8];
 404         u8         reserved_3[0x4];
 405         u8         stat_rate[0x4];
 406         u8         hop_limit[0x8];
 407
 408         u8         reserved_4[0x4];
 409         u8         tclass[0x8];
 410         u8         flow_label[0x14];
 411
 412         u8         rgid_rip[16][0x8];
 413
 414         u8         reserved_5[0x4];
 415         u8         f_dscp[0x1];
 416         u8         f_ecn[0x1];
 417         u8         reserved_6[0x1];
 418         u8         f_eth_prio[0x1];
 419         u8         ecn[0x2];
 420         u8         dscp[0x6];
 421         u8         udp_sport[0x10];
 422
 423         u8         dei_cfi[0x1];
 424         u8         eth_prio[0x3];
 425         u8         sl[0x4];
 426         u8         port[0x8];
 427         u8         rmac_47_32[0x10];
 428
 429         u8         rmac_31_0[0x20];
 430 };
 431
 432 struct mlx5_ifc_flow_table_nic_cap_bits {
 433         u8         reserved_0[0x200];
 434
 435         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 436
 437         u8         reserved_1[0x200];
 438
 439         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 440
 441         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 442
 443         u8         reserved_2[0x200];
 444
 445         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 446
 447         u8         reserved_3[0x7200];
 448 };
 449
 450 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 451         u8         csum_cap[0x1];
 452         u8         vlan_cap[0x1];
 453         u8         lro_cap[0x1];
 454         u8         lro_psh_flag[0x1];
 455         u8         lro_time_stamp[0x1];
 456         u8         reserved_0[0x6];
 457         u8         max_lso_cap[0x5];
 458         u8         reserved_1[0x4];
 459         u8         rss_ind_tbl_cap[0x4];
 460         u8         reserved_2[0x3];
 461         u8         tunnel_lso_const_out_ip_id[0x1];
 462         u8         reserved_3[0x2];
 463         u8         tunnel_statless_gre[0x1];
 464         u8         tunnel_stateless_vxlan[0x1];
 465
 466         u8         reserved_4[0x20];
 467
 468         u8         reserved_5[0x10];
 469         u8         lro_min_mss_size[0x10];
 470
 471         u8         reserved_6[0x120];
 472
 473         u8         lro_timer_supported_periods[4][0x20];
 474
 475         u8         reserved_7[0x600];
 476 };
 477
 478 struct mlx5_ifc_roce_cap_bits {
 479         u8         roce_apm[0x1];
 480         u8         reserved_0[0x1f];
 481
 482         u8         reserved_1[0x60];
 483
 484         u8         reserved_2[0xc];
 485         u8         l3_type[0x4];
 486         u8         reserved_3[0x8];
 487         u8         roce_version[0x8];
 488
 489         u8         reserved_4[0x10];
 490         u8         r_roce_dest_udp_port[0x10];
 491
 492         u8         r_roce_max_src_udp_port[0x10];
 493         u8         r_roce_min_src_udp_port[0x10];
 494
 495         u8         reserved_5[0x10];
 496         u8         roce_address_table_size[0x10];
 497
 498         u8         reserved_6[0x700];
 499 };
 500
 501 enum {
 502         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 503         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 504         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 505         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 506         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 507         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 508         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 509         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 510         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 511 };
 512
 513 enum {
 514         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 515         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 516         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 517         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 518         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 519         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 520         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 521         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 522         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 523 };
 524
 525 struct mlx5_ifc_atomic_caps_bits {
 526         u8         reserved_0[0x40];
 527
 528         u8         atomic_req_endianness[0x1];
 529         u8         reserved_1[0x1f];
 530
 531         u8         reserved_2[0x20];
 532
 533         u8         reserved_3[0x10];
 534         u8         atomic_operations[0x10];
 535
 536         u8         reserved_4[0x10];
 537         u8         atomic_size_qp[0x10];
 538
 539         u8         reserved_5[0x10];
 540         u8         atomic_size_dc[0x10];
 541
 542         u8         reserved_6[0x720];
 543 };
 544
 545 struct mlx5_ifc_odp_cap_bits {
 546         u8         reserved_0[0x40];
 547
 548         u8         sig[0x1];
 549         u8         reserved_1[0x1f];
 550
 551         u8         reserved_2[0x20];
 552
 553         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 554
 555         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 556
 557         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 558
 559         u8         reserved_3[0x720];
 560 };
 561
 562 enum {
 563         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 564         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 565         MLX5_WQ_TYPE_STRQ         = 0x2,
 566 };
 567
 568 enum {
 569         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 570         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 571 };
 572
 573 enum {
 574         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 575         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 576         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 577         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 578         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 579 };
 580
 581 enum {
 582         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 583         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 584         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 585         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 586         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 587         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 588 };
 589
 590 enum {
 591         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 592         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 593 };
 594
 595 enum {
 596         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 597         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 598         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 599 };
 600
 601 enum {
 602         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 603         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 604 };
 605
 606 struct mlx5_ifc_cmd_hca_cap_bits {
 607         u8         reserved_0[0x80];
 608
 609         u8         log_max_srq_sz[0x8];
 610         u8         log_max_qp_sz[0x8];
 611         u8         reserved_1[0xb];
 612         u8         log_max_qp[0x5];
 613
 614         u8         reserved_2[0xb];
 615         u8         log_max_srq[0x5];
 616         u8         reserved_3[0x10];
 617
 618         u8         reserved_4[0x8];
 619         u8         log_max_cq_sz[0x8];
 620         u8         reserved_5[0xb];
 621         u8         log_max_cq[0x5];
 622
 623         u8         log_max_eq_sz[0x8];
 624         u8         reserved_6[0x2];
 625         u8         log_max_mkey[0x6];
 626         u8         reserved_7[0xc];
 627         u8         log_max_eq[0x4];
 628
 629         u8         max_indirection[0x8];
 630         u8         reserved_8[0x1];
 631         u8         log_max_mrw_sz[0x7];
 632         u8         reserved_9[0x2];
 633         u8         log_max_bsf_list_size[0x6];
 634         u8         reserved_10[0x2];
 635         u8         log_max_klm_list_size[0x6];
 636
 637         u8         reserved_11[0xa];
 638         u8         log_max_ra_req_dc[0x6];
 639         u8         reserved_12[0xa];
 640         u8         log_max_ra_res_dc[0x6];
 641
 642         u8         reserved_13[0xa];
 643         u8         log_max_ra_req_qp[0x6];
 644         u8         reserved_14[0xa];
 645         u8         log_max_ra_res_qp[0x6];
 646
 647         u8         pad_cap[0x1];
 648         u8         cc_query_allowed[0x1];
 649         u8         cc_modify_allowed[0x1];
 650         u8         reserved_15[0xd];
 651         u8         gid_table_size[0x10];
 652
 653         u8         out_of_seq_cnt[0x1];
 654         u8         vport_counters[0x1];
 655         u8         reserved_16[0x4];
 656         u8         max_qp_cnt[0xa];
 657         u8         pkey_table_size[0x10];
 658
 659         u8         vport_group_manager[0x1];
 660         u8         vhca_group_manager[0x1];
 661         u8         ib_virt[0x1];
 662         u8         eth_virt[0x1];
 663         u8         reserved_17[0x1];
 664         u8         ets[0x1];
 665         u8         nic_flow_table[0x1];
 666         u8         reserved_18[0x4];
 667         u8         local_ca_ack_delay[0x5];
 668         u8         reserved_19[0x6];
 669         u8         port_type[0x2];
 670         u8         num_ports[0x8];
 671
 672         u8         reserved_20[0x3];
 673         u8         log_max_msg[0x5];
 674         u8         reserved_21[0x18];
 675
 676         u8         stat_rate_support[0x10];
 677         u8         reserved_22[0xc];
 678         u8         cqe_version[0x4];
 679
 680         u8         compact_address_vector[0x1];
 681         u8         reserved_23[0xe];
 682         u8         drain_sigerr[0x1];
 683         u8         cmdif_checksum[0x2];
 684         u8         sigerr_cqe[0x1];
 685         u8         reserved_24[0x1];
 686         u8         wq_signature[0x1];
 687         u8         sctr_data_cqe[0x1];
 688         u8         reserved_25[0x1];
 689         u8         sho[0x1];
 690         u8         tph[0x1];
 691         u8         rf[0x1];
 692         u8         dct[0x1];
 693         u8         reserved_26[0x1];
 694         u8         eth_net_offloads[0x1];
 695         u8         roce[0x1];
 696         u8         atomic[0x1];
 697         u8         reserved_27[0x1];
 698
 699         u8         cq_oi[0x1];
 700         u8         cq_resize[0x1];
 701         u8         cq_moderation[0x1];
 702         u8         reserved_28[0x3];
 703         u8         cq_eq_remap[0x1];
 704         u8         pg[0x1];
 705         u8         block_lb_mc[0x1];
 706         u8         reserved_29[0x1];
 707         u8         scqe_break_moderation[0x1];
 708         u8         reserved_30[0x1];
 709         u8         cd[0x1];
 710         u8         reserved_31[0x1];
 711         u8         apm[0x1];
 712         u8         reserved_32[0x7];
 713         u8         qkv[0x1];
 714         u8         pkv[0x1];
 715         u8         reserved_33[0x4];
 716         u8         xrc[0x1];
 717         u8         ud[0x1];
 718         u8         uc[0x1];
 719         u8         rc[0x1];
 720
 721         u8         reserved_34[0xa];
 722         u8         uar_sz[0x6];
 723         u8         reserved_35[0x8];
 724         u8         log_pg_sz[0x8];
 725
 726         u8         bf[0x1];
 727         u8         reserved_36[0x1];
 728         u8         pad_tx_eth_packet[0x1];
 729         u8         reserved_37[0x8];
 730         u8         log_bf_reg_size[0x5];
 731         u8         reserved_38[0x10];
 732
 733         u8         reserved_39[0x10];
 734         u8         max_wqe_sz_sq[0x10];
 735
 736         u8         reserved_40[0x10];
 737         u8         max_wqe_sz_rq[0x10];
 738
 739         u8         reserved_41[0x10];
 740         u8         max_wqe_sz_sq_dc[0x10];
 741
 742         u8         reserved_42[0x7];
 743         u8         max_qp_mcg[0x19];
 744
 745         u8         reserved_43[0x18];
 746         u8         log_max_mcg[0x8];
 747
 748         u8         reserved_44[0x3];
 749         u8         log_max_transport_domain[0x5];
 750         u8         reserved_45[0x3];
 751         u8         log_max_pd[0x5];
 752         u8         reserved_46[0xb];
 753         u8         log_max_xrcd[0x5];
 754
 755         u8         reserved_47[0x20];
 756
 757         u8         reserved_48[0x3];
 758         u8         log_max_rq[0x5];
 759         u8         reserved_49[0x3];
 760         u8         log_max_sq[0x5];
 761         u8         reserved_50[0x3];
 762         u8         log_max_tir[0x5];
 763         u8         reserved_51[0x3];
 764         u8         log_max_tis[0x5];
 765
 766         u8         basic_cyclic_rcv_wqe[0x1];
 767         u8         reserved_52[0x2];
 768         u8         log_max_rmp[0x5];
 769         u8         reserved_53[0x3];
 770         u8         log_max_rqt[0x5];
 771         u8         reserved_54[0x3];
 772         u8         log_max_rqt_size[0x5];
 773         u8         reserved_55[0x3];
 774         u8         log_max_tis_per_sq[0x5];
 775
 776         u8         reserved_56[0x3];
 777         u8         log_max_stride_sz_rq[0x5];
 778         u8         reserved_57[0x3];
 779         u8         log_min_stride_sz_rq[0x5];
 780         u8         reserved_58[0x3];
 781         u8         log_max_stride_sz_sq[0x5];
 782         u8         reserved_59[0x3];
 783         u8         log_min_stride_sz_sq[0x5];
 784
 785         u8         reserved_60[0x1b];
 786         u8         log_max_wq_sz[0x5];
 787
 788         u8         reserved_61[0xa0];
 789
 790         u8         reserved_62[0x3];
 791         u8         log_max_l2_table[0x5];
 792         u8         reserved_63[0x8];
 793         u8         log_uar_page_sz[0x10];
 794
 795         u8         reserved_64[0x100];
 796
 797         u8         reserved_65[0x1f];
 798         u8         cqe_zip[0x1];
 799
 800         u8         cqe_zip_timeout[0x10];
 801         u8         cqe_zip_max_num[0x10];
 802
 803         u8         reserved_66[0x220];
 804 };
 805
 806 enum {
 807         MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_FLOW_TABLE_  = 0x1,
 808         MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_TIR          = 0x2,
 809 };
 810
 811 struct mlx5_ifc_dest_format_struct_bits {
 812         u8         destination_type[0x8];
 813         u8         destination_id[0x18];
 814
 815         u8         reserved_0[0x20];
 816 };
 817
 818 struct mlx5_ifc_fte_match_param_bits {
 819         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 820
 821         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 822
 823         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 824
 825         u8         reserved_0[0xa00];
 826 };
 827
 828 enum {
 829         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
 830         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
 831         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
 832         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
 833         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
 834 };
 835
 836 struct mlx5_ifc_rx_hash_field_select_bits {
 837         u8         l3_prot_type[0x1];
 838         u8         l4_prot_type[0x1];
 839         u8         selected_fields[0x1e];
 840 };
 841
 842 enum {
 843         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
 844         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
 845 };
 846
 847 enum {
 848         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
 849         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
 850 };
 851
 852 struct mlx5_ifc_wq_bits {
 853         u8         wq_type[0x4];
 854         u8         wq_signature[0x1];
 855         u8         end_padding_mode[0x2];
 856         u8         cd_slave[0x1];
 857         u8         reserved_0[0x18];
 858
 859         u8         hds_skip_first_sge[0x1];
 860         u8         log2_hds_buf_size[0x3];
 861         u8         reserved_1[0x7];
 862         u8         page_offset[0x5];
 863         u8         lwm[0x10];
 864
 865         u8         reserved_2[0x8];
 866         u8         pd[0x18];
 867
 868         u8         reserved_3[0x8];
 869         u8         uar_page[0x18];
 870
 871         u8         dbr_addr[0x40];
 872
 873         u8         hw_counter[0x20];
 874
 875         u8         sw_counter[0x20];
 876
 877         u8         reserved_4[0xc];
 878         u8         log_wq_stride[0x4];
 879         u8         reserved_5[0x3];
 880         u8         log_wq_pg_sz[0x5];
 881         u8         reserved_6[0x3];
 882         u8         log_wq_sz[0x5];
 883
 884         u8         reserved_7[0x4e0];
 885
 886         struct mlx5_ifc_cmd_pas_bits pas[0];
 887 };
 888
 889 struct mlx5_ifc_rq_num_bits {
 890         u8         reserved_0[0x8];
 891         u8         rq_num[0x18];
 892 };
 893
 894 struct mlx5_ifc_mac_address_layout_bits {
 895         u8         reserved_0[0x10];
 896         u8         mac_addr_47_32[0x10];
 897
 898         u8         mac_addr_31_0[0x20];
 899 };
 900
 901 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
 902         u8         reserved_0[0xa0];
 903
 904         u8         min_time_between_cnps[0x20];
 905
 906         u8         reserved_1[0x12];
 907         u8         cnp_dscp[0x6];
 908         u8         reserved_2[0x5];
 909         u8         cnp_802p_prio[0x3];
 910
 911         u8         reserved_3[0x720];
 912 };
 913
 914 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
 915         u8         reserved_0[0x60];
 916
 917         u8         reserved_1[0x4];
 918         u8         clamp_tgt_rate[0x1];
 919         u8         reserved_2[0x3];
 920         u8         clamp_tgt_rate_after_time_inc[0x1];
 921         u8         reserved_3[0x17];
 922
 923         u8         reserved_4[0x20];
 924
 925         u8         rpg_time_reset[0x20];
 926
 927         u8         rpg_byte_reset[0x20];
 928
 929         u8         rpg_threshold[0x20];
 930
 931         u8         rpg_max_rate[0x20];
 932
 933         u8         rpg_ai_rate[0x20];
 934
 935         u8         rpg_hai_rate[0x20];
 936
 937         u8         rpg_gd[0x20];
 938
 939         u8         rpg_min_dec_fac[0x20];
 940
 941         u8         rpg_min_rate[0x20];
 942
 943         u8         reserved_5[0xe0];
 944
 945         u8         rate_to_set_on_first_cnp[0x20];
 946
 947         u8         dce_tcp_g[0x20];
 948
 949         u8         dce_tcp_rtt[0x20];
 950
 951         u8         rate_reduce_monitor_period[0x20];
 952
 953         u8         reserved_6[0x20];
 954
 955         u8         initial_alpha_value[0x20];
 956
 957         u8         reserved_7[0x4a0];
 958 };
 959
 960 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
 961         u8         reserved_0[0x80];
 962
 963         u8         rppp_max_rps[0x20];
 964
 965         u8         rpg_time_reset[0x20];
 966
 967         u8         rpg_byte_reset[0x20];
 968
 969         u8         rpg_threshold[0x20];
 970
 971         u8         rpg_max_rate[0x20];
 972
 973         u8         rpg_ai_rate[0x20];
 974
 975         u8         rpg_hai_rate[0x20];
 976
 977         u8         rpg_gd[0x20];
 978
 979         u8         rpg_min_dec_fac[0x20];
 980
 981         u8         rpg_min_rate[0x20];
 982
 983         u8         reserved_1[0x640];
 984 };
 985
 986 enum {
 987         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
 988         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
 989         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
 990 };
 991
 992 struct mlx5_ifc_resize_field_select_bits {
 993         u8         resize_field_select[0x20];
 994 };
 995
 996 enum {
 997         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
 998         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
 999         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1000         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1001 };
1002
1003 struct mlx5_ifc_modify_field_select_bits {
1004         u8         modify_field_select[0x20];
1005 };
1006
1007 struct mlx5_ifc_field_select_r_roce_np_bits {
1008         u8         field_select_r_roce_np[0x20];
1009 };
1010
1011 struct mlx5_ifc_field_select_r_roce_rp_bits {
1012         u8         field_select_r_roce_rp[0x20];
1013 };
1014
1015 enum {
1016         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1017         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1018         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1019         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1020         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1021         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1022         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1023         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1024         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1025         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1026 };
1027
1028 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1029         u8         field_select_8021qaurp[0x20];
1030 };
1031
1032 struct mlx5_ifc_phys_layer_cntrs_bits {
1033         u8         time_since_last_clear_high[0x20];
1034
1035         u8         time_since_last_clear_low[0x20];
1036
1037         u8         symbol_errors_high[0x20];
1038
1039         u8         symbol_errors_low[0x20];
1040
1041         u8         sync_headers_errors_high[0x20];
1042
1043         u8         sync_headers_errors_low[0x20];
1044
1045         u8         edpl_bip_errors_lane0_high[0x20];
1046
1047         u8         edpl_bip_errors_lane0_low[0x20];
1048
1049         u8         edpl_bip_errors_lane1_high[0x20];
1050
1051         u8         edpl_bip_errors_lane1_low[0x20];
1052
1053         u8         edpl_bip_errors_lane2_high[0x20];
1054
1055         u8         edpl_bip_errors_lane2_low[0x20];
1056
1057         u8         edpl_bip_errors_lane3_high[0x20];
1058
1059         u8         edpl_bip_errors_lane3_low[0x20];
1060
1061         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1062
1063         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1064
1065         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1066
1067         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1068
1069         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1070
1071         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1072
1073         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1074
1075         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1076
1077         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1078
1079         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1080
1081         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1082
1083         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1084
1085         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1086
1087         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1088
1089         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1090
1091         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1092
1093         u8         rs_fec_corrected_blocks_high[0x20];
1094
1095         u8         rs_fec_corrected_blocks_low[0x20];
1096
1097         u8         rs_fec_uncorrectable_blocks_high[0x20];
1098
1099         u8         rs_fec_uncorrectable_blocks_low[0x20];
1100
1101         u8         rs_fec_no_errors_blocks_high[0x20];
1102
1103         u8         rs_fec_no_errors_blocks_low[0x20];
1104
1105         u8         rs_fec_single_error_blocks_high[0x20];
1106
1107         u8         rs_fec_single_error_blocks_low[0x20];
1108
1109         u8         rs_fec_corrected_symbols_total_high[0x20];
1110
1111         u8         rs_fec_corrected_symbols_total_low[0x20];
1112
1113         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1114
1115         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1116
1117         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1118
1119         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1120
1121         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1122
1123         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1124
1125         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1126
1127         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1128
1129         u8         link_down_events[0x20];
1130
1131         u8         successful_recovery_events[0x20];
1132
1133         u8         reserved_0[0x180];
1134 };
1135
1136 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1137         u8         transmit_queue_high[0x20];
1138
1139         u8         transmit_queue_low[0x20];
1140
1141         u8         reserved_0[0x780];
1142 };
1143
1144 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1145         u8         rx_octets_high[0x20];
1146
1147         u8         rx_octets_low[0x20];
1148
1149         u8         reserved_0[0xc0];
1150
1151         u8         rx_frames_high[0x20];
1152
1153         u8         rx_frames_low[0x20];
1154
1155         u8         tx_octets_high[0x20];
1156
1157         u8         tx_octets_low[0x20];
1158
1159         u8         reserved_1[0xc0];
1160
1161         u8         tx_frames_high[0x20];
1162
1163         u8         tx_frames_low[0x20];
1164
1165         u8         rx_pause_high[0x20];
1166
1167         u8         rx_pause_low[0x20];
1168
1169         u8         rx_pause_duration_high[0x20];
1170
1171         u8         rx_pause_duration_low[0x20];
1172
1173         u8         tx_pause_high[0x20];
1174
1175         u8         tx_pause_low[0x20];
1176
1177         u8         tx_pause_duration_high[0x20];
1178
1179         u8         tx_pause_duration_low[0x20];
1180
1181         u8         rx_pause_transition_high[0x20];
1182
1183         u8         rx_pause_transition_low[0x20];
1184
1185         u8         reserved_2[0x400];
1186 };
1187
1188 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1189         u8         port_transmit_wait_high[0x20];
1190
1191         u8         port_transmit_wait_low[0x20];
1192
1193         u8         reserved_0[0x780];
1194 };
1195
1196 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1197         u8         dot3stats_alignment_errors_high[0x20];
1198
1199         u8         dot3stats_alignment_errors_low[0x20];
1200
1201         u8         dot3stats_fcs_errors_high[0x20];
1202
1203         u8         dot3stats_fcs_errors_low[0x20];
1204
1205         u8         dot3stats_single_collision_frames_high[0x20];
1206
1207         u8         dot3stats_single_collision_frames_low[0x20];
1208
1209         u8         dot3stats_multiple_collision_frames_high[0x20];
1210
1211         u8         dot3stats_multiple_collision_frames_low[0x20];
1212
1213         u8         dot3stats_sqe_test_errors_high[0x20];
1214
1215         u8         dot3stats_sqe_test_errors_low[0x20];
1216
1217         u8         dot3stats_deferred_transmissions_high[0x20];
1218
1219         u8         dot3stats_deferred_transmissions_low[0x20];
1220
1221         u8         dot3stats_late_collisions_high[0x20];
1222
1223         u8         dot3stats_late_collisions_low[0x20];
1224
1225         u8         dot3stats_excessive_collisions_high[0x20];
1226
1227         u8         dot3stats_excessive_collisions_low[0x20];
1228
1229         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1230
1231         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1232
1233         u8         dot3stats_carrier_sense_errors_high[0x20];
1234
1235         u8         dot3stats_carrier_sense_errors_low[0x20];
1236
1237         u8         dot3stats_frame_too_longs_high[0x20];
1238
1239         u8         dot3stats_frame_too_longs_low[0x20];
1240
1241         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1242
1243         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1244
1245         u8         dot3stats_symbol_errors_high[0x20];
1246
1247         u8         dot3stats_symbol_errors_low[0x20];
1248
1249         u8         dot3control_in_unknown_opcodes_high[0x20];
1250
1251         u8         dot3control_in_unknown_opcodes_low[0x20];
1252
1253         u8         dot3in_pause_frames_high[0x20];
1254
1255         u8         dot3in_pause_frames_low[0x20];
1256
1257         u8         dot3out_pause_frames_high[0x20];
1258
1259         u8         dot3out_pause_frames_low[0x20];
1260
1261         u8         reserved_0[0x3c0];
1262 };
1263
1264 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1265         u8         ether_stats_drop_events_high[0x20];
1266
1267         u8         ether_stats_drop_events_low[0x20];
1268
1269         u8         ether_stats_octets_high[0x20];
1270
1271         u8         ether_stats_octets_low[0x20];
1272
1273         u8         ether_stats_pkts_high[0x20];
1274
1275         u8         ether_stats_pkts_low[0x20];
1276
1277         u8         ether_stats_broadcast_pkts_high[0x20];
1278
1279         u8         ether_stats_broadcast_pkts_low[0x20];
1280
1281         u8         ether_stats_multicast_pkts_high[0x20];
1282
1283         u8         ether_stats_multicast_pkts_low[0x20];
1284
1285         u8         ether_stats_crc_align_errors_high[0x20];
1286
1287         u8         ether_stats_crc_align_errors_low[0x20];
1288
1289         u8         ether_stats_undersize_pkts_high[0x20];
1290
1291         u8         ether_stats_undersize_pkts_low[0x20];
1292
1293         u8         ether_stats_oversize_pkts_high[0x20];
1294
1295         u8         ether_stats_oversize_pkts_low[0x20];
1296
1297         u8         ether_stats_fragments_high[0x20];
1298
1299         u8         ether_stats_fragments_low[0x20];
1300
1301         u8         ether_stats_jabbers_high[0x20];
1302
1303         u8         ether_stats_jabbers_low[0x20];
1304
1305         u8         ether_stats_collisions_high[0x20];
1306
1307         u8         ether_stats_collisions_low[0x20];
1308
1309         u8         ether_stats_pkts64octets_high[0x20];
1310
1311         u8         ether_stats_pkts64octets_low[0x20];
1312
1313         u8         ether_stats_pkts65to127octets_high[0x20];
1314
1315         u8         ether_stats_pkts65to127octets_low[0x20];
1316
1317         u8         ether_stats_pkts128to255octets_high[0x20];
1318
1319         u8         ether_stats_pkts128to255octets_low[0x20];
1320
1321         u8         ether_stats_pkts256to511octets_high[0x20];
1322
1323         u8         ether_stats_pkts256to511octets_low[0x20];
1324
1325         u8         ether_stats_pkts512to1023octets_high[0x20];
1326
1327         u8         ether_stats_pkts512to1023octets_low[0x20];
1328
1329         u8         ether_stats_pkts1024to1518octets_high[0x20];
1330
1331         u8         ether_stats_pkts1024to1518octets_low[0x20];
1332
1333         u8         ether_stats_pkts1519to2047octets_high[0x20];
1334
1335         u8         ether_stats_pkts1519to2047octets_low[0x20];
1336
1337         u8         ether_stats_pkts2048to4095octets_high[0x20];
1338
1339         u8         ether_stats_pkts2048to4095octets_low[0x20];
1340
1341         u8         ether_stats_pkts4096to8191octets_high[0x20];
1342
1343         u8         ether_stats_pkts4096to8191octets_low[0x20];
1344
1345         u8         ether_stats_pkts8192to10239octets_high[0x20];
1346
1347         u8         ether_stats_pkts8192to10239octets_low[0x20];
1348
1349         u8         reserved_0[0x280];
1350 };
1351
1352 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1353         u8         if_in_octets_high[0x20];
1354
1355         u8         if_in_octets_low[0x20];
1356
1357         u8         if_in_ucast_pkts_high[0x20];
1358
1359         u8         if_in_ucast_pkts_low[0x20];
1360
1361         u8         if_in_discards_high[0x20];
1362
1363         u8         if_in_discards_low[0x20];
1364
1365         u8         if_in_errors_high[0x20];
1366
1367         u8         if_in_errors_low[0x20];
1368
1369         u8         if_in_unknown_protos_high[0x20];
1370
1371         u8         if_in_unknown_protos_low[0x20];
1372
1373         u8         if_out_octets_high[0x20];
1374
1375         u8         if_out_octets_low[0x20];
1376
1377         u8         if_out_ucast_pkts_high[0x20];
1378
1379         u8         if_out_ucast_pkts_low[0x20];
1380
1381         u8         if_out_discards_high[0x20];
1382
1383         u8         if_out_discards_low[0x20];
1384
1385         u8         if_out_errors_high[0x20];
1386
1387         u8         if_out_errors_low[0x20];
1388
1389         u8         if_in_multicast_pkts_high[0x20];
1390
1391         u8         if_in_multicast_pkts_low[0x20];
1392
1393         u8         if_in_broadcast_pkts_high[0x20];
1394
1395         u8         if_in_broadcast_pkts_low[0x20];
1396
1397         u8         if_out_multicast_pkts_high[0x20];
1398
1399         u8         if_out_multicast_pkts_low[0x20];
1400
1401         u8         if_out_broadcast_pkts_high[0x20];
1402
1403         u8         if_out_broadcast_pkts_low[0x20];
1404
1405         u8         reserved_0[0x480];
1406 };
1407
1408 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1409         u8         a_frames_transmitted_ok_high[0x20];
1410
1411         u8         a_frames_transmitted_ok_low[0x20];
1412
1413         u8         a_frames_received_ok_high[0x20];
1414
1415         u8         a_frames_received_ok_low[0x20];
1416
1417         u8         a_frame_check_sequence_errors_high[0x20];
1418
1419         u8         a_frame_check_sequence_errors_low[0x20];
1420
1421         u8         a_alignment_errors_high[0x20];
1422
1423         u8         a_alignment_errors_low[0x20];
1424
1425         u8         a_octets_transmitted_ok_high[0x20];
1426
1427         u8         a_octets_transmitted_ok_low[0x20];
1428
1429         u8         a_octets_received_ok_high[0x20];
1430
1431         u8         a_octets_received_ok_low[0x20];
1432
1433         u8         a_multicast_frames_xmitted_ok_high[0x20];
1434
1435         u8         a_multicast_frames_xmitted_ok_low[0x20];
1436
1437         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1438
1439         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1440
1441         u8         a_multicast_frames_received_ok_high[0x20];
1442
1443         u8         a_multicast_frames_received_ok_low[0x20];
1444
1445         u8         a_broadcast_frames_received_ok_high[0x20];
1446
1447         u8         a_broadcast_frames_received_ok_low[0x20];
1448
1449         u8         a_in_range_length_errors_high[0x20];
1450
1451         u8         a_in_range_length_errors_low[0x20];
1452
1453         u8         a_out_of_range_length_field_high[0x20];
1454
1455         u8         a_out_of_range_length_field_low[0x20];
1456
1457         u8         a_frame_too_long_errors_high[0x20];
1458
1459         u8         a_frame_too_long_errors_low[0x20];
1460
1461         u8         a_symbol_error_during_carrier_high[0x20];
1462
1463         u8         a_symbol_error_during_carrier_low[0x20];
1464
1465         u8         a_mac_control_frames_transmitted_high[0x20];
1466
1467         u8         a_mac_control_frames_transmitted_low[0x20];
1468
1469         u8         a_mac_control_frames_received_high[0x20];
1470
1471         u8         a_mac_control_frames_received_low[0x20];
1472
1473         u8         a_unsupported_opcodes_received_high[0x20];
1474
1475         u8         a_unsupported_opcodes_received_low[0x20];
1476
1477         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1478
1479         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1480
1481         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1482
1483         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1484
1485         u8         reserved_0[0x300];
1486 };
1487
1488 struct mlx5_ifc_cmd_inter_comp_event_bits {
1489         u8         command_completion_vector[0x20];
1490
1491         u8         reserved_0[0xc0];
1492 };
1493
1494 struct mlx5_ifc_stall_vl_event_bits {
1495         u8         reserved_0[0x18];
1496         u8         port_num[0x1];
1497         u8         reserved_1[0x3];
1498         u8         vl[0x4];
1499
1500         u8         reserved_2[0xa0];
1501 };
1502
1503 struct mlx5_ifc_db_bf_congestion_event_bits {
1504         u8         event_subtype[0x8];
1505         u8         reserved_0[0x8];
1506         u8         congestion_level[0x8];
1507         u8         reserved_1[0x8];
1508
1509         u8         reserved_2[0xa0];
1510 };
1511
1512 struct mlx5_ifc_gpio_event_bits {
1513         u8         reserved_0[0x60];
1514
1515         u8         gpio_event_hi[0x20];
1516
1517         u8         gpio_event_lo[0x20];
1518
1519         u8         reserved_1[0x40];
1520 };
1521
1522 struct mlx5_ifc_port_state_change_event_bits {
1523         u8         reserved_0[0x40];
1524
1525         u8         port_num[0x4];
1526         u8         reserved_1[0x1c];
1527
1528         u8         reserved_2[0x80];
1529 };
1530
1531 struct mlx5_ifc_dropped_packet_logged_bits {
1532         u8         reserved_0[0xe0];
1533 };
1534
1535 enum {
1536         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1537         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1538 };
1539
1540 struct mlx5_ifc_cq_error_bits {
1541         u8         reserved_0[0x8];
1542         u8         cqn[0x18];
1543
1544         u8         reserved_1[0x20];
1545
1546         u8         reserved_2[0x18];
1547         u8         syndrome[0x8];
1548
1549         u8         reserved_3[0x80];
1550 };
1551
1552 struct mlx5_ifc_rdma_page_fault_event_bits {
1553         u8         bytes_committed[0x20];
1554
1555         u8         r_key[0x20];
1556
1557         u8         reserved_0[0x10];
1558         u8         packet_len[0x10];
1559
1560         u8         rdma_op_len[0x20];
1561
1562         u8         rdma_va[0x40];
1563
1564         u8         reserved_1[0x5];
1565         u8         rdma[0x1];
1566         u8         write[0x1];
1567         u8         requestor[0x1];
1568         u8         qp_number[0x18];
1569 };
1570
1571 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1572         u8         bytes_committed[0x20];
1573
1574         u8         reserved_0[0x10];
1575         u8         wqe_index[0x10];
1576
1577         u8         reserved_1[0x10];
1578         u8         len[0x10];
1579
1580         u8         reserved_2[0x60];
1581
1582         u8         reserved_3[0x5];
1583         u8         rdma[0x1];
1584         u8         write_read[0x1];
1585         u8         requestor[0x1];
1586         u8         qpn[0x18];
1587 };
1588
1589 struct mlx5_ifc_qp_events_bits {
1590         u8         reserved_0[0xa0];
1591
1592         u8         type[0x8];
1593         u8         reserved_1[0x18];
1594
1595         u8         reserved_2[0x8];
1596         u8         qpn_rqn_sqn[0x18];
1597 };
1598
1599 struct mlx5_ifc_dct_events_bits {
1600         u8         reserved_0[0xc0];
1601
1602         u8         reserved_1[0x8];
1603         u8         dct_number[0x18];
1604 };
1605
1606 struct mlx5_ifc_comp_event_bits {
1607         u8         reserved_0[0xc0];
1608
1609         u8         reserved_1[0x8];
1610         u8         cq_number[0x18];
1611 };
1612
1613 enum {
1614         MLX5_QPC_STATE_RST        = 0x0,
1615         MLX5_QPC_STATE_INIT       = 0x1,
1616         MLX5_QPC_STATE_RTR        = 0x2,
1617         MLX5_QPC_STATE_RTS        = 0x3,
1618         MLX5_QPC_STATE_SQER       = 0x4,
1619         MLX5_QPC_STATE_ERR        = 0x6,
1620         MLX5_QPC_STATE_SQD        = 0x7,
1621         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1622 };
1623
1624 enum {
1625         MLX5_QPC_ST_RC            = 0x0,
1626         MLX5_QPC_ST_UC            = 0x1,
1627         MLX5_QPC_ST_UD            = 0x2,
1628         MLX5_QPC_ST_XRC           = 0x3,
1629         MLX5_QPC_ST_DCI           = 0x5,
1630         MLX5_QPC_ST_QP0           = 0x7,
1631         MLX5_QPC_ST_QP1           = 0x8,
1632         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1633         MLX5_QPC_ST_REG_UMR       = 0xc,
1634 };
1635
1636 enum {
1637         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1638         MLX5_QPC_PM_STATE_REARM     = 0x1,
1639         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1640         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1641 };
1642
1643 enum {
1644         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1645         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1646 };
1647
1648 enum {
1649         MLX5_QPC_MTU_256_BYTES        = 0x1,
1650         MLX5_QPC_MTU_512_BYTES        = 0x2,
1651         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1652         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1653         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1654         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1655 };
1656
1657 enum {
1658         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1659         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1660         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1661         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1662         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1663         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1664         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1665         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1666 };
1667
1668 enum {
1669         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1670         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1671         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1672 };
1673
1674 enum {
1675         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1676         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1677         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1678 };
1679
1680 struct mlx5_ifc_qpc_bits {
1681         u8         state[0x4];
1682         u8         reserved_0[0x4];
1683         u8         st[0x8];
1684         u8         reserved_1[0x3];
1685         u8         pm_state[0x2];
1686         u8         reserved_2[0x7];
1687         u8         end_padding_mode[0x2];
1688         u8         reserved_3[0x2];
1689
1690         u8         wq_signature[0x1];
1691         u8         block_lb_mc[0x1];
1692         u8         atomic_like_write_en[0x1];
1693         u8         latency_sensitive[0x1];
1694         u8         reserved_4[0x1];
1695         u8         drain_sigerr[0x1];
1696         u8         reserved_5[0x2];
1697         u8         pd[0x18];
1698
1699         u8         mtu[0x3];
1700         u8         log_msg_max[0x5];
1701         u8         reserved_6[0x1];
1702         u8         log_rq_size[0x4];
1703         u8         log_rq_stride[0x3];
1704         u8         no_sq[0x1];
1705         u8         log_sq_size[0x4];
1706         u8         reserved_7[0x6];
1707         u8         rlky[0x1];
1708         u8         reserved_8[0x4];
1709
1710         u8         counter_set_id[0x8];
1711         u8         uar_page[0x18];
1712
1713         u8         reserved_9[0x8];
1714         u8         user_index[0x18];
1715
1716         u8         reserved_10[0x3];
1717         u8         log_page_size[0x5];
1718         u8         remote_qpn[0x18];
1719
1720         struct mlx5_ifc_ads_bits primary_address_path;
1721
1722         struct mlx5_ifc_ads_bits secondary_address_path;
1723
1724         u8         log_ack_req_freq[0x4];
1725         u8         reserved_11[0x4];
1726         u8         log_sra_max[0x3];
1727         u8         reserved_12[0x2];
1728         u8         retry_count[0x3];
1729         u8         rnr_retry[0x3];
1730         u8         reserved_13[0x1];
1731         u8         fre[0x1];
1732         u8         cur_rnr_retry[0x3];
1733         u8         cur_retry_count[0x3];
1734         u8         reserved_14[0x5];
1735
1736         u8         reserved_15[0x20];
1737
1738         u8         reserved_16[0x8];
1739         u8         next_send_psn[0x18];
1740
1741         u8         reserved_17[0x8];
1742         u8         cqn_snd[0x18];
1743
1744         u8         reserved_18[0x40];
1745
1746         u8         reserved_19[0x8];
1747         u8         last_acked_psn[0x18];
1748
1749         u8         reserved_20[0x8];
1750         u8         ssn[0x18];
1751
1752         u8         reserved_21[0x8];
1753         u8         log_rra_max[0x3];
1754         u8         reserved_22[0x1];
1755         u8         atomic_mode[0x4];
1756         u8         rre[0x1];
1757         u8         rwe[0x1];
1758         u8         rae[0x1];
1759         u8         reserved_23[0x1];
1760         u8         page_offset[0x6];
1761         u8         reserved_24[0x3];
1762         u8         cd_slave_receive[0x1];
1763         u8         cd_slave_send[0x1];
1764         u8         cd_master[0x1];
1765
1766         u8         reserved_25[0x3];
1767         u8         min_rnr_nak[0x5];
1768         u8         next_rcv_psn[0x18];
1769
1770         u8         reserved_26[0x8];
1771         u8         xrcd[0x18];
1772
1773         u8         reserved_27[0x8];
1774         u8         cqn_rcv[0x18];
1775
1776         u8         dbr_addr[0x40];
1777
1778         u8         q_key[0x20];
1779
1780         u8         reserved_28[0x5];
1781         u8         rq_type[0x3];
1782         u8         srqn_rmpn[0x18];
1783
1784         u8         reserved_29[0x8];
1785         u8         rmsn[0x18];
1786
1787         u8         hw_sq_wqebb_counter[0x10];
1788         u8         sw_sq_wqebb_counter[0x10];
1789
1790         u8         hw_rq_counter[0x20];
1791
1792         u8         sw_rq_counter[0x20];
1793
1794         u8         reserved_30[0x20];
1795
1796         u8         reserved_31[0xf];
1797         u8         cgs[0x1];
1798         u8         cs_req[0x8];
1799         u8         cs_res[0x8];
1800
1801         u8         dc_access_key[0x40];
1802
1803         u8         reserved_32[0xc0];
1804 };
1805
1806 struct mlx5_ifc_roce_addr_layout_bits {
1807         u8         source_l3_address[16][0x8];
1808
1809         u8         reserved_0[0x3];
1810         u8         vlan_valid[0x1];
1811         u8         vlan_id[0xc];
1812         u8         source_mac_47_32[0x10];
1813
1814         u8         source_mac_31_0[0x20];
1815
1816         u8         reserved_1[0x14];
1817         u8         roce_l3_type[0x4];
1818         u8         roce_version[0x8];
1819
1820         u8         reserved_2[0x20];
1821 };
1822
1823 union mlx5_ifc_hca_cap_union_bits {
1824         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1825         struct mlx5_ifc_odp_cap_bits odp_cap;
1826         struct mlx5_ifc_atomic_caps_bits atomic_caps;
1827         struct mlx5_ifc_roce_cap_bits roce_cap;
1828         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1829         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1830         u8         reserved_0[0x8000];
1831 };
1832
1833 enum {
1834         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1835         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1836         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1837 };
1838
1839 struct mlx5_ifc_flow_context_bits {
1840         u8         reserved_0[0x20];
1841
1842         u8         group_id[0x20];
1843
1844         u8         reserved_1[0x8];
1845         u8         flow_tag[0x18];
1846
1847         u8         reserved_2[0x10];
1848         u8         action[0x10];
1849
1850         u8         reserved_3[0x8];
1851         u8         destination_list_size[0x18];
1852
1853         u8         reserved_4[0x160];
1854
1855         struct mlx5_ifc_fte_match_param_bits match_value;
1856
1857         u8         reserved_5[0x600];
1858
1859         struct mlx5_ifc_dest_format_struct_bits destination[0];
1860 };
1861
1862 enum {
1863         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
1864         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
1865 };
1866
1867 struct mlx5_ifc_xrc_srqc_bits {
1868         u8         state[0x4];
1869         u8         log_xrc_srq_size[0x4];
1870         u8         reserved_0[0x18];
1871
1872         u8         wq_signature[0x1];
1873         u8         cont_srq[0x1];
1874         u8         reserved_1[0x1];
1875         u8         rlky[0x1];
1876         u8         basic_cyclic_rcv_wqe[0x1];
1877         u8         log_rq_stride[0x3];
1878         u8         xrcd[0x18];
1879
1880         u8         page_offset[0x6];
1881         u8         reserved_2[0x2];
1882         u8         cqn[0x18];
1883
1884         u8         reserved_3[0x20];
1885
1886         u8         user_index_equal_xrc_srqn[0x1];
1887         u8         reserved_4[0x1];
1888         u8         log_page_size[0x6];
1889         u8         user_index[0x18];
1890
1891         u8         reserved_5[0x20];
1892
1893         u8         reserved_6[0x8];
1894         u8         pd[0x18];
1895
1896         u8         lwm[0x10];
1897         u8         wqe_cnt[0x10];
1898
1899         u8         reserved_7[0x40];
1900
1901         u8         db_record_addr_h[0x20];
1902
1903         u8         db_record_addr_l[0x1e];
1904         u8         reserved_8[0x2];
1905
1906         u8         reserved_9[0x80];
1907 };
1908
1909 struct mlx5_ifc_traffic_counter_bits {
1910         u8         packets[0x40];
1911
1912         u8         octets[0x40];
1913 };
1914
1915 struct mlx5_ifc_tisc_bits {
1916         u8         reserved_0[0xc];
1917         u8         prio[0x4];
1918         u8         reserved_1[0x10];
1919
1920         u8         reserved_2[0x100];
1921
1922         u8         reserved_3[0x8];
1923         u8         transport_domain[0x18];
1924
1925         u8         reserved_4[0x3c0];
1926 };
1927
1928 enum {
1929         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
1930         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
1931 };
1932
1933 enum {
1934         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
1935         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
1936 };
1937
1938 enum {
1939         MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
1940         MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
1941         MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
1942 };
1943
1944 enum {
1945         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
1946         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
1947 };
1948
1949 struct mlx5_ifc_tirc_bits {
1950         u8         reserved_0[0x20];
1951
1952         u8         disp_type[0x4];
1953         u8         reserved_1[0x1c];
1954
1955         u8         reserved_2[0x40];
1956
1957         u8         reserved_3[0x4];
1958         u8         lro_timeout_period_usecs[0x10];
1959         u8         lro_enable_mask[0x4];
1960         u8         lro_max_ip_payload_size[0x8];
1961
1962         u8         reserved_4[0x40];
1963
1964         u8         reserved_5[0x8];
1965         u8         inline_rqn[0x18];
1966
1967         u8         rx_hash_symmetric[0x1];
1968         u8         reserved_6[0x1];
1969         u8         tunneled_offload_en[0x1];
1970         u8         reserved_7[0x5];
1971         u8         indirect_table[0x18];
1972
1973         u8         rx_hash_fn[0x4];
1974         u8         reserved_8[0x2];
1975         u8         self_lb_block[0x2];
1976         u8         transport_domain[0x18];
1977
1978         u8         rx_hash_toeplitz_key[10][0x20];
1979
1980         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1981
1982         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1983
1984         u8         reserved_9[0x4c0];
1985 };
1986
1987 enum {
1988         MLX5_SRQC_STATE_GOOD   = 0x0,
1989         MLX5_SRQC_STATE_ERROR  = 0x1,
1990 };
1991
1992 struct mlx5_ifc_srqc_bits {
1993         u8         state[0x4];
1994         u8         log_srq_size[0x4];
1995         u8         reserved_0[0x18];
1996
1997         u8         wq_signature[0x1];
1998         u8         cont_srq[0x1];
1999         u8         reserved_1[0x1];
2000         u8         rlky[0x1];
2001         u8         reserved_2[0x1];
2002         u8         log_rq_stride[0x3];
2003         u8         xrcd[0x18];
2004
2005         u8         page_offset[0x6];
2006         u8         reserved_3[0x2];
2007         u8         cqn[0x18];
2008
2009         u8         reserved_4[0x20];
2010
2011         u8         reserved_5[0x2];
2012         u8         log_page_size[0x6];
2013         u8         reserved_6[0x18];
2014
2015         u8         reserved_7[0x20];
2016
2017         u8         reserved_8[0x8];
2018         u8         pd[0x18];
2019
2020         u8         lwm[0x10];
2021         u8         wqe_cnt[0x10];
2022
2023         u8         reserved_9[0x40];
2024
2025         u8         dbr_addr[0x40];
2026
2027         u8         reserved_10[0x80];
2028 };
2029
2030 enum {
2031         MLX5_SQC_STATE_RST  = 0x0,
2032         MLX5_SQC_STATE_RDY  = 0x1,
2033         MLX5_SQC_STATE_ERR  = 0x3,
2034 };
2035
2036 struct mlx5_ifc_sqc_bits {
2037         u8         rlky[0x1];
2038         u8         cd_master[0x1];
2039         u8         fre[0x1];
2040         u8         flush_in_error_en[0x1];
2041         u8         reserved_0[0x4];
2042         u8         state[0x4];
2043         u8         reserved_1[0x14];
2044
2045         u8         reserved_2[0x8];
2046         u8         user_index[0x18];
2047
2048         u8         reserved_3[0x8];
2049         u8         cqn[0x18];
2050
2051         u8         reserved_4[0xa0];
2052
2053         u8         tis_lst_sz[0x10];
2054         u8         reserved_5[0x10];
2055
2056         u8         reserved_6[0x40];
2057
2058         u8         reserved_7[0x8];
2059         u8         tis_num_0[0x18];
2060
2061         struct mlx5_ifc_wq_bits wq;
2062 };
2063
2064 struct mlx5_ifc_rqtc_bits {
2065         u8         reserved_0[0xa0];
2066
2067         u8         reserved_1[0x10];
2068         u8         rqt_max_size[0x10];
2069
2070         u8         reserved_2[0x10];
2071         u8         rqt_actual_size[0x10];
2072
2073         u8         reserved_3[0x6a0];
2074
2075         struct mlx5_ifc_rq_num_bits rq_num[0];
2076 };
2077
2078 enum {
2079         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2080         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2081 };
2082
2083 enum {
2084         MLX5_RQC_STATE_RST  = 0x0,
2085         MLX5_RQC_STATE_RDY  = 0x1,
2086         MLX5_RQC_STATE_ERR  = 0x3,
2087 };
2088
2089 struct mlx5_ifc_rqc_bits {
2090         u8         rlky[0x1];
2091         u8         reserved_0[0x2];
2092         u8         vsd[0x1];
2093         u8         mem_rq_type[0x4];
2094         u8         state[0x4];
2095         u8         reserved_1[0x1];
2096         u8         flush_in_error_en[0x1];
2097         u8         reserved_2[0x12];
2098
2099         u8         reserved_3[0x8];
2100         u8         user_index[0x18];
2101
2102         u8         reserved_4[0x8];
2103         u8         cqn[0x18];
2104
2105         u8         counter_set_id[0x8];
2106         u8         reserved_5[0x18];
2107
2108         u8         reserved_6[0x8];
2109         u8         rmpn[0x18];
2110
2111         u8         reserved_7[0xe0];
2112
2113         struct mlx5_ifc_wq_bits wq;
2114 };
2115
2116 enum {
2117         MLX5_RMPC_STATE_RDY  = 0x1,
2118         MLX5_RMPC_STATE_ERR  = 0x3,
2119 };
2120
2121 struct mlx5_ifc_rmpc_bits {
2122         u8         reserved_0[0x8];
2123         u8         state[0x4];
2124         u8         reserved_1[0x14];
2125
2126         u8         basic_cyclic_rcv_wqe[0x1];
2127         u8         reserved_2[0x1f];
2128
2129         u8         reserved_3[0x140];
2130
2131         struct mlx5_ifc_wq_bits wq;
2132 };
2133
2134 enum {
2135         MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
2136 };
2137
2138 struct mlx5_ifc_nic_vport_context_bits {
2139         u8         reserved_0[0x1f];
2140         u8         roce_en[0x1];
2141
2142         u8         reserved_1[0x760];
2143
2144         u8         reserved_2[0x5];
2145         u8         allowed_list_type[0x3];
2146         u8         reserved_3[0xc];
2147         u8         allowed_list_size[0xc];
2148
2149         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2150
2151         u8         reserved_4[0x20];
2152
2153         u8         current_uc_mac_address[0][0x40];
2154 };
2155
2156 enum {
2157         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2158         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2159         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2160 };
2161
2162 struct mlx5_ifc_mkc_bits {
2163         u8         reserved_0[0x1];
2164         u8         free[0x1];
2165         u8         reserved_1[0xd];
2166         u8         small_fence_on_rdma_read_response[0x1];
2167         u8         umr_en[0x1];
2168         u8         a[0x1];
2169         u8         rw[0x1];
2170         u8         rr[0x1];
2171         u8         lw[0x1];
2172         u8         lr[0x1];
2173         u8         access_mode[0x2];
2174         u8         reserved_2[0x8];
2175
2176         u8         qpn[0x18];
2177         u8         mkey_7_0[0x8];
2178
2179         u8         reserved_3[0x20];
2180
2181         u8         length64[0x1];
2182         u8         bsf_en[0x1];
2183         u8         sync_umr[0x1];
2184         u8         reserved_4[0x2];
2185         u8         expected_sigerr_count[0x1];
2186         u8         reserved_5[0x1];
2187         u8         en_rinval[0x1];
2188         u8         pd[0x18];
2189
2190         u8         start_addr[0x40];
2191
2192         u8         len[0x40];
2193
2194         u8         bsf_octword_size[0x20];
2195
2196         u8         reserved_6[0x80];
2197
2198         u8         translations_octword_size[0x20];
2199
2200         u8         reserved_7[0x1b];
2201         u8         log_page_size[0x5];
2202
2203         u8         reserved_8[0x20];
2204 };
2205
2206 struct mlx5_ifc_pkey_bits {
2207         u8         reserved_0[0x10];
2208         u8         pkey[0x10];
2209 };
2210
2211 struct mlx5_ifc_array128_auto_bits {
2212         u8         array128_auto[16][0x8];
2213 };
2214
2215 struct mlx5_ifc_hca_vport_context_bits {
2216         u8         field_select[0x20];
2217
2218         u8         reserved_0[0xe0];
2219
2220         u8         sm_virt_aware[0x1];
2221         u8         has_smi[0x1];
2222         u8         has_raw[0x1];
2223         u8         grh_required[0x1];
2224         u8         reserved_1[0xc];
2225         u8         port_physical_state[0x4];
2226         u8         vport_state_policy[0x4];
2227         u8         port_state[0x4];
2228         u8         vport_state[0x4];
2229
2230         u8         reserved_2[0x20];
2231
2232         u8         system_image_guid[0x40];
2233
2234         u8         port_guid[0x40];
2235
2236         u8         node_guid[0x40];
2237
2238         u8         cap_mask1[0x20];
2239
2240         u8         cap_mask1_field_select[0x20];
2241
2242         u8         cap_mask2[0x20];
2243
2244         u8         cap_mask2_field_select[0x20];
2245
2246         u8         reserved_3[0x80];
2247
2248         u8         lid[0x10];
2249         u8         reserved_4[0x4];
2250         u8         init_type_reply[0x4];
2251         u8         lmc[0x3];
2252         u8         subnet_timeout[0x5];
2253
2254         u8         sm_lid[0x10];
2255         u8         sm_sl[0x4];
2256         u8         reserved_5[0xc];
2257
2258         u8         qkey_violation_counter[0x10];
2259         u8         pkey_violation_counter[0x10];
2260
2261         u8         reserved_6[0xca0];
2262 };
2263
2264 enum {
2265         MLX5_EQC_STATUS_OK                = 0x0,
2266         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2267 };
2268
2269 enum {
2270         MLX5_EQC_ST_ARMED  = 0x9,
2271         MLX5_EQC_ST_FIRED  = 0xa,
2272 };
2273
2274 struct mlx5_ifc_eqc_bits {
2275         u8         status[0x4];
2276         u8         reserved_0[0x9];
2277         u8         ec[0x1];
2278         u8         oi[0x1];
2279         u8         reserved_1[0x5];
2280         u8         st[0x4];
2281         u8         reserved_2[0x8];
2282
2283         u8         reserved_3[0x20];
2284
2285         u8         reserved_4[0x14];
2286         u8         page_offset[0x6];
2287         u8         reserved_5[0x6];
2288
2289         u8         reserved_6[0x3];
2290         u8         log_eq_size[0x5];
2291         u8         uar_page[0x18];
2292
2293         u8         reserved_7[0x20];
2294
2295         u8         reserved_8[0x18];
2296         u8         intr[0x8];
2297
2298         u8         reserved_9[0x3];
2299         u8         log_page_size[0x5];
2300         u8         reserved_10[0x18];
2301
2302         u8         reserved_11[0x60];
2303
2304         u8         reserved_12[0x8];
2305         u8         consumer_counter[0x18];
2306
2307         u8         reserved_13[0x8];
2308         u8         producer_counter[0x18];
2309
2310         u8         reserved_14[0x80];
2311 };
2312
2313 enum {
2314         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2315         MLX5_DCTC_STATE_DRAINING  = 0x1,
2316         MLX5_DCTC_STATE_DRAINED   = 0x2,
2317 };
2318
2319 enum {
2320         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2321         MLX5_DCTC_CS_RES_NA         = 0x1,
2322         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2323 };
2324
2325 enum {
2326         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2327         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2328         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2329         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2330         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2331 };
2332
2333 struct mlx5_ifc_dctc_bits {
2334         u8         reserved_0[0x4];
2335         u8         state[0x4];
2336         u8         reserved_1[0x18];
2337
2338         u8         reserved_2[0x8];
2339         u8         user_index[0x18];
2340
2341         u8         reserved_3[0x8];
2342         u8         cqn[0x18];
2343
2344         u8         counter_set_id[0x8];
2345         u8         atomic_mode[0x4];
2346         u8         rre[0x1];
2347         u8         rwe[0x1];
2348         u8         rae[0x1];
2349         u8         atomic_like_write_en[0x1];
2350         u8         latency_sensitive[0x1];
2351         u8         rlky[0x1];
2352         u8         free_ar[0x1];
2353         u8         reserved_4[0xd];
2354
2355         u8         reserved_5[0x8];
2356         u8         cs_res[0x8];
2357         u8         reserved_6[0x3];
2358         u8         min_rnr_nak[0x5];
2359         u8         reserved_7[0x8];
2360
2361         u8         reserved_8[0x8];
2362         u8         srqn[0x18];
2363
2364         u8         reserved_9[0x8];
2365         u8         pd[0x18];
2366
2367         u8         tclass[0x8];
2368         u8         reserved_10[0x4];
2369         u8         flow_label[0x14];
2370
2371         u8         dc_access_key[0x40];
2372
2373         u8         reserved_11[0x5];
2374         u8         mtu[0x3];
2375         u8         port[0x8];
2376         u8         pkey_index[0x10];
2377
2378         u8         reserved_12[0x8];
2379         u8         my_addr_index[0x8];
2380         u8         reserved_13[0x8];
2381         u8         hop_limit[0x8];
2382
2383         u8         dc_access_key_violation_count[0x20];
2384
2385         u8         reserved_14[0x14];
2386         u8         dei_cfi[0x1];
2387         u8         eth_prio[0x3];
2388         u8         ecn[0x2];
2389         u8         dscp[0x6];
2390
2391         u8         reserved_15[0x40];
2392 };
2393
2394 enum {
2395         MLX5_CQC_STATUS_OK             = 0x0,
2396         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2397         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2398 };
2399
2400 enum {
2401         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2402         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2403 };
2404
2405 enum {
2406         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2407         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2408         MLX5_CQC_ST_FIRED                                 = 0xa,
2409 };
2410
2411 struct mlx5_ifc_cqc_bits {
2412         u8         status[0x4];
2413         u8         reserved_0[0x4];
2414         u8         cqe_sz[0x3];
2415         u8         cc[0x1];
2416         u8         reserved_1[0x1];
2417         u8         scqe_break_moderation_en[0x1];
2418         u8         oi[0x1];
2419         u8         reserved_2[0x2];
2420         u8         cqe_zip_en[0x1];
2421         u8         mini_cqe_res_format[0x2];
2422         u8         st[0x4];
2423         u8         reserved_3[0x8];
2424
2425         u8         reserved_4[0x20];
2426
2427         u8         reserved_5[0x14];
2428         u8         page_offset[0x6];
2429         u8         reserved_6[0x6];
2430
2431         u8         reserved_7[0x3];
2432         u8         log_cq_size[0x5];
2433         u8         uar_page[0x18];
2434
2435         u8         reserved_8[0x4];
2436         u8         cq_period[0xc];
2437         u8         cq_max_count[0x10];
2438
2439         u8         reserved_9[0x18];
2440         u8         c_eqn[0x8];
2441
2442         u8         reserved_10[0x3];
2443         u8         log_page_size[0x5];
2444         u8         reserved_11[0x18];
2445
2446         u8         reserved_12[0x20];
2447
2448         u8         reserved_13[0x8];
2449         u8         last_notified_index[0x18];
2450
2451         u8         reserved_14[0x8];
2452         u8         last_solicit_index[0x18];
2453
2454         u8         reserved_15[0x8];
2455         u8         consumer_counter[0x18];
2456
2457         u8         reserved_16[0x8];
2458         u8         producer_counter[0x18];
2459
2460         u8         reserved_17[0x40];
2461
2462         u8         dbr_addr[0x40];
2463 };
2464
2465 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2466         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2467         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2468         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2469         u8         reserved_0[0x800];
2470 };
2471
2472 struct mlx5_ifc_query_adapter_param_block_bits {
2473         u8         reserved_0[0xe0];
2474
2475         u8         reserved_1[0x10];
2476         u8         vsd_vendor_id[0x10];
2477
2478         u8         vsd[208][0x8];
2479
2480         u8         vsd_contd_psid[16][0x8];
2481 };
2482
2483 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2484         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2485         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2486         u8         reserved_0[0x20];
2487 };
2488
2489 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2490         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2491         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2492         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2493         u8         reserved_0[0x20];
2494 };
2495
2496 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2497         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2498         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2499         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2500         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2501         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2502         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2503         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2504         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2505         u8         reserved_0[0x7c0];
2506 };
2507
2508 union mlx5_ifc_event_auto_bits {
2509         struct mlx5_ifc_comp_event_bits comp_event;
2510         struct mlx5_ifc_dct_events_bits dct_events;
2511         struct mlx5_ifc_qp_events_bits qp_events;
2512         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2513         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2514         struct mlx5_ifc_cq_error_bits cq_error;
2515         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2516         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2517         struct mlx5_ifc_gpio_event_bits gpio_event;
2518         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2519         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2520         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2521         u8         reserved_0[0xe0];
2522 };
2523
2524 struct mlx5_ifc_health_buffer_bits {
2525         u8         reserved_0[0x100];
2526
2527         u8         assert_existptr[0x20];
2528
2529         u8         assert_callra[0x20];
2530
2531         u8         reserved_1[0x40];
2532
2533         u8         fw_version[0x20];
2534
2535         u8         hw_id[0x20];
2536
2537         u8         reserved_2[0x20];
2538
2539         u8         irisc_index[0x8];
2540         u8         synd[0x8];
2541         u8         ext_synd[0x10];
2542 };
2543
2544 struct mlx5_ifc_register_loopback_control_bits {
2545         u8         no_lb[0x1];
2546         u8         reserved_0[0x7];
2547         u8         port[0x8];
2548         u8         reserved_1[0x10];
2549
2550         u8         reserved_2[0x60];
2551 };
2552
2553 struct mlx5_ifc_teardown_hca_out_bits {
2554         u8         status[0x8];
2555         u8         reserved_0[0x18];
2556
2557         u8         syndrome[0x20];
2558
2559         u8         reserved_1[0x40];
2560 };
2561
2562 enum {
2563         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2564         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2565 };
2566
2567 struct mlx5_ifc_teardown_hca_in_bits {
2568         u8         opcode[0x10];
2569         u8         reserved_0[0x10];
2570
2571         u8         reserved_1[0x10];
2572         u8         op_mod[0x10];
2573
2574         u8         reserved_2[0x10];
2575         u8         profile[0x10];
2576
2577         u8         reserved_3[0x20];
2578 };
2579
2580 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2581         u8         status[0x8];
2582         u8         reserved_0[0x18];
2583
2584         u8         syndrome[0x20];
2585
2586         u8         reserved_1[0x40];
2587 };
2588
2589 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2590         u8         opcode[0x10];
2591         u8         reserved_0[0x10];
2592
2593         u8         reserved_1[0x10];
2594         u8         op_mod[0x10];
2595
2596         u8         reserved_2[0x8];
2597         u8         qpn[0x18];
2598
2599         u8         reserved_3[0x20];
2600
2601         u8         opt_param_mask[0x20];
2602
2603         u8         reserved_4[0x20];
2604
2605         struct mlx5_ifc_qpc_bits qpc;
2606
2607         u8         reserved_5[0x80];
2608 };
2609
2610 struct mlx5_ifc_sqd2rts_qp_out_bits {
2611         u8         status[0x8];
2612         u8         reserved_0[0x18];
2613
2614         u8         syndrome[0x20];
2615
2616         u8         reserved_1[0x40];
2617 };
2618
2619 struct mlx5_ifc_sqd2rts_qp_in_bits {
2620         u8         opcode[0x10];
2621         u8         reserved_0[0x10];
2622
2623         u8         reserved_1[0x10];
2624         u8         op_mod[0x10];
2625
2626         u8         reserved_2[0x8];
2627         u8         qpn[0x18];
2628
2629         u8         reserved_3[0x20];
2630
2631         u8         opt_param_mask[0x20];
2632
2633         u8         reserved_4[0x20];
2634
2635         struct mlx5_ifc_qpc_bits qpc;
2636
2637         u8         reserved_5[0x80];
2638 };
2639
2640 struct mlx5_ifc_set_roce_address_out_bits {
2641         u8         status[0x8];
2642         u8         reserved_0[0x18];
2643
2644         u8         syndrome[0x20];
2645
2646         u8         reserved_1[0x40];
2647 };
2648
2649 struct mlx5_ifc_set_roce_address_in_bits {
2650         u8         opcode[0x10];
2651         u8         reserved_0[0x10];
2652
2653         u8         reserved_1[0x10];
2654         u8         op_mod[0x10];
2655
2656         u8         roce_address_index[0x10];
2657         u8         reserved_2[0x10];
2658
2659         u8         reserved_3[0x20];
2660
2661         struct mlx5_ifc_roce_addr_layout_bits roce_address;
2662 };
2663
2664 struct mlx5_ifc_set_mad_demux_out_bits {
2665         u8         status[0x8];
2666         u8         reserved_0[0x18];
2667
2668         u8         syndrome[0x20];
2669
2670         u8         reserved_1[0x40];
2671 };
2672
2673 enum {
2674         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
2675         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
2676 };
2677
2678 struct mlx5_ifc_set_mad_demux_in_bits {
2679         u8         opcode[0x10];
2680         u8         reserved_0[0x10];
2681
2682         u8         reserved_1[0x10];
2683         u8         op_mod[0x10];
2684
2685         u8         reserved_2[0x20];
2686
2687         u8         reserved_3[0x6];
2688         u8         demux_mode[0x2];
2689         u8         reserved_4[0x18];
2690 };
2691
2692 struct mlx5_ifc_set_l2_table_entry_out_bits {
2693         u8         status[0x8];
2694         u8         reserved_0[0x18];
2695
2696         u8         syndrome[0x20];
2697
2698         u8         reserved_1[0x40];
2699 };
2700
2701 struct mlx5_ifc_set_l2_table_entry_in_bits {
2702         u8         opcode[0x10];
2703         u8         reserved_0[0x10];
2704
2705         u8         reserved_1[0x10];
2706         u8         op_mod[0x10];
2707
2708         u8         reserved_2[0x60];
2709
2710         u8         reserved_3[0x8];
2711         u8         table_index[0x18];
2712
2713         u8         reserved_4[0x20];
2714
2715         u8         reserved_5[0x13];
2716         u8         vlan_valid[0x1];
2717         u8         vlan[0xc];
2718
2719         struct mlx5_ifc_mac_address_layout_bits mac_address;
2720
2721         u8         reserved_6[0xc0];
2722 };
2723
2724 struct mlx5_ifc_set_issi_out_bits {
2725         u8         status[0x8];
2726         u8         reserved_0[0x18];
2727
2728         u8         syndrome[0x20];
2729
2730         u8         reserved_1[0x40];
2731 };
2732
2733 struct mlx5_ifc_set_issi_in_bits {
2734         u8         opcode[0x10];
2735         u8         reserved_0[0x10];
2736
2737         u8         reserved_1[0x10];
2738         u8         op_mod[0x10];
2739
2740         u8         reserved_2[0x10];
2741         u8         current_issi[0x10];
2742
2743         u8         reserved_3[0x20];
2744 };
2745
2746 struct mlx5_ifc_set_hca_cap_out_bits {
2747         u8         status[0x8];
2748         u8         reserved_0[0x18];
2749
2750         u8         syndrome[0x20];
2751
2752         u8         reserved_1[0x40];
2753 };
2754
2755 struct mlx5_ifc_set_hca_cap_in_bits {
2756         u8         opcode[0x10];
2757         u8         reserved_0[0x10];
2758
2759         u8         reserved_1[0x10];
2760         u8         op_mod[0x10];
2761
2762         u8         reserved_2[0x40];
2763
2764         union mlx5_ifc_hca_cap_union_bits capability;
2765 };
2766
2767 struct mlx5_ifc_set_fte_out_bits {
2768         u8         status[0x8];
2769         u8         reserved_0[0x18];
2770
2771         u8         syndrome[0x20];
2772
2773         u8         reserved_1[0x40];
2774 };
2775
2776 struct mlx5_ifc_set_fte_in_bits {
2777         u8         opcode[0x10];
2778         u8         reserved_0[0x10];
2779
2780         u8         reserved_1[0x10];
2781         u8         op_mod[0x10];
2782
2783         u8         reserved_2[0x40];
2784
2785         u8         table_type[0x8];
2786         u8         reserved_3[0x18];
2787
2788         u8         reserved_4[0x8];
2789         u8         table_id[0x18];
2790
2791         u8         reserved_5[0x40];
2792
2793         u8         flow_index[0x20];
2794
2795         u8         reserved_6[0xe0];
2796
2797         struct mlx5_ifc_flow_context_bits flow_context;
2798 };
2799
2800 struct mlx5_ifc_rts2rts_qp_out_bits {
2801         u8         status[0x8];
2802         u8         reserved_0[0x18];
2803
2804         u8         syndrome[0x20];
2805
2806         u8         reserved_1[0x40];
2807 };
2808
2809 struct mlx5_ifc_rts2rts_qp_in_bits {
2810         u8         opcode[0x10];
2811         u8         reserved_0[0x10];
2812
2813         u8         reserved_1[0x10];
2814         u8         op_mod[0x10];
2815
2816         u8         reserved_2[0x8];
2817         u8         qpn[0x18];
2818
2819         u8         reserved_3[0x20];
2820
2821         u8         opt_param_mask[0x20];
2822
2823         u8         reserved_4[0x20];
2824
2825         struct mlx5_ifc_qpc_bits qpc;
2826
2827         u8         reserved_5[0x80];
2828 };
2829
2830 struct mlx5_ifc_rtr2rts_qp_out_bits {
2831         u8         status[0x8];
2832         u8         reserved_0[0x18];
2833
2834         u8         syndrome[0x20];
2835
2836         u8         reserved_1[0x40];
2837 };
2838
2839 struct mlx5_ifc_rtr2rts_qp_in_bits {
2840         u8         opcode[0x10];
2841         u8         reserved_0[0x10];
2842
2843         u8         reserved_1[0x10];
2844         u8         op_mod[0x10];
2845
2846         u8         reserved_2[0x8];
2847         u8         qpn[0x18];
2848
2849         u8         reserved_3[0x20];
2850
2851         u8         opt_param_mask[0x20];
2852
2853         u8         reserved_4[0x20];
2854
2855         struct mlx5_ifc_qpc_bits qpc;
2856
2857         u8         reserved_5[0x80];
2858 };
2859
2860 struct mlx5_ifc_rst2init_qp_out_bits {
2861         u8         status[0x8];
2862         u8         reserved_0[0x18];
2863
2864         u8         syndrome[0x20];
2865
2866         u8         reserved_1[0x40];
2867 };
2868
2869 struct mlx5_ifc_rst2init_qp_in_bits {
2870         u8         opcode[0x10];
2871         u8         reserved_0[0x10];
2872
2873         u8         reserved_1[0x10];
2874         u8         op_mod[0x10];
2875
2876         u8         reserved_2[0x8];
2877         u8         qpn[0x18];
2878
2879         u8         reserved_3[0x20];
2880
2881         u8         opt_param_mask[0x20];
2882
2883         u8         reserved_4[0x20];
2884
2885         struct mlx5_ifc_qpc_bits qpc;
2886
2887         u8         reserved_5[0x80];
2888 };
2889
2890 struct mlx5_ifc_query_xrc_srq_out_bits {
2891         u8         status[0x8];
2892         u8         reserved_0[0x18];
2893
2894         u8         syndrome[0x20];
2895
2896         u8         reserved_1[0x40];
2897
2898         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
2899
2900         u8         reserved_2[0x600];
2901
2902         u8         pas[0][0x40];
2903 };
2904
2905 struct mlx5_ifc_query_xrc_srq_in_bits {
2906         u8         opcode[0x10];
2907         u8         reserved_0[0x10];
2908
2909         u8         reserved_1[0x10];
2910         u8         op_mod[0x10];
2911
2912         u8         reserved_2[0x8];
2913         u8         xrc_srqn[0x18];
2914
2915         u8         reserved_3[0x20];
2916 };
2917
2918 enum {
2919         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
2920         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
2921 };
2922
2923 struct mlx5_ifc_query_vport_state_out_bits {
2924         u8         status[0x8];
2925         u8         reserved_0[0x18];
2926
2927         u8         syndrome[0x20];
2928
2929         u8         reserved_1[0x20];
2930
2931         u8         reserved_2[0x18];
2932         u8         admin_state[0x4];
2933         u8         state[0x4];
2934 };
2935
2936 enum {
2937         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
2938 };
2939
2940 struct mlx5_ifc_query_vport_state_in_bits {
2941         u8         opcode[0x10];
2942         u8         reserved_0[0x10];
2943
2944         u8         reserved_1[0x10];
2945         u8         op_mod[0x10];
2946
2947         u8         other_vport[0x1];
2948         u8         reserved_2[0xf];
2949         u8         vport_number[0x10];
2950
2951         u8         reserved_3[0x20];
2952 };
2953
2954 struct mlx5_ifc_query_vport_counter_out_bits {
2955         u8         status[0x8];
2956         u8         reserved_0[0x18];
2957
2958         u8         syndrome[0x20];
2959
2960         u8         reserved_1[0x40];
2961
2962         struct mlx5_ifc_traffic_counter_bits received_errors;
2963
2964         struct mlx5_ifc_traffic_counter_bits transmit_errors;
2965
2966         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
2967
2968         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
2969
2970         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
2971
2972         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
2973
2974         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
2975
2976         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
2977
2978         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
2979
2980         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
2981
2982         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
2983
2984         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
2985
2986         u8         reserved_2[0xa00];
2987 };
2988
2989 enum {
2990         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
2991 };
2992
2993 struct mlx5_ifc_query_vport_counter_in_bits {
2994         u8         opcode[0x10];
2995         u8         reserved_0[0x10];
2996
2997         u8         reserved_1[0x10];
2998         u8         op_mod[0x10];
2999
3000         u8         other_vport[0x1];
3001         u8         reserved_2[0xf];
3002         u8         vport_number[0x10];
3003
3004         u8         reserved_3[0x60];
3005
3006         u8         clear[0x1];
3007         u8         reserved_4[0x1f];
3008
3009         u8         reserved_5[0x20];
3010 };
3011
3012 struct mlx5_ifc_query_tis_out_bits {
3013         u8         status[0x8];
3014         u8         reserved_0[0x18];
3015
3016         u8         syndrome[0x20];
3017
3018         u8         reserved_1[0x40];
3019
3020         struct mlx5_ifc_tisc_bits tis_context;
3021 };
3022
3023 struct mlx5_ifc_query_tis_in_bits {
3024         u8         opcode[0x10];
3025         u8         reserved_0[0x10];
3026
3027         u8         reserved_1[0x10];
3028         u8         op_mod[0x10];
3029
3030         u8         reserved_2[0x8];
3031         u8         tisn[0x18];
3032
3033         u8         reserved_3[0x20];
3034 };
3035
3036 struct mlx5_ifc_query_tir_out_bits {
3037         u8         status[0x8];
3038         u8         reserved_0[0x18];
3039
3040         u8         syndrome[0x20];
3041
3042         u8         reserved_1[0xc0];
3043
3044         struct mlx5_ifc_tirc_bits tir_context;
3045 };
3046
3047 struct mlx5_ifc_query_tir_in_bits {
3048         u8         opcode[0x10];
3049         u8         reserved_0[0x10];
3050
3051         u8         reserved_1[0x10];
3052         u8         op_mod[0x10];
3053
3054         u8         reserved_2[0x8];
3055         u8         tirn[0x18];
3056
3057         u8         reserved_3[0x20];
3058 };
3059
3060 struct mlx5_ifc_query_srq_out_bits {
3061         u8         status[0x8];
3062         u8         reserved_0[0x18];
3063
3064         u8         syndrome[0x20];
3065
3066         u8         reserved_1[0x40];
3067
3068         struct mlx5_ifc_srqc_bits srq_context_entry;
3069
3070         u8         reserved_2[0x600];
3071
3072         u8         pas[0][0x40];
3073 };
3074
3075 struct mlx5_ifc_query_srq_in_bits {
3076         u8         opcode[0x10];
3077         u8         reserved_0[0x10];
3078
3079         u8         reserved_1[0x10];
3080         u8         op_mod[0x10];
3081
3082         u8         reserved_2[0x8];
3083         u8         srqn[0x18];
3084
3085         u8         reserved_3[0x20];
3086 };
3087
3088 struct mlx5_ifc_query_sq_out_bits {
3089         u8         status[0x8];
3090         u8         reserved_0[0x18];
3091
3092         u8         syndrome[0x20];
3093
3094         u8         reserved_1[0xc0];
3095
3096         struct mlx5_ifc_sqc_bits sq_context;
3097 };
3098
3099 struct mlx5_ifc_query_sq_in_bits {
3100         u8         opcode[0x10];
3101         u8         reserved_0[0x10];
3102
3103         u8         reserved_1[0x10];
3104         u8         op_mod[0x10];
3105
3106         u8         reserved_2[0x8];
3107         u8         sqn[0x18];
3108
3109         u8         reserved_3[0x20];
3110 };
3111
3112 struct mlx5_ifc_query_special_contexts_out_bits {
3113         u8         status[0x8];
3114         u8         reserved_0[0x18];
3115
3116         u8         syndrome[0x20];
3117
3118         u8         reserved_1[0x20];
3119
3120         u8         resd_lkey[0x20];
3121 };
3122
3123 struct mlx5_ifc_query_special_contexts_in_bits {
3124         u8         opcode[0x10];
3125         u8         reserved_0[0x10];
3126
3127         u8         reserved_1[0x10];
3128         u8         op_mod[0x10];
3129
3130         u8         reserved_2[0x40];
3131 };
3132
3133 struct mlx5_ifc_query_rqt_out_bits {
3134         u8         status[0x8];
3135         u8         reserved_0[0x18];
3136
3137         u8         syndrome[0x20];
3138
3139         u8         reserved_1[0xc0];
3140
3141         struct mlx5_ifc_rqtc_bits rqt_context;
3142 };
3143
3144 struct mlx5_ifc_query_rqt_in_bits {
3145         u8         opcode[0x10];
3146         u8         reserved_0[0x10];
3147
3148         u8         reserved_1[0x10];
3149         u8         op_mod[0x10];
3150
3151         u8         reserved_2[0x8];
3152         u8         rqtn[0x18];
3153
3154         u8         reserved_3[0x20];
3155 };
3156
3157 struct mlx5_ifc_query_rq_out_bits {
3158         u8         status[0x8];
3159         u8         reserved_0[0x18];
3160
3161         u8         syndrome[0x20];
3162
3163         u8         reserved_1[0xc0];
3164
3165         struct mlx5_ifc_rqc_bits rq_context;
3166 };
3167
3168 struct mlx5_ifc_query_rq_in_bits {
3169         u8         opcode[0x10];
3170         u8         reserved_0[0x10];
3171
3172         u8         reserved_1[0x10];
3173         u8         op_mod[0x10];
3174
3175         u8         reserved_2[0x8];
3176         u8         rqn[0x18];
3177
3178         u8         reserved_3[0x20];
3179 };
3180
3181 struct mlx5_ifc_query_roce_address_out_bits {
3182         u8         status[0x8];
3183         u8         reserved_0[0x18];
3184
3185         u8         syndrome[0x20];
3186
3187         u8         reserved_1[0x40];
3188
3189         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3190 };
3191
3192 struct mlx5_ifc_query_roce_address_in_bits {
3193         u8         opcode[0x10];
3194         u8         reserved_0[0x10];
3195
3196         u8         reserved_1[0x10];
3197         u8         op_mod[0x10];
3198
3199         u8         roce_address_index[0x10];
3200         u8         reserved_2[0x10];
3201
3202         u8         reserved_3[0x20];
3203 };
3204
3205 struct mlx5_ifc_query_rmp_out_bits {
3206         u8         status[0x8];
3207         u8         reserved_0[0x18];
3208
3209         u8         syndrome[0x20];
3210
3211         u8         reserved_1[0xc0];
3212
3213         struct mlx5_ifc_rmpc_bits rmp_context;
3214 };
3215
3216 struct mlx5_ifc_query_rmp_in_bits {
3217         u8         opcode[0x10];
3218         u8         reserved_0[0x10];
3219
3220         u8         reserved_1[0x10];
3221         u8         op_mod[0x10];
3222
3223         u8         reserved_2[0x8];
3224         u8         rmpn[0x18];
3225
3226         u8         reserved_3[0x20];
3227 };
3228
3229 struct mlx5_ifc_query_qp_out_bits {
3230         u8         status[0x8];
3231         u8         reserved_0[0x18];
3232
3233         u8         syndrome[0x20];
3234
3235         u8         reserved_1[0x40];
3236
3237         u8         opt_param_mask[0x20];
3238
3239         u8         reserved_2[0x20];
3240
3241         struct mlx5_ifc_qpc_bits qpc;
3242
3243         u8         reserved_3[0x80];
3244
3245         u8         pas[0][0x40];
3246 };
3247
3248 struct mlx5_ifc_query_qp_in_bits {
3249         u8         opcode[0x10];
3250         u8         reserved_0[0x10];
3251
3252         u8         reserved_1[0x10];
3253         u8         op_mod[0x10];
3254
3255         u8         reserved_2[0x8];
3256         u8         qpn[0x18];
3257
3258         u8         reserved_3[0x20];
3259 };
3260
3261 struct mlx5_ifc_query_q_counter_out_bits {
3262         u8         status[0x8];
3263         u8         reserved_0[0x18];
3264
3265         u8         syndrome[0x20];
3266
3267         u8         reserved_1[0x40];
3268
3269         u8         rx_write_requests[0x20];
3270
3271         u8         reserved_2[0x20];
3272
3273         u8         rx_read_requests[0x20];
3274
3275         u8         reserved_3[0x20];
3276
3277         u8         rx_atomic_requests[0x20];
3278
3279         u8         reserved_4[0x20];
3280
3281         u8         rx_dct_connect[0x20];
3282
3283         u8         reserved_5[0x20];
3284
3285         u8         out_of_buffer[0x20];
3286
3287         u8         reserved_6[0x20];
3288
3289         u8         out_of_sequence[0x20];
3290
3291         u8         reserved_7[0x620];
3292 };
3293
3294 struct mlx5_ifc_query_q_counter_in_bits {
3295         u8         opcode[0x10];
3296         u8         reserved_0[0x10];
3297
3298         u8         reserved_1[0x10];
3299         u8         op_mod[0x10];
3300
3301         u8         reserved_2[0x80];
3302
3303         u8         clear[0x1];
3304         u8         reserved_3[0x1f];
3305
3306         u8         reserved_4[0x18];
3307         u8         counter_set_id[0x8];
3308 };
3309
3310 struct mlx5_ifc_query_pages_out_bits {
3311         u8         status[0x8];
3312         u8         reserved_0[0x18];
3313
3314         u8         syndrome[0x20];
3315
3316         u8         reserved_1[0x10];
3317         u8         function_id[0x10];
3318
3319         u8         num_pages[0x20];
3320 };
3321
3322 enum {
3323         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3324         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3325         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3326 };
3327
3328 struct mlx5_ifc_query_pages_in_bits {
3329         u8         opcode[0x10];
3330         u8         reserved_0[0x10];
3331
3332         u8         reserved_1[0x10];
3333         u8         op_mod[0x10];
3334
3335         u8         reserved_2[0x10];
3336         u8         function_id[0x10];
3337
3338         u8         reserved_3[0x20];
3339 };
3340
3341 struct mlx5_ifc_query_nic_vport_context_out_bits {
3342         u8         status[0x8];
3343         u8         reserved_0[0x18];
3344
3345         u8         syndrome[0x20];
3346
3347         u8         reserved_1[0x40];
3348
3349         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3350 };
3351
3352 struct mlx5_ifc_query_nic_vport_context_in_bits {
3353         u8         opcode[0x10];
3354         u8         reserved_0[0x10];
3355
3356         u8         reserved_1[0x10];
3357         u8         op_mod[0x10];
3358
3359         u8         other_vport[0x1];
3360         u8         reserved_2[0xf];
3361         u8         vport_number[0x10];
3362
3363         u8         reserved_3[0x5];
3364         u8         allowed_list_type[0x3];
3365         u8         reserved_4[0x18];
3366 };
3367
3368 struct mlx5_ifc_query_mkey_out_bits {
3369         u8         status[0x8];
3370         u8         reserved_0[0x18];
3371
3372         u8         syndrome[0x20];
3373
3374         u8         reserved_1[0x40];
3375
3376         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3377
3378         u8         reserved_2[0x600];
3379
3380         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3381
3382         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3383 };
3384
3385 struct mlx5_ifc_query_mkey_in_bits {
3386         u8         opcode[0x10];
3387         u8         reserved_0[0x10];
3388
3389         u8         reserved_1[0x10];
3390         u8         op_mod[0x10];
3391
3392         u8         reserved_2[0x8];
3393         u8         mkey_index[0x18];
3394
3395         u8         pg_access[0x1];
3396         u8         reserved_3[0x1f];
3397 };
3398
3399 struct mlx5_ifc_query_mad_demux_out_bits {
3400         u8         status[0x8];
3401         u8         reserved_0[0x18];
3402
3403         u8         syndrome[0x20];
3404
3405         u8         reserved_1[0x40];
3406
3407         u8         mad_dumux_parameters_block[0x20];
3408 };
3409
3410 struct mlx5_ifc_query_mad_demux_in_bits {
3411         u8         opcode[0x10];
3412         u8         reserved_0[0x10];
3413
3414         u8         reserved_1[0x10];
3415         u8         op_mod[0x10];
3416
3417         u8         reserved_2[0x40];
3418 };
3419
3420 struct mlx5_ifc_query_l2_table_entry_out_bits {
3421         u8         status[0x8];
3422         u8         reserved_0[0x18];
3423
3424         u8         syndrome[0x20];
3425
3426         u8         reserved_1[0xa0];
3427
3428         u8         reserved_2[0x13];
3429         u8         vlan_valid[0x1];
3430         u8         vlan[0xc];
3431
3432         struct mlx5_ifc_mac_address_layout_bits mac_address;
3433
3434         u8         reserved_3[0xc0];
3435 };
3436
3437 struct mlx5_ifc_query_l2_table_entry_in_bits {
3438         u8         opcode[0x10];
3439         u8         reserved_0[0x10];
3440
3441         u8         reserved_1[0x10];
3442         u8         op_mod[0x10];
3443
3444         u8         reserved_2[0x60];
3445
3446         u8         reserved_3[0x8];
3447         u8         table_index[0x18];
3448
3449         u8         reserved_4[0x140];
3450 };
3451
3452 struct mlx5_ifc_query_issi_out_bits {
3453         u8         status[0x8];
3454         u8         reserved_0[0x18];
3455
3456         u8         syndrome[0x20];
3457
3458         u8         reserved_1[0x10];
3459         u8         current_issi[0x10];
3460
3461         u8         reserved_2[0xa0];
3462
3463         u8         supported_issi_reserved[76][0x8];
3464         u8         supported_issi_dw0[0x20];
3465 };
3466
3467 struct mlx5_ifc_query_issi_in_bits {
3468         u8         opcode[0x10];
3469         u8         reserved_0[0x10];
3470
3471         u8         reserved_1[0x10];
3472         u8         op_mod[0x10];
3473
3474         u8         reserved_2[0x40];
3475 };
3476
3477 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3478         u8         status[0x8];
3479         u8         reserved_0[0x18];
3480
3481         u8         syndrome[0x20];
3482
3483         u8         reserved_1[0x40];
3484
3485         struct mlx5_ifc_pkey_bits pkey[0];
3486 };
3487
3488 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3489         u8         opcode[0x10];
3490         u8         reserved_0[0x10];
3491
3492         u8         reserved_1[0x10];
3493         u8         op_mod[0x10];
3494
3495         u8         other_vport[0x1];
3496         u8         reserved_2[0xb];
3497         u8         port_num[0x4];
3498         u8         vport_number[0x10];
3499
3500         u8         reserved_3[0x10];
3501         u8         pkey_index[0x10];
3502 };
3503
3504 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3505         u8         status[0x8];
3506         u8         reserved_0[0x18];
3507
3508         u8         syndrome[0x20];
3509
3510         u8         reserved_1[0x20];
3511
3512         u8         gids_num[0x10];
3513         u8         reserved_2[0x10];
3514
3515         struct mlx5_ifc_array128_auto_bits gid[0];
3516 };
3517
3518 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3519         u8         opcode[0x10];
3520         u8         reserved_0[0x10];
3521
3522         u8         reserved_1[0x10];
3523         u8         op_mod[0x10];
3524
3525         u8         other_vport[0x1];
3526         u8         reserved_2[0xb];
3527         u8         port_num[0x4];
3528         u8         vport_number[0x10];
3529
3530         u8         reserved_3[0x10];
3531         u8         gid_index[0x10];
3532 };
3533
3534 struct mlx5_ifc_query_hca_vport_context_out_bits {
3535         u8         status[0x8];
3536         u8         reserved_0[0x18];
3537
3538         u8         syndrome[0x20];
3539
3540         u8         reserved_1[0x40];
3541
3542         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3543 };
3544
3545 struct mlx5_ifc_query_hca_vport_context_in_bits {
3546         u8         opcode[0x10];
3547         u8         reserved_0[0x10];
3548
3549         u8         reserved_1[0x10];
3550         u8         op_mod[0x10];
3551
3552         u8         other_vport[0x1];
3553         u8         reserved_2[0xb];
3554         u8         port_num[0x4];
3555         u8         vport_number[0x10];
3556
3557         u8         reserved_3[0x20];
3558 };
3559
3560 struct mlx5_ifc_query_hca_cap_out_bits {
3561         u8         status[0x8];
3562         u8         reserved_0[0x18];
3563
3564         u8         syndrome[0x20];
3565
3566         u8         reserved_1[0x40];
3567
3568         union mlx5_ifc_hca_cap_union_bits capability;
3569 };
3570
3571 struct mlx5_ifc_query_hca_cap_in_bits {
3572         u8         opcode[0x10];
3573         u8         reserved_0[0x10];
3574
3575         u8         reserved_1[0x10];
3576         u8         op_mod[0x10];
3577
3578         u8         reserved_2[0x40];
3579 };
3580
3581 struct mlx5_ifc_query_flow_table_out_bits {
3582         u8         status[0x8];
3583         u8         reserved_0[0x18];
3584
3585         u8         syndrome[0x20];
3586
3587         u8         reserved_1[0x80];
3588
3589         u8         reserved_2[0x8];
3590         u8         level[0x8];
3591         u8         reserved_3[0x8];
3592         u8         log_size[0x8];
3593
3594         u8         reserved_4[0x120];
3595 };
3596
3597 struct mlx5_ifc_query_flow_table_in_bits {
3598         u8         opcode[0x10];
3599         u8         reserved_0[0x10];
3600
3601         u8         reserved_1[0x10];
3602         u8         op_mod[0x10];
3603
3604         u8         reserved_2[0x40];
3605
3606         u8         table_type[0x8];
3607         u8         reserved_3[0x18];
3608
3609         u8         reserved_4[0x8];
3610         u8         table_id[0x18];
3611
3612         u8         reserved_5[0x140];
3613 };
3614
3615 struct mlx5_ifc_query_fte_out_bits {
3616         u8         status[0x8];
3617         u8         reserved_0[0x18];
3618
3619         u8         syndrome[0x20];
3620
3621         u8         reserved_1[0x1c0];
3622
3623         struct mlx5_ifc_flow_context_bits flow_context;
3624 };
3625
3626 struct mlx5_ifc_query_fte_in_bits {
3627         u8         opcode[0x10];
3628         u8         reserved_0[0x10];
3629
3630         u8         reserved_1[0x10];
3631         u8         op_mod[0x10];
3632
3633         u8         reserved_2[0x40];
3634
3635         u8         table_type[0x8];
3636         u8         reserved_3[0x18];
3637
3638         u8         reserved_4[0x8];
3639         u8         table_id[0x18];
3640
3641         u8         reserved_5[0x40];
3642
3643         u8         flow_index[0x20];
3644
3645         u8         reserved_6[0xe0];
3646 };
3647
3648 enum {
3649         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
3650         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
3651         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
3652 };
3653
3654 struct mlx5_ifc_query_flow_group_out_bits {
3655         u8         status[0x8];
3656         u8         reserved_0[0x18];
3657
3658         u8         syndrome[0x20];
3659
3660         u8         reserved_1[0xa0];
3661
3662         u8         start_flow_index[0x20];
3663
3664         u8         reserved_2[0x20];
3665
3666         u8         end_flow_index[0x20];
3667
3668         u8         reserved_3[0xa0];
3669
3670         u8         reserved_4[0x18];
3671         u8         match_criteria_enable[0x8];
3672
3673         struct mlx5_ifc_fte_match_param_bits match_criteria;
3674
3675         u8         reserved_5[0xe00];
3676 };
3677
3678 struct mlx5_ifc_query_flow_group_in_bits {
3679         u8         opcode[0x10];
3680         u8         reserved_0[0x10];
3681
3682         u8         reserved_1[0x10];
3683         u8         op_mod[0x10];
3684
3685         u8         reserved_2[0x40];
3686
3687         u8         table_type[0x8];
3688         u8         reserved_3[0x18];
3689
3690         u8         reserved_4[0x8];
3691         u8         table_id[0x18];
3692
3693         u8         group_id[0x20];
3694
3695         u8         reserved_5[0x120];
3696 };
3697
3698 struct mlx5_ifc_query_eq_out_bits {
3699         u8         status[0x8];
3700         u8         reserved_0[0x18];
3701
3702         u8         syndrome[0x20];
3703
3704         u8         reserved_1[0x40];
3705
3706         struct mlx5_ifc_eqc_bits eq_context_entry;
3707
3708         u8         reserved_2[0x40];
3709
3710         u8         event_bitmask[0x40];
3711
3712         u8         reserved_3[0x580];
3713
3714         u8         pas[0][0x40];
3715 };
3716
3717 struct mlx5_ifc_query_eq_in_bits {
3718         u8         opcode[0x10];
3719         u8         reserved_0[0x10];
3720
3721         u8         reserved_1[0x10];
3722         u8         op_mod[0x10];
3723
3724         u8         reserved_2[0x18];
3725         u8         eq_number[0x8];
3726
3727         u8         reserved_3[0x20];
3728 };
3729
3730 struct mlx5_ifc_query_dct_out_bits {
3731         u8         status[0x8];
3732         u8         reserved_0[0x18];
3733
3734         u8         syndrome[0x20];
3735
3736         u8         reserved_1[0x40];
3737
3738         struct mlx5_ifc_dctc_bits dct_context_entry;
3739
3740         u8         reserved_2[0x180];
3741 };
3742
3743 struct mlx5_ifc_query_dct_in_bits {
3744         u8         opcode[0x10];
3745         u8         reserved_0[0x10];
3746
3747         u8         reserved_1[0x10];
3748         u8         op_mod[0x10];
3749
3750         u8         reserved_2[0x8];
3751         u8         dctn[0x18];
3752
3753         u8         reserved_3[0x20];
3754 };
3755
3756 struct mlx5_ifc_query_cq_out_bits {
3757         u8         status[0x8];
3758         u8         reserved_0[0x18];
3759
3760         u8         syndrome[0x20];
3761
3762         u8         reserved_1[0x40];
3763
3764         struct mlx5_ifc_cqc_bits cq_context;
3765
3766         u8         reserved_2[0x600];
3767
3768         u8         pas[0][0x40];
3769 };
3770
3771 struct mlx5_ifc_query_cq_in_bits {
3772         u8         opcode[0x10];
3773         u8         reserved_0[0x10];
3774
3775         u8         reserved_1[0x10];
3776         u8         op_mod[0x10];
3777
3778         u8         reserved_2[0x8];
3779         u8         cqn[0x18];
3780
3781         u8         reserved_3[0x20];
3782 };
3783
3784 struct mlx5_ifc_query_cong_status_out_bits {
3785         u8         status[0x8];
3786         u8         reserved_0[0x18];
3787
3788         u8         syndrome[0x20];
3789
3790         u8         reserved_1[0x20];
3791
3792         u8         enable[0x1];
3793         u8         tag_enable[0x1];
3794         u8         reserved_2[0x1e];
3795 };
3796
3797 struct mlx5_ifc_query_cong_status_in_bits {
3798         u8         opcode[0x10];
3799         u8         reserved_0[0x10];
3800
3801         u8         reserved_1[0x10];
3802         u8         op_mod[0x10];
3803
3804         u8         reserved_2[0x18];
3805         u8         priority[0x4];
3806         u8         cong_protocol[0x4];
3807
3808         u8         reserved_3[0x20];
3809 };
3810
3811 struct mlx5_ifc_query_cong_statistics_out_bits {
3812         u8         status[0x8];
3813         u8         reserved_0[0x18];
3814
3815         u8         syndrome[0x20];
3816
3817         u8         reserved_1[0x40];
3818
3819         u8         cur_flows[0x20];
3820
3821         u8         sum_flows[0x20];
3822
3823         u8         cnp_ignored_high[0x20];
3824
3825         u8         cnp_ignored_low[0x20];
3826
3827         u8         cnp_handled_high[0x20];
3828
3829         u8         cnp_handled_low[0x20];
3830
3831         u8         reserved_2[0x100];
3832
3833         u8         time_stamp_high[0x20];
3834
3835         u8         time_stamp_low[0x20];
3836
3837         u8         accumulators_period[0x20];
3838
3839         u8         ecn_marked_roce_packets_high[0x20];
3840
3841         u8         ecn_marked_roce_packets_low[0x20];
3842
3843         u8         cnps_sent_high[0x20];
3844
3845         u8         cnps_sent_low[0x20];
3846
3847         u8         reserved_3[0x560];
3848 };
3849
3850 struct mlx5_ifc_query_cong_statistics_in_bits {
3851         u8         opcode[0x10];
3852         u8         reserved_0[0x10];
3853
3854         u8         reserved_1[0x10];
3855         u8         op_mod[0x10];
3856
3857         u8         clear[0x1];
3858         u8         reserved_2[0x1f];
3859
3860         u8         reserved_3[0x20];
3861 };
3862
3863 struct mlx5_ifc_query_cong_params_out_bits {
3864         u8         status[0x8];
3865         u8         reserved_0[0x18];
3866
3867         u8         syndrome[0x20];
3868
3869         u8         reserved_1[0x40];
3870
3871         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
3872 };
3873
3874 struct mlx5_ifc_query_cong_params_in_bits {
3875         u8         opcode[0x10];
3876         u8         reserved_0[0x10];
3877
3878         u8         reserved_1[0x10];
3879         u8         op_mod[0x10];
3880
3881         u8         reserved_2[0x1c];
3882         u8         cong_protocol[0x4];
3883
3884         u8         reserved_3[0x20];
3885 };
3886
3887 struct mlx5_ifc_query_adapter_out_bits {
3888         u8         status[0x8];
3889         u8         reserved_0[0x18];
3890
3891         u8         syndrome[0x20];
3892
3893         u8         reserved_1[0x40];
3894
3895         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
3896 };
3897
3898 struct mlx5_ifc_query_adapter_in_bits {
3899         u8         opcode[0x10];
3900         u8         reserved_0[0x10];
3901
3902         u8         reserved_1[0x10];
3903         u8         op_mod[0x10];
3904
3905         u8         reserved_2[0x40];
3906 };
3907
3908 struct mlx5_ifc_qp_2rst_out_bits {
3909         u8         status[0x8];
3910         u8         reserved_0[0x18];
3911
3912         u8         syndrome[0x20];
3913
3914         u8         reserved_1[0x40];
3915 };
3916
3917 struct mlx5_ifc_qp_2rst_in_bits {
3918         u8         opcode[0x10];
3919         u8         reserved_0[0x10];
3920
3921         u8         reserved_1[0x10];
3922         u8         op_mod[0x10];
3923
3924         u8         reserved_2[0x8];
3925         u8         qpn[0x18];
3926
3927         u8         reserved_3[0x20];
3928 };
3929
3930 struct mlx5_ifc_qp_2err_out_bits {
3931         u8         status[0x8];
3932         u8         reserved_0[0x18];
3933
3934         u8         syndrome[0x20];
3935
3936         u8         reserved_1[0x40];
3937 };
3938
3939 struct mlx5_ifc_qp_2err_in_bits {
3940         u8         opcode[0x10];
3941         u8         reserved_0[0x10];
3942
3943         u8         reserved_1[0x10];
3944         u8         op_mod[0x10];
3945
3946         u8         reserved_2[0x8];
3947         u8         qpn[0x18];
3948
3949         u8         reserved_3[0x20];
3950 };
3951
3952 struct mlx5_ifc_page_fault_resume_out_bits {
3953         u8         status[0x8];
3954         u8         reserved_0[0x18];
3955
3956         u8         syndrome[0x20];
3957
3958         u8         reserved_1[0x40];
3959 };
3960
3961 struct mlx5_ifc_page_fault_resume_in_bits {
3962         u8         opcode[0x10];
3963         u8         reserved_0[0x10];
3964
3965         u8         reserved_1[0x10];
3966         u8         op_mod[0x10];
3967
3968         u8         error[0x1];
3969         u8         reserved_2[0x4];
3970         u8         rdma[0x1];
3971         u8         read_write[0x1];
3972         u8         req_res[0x1];
3973         u8         qpn[0x18];
3974
3975         u8         reserved_3[0x20];
3976 };
3977
3978 struct mlx5_ifc_nop_out_bits {
3979         u8         status[0x8];
3980         u8         reserved_0[0x18];
3981
3982         u8         syndrome[0x20];
3983
3984         u8         reserved_1[0x40];
3985 };
3986
3987 struct mlx5_ifc_nop_in_bits {
3988         u8         opcode[0x10];
3989         u8         reserved_0[0x10];
3990
3991         u8         reserved_1[0x10];
3992         u8         op_mod[0x10];
3993
3994         u8         reserved_2[0x40];
3995 };
3996
3997 struct mlx5_ifc_modify_vport_state_out_bits {
3998         u8         status[0x8];
3999         u8         reserved_0[0x18];
4000
4001         u8         syndrome[0x20];
4002
4003         u8         reserved_1[0x40];
4004 };
4005
4006 struct mlx5_ifc_modify_vport_state_in_bits {
4007         u8         opcode[0x10];
4008         u8         reserved_0[0x10];
4009
4010         u8         reserved_1[0x10];
4011         u8         op_mod[0x10];
4012
4013         u8         other_vport[0x1];
4014         u8         reserved_2[0xf];
4015         u8         vport_number[0x10];
4016
4017         u8         reserved_3[0x18];
4018         u8         admin_state[0x4];
4019         u8         reserved_4[0x4];
4020 };
4021
4022 struct mlx5_ifc_modify_tis_out_bits {
4023         u8         status[0x8];
4024         u8         reserved_0[0x18];
4025
4026         u8         syndrome[0x20];
4027
4028         u8         reserved_1[0x40];
4029 };
4030
4031 struct mlx5_ifc_modify_tis_in_bits {
4032         u8         opcode[0x10];
4033         u8         reserved_0[0x10];
4034
4035         u8         reserved_1[0x10];
4036         u8         op_mod[0x10];
4037
4038         u8         reserved_2[0x8];
4039         u8         tisn[0x18];
4040
4041         u8         reserved_3[0x20];
4042
4043         u8         modify_bitmask[0x40];
4044
4045         u8         reserved_4[0x40];
4046
4047         struct mlx5_ifc_tisc_bits ctx;
4048 };
4049
4050 struct mlx5_ifc_modify_tir_out_bits {
4051         u8         status[0x8];
4052         u8         reserved_0[0x18];
4053
4054         u8         syndrome[0x20];
4055
4056         u8         reserved_1[0x40];
4057 };
4058
4059 struct mlx5_ifc_modify_tir_in_bits {
4060         u8         opcode[0x10];
4061         u8         reserved_0[0x10];
4062
4063         u8         reserved_1[0x10];
4064         u8         op_mod[0x10];
4065
4066         u8         reserved_2[0x8];
4067         u8         tirn[0x18];
4068
4069         u8         reserved_3[0x20];
4070
4071         u8         modify_bitmask[0x40];
4072
4073         u8         reserved_4[0x40];
4074
4075         struct mlx5_ifc_tirc_bits ctx;
4076 };
4077
4078 struct mlx5_ifc_modify_sq_out_bits {
4079         u8         status[0x8];
4080         u8         reserved_0[0x18];
4081
4082         u8         syndrome[0x20];
4083
4084         u8         reserved_1[0x40];
4085 };
4086
4087 struct mlx5_ifc_modify_sq_in_bits {
4088         u8         opcode[0x10];
4089         u8         reserved_0[0x10];
4090
4091         u8         reserved_1[0x10];
4092         u8         op_mod[0x10];
4093
4094         u8         sq_state[0x4];
4095         u8         reserved_2[0x4];
4096         u8         sqn[0x18];
4097
4098         u8         reserved_3[0x20];
4099
4100         u8         modify_bitmask[0x40];
4101
4102         u8         reserved_4[0x40];
4103
4104         struct mlx5_ifc_sqc_bits ctx;
4105 };
4106
4107 struct mlx5_ifc_modify_rqt_out_bits {
4108         u8         status[0x8];
4109         u8         reserved_0[0x18];
4110
4111         u8         syndrome[0x20];
4112
4113         u8         reserved_1[0x40];
4114 };
4115
4116 struct mlx5_ifc_modify_rqt_in_bits {
4117         u8         opcode[0x10];
4118         u8         reserved_0[0x10];
4119
4120         u8         reserved_1[0x10];
4121         u8         op_mod[0x10];
4122
4123         u8         reserved_2[0x8];
4124         u8         rqtn[0x18];
4125
4126         u8         reserved_3[0x20];
4127
4128         u8         modify_bitmask[0x40];
4129
4130         u8         reserved_4[0x40];
4131
4132         struct mlx5_ifc_rqtc_bits ctx;
4133 };
4134
4135 struct mlx5_ifc_modify_rq_out_bits {
4136         u8         status[0x8];
4137         u8         reserved_0[0x18];
4138
4139         u8         syndrome[0x20];
4140
4141         u8         reserved_1[0x40];
4142 };
4143
4144 struct mlx5_ifc_modify_rq_in_bits {
4145         u8         opcode[0x10];
4146         u8         reserved_0[0x10];
4147
4148         u8         reserved_1[0x10];
4149         u8         op_mod[0x10];
4150
4151         u8         rq_state[0x4];
4152         u8         reserved_2[0x4];
4153         u8         rqn[0x18];
4154
4155         u8         reserved_3[0x20];
4156
4157         u8         modify_bitmask[0x40];
4158
4159         u8         reserved_4[0x40];
4160
4161         struct mlx5_ifc_rqc_bits ctx;
4162 };
4163
4164 struct mlx5_ifc_modify_rmp_out_bits {
4165         u8         status[0x8];
4166         u8         reserved_0[0x18];
4167
4168         u8         syndrome[0x20];
4169
4170         u8         reserved_1[0x40];
4171 };
4172
4173 struct mlx5_ifc_rmp_bitmask_bits {
4174         u8         reserved[0x20];
4175
4176         u8         reserved1[0x1f];
4177         u8         lwm[0x1];
4178 };
4179
4180 struct mlx5_ifc_modify_rmp_in_bits {
4181         u8         opcode[0x10];
4182         u8         reserved_0[0x10];
4183
4184         u8         reserved_1[0x10];
4185         u8         op_mod[0x10];
4186
4187         u8         rmp_state[0x4];
4188         u8         reserved_2[0x4];
4189         u8         rmpn[0x18];
4190
4191         u8         reserved_3[0x20];
4192
4193         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4194
4195         u8         reserved_4[0x40];
4196
4197         struct mlx5_ifc_rmpc_bits ctx;
4198 };
4199
4200 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4201         u8         status[0x8];
4202         u8         reserved_0[0x18];
4203
4204         u8         syndrome[0x20];
4205
4206         u8         reserved_1[0x40];
4207 };
4208
4209 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4210         u8         reserved_0[0x1c];
4211         u8         permanent_address[0x1];
4212         u8         addresses_list[0x1];
4213         u8         roce_en[0x1];
4214         u8         reserved_1[0x1];
4215 };
4216
4217 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4218         u8         opcode[0x10];
4219         u8         reserved_0[0x10];
4220
4221         u8         reserved_1[0x10];
4222         u8         op_mod[0x10];
4223
4224         u8         other_vport[0x1];
4225         u8         reserved_2[0xf];
4226         u8         vport_number[0x10];
4227
4228         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4229
4230         u8         reserved_3[0x780];
4231
4232         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4233 };
4234
4235 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4236         u8         status[0x8];
4237         u8         reserved_0[0x18];
4238
4239         u8         syndrome[0x20];
4240
4241         u8         reserved_1[0x40];
4242 };
4243
4244 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4245         u8         opcode[0x10];
4246         u8         reserved_0[0x10];
4247
4248         u8         reserved_1[0x10];
4249         u8         op_mod[0x10];
4250
4251         u8         other_vport[0x1];
4252         u8         reserved_2[0xb];
4253         u8         port_num[0x4];
4254         u8         vport_number[0x10];
4255
4256         u8         reserved_3[0x20];
4257
4258         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4259 };
4260
4261 struct mlx5_ifc_modify_cq_out_bits {
4262         u8         status[0x8];
4263         u8         reserved_0[0x18];
4264
4265         u8         syndrome[0x20];
4266
4267         u8         reserved_1[0x40];
4268 };
4269
4270 enum {
4271         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4272         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4273 };
4274
4275 struct mlx5_ifc_modify_cq_in_bits {
4276         u8         opcode[0x10];
4277         u8         reserved_0[0x10];
4278
4279         u8         reserved_1[0x10];
4280         u8         op_mod[0x10];
4281
4282         u8         reserved_2[0x8];
4283         u8         cqn[0x18];
4284
4285         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4286
4287         struct mlx5_ifc_cqc_bits cq_context;
4288
4289         u8         reserved_3[0x600];
4290
4291         u8         pas[0][0x40];
4292 };
4293
4294 struct mlx5_ifc_modify_cong_status_out_bits {
4295         u8         status[0x8];
4296         u8         reserved_0[0x18];
4297
4298         u8         syndrome[0x20];
4299
4300         u8         reserved_1[0x40];
4301 };
4302
4303 struct mlx5_ifc_modify_cong_status_in_bits {
4304         u8         opcode[0x10];
4305         u8         reserved_0[0x10];
4306
4307         u8         reserved_1[0x10];
4308         u8         op_mod[0x10];
4309
4310         u8         reserved_2[0x18];
4311         u8         priority[0x4];
4312         u8         cong_protocol[0x4];
4313
4314         u8         enable[0x1];
4315         u8         tag_enable[0x1];
4316         u8         reserved_3[0x1e];
4317 };
4318
4319 struct mlx5_ifc_modify_cong_params_out_bits {
4320         u8         status[0x8];
4321         u8         reserved_0[0x18];
4322
4323         u8         syndrome[0x20];
4324
4325         u8         reserved_1[0x40];
4326 };
4327
4328 struct mlx5_ifc_modify_cong_params_in_bits {
4329         u8         opcode[0x10];
4330         u8         reserved_0[0x10];
4331
4332         u8         reserved_1[0x10];
4333         u8         op_mod[0x10];
4334
4335         u8         reserved_2[0x1c];
4336         u8         cong_protocol[0x4];
4337
4338         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4339
4340         u8         reserved_3[0x80];
4341
4342         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4343 };
4344
4345 struct mlx5_ifc_manage_pages_out_bits {
4346         u8         status[0x8];
4347         u8         reserved_0[0x18];
4348
4349         u8         syndrome[0x20];
4350
4351         u8         output_num_entries[0x20];
4352
4353         u8         reserved_1[0x20];
4354
4355         u8         pas[0][0x40];
4356 };
4357
4358 enum {
4359         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
4360         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
4361         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
4362 };
4363
4364 struct mlx5_ifc_manage_pages_in_bits {
4365         u8         opcode[0x10];
4366         u8         reserved_0[0x10];
4367
4368         u8         reserved_1[0x10];
4369         u8         op_mod[0x10];
4370
4371         u8         reserved_2[0x10];
4372         u8         function_id[0x10];
4373
4374         u8         input_num_entries[0x20];
4375
4376         u8         pas[0][0x40];
4377 };
4378
4379 struct mlx5_ifc_mad_ifc_out_bits {
4380         u8         status[0x8];
4381         u8         reserved_0[0x18];
4382
4383         u8         syndrome[0x20];
4384
4385         u8         reserved_1[0x40];
4386
4387         u8         response_mad_packet[256][0x8];
4388 };
4389
4390 struct mlx5_ifc_mad_ifc_in_bits {
4391         u8         opcode[0x10];
4392         u8         reserved_0[0x10];
4393
4394         u8         reserved_1[0x10];
4395         u8         op_mod[0x10];
4396
4397         u8         remote_lid[0x10];
4398         u8         reserved_2[0x8];
4399         u8         port[0x8];
4400
4401         u8         reserved_3[0x20];
4402
4403         u8         mad[256][0x8];
4404 };
4405
4406 struct mlx5_ifc_init_hca_out_bits {
4407         u8         status[0x8];
4408         u8         reserved_0[0x18];
4409
4410         u8         syndrome[0x20];
4411
4412         u8         reserved_1[0x40];
4413 };
4414
4415 struct mlx5_ifc_init_hca_in_bits {
4416         u8         opcode[0x10];
4417         u8         reserved_0[0x10];
4418
4419         u8         reserved_1[0x10];
4420         u8         op_mod[0x10];
4421
4422         u8         reserved_2[0x40];
4423 };
4424
4425 struct mlx5_ifc_init2rtr_qp_out_bits {
4426         u8         status[0x8];
4427         u8         reserved_0[0x18];
4428
4429         u8         syndrome[0x20];
4430
4431         u8         reserved_1[0x40];
4432 };
4433
4434 struct mlx5_ifc_init2rtr_qp_in_bits {
4435         u8         opcode[0x10];
4436         u8         reserved_0[0x10];
4437
4438         u8         reserved_1[0x10];
4439         u8         op_mod[0x10];
4440
4441         u8         reserved_2[0x8];
4442         u8         qpn[0x18];
4443
4444         u8         reserved_3[0x20];
4445
4446         u8         opt_param_mask[0x20];
4447
4448         u8         reserved_4[0x20];
4449
4450         struct mlx5_ifc_qpc_bits qpc;
4451
4452         u8         reserved_5[0x80];
4453 };
4454
4455 struct mlx5_ifc_init2init_qp_out_bits {
4456         u8         status[0x8];
4457         u8         reserved_0[0x18];
4458
4459         u8         syndrome[0x20];
4460
4461         u8         reserved_1[0x40];
4462 };
4463
4464 struct mlx5_ifc_init2init_qp_in_bits {
4465         u8         opcode[0x10];
4466         u8         reserved_0[0x10];
4467
4468         u8         reserved_1[0x10];
4469         u8         op_mod[0x10];
4470
4471         u8         reserved_2[0x8];
4472         u8         qpn[0x18];
4473
4474         u8         reserved_3[0x20];
4475
4476         u8         opt_param_mask[0x20];
4477
4478         u8         reserved_4[0x20];
4479
4480         struct mlx5_ifc_qpc_bits qpc;
4481
4482         u8         reserved_5[0x80];
4483 };
4484
4485 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4486         u8         status[0x8];
4487         u8         reserved_0[0x18];
4488
4489         u8         syndrome[0x20];
4490
4491         u8         reserved_1[0x40];
4492
4493         u8         packet_headers_log[128][0x8];
4494
4495         u8         packet_syndrome[64][0x8];
4496 };
4497
4498 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4499         u8         opcode[0x10];
4500         u8         reserved_0[0x10];
4501
4502         u8         reserved_1[0x10];
4503         u8         op_mod[0x10];
4504
4505         u8         reserved_2[0x40];
4506 };
4507
4508 struct mlx5_ifc_gen_eqe_in_bits {
4509         u8         opcode[0x10];
4510         u8         reserved_0[0x10];
4511
4512         u8         reserved_1[0x10];
4513         u8         op_mod[0x10];
4514
4515         u8         reserved_2[0x18];
4516         u8         eq_number[0x8];
4517
4518         u8         reserved_3[0x20];
4519
4520         u8         eqe[64][0x8];
4521 };
4522
4523 struct mlx5_ifc_gen_eq_out_bits {
4524         u8         status[0x8];
4525         u8         reserved_0[0x18];
4526
4527         u8         syndrome[0x20];
4528
4529         u8         reserved_1[0x40];
4530 };
4531
4532 struct mlx5_ifc_enable_hca_out_bits {
4533         u8         status[0x8];
4534         u8         reserved_0[0x18];
4535
4536         u8         syndrome[0x20];
4537
4538         u8         reserved_1[0x20];
4539 };
4540
4541 struct mlx5_ifc_enable_hca_in_bits {
4542         u8         opcode[0x10];
4543         u8         reserved_0[0x10];
4544
4545         u8         reserved_1[0x10];
4546         u8         op_mod[0x10];
4547
4548         u8         reserved_2[0x10];
4549         u8         function_id[0x10];
4550
4551         u8         reserved_3[0x20];
4552 };
4553
4554 struct mlx5_ifc_drain_dct_out_bits {
4555         u8         status[0x8];
4556         u8         reserved_0[0x18];
4557
4558         u8         syndrome[0x20];
4559
4560         u8         reserved_1[0x40];
4561 };
4562
4563 struct mlx5_ifc_drain_dct_in_bits {
4564         u8         opcode[0x10];
4565         u8         reserved_0[0x10];
4566
4567         u8         reserved_1[0x10];
4568         u8         op_mod[0x10];
4569
4570         u8         reserved_2[0x8];
4571         u8         dctn[0x18];
4572
4573         u8         reserved_3[0x20];
4574 };
4575
4576 struct mlx5_ifc_disable_hca_out_bits {
4577         u8         status[0x8];
4578         u8         reserved_0[0x18];
4579
4580         u8         syndrome[0x20];
4581
4582         u8         reserved_1[0x20];
4583 };
4584
4585 struct mlx5_ifc_disable_hca_in_bits {
4586         u8         opcode[0x10];
4587         u8         reserved_0[0x10];
4588
4589         u8         reserved_1[0x10];
4590         u8         op_mod[0x10];
4591
4592         u8         reserved_2[0x10];
4593         u8         function_id[0x10];
4594
4595         u8         reserved_3[0x20];
4596 };
4597
4598 struct mlx5_ifc_detach_from_mcg_out_bits {
4599         u8         status[0x8];
4600         u8         reserved_0[0x18];
4601
4602         u8         syndrome[0x20];
4603
4604         u8         reserved_1[0x40];
4605 };
4606
4607 struct mlx5_ifc_detach_from_mcg_in_bits {
4608         u8         opcode[0x10];
4609         u8         reserved_0[0x10];
4610
4611         u8         reserved_1[0x10];
4612         u8         op_mod[0x10];
4613
4614         u8         reserved_2[0x8];
4615         u8         qpn[0x18];
4616
4617         u8         reserved_3[0x20];
4618
4619         u8         multicast_gid[16][0x8];
4620 };
4621
4622 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4623         u8         status[0x8];
4624         u8         reserved_0[0x18];
4625
4626         u8         syndrome[0x20];
4627
4628         u8         reserved_1[0x40];
4629 };
4630
4631 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4632         u8         opcode[0x10];
4633         u8         reserved_0[0x10];
4634
4635         u8         reserved_1[0x10];
4636         u8         op_mod[0x10];
4637
4638         u8         reserved_2[0x8];
4639         u8         xrc_srqn[0x18];
4640
4641         u8         reserved_3[0x20];
4642 };
4643
4644 struct mlx5_ifc_destroy_tis_out_bits {
4645         u8         status[0x8];
4646         u8         reserved_0[0x18];
4647
4648         u8         syndrome[0x20];
4649
4650         u8         reserved_1[0x40];
4651 };
4652
4653 struct mlx5_ifc_destroy_tis_in_bits {
4654         u8         opcode[0x10];
4655         u8         reserved_0[0x10];
4656
4657         u8         reserved_1[0x10];
4658         u8         op_mod[0x10];
4659
4660         u8         reserved_2[0x8];
4661         u8         tisn[0x18];
4662
4663         u8         reserved_3[0x20];
4664 };
4665
4666 struct mlx5_ifc_destroy_tir_out_bits {
4667         u8         status[0x8];
4668         u8         reserved_0[0x18];
4669
4670         u8         syndrome[0x20];
4671
4672         u8         reserved_1[0x40];
4673 };
4674
4675 struct mlx5_ifc_destroy_tir_in_bits {
4676         u8         opcode[0x10];
4677         u8         reserved_0[0x10];
4678
4679         u8         reserved_1[0x10];
4680         u8         op_mod[0x10];
4681
4682         u8         reserved_2[0x8];
4683         u8         tirn[0x18];
4684
4685         u8         reserved_3[0x20];
4686 };
4687
4688 struct mlx5_ifc_destroy_srq_out_bits {
4689         u8         status[0x8];
4690         u8         reserved_0[0x18];
4691
4692         u8         syndrome[0x20];
4693
4694         u8         reserved_1[0x40];
4695 };
4696
4697 struct mlx5_ifc_destroy_srq_in_bits {
4698         u8         opcode[0x10];
4699         u8         reserved_0[0x10];
4700
4701         u8         reserved_1[0x10];
4702         u8         op_mod[0x10];
4703
4704         u8         reserved_2[0x8];
4705         u8         srqn[0x18];
4706
4707         u8         reserved_3[0x20];
4708 };
4709
4710 struct mlx5_ifc_destroy_sq_out_bits {
4711         u8         status[0x8];
4712         u8         reserved_0[0x18];
4713
4714         u8         syndrome[0x20];
4715
4716         u8         reserved_1[0x40];
4717 };
4718
4719 struct mlx5_ifc_destroy_sq_in_bits {
4720         u8         opcode[0x10];
4721         u8         reserved_0[0x10];
4722
4723         u8         reserved_1[0x10];
4724         u8         op_mod[0x10];
4725
4726         u8         reserved_2[0x8];
4727         u8         sqn[0x18];
4728
4729         u8         reserved_3[0x20];
4730 };
4731
4732 struct mlx5_ifc_destroy_rqt_out_bits {
4733         u8         status[0x8];
4734         u8         reserved_0[0x18];
4735
4736         u8         syndrome[0x20];
4737
4738         u8         reserved_1[0x40];
4739 };
4740
4741 struct mlx5_ifc_destroy_rqt_in_bits {
4742         u8         opcode[0x10];
4743         u8         reserved_0[0x10];
4744
4745         u8         reserved_1[0x10];
4746         u8         op_mod[0x10];
4747
4748         u8         reserved_2[0x8];
4749         u8         rqtn[0x18];
4750
4751         u8         reserved_3[0x20];
4752 };
4753
4754 struct mlx5_ifc_destroy_rq_out_bits {
4755         u8         status[0x8];
4756         u8         reserved_0[0x18];
4757
4758         u8         syndrome[0x20];
4759
4760         u8         reserved_1[0x40];
4761 };
4762
4763 struct mlx5_ifc_destroy_rq_in_bits {
4764         u8         opcode[0x10];
4765         u8         reserved_0[0x10];
4766
4767         u8         reserved_1[0x10];
4768         u8         op_mod[0x10];
4769
4770         u8         reserved_2[0x8];
4771         u8         rqn[0x18];
4772
4773         u8         reserved_3[0x20];
4774 };
4775
4776 struct mlx5_ifc_destroy_rmp_out_bits {
4777         u8         status[0x8];
4778         u8         reserved_0[0x18];
4779
4780         u8         syndrome[0x20];
4781
4782         u8         reserved_1[0x40];
4783 };
4784
4785 struct mlx5_ifc_destroy_rmp_in_bits {
4786         u8         opcode[0x10];
4787         u8         reserved_0[0x10];
4788
4789         u8         reserved_1[0x10];
4790         u8         op_mod[0x10];
4791
4792         u8         reserved_2[0x8];
4793         u8         rmpn[0x18];
4794
4795         u8         reserved_3[0x20];
4796 };
4797
4798 struct mlx5_ifc_destroy_qp_out_bits {
4799         u8         status[0x8];
4800         u8         reserved_0[0x18];
4801
4802         u8         syndrome[0x20];
4803
4804         u8         reserved_1[0x40];
4805 };
4806
4807 struct mlx5_ifc_destroy_qp_in_bits {
4808         u8         opcode[0x10];
4809         u8         reserved_0[0x10];
4810
4811         u8         reserved_1[0x10];
4812         u8         op_mod[0x10];
4813
4814         u8         reserved_2[0x8];
4815         u8         qpn[0x18];
4816
4817         u8         reserved_3[0x20];
4818 };
4819
4820 struct mlx5_ifc_destroy_psv_out_bits {
4821         u8         status[0x8];
4822         u8         reserved_0[0x18];
4823
4824         u8         syndrome[0x20];
4825
4826         u8         reserved_1[0x40];
4827 };
4828
4829 struct mlx5_ifc_destroy_psv_in_bits {
4830         u8         opcode[0x10];
4831         u8         reserved_0[0x10];
4832
4833         u8         reserved_1[0x10];
4834         u8         op_mod[0x10];
4835
4836         u8         reserved_2[0x8];
4837         u8         psvn[0x18];
4838
4839         u8         reserved_3[0x20];
4840 };
4841
4842 struct mlx5_ifc_destroy_mkey_out_bits {
4843         u8         status[0x8];
4844         u8         reserved_0[0x18];
4845
4846         u8         syndrome[0x20];
4847
4848         u8         reserved_1[0x40];
4849 };
4850
4851 struct mlx5_ifc_destroy_mkey_in_bits {
4852         u8         opcode[0x10];
4853         u8         reserved_0[0x10];
4854
4855         u8         reserved_1[0x10];
4856         u8         op_mod[0x10];
4857
4858         u8         reserved_2[0x8];
4859         u8         mkey_index[0x18];
4860
4861         u8         reserved_3[0x20];
4862 };
4863
4864 struct mlx5_ifc_destroy_flow_table_out_bits {
4865         u8         status[0x8];
4866         u8         reserved_0[0x18];
4867
4868         u8         syndrome[0x20];
4869
4870         u8         reserved_1[0x40];
4871 };
4872
4873 struct mlx5_ifc_destroy_flow_table_in_bits {
4874         u8         opcode[0x10];
4875         u8         reserved_0[0x10];
4876
4877         u8         reserved_1[0x10];
4878         u8         op_mod[0x10];
4879
4880         u8         reserved_2[0x40];
4881
4882         u8         table_type[0x8];
4883         u8         reserved_3[0x18];
4884
4885         u8         reserved_4[0x8];
4886         u8         table_id[0x18];
4887
4888         u8         reserved_5[0x140];
4889 };
4890
4891 struct mlx5_ifc_destroy_flow_group_out_bits {
4892         u8         status[0x8];
4893         u8         reserved_0[0x18];
4894
4895         u8         syndrome[0x20];
4896
4897         u8         reserved_1[0x40];
4898 };
4899
4900 struct mlx5_ifc_destroy_flow_group_in_bits {
4901         u8         opcode[0x10];
4902         u8         reserved_0[0x10];
4903
4904         u8         reserved_1[0x10];
4905         u8         op_mod[0x10];
4906
4907         u8         reserved_2[0x40];
4908
4909         u8         table_type[0x8];
4910         u8         reserved_3[0x18];
4911
4912         u8         reserved_4[0x8];
4913         u8         table_id[0x18];
4914
4915         u8         group_id[0x20];
4916
4917         u8         reserved_5[0x120];
4918 };
4919
4920 struct mlx5_ifc_destroy_eq_out_bits {
4921         u8         status[0x8];
4922         u8         reserved_0[0x18];
4923
4924         u8         syndrome[0x20];
4925
4926         u8         reserved_1[0x40];
4927 };
4928
4929 struct mlx5_ifc_destroy_eq_in_bits {
4930         u8         opcode[0x10];
4931         u8         reserved_0[0x10];
4932
4933         u8         reserved_1[0x10];
4934         u8         op_mod[0x10];
4935
4936         u8         reserved_2[0x18];
4937         u8         eq_number[0x8];
4938
4939         u8         reserved_3[0x20];
4940 };
4941
4942 struct mlx5_ifc_destroy_dct_out_bits {
4943         u8         status[0x8];
4944         u8         reserved_0[0x18];
4945
4946         u8         syndrome[0x20];
4947
4948         u8         reserved_1[0x40];
4949 };
4950
4951 struct mlx5_ifc_destroy_dct_in_bits {
4952         u8         opcode[0x10];
4953         u8         reserved_0[0x10];
4954
4955         u8         reserved_1[0x10];
4956         u8         op_mod[0x10];
4957
4958         u8         reserved_2[0x8];
4959         u8         dctn[0x18];
4960
4961         u8         reserved_3[0x20];
4962 };
4963
4964 struct mlx5_ifc_destroy_cq_out_bits {
4965         u8         status[0x8];
4966         u8         reserved_0[0x18];
4967
4968         u8         syndrome[0x20];
4969
4970         u8         reserved_1[0x40];
4971 };
4972
4973 struct mlx5_ifc_destroy_cq_in_bits {
4974         u8         opcode[0x10];
4975         u8         reserved_0[0x10];
4976
4977         u8         reserved_1[0x10];
4978         u8         op_mod[0x10];
4979
4980         u8         reserved_2[0x8];
4981         u8         cqn[0x18];
4982
4983         u8         reserved_3[0x20];
4984 };
4985
4986 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
4987         u8         status[0x8];
4988         u8         reserved_0[0x18];
4989
4990         u8         syndrome[0x20];
4991
4992         u8         reserved_1[0x40];
4993 };
4994
4995 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
4996         u8         opcode[0x10];
4997         u8         reserved_0[0x10];
4998
4999         u8         reserved_1[0x10];
5000         u8         op_mod[0x10];
5001
5002         u8         reserved_2[0x20];
5003
5004         u8         reserved_3[0x10];
5005         u8         vxlan_udp_port[0x10];
5006 };
5007
5008 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5009         u8         status[0x8];
5010         u8         reserved_0[0x18];
5011
5012         u8         syndrome[0x20];
5013
5014         u8         reserved_1[0x40];
5015 };
5016
5017 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5018         u8         opcode[0x10];
5019         u8         reserved_0[0x10];
5020
5021         u8         reserved_1[0x10];
5022         u8         op_mod[0x10];
5023
5024         u8         reserved_2[0x60];
5025
5026         u8         reserved_3[0x8];
5027         u8         table_index[0x18];
5028
5029         u8         reserved_4[0x140];
5030 };
5031
5032 struct mlx5_ifc_delete_fte_out_bits {
5033         u8         status[0x8];
5034         u8         reserved_0[0x18];
5035
5036         u8         syndrome[0x20];
5037
5038         u8         reserved_1[0x40];
5039 };
5040
5041 struct mlx5_ifc_delete_fte_in_bits {
5042         u8         opcode[0x10];
5043         u8         reserved_0[0x10];
5044
5045         u8         reserved_1[0x10];
5046         u8         op_mod[0x10];
5047
5048         u8         reserved_2[0x40];
5049
5050         u8         table_type[0x8];
5051         u8         reserved_3[0x18];
5052
5053         u8         reserved_4[0x8];
5054         u8         table_id[0x18];
5055
5056         u8         reserved_5[0x40];
5057
5058         u8         flow_index[0x20];
5059
5060         u8         reserved_6[0xe0];
5061 };
5062
5063 struct mlx5_ifc_dealloc_xrcd_out_bits {
5064         u8         status[0x8];
5065         u8         reserved_0[0x18];
5066
5067         u8         syndrome[0x20];
5068
5069         u8         reserved_1[0x40];
5070 };
5071
5072 struct mlx5_ifc_dealloc_xrcd_in_bits {
5073         u8         opcode[0x10];
5074         u8         reserved_0[0x10];
5075
5076         u8         reserved_1[0x10];
5077         u8         op_mod[0x10];
5078
5079         u8         reserved_2[0x8];
5080         u8         xrcd[0x18];
5081
5082         u8         reserved_3[0x20];
5083 };
5084
5085 struct mlx5_ifc_dealloc_uar_out_bits {
5086         u8         status[0x8];
5087         u8         reserved_0[0x18];
5088
5089         u8         syndrome[0x20];
5090
5091         u8         reserved_1[0x40];
5092 };
5093
5094 struct mlx5_ifc_dealloc_uar_in_bits {
5095         u8         opcode[0x10];
5096         u8         reserved_0[0x10];
5097
5098         u8         reserved_1[0x10];
5099         u8         op_mod[0x10];
5100
5101         u8         reserved_2[0x8];
5102         u8         uar[0x18];
5103
5104         u8         reserved_3[0x20];
5105 };
5106
5107 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5108         u8         status[0x8];
5109         u8         reserved_0[0x18];
5110
5111         u8         syndrome[0x20];
5112
5113         u8         reserved_1[0x40];
5114 };
5115
5116 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5117         u8         opcode[0x10];
5118         u8         reserved_0[0x10];
5119
5120         u8         reserved_1[0x10];
5121         u8         op_mod[0x10];
5122
5123         u8         reserved_2[0x8];
5124         u8         transport_domain[0x18];
5125
5126         u8         reserved_3[0x20];
5127 };
5128
5129 struct mlx5_ifc_dealloc_q_counter_out_bits {
5130         u8         status[0x8];
5131         u8         reserved_0[0x18];
5132
5133         u8         syndrome[0x20];
5134
5135         u8         reserved_1[0x40];
5136 };
5137
5138 struct mlx5_ifc_dealloc_q_counter_in_bits {
5139         u8         opcode[0x10];
5140         u8         reserved_0[0x10];
5141
5142         u8         reserved_1[0x10];
5143         u8         op_mod[0x10];
5144
5145         u8         reserved_2[0x18];
5146         u8         counter_set_id[0x8];
5147
5148         u8         reserved_3[0x20];
5149 };
5150
5151 struct mlx5_ifc_dealloc_pd_out_bits {
5152         u8         status[0x8];
5153         u8         reserved_0[0x18];
5154
5155         u8         syndrome[0x20];
5156
5157         u8         reserved_1[0x40];
5158 };
5159
5160 struct mlx5_ifc_dealloc_pd_in_bits {
5161         u8         opcode[0x10];
5162         u8         reserved_0[0x10];
5163
5164         u8         reserved_1[0x10];
5165         u8         op_mod[0x10];
5166
5167         u8         reserved_2[0x8];
5168         u8         pd[0x18];
5169
5170         u8         reserved_3[0x20];
5171 };
5172
5173 struct mlx5_ifc_create_xrc_srq_out_bits {
5174         u8         status[0x8];
5175         u8         reserved_0[0x18];
5176
5177         u8         syndrome[0x20];
5178
5179         u8         reserved_1[0x8];
5180         u8         xrc_srqn[0x18];
5181
5182         u8         reserved_2[0x20];
5183 };
5184
5185 struct mlx5_ifc_create_xrc_srq_in_bits {
5186         u8         opcode[0x10];
5187         u8         reserved_0[0x10];
5188
5189         u8         reserved_1[0x10];
5190         u8         op_mod[0x10];
5191
5192         u8         reserved_2[0x40];
5193
5194         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5195
5196         u8         reserved_3[0x600];
5197
5198         u8         pas[0][0x40];
5199 };
5200
5201 struct mlx5_ifc_create_tis_out_bits {
5202         u8         status[0x8];
5203         u8         reserved_0[0x18];
5204
5205         u8         syndrome[0x20];
5206
5207         u8         reserved_1[0x8];
5208         u8         tisn[0x18];
5209
5210         u8         reserved_2[0x20];
5211 };
5212
5213 struct mlx5_ifc_create_tis_in_bits {
5214         u8         opcode[0x10];
5215         u8         reserved_0[0x10];
5216
5217         u8         reserved_1[0x10];
5218         u8         op_mod[0x10];
5219
5220         u8         reserved_2[0xc0];
5221
5222         struct mlx5_ifc_tisc_bits ctx;
5223 };
5224
5225 struct mlx5_ifc_create_tir_out_bits {
5226         u8         status[0x8];
5227         u8         reserved_0[0x18];
5228
5229         u8         syndrome[0x20];
5230
5231         u8         reserved_1[0x8];
5232         u8         tirn[0x18];
5233
5234         u8         reserved_2[0x20];
5235 };
5236
5237 struct mlx5_ifc_create_tir_in_bits {
5238         u8         opcode[0x10];
5239         u8         reserved_0[0x10];
5240
5241         u8         reserved_1[0x10];
5242         u8         op_mod[0x10];
5243
5244         u8         reserved_2[0xc0];
5245
5246         struct mlx5_ifc_tirc_bits ctx;
5247 };
5248
5249 struct mlx5_ifc_create_srq_out_bits {
5250         u8         status[0x8];
5251         u8         reserved_0[0x18];
5252
5253         u8         syndrome[0x20];
5254
5255         u8         reserved_1[0x8];
5256         u8         srqn[0x18];
5257
5258         u8         reserved_2[0x20];
5259 };
5260
5261 struct mlx5_ifc_create_srq_in_bits {
5262         u8         opcode[0x10];
5263         u8         reserved_0[0x10];
5264
5265         u8         reserved_1[0x10];
5266         u8         op_mod[0x10];
5267
5268         u8         reserved_2[0x40];
5269
5270         struct mlx5_ifc_srqc_bits srq_context_entry;
5271
5272         u8         reserved_3[0x600];
5273
5274         u8         pas[0][0x40];
5275 };
5276
5277 struct mlx5_ifc_create_sq_out_bits {
5278         u8         status[0x8];
5279         u8         reserved_0[0x18];
5280
5281         u8         syndrome[0x20];
5282
5283         u8         reserved_1[0x8];
5284         u8         sqn[0x18];
5285
5286         u8         reserved_2[0x20];
5287 };
5288
5289 struct mlx5_ifc_create_sq_in_bits {
5290         u8         opcode[0x10];
5291         u8         reserved_0[0x10];
5292
5293         u8         reserved_1[0x10];
5294         u8         op_mod[0x10];
5295
5296         u8         reserved_2[0xc0];
5297
5298         struct mlx5_ifc_sqc_bits ctx;
5299 };
5300
5301 struct mlx5_ifc_create_rqt_out_bits {
5302         u8         status[0x8];
5303         u8         reserved_0[0x18];
5304
5305         u8         syndrome[0x20];
5306
5307         u8         reserved_1[0x8];
5308         u8         rqtn[0x18];
5309
5310         u8         reserved_2[0x20];
5311 };
5312
5313 struct mlx5_ifc_create_rqt_in_bits {
5314         u8         opcode[0x10];
5315         u8         reserved_0[0x10];
5316
5317         u8         reserved_1[0x10];
5318         u8         op_mod[0x10];
5319
5320         u8         reserved_2[0xc0];
5321
5322         struct mlx5_ifc_rqtc_bits rqt_context;
5323 };
5324
5325 struct mlx5_ifc_create_rq_out_bits {
5326         u8         status[0x8];
5327         u8         reserved_0[0x18];
5328
5329         u8         syndrome[0x20];
5330
5331         u8         reserved_1[0x8];
5332         u8         rqn[0x18];
5333
5334         u8         reserved_2[0x20];
5335 };
5336
5337 struct mlx5_ifc_create_rq_in_bits {
5338         u8         opcode[0x10];
5339         u8         reserved_0[0x10];
5340
5341         u8         reserved_1[0x10];
5342         u8         op_mod[0x10];
5343
5344         u8         reserved_2[0xc0];
5345
5346         struct mlx5_ifc_rqc_bits ctx;
5347 };
5348
5349 struct mlx5_ifc_create_rmp_out_bits {
5350         u8         status[0x8];
5351         u8         reserved_0[0x18];
5352
5353         u8         syndrome[0x20];
5354
5355         u8         reserved_1[0x8];
5356         u8         rmpn[0x18];
5357
5358         u8         reserved_2[0x20];
5359 };
5360
5361 struct mlx5_ifc_create_rmp_in_bits {
5362         u8         opcode[0x10];
5363         u8         reserved_0[0x10];
5364
5365         u8         reserved_1[0x10];
5366         u8         op_mod[0x10];
5367
5368         u8         reserved_2[0xc0];
5369
5370         struct mlx5_ifc_rmpc_bits ctx;
5371 };
5372
5373 struct mlx5_ifc_create_qp_out_bits {
5374         u8         status[0x8];
5375         u8         reserved_0[0x18];
5376
5377         u8         syndrome[0x20];
5378
5379         u8         reserved_1[0x8];
5380         u8         qpn[0x18];
5381
5382         u8         reserved_2[0x20];
5383 };
5384
5385 struct mlx5_ifc_create_qp_in_bits {
5386         u8         opcode[0x10];
5387         u8         reserved_0[0x10];
5388
5389         u8         reserved_1[0x10];
5390         u8         op_mod[0x10];
5391
5392         u8         reserved_2[0x40];
5393
5394         u8         opt_param_mask[0x20];
5395
5396         u8         reserved_3[0x20];
5397
5398         struct mlx5_ifc_qpc_bits qpc;
5399
5400         u8         reserved_4[0x80];
5401
5402         u8         pas[0][0x40];
5403 };
5404
5405 struct mlx5_ifc_create_psv_out_bits {
5406         u8         status[0x8];
5407         u8         reserved_0[0x18];
5408
5409         u8         syndrome[0x20];
5410
5411         u8         reserved_1[0x40];
5412
5413         u8         reserved_2[0x8];
5414         u8         psv0_index[0x18];
5415
5416         u8         reserved_3[0x8];
5417         u8         psv1_index[0x18];
5418
5419         u8         reserved_4[0x8];
5420         u8         psv2_index[0x18];
5421
5422         u8         reserved_5[0x8];
5423         u8         psv3_index[0x18];
5424 };
5425
5426 struct mlx5_ifc_create_psv_in_bits {
5427         u8         opcode[0x10];
5428         u8         reserved_0[0x10];
5429
5430         u8         reserved_1[0x10];
5431         u8         op_mod[0x10];
5432
5433         u8         num_psv[0x4];
5434         u8         reserved_2[0x4];
5435         u8         pd[0x18];
5436
5437         u8         reserved_3[0x20];
5438 };
5439
5440 struct mlx5_ifc_create_mkey_out_bits {
5441         u8         status[0x8];
5442         u8         reserved_0[0x18];
5443
5444         u8         syndrome[0x20];
5445
5446         u8         reserved_1[0x8];
5447         u8         mkey_index[0x18];
5448
5449         u8         reserved_2[0x20];
5450 };
5451
5452 struct mlx5_ifc_create_mkey_in_bits {
5453         u8         opcode[0x10];
5454         u8         reserved_0[0x10];
5455
5456         u8         reserved_1[0x10];
5457         u8         op_mod[0x10];
5458
5459         u8         reserved_2[0x20];
5460
5461         u8         pg_access[0x1];
5462         u8         reserved_3[0x1f];
5463
5464         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5465
5466         u8         reserved_4[0x80];
5467
5468         u8         translations_octword_actual_size[0x20];
5469
5470         u8         reserved_5[0x560];
5471
5472         u8         klm_pas_mtt[0][0x20];
5473 };
5474
5475 struct mlx5_ifc_create_flow_table_out_bits {
5476         u8         status[0x8];
5477         u8         reserved_0[0x18];
5478
5479         u8         syndrome[0x20];
5480
5481         u8         reserved_1[0x8];
5482         u8         table_id[0x18];
5483
5484         u8         reserved_2[0x20];
5485 };
5486
5487 struct mlx5_ifc_create_flow_table_in_bits {
5488         u8         opcode[0x10];
5489         u8         reserved_0[0x10];
5490
5491         u8         reserved_1[0x10];
5492         u8         op_mod[0x10];
5493
5494         u8         reserved_2[0x40];
5495
5496         u8         table_type[0x8];
5497         u8         reserved_3[0x18];
5498
5499         u8         reserved_4[0x20];
5500
5501         u8         reserved_5[0x8];
5502         u8         level[0x8];
5503         u8         reserved_6[0x8];
5504         u8         log_size[0x8];
5505
5506         u8         reserved_7[0x120];
5507 };
5508
5509 struct mlx5_ifc_create_flow_group_out_bits {
5510         u8         status[0x8];
5511         u8         reserved_0[0x18];
5512
5513         u8         syndrome[0x20];
5514
5515         u8         reserved_1[0x8];
5516         u8         group_id[0x18];
5517
5518         u8         reserved_2[0x20];
5519 };
5520
5521 enum {
5522         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5523         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5524         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5525 };
5526
5527 struct mlx5_ifc_create_flow_group_in_bits {
5528         u8         opcode[0x10];
5529         u8         reserved_0[0x10];
5530
5531         u8         reserved_1[0x10];
5532         u8         op_mod[0x10];
5533
5534         u8         reserved_2[0x40];
5535
5536         u8         table_type[0x8];
5537         u8         reserved_3[0x18];
5538
5539         u8         reserved_4[0x8];
5540         u8         table_id[0x18];
5541
5542         u8         reserved_5[0x20];
5543
5544         u8         start_flow_index[0x20];
5545
5546         u8         reserved_6[0x20];
5547
5548         u8         end_flow_index[0x20];
5549
5550         u8         reserved_7[0xa0];
5551
5552         u8         reserved_8[0x18];
5553         u8         match_criteria_enable[0x8];
5554
5555         struct mlx5_ifc_fte_match_param_bits match_criteria;
5556
5557         u8         reserved_9[0xe00];
5558 };
5559
5560 struct mlx5_ifc_create_eq_out_bits {
5561         u8         status[0x8];
5562         u8         reserved_0[0x18];
5563
5564         u8         syndrome[0x20];
5565
5566         u8         reserved_1[0x18];
5567         u8         eq_number[0x8];
5568
5569         u8         reserved_2[0x20];
5570 };
5571
5572 struct mlx5_ifc_create_eq_in_bits {
5573         u8         opcode[0x10];
5574         u8         reserved_0[0x10];
5575
5576         u8         reserved_1[0x10];
5577         u8         op_mod[0x10];
5578
5579         u8         reserved_2[0x40];
5580
5581         struct mlx5_ifc_eqc_bits eq_context_entry;
5582
5583         u8         reserved_3[0x40];
5584
5585         u8         event_bitmask[0x40];
5586
5587         u8         reserved_4[0x580];
5588
5589         u8         pas[0][0x40];
5590 };
5591
5592 struct mlx5_ifc_create_dct_out_bits {
5593         u8         status[0x8];
5594         u8         reserved_0[0x18];
5595
5596         u8         syndrome[0x20];
5597
5598         u8         reserved_1[0x8];
5599         u8         dctn[0x18];
5600
5601         u8         reserved_2[0x20];
5602 };
5603
5604 struct mlx5_ifc_create_dct_in_bits {
5605         u8         opcode[0x10];
5606         u8         reserved_0[0x10];
5607
5608         u8         reserved_1[0x10];
5609         u8         op_mod[0x10];
5610
5611         u8         reserved_2[0x40];
5612
5613         struct mlx5_ifc_dctc_bits dct_context_entry;
5614
5615         u8         reserved_3[0x180];
5616 };
5617
5618 struct mlx5_ifc_create_cq_out_bits {
5619         u8         status[0x8];
5620         u8         reserved_0[0x18];
5621
5622         u8         syndrome[0x20];
5623
5624         u8         reserved_1[0x8];
5625         u8         cqn[0x18];
5626
5627         u8         reserved_2[0x20];
5628 };
5629
5630 struct mlx5_ifc_create_cq_in_bits {
5631         u8         opcode[0x10];
5632         u8         reserved_0[0x10];
5633
5634         u8         reserved_1[0x10];
5635         u8         op_mod[0x10];
5636
5637         u8         reserved_2[0x40];
5638
5639         struct mlx5_ifc_cqc_bits cq_context;
5640
5641         u8         reserved_3[0x600];
5642
5643         u8         pas[0][0x40];
5644 };
5645
5646 struct mlx5_ifc_config_int_moderation_out_bits {
5647         u8         status[0x8];
5648         u8         reserved_0[0x18];
5649
5650         u8         syndrome[0x20];
5651
5652         u8         reserved_1[0x4];
5653         u8         min_delay[0xc];
5654         u8         int_vector[0x10];
5655
5656         u8         reserved_2[0x20];
5657 };
5658
5659 enum {
5660         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
5661         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
5662 };
5663
5664 struct mlx5_ifc_config_int_moderation_in_bits {
5665         u8         opcode[0x10];
5666         u8         reserved_0[0x10];
5667
5668         u8         reserved_1[0x10];
5669         u8         op_mod[0x10];
5670
5671         u8         reserved_2[0x4];
5672         u8         min_delay[0xc];
5673         u8         int_vector[0x10];
5674
5675         u8         reserved_3[0x20];
5676 };
5677
5678 struct mlx5_ifc_attach_to_mcg_out_bits {
5679         u8         status[0x8];
5680         u8         reserved_0[0x18];
5681
5682         u8         syndrome[0x20];
5683
5684         u8         reserved_1[0x40];
5685 };
5686
5687 struct mlx5_ifc_attach_to_mcg_in_bits {
5688         u8         opcode[0x10];
5689         u8         reserved_0[0x10];
5690
5691         u8         reserved_1[0x10];
5692         u8         op_mod[0x10];
5693
5694         u8         reserved_2[0x8];
5695         u8         qpn[0x18];
5696
5697         u8         reserved_3[0x20];
5698
5699         u8         multicast_gid[16][0x8];
5700 };
5701
5702 struct mlx5_ifc_arm_xrc_srq_out_bits {
5703         u8         status[0x8];
5704         u8         reserved_0[0x18];
5705
5706         u8         syndrome[0x20];
5707
5708         u8         reserved_1[0x40];
5709 };
5710
5711 enum {
5712         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
5713 };
5714
5715 struct mlx5_ifc_arm_xrc_srq_in_bits {
5716         u8         opcode[0x10];
5717         u8         reserved_0[0x10];
5718
5719         u8         reserved_1[0x10];
5720         u8         op_mod[0x10];
5721
5722         u8         reserved_2[0x8];
5723         u8         xrc_srqn[0x18];
5724
5725         u8         reserved_3[0x10];
5726         u8         lwm[0x10];
5727 };
5728
5729 struct mlx5_ifc_arm_rq_out_bits {
5730         u8         status[0x8];
5731         u8         reserved_0[0x18];
5732
5733         u8         syndrome[0x20];
5734
5735         u8         reserved_1[0x40];
5736 };
5737
5738 enum {
5739         MLX5_ARM_RQ_IN_OP_MOD_SRQ_  = 0x1,
5740 };
5741
5742 struct mlx5_ifc_arm_rq_in_bits {
5743         u8         opcode[0x10];
5744         u8         reserved_0[0x10];
5745
5746         u8         reserved_1[0x10];
5747         u8         op_mod[0x10];
5748
5749         u8         reserved_2[0x8];
5750         u8         srq_number[0x18];
5751
5752         u8         reserved_3[0x10];
5753         u8         lwm[0x10];
5754 };
5755
5756 struct mlx5_ifc_arm_dct_out_bits {
5757         u8         status[0x8];
5758         u8         reserved_0[0x18];
5759
5760         u8         syndrome[0x20];
5761
5762         u8         reserved_1[0x40];
5763 };
5764
5765 struct mlx5_ifc_arm_dct_in_bits {
5766         u8         opcode[0x10];
5767         u8         reserved_0[0x10];
5768
5769         u8         reserved_1[0x10];
5770         u8         op_mod[0x10];
5771
5772         u8         reserved_2[0x8];
5773         u8         dct_number[0x18];
5774
5775         u8         reserved_3[0x20];
5776 };
5777
5778 struct mlx5_ifc_alloc_xrcd_out_bits {
5779         u8         status[0x8];
5780         u8         reserved_0[0x18];
5781
5782         u8         syndrome[0x20];
5783
5784         u8         reserved_1[0x8];
5785         u8         xrcd[0x18];
5786
5787         u8         reserved_2[0x20];
5788 };
5789
5790 struct mlx5_ifc_alloc_xrcd_in_bits {
5791         u8         opcode[0x10];
5792         u8         reserved_0[0x10];
5793
5794         u8         reserved_1[0x10];
5795         u8         op_mod[0x10];
5796
5797         u8         reserved_2[0x40];
5798 };
5799
5800 struct mlx5_ifc_alloc_uar_out_bits {
5801         u8         status[0x8];
5802         u8         reserved_0[0x18];
5803
5804         u8         syndrome[0x20];
5805
5806         u8         reserved_1[0x8];
5807         u8         uar[0x18];
5808
5809         u8         reserved_2[0x20];
5810 };
5811
5812 struct mlx5_ifc_alloc_uar_in_bits {
5813         u8         opcode[0x10];
5814         u8         reserved_0[0x10];
5815
5816         u8         reserved_1[0x10];
5817         u8         op_mod[0x10];
5818
5819         u8         reserved_2[0x40];
5820 };
5821
5822 struct mlx5_ifc_alloc_transport_domain_out_bits {
5823         u8         status[0x8];
5824         u8         reserved_0[0x18];
5825
5826         u8         syndrome[0x20];
5827
5828         u8         reserved_1[0x8];
5829         u8         transport_domain[0x18];
5830
5831         u8         reserved_2[0x20];
5832 };
5833
5834 struct mlx5_ifc_alloc_transport_domain_in_bits {
5835         u8         opcode[0x10];
5836         u8         reserved_0[0x10];
5837
5838         u8         reserved_1[0x10];
5839         u8         op_mod[0x10];
5840
5841         u8         reserved_2[0x40];
5842 };
5843
5844 struct mlx5_ifc_alloc_q_counter_out_bits {
5845         u8         status[0x8];
5846         u8         reserved_0[0x18];
5847
5848         u8         syndrome[0x20];
5849
5850         u8         reserved_1[0x18];
5851         u8         counter_set_id[0x8];
5852
5853         u8         reserved_2[0x20];
5854 };
5855
5856 struct mlx5_ifc_alloc_q_counter_in_bits {
5857         u8         opcode[0x10];
5858         u8         reserved_0[0x10];
5859
5860         u8         reserved_1[0x10];
5861         u8         op_mod[0x10];
5862
5863         u8         reserved_2[0x40];
5864 };
5865
5866 struct mlx5_ifc_alloc_pd_out_bits {
5867         u8         status[0x8];
5868         u8         reserved_0[0x18];
5869
5870         u8         syndrome[0x20];
5871
5872         u8         reserved_1[0x8];
5873         u8         pd[0x18];
5874
5875         u8         reserved_2[0x20];
5876 };
5877
5878 struct mlx5_ifc_alloc_pd_in_bits {
5879         u8         opcode[0x10];
5880         u8         reserved_0[0x10];
5881
5882         u8         reserved_1[0x10];
5883         u8         op_mod[0x10];
5884
5885         u8         reserved_2[0x40];
5886 };
5887
5888 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
5889         u8         status[0x8];
5890         u8         reserved_0[0x18];
5891
5892         u8         syndrome[0x20];
5893
5894         u8         reserved_1[0x40];
5895 };
5896
5897 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
5898         u8         opcode[0x10];
5899         u8         reserved_0[0x10];
5900
5901         u8         reserved_1[0x10];
5902         u8         op_mod[0x10];
5903
5904         u8         reserved_2[0x20];
5905
5906         u8         reserved_3[0x10];
5907         u8         vxlan_udp_port[0x10];
5908 };
5909
5910 struct mlx5_ifc_access_register_out_bits {
5911         u8         status[0x8];
5912         u8         reserved_0[0x18];
5913
5914         u8         syndrome[0x20];
5915
5916         u8         reserved_1[0x40];
5917
5918         u8         register_data[0][0x20];
5919 };
5920
5921 enum {
5922         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
5923         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
5924 };
5925
5926 struct mlx5_ifc_access_register_in_bits {
5927         u8         opcode[0x10];
5928         u8         reserved_0[0x10];
5929
5930         u8         reserved_1[0x10];
5931         u8         op_mod[0x10];
5932
5933         u8         reserved_2[0x10];
5934         u8         register_id[0x10];
5935
5936         u8         argument[0x20];
5937
5938         u8         register_data[0][0x20];
5939 };
5940
5941 struct mlx5_ifc_sltp_reg_bits {
5942         u8         status[0x4];
5943         u8         version[0x4];
5944         u8         local_port[0x8];
5945         u8         pnat[0x2];
5946         u8         reserved_0[0x2];
5947         u8         lane[0x4];
5948         u8         reserved_1[0x8];
5949
5950         u8         reserved_2[0x20];
5951
5952         u8         reserved_3[0x7];
5953         u8         polarity[0x1];
5954         u8         ob_tap0[0x8];
5955         u8         ob_tap1[0x8];
5956         u8         ob_tap2[0x8];
5957
5958         u8         reserved_4[0xc];
5959         u8         ob_preemp_mode[0x4];
5960         u8         ob_reg[0x8];
5961         u8         ob_bias[0x8];
5962
5963         u8         reserved_5[0x20];
5964 };
5965
5966 struct mlx5_ifc_slrg_reg_bits {
5967         u8         status[0x4];
5968         u8         version[0x4];
5969         u8         local_port[0x8];
5970         u8         pnat[0x2];
5971         u8         reserved_0[0x2];
5972         u8         lane[0x4];
5973         u8         reserved_1[0x8];
5974
5975         u8         time_to_link_up[0x10];
5976         u8         reserved_2[0xc];
5977         u8         grade_lane_speed[0x4];
5978
5979         u8         grade_version[0x8];
5980         u8         grade[0x18];
5981
5982         u8         reserved_3[0x4];
5983         u8         height_grade_type[0x4];
5984         u8         height_grade[0x18];
5985
5986         u8         height_dz[0x10];
5987         u8         height_dv[0x10];
5988
5989         u8         reserved_4[0x10];
5990         u8         height_sigma[0x10];
5991
5992         u8         reserved_5[0x20];
5993
5994         u8         reserved_6[0x4];
5995         u8         phase_grade_type[0x4];
5996         u8         phase_grade[0x18];
5997
5998         u8         reserved_7[0x8];
5999         u8         phase_eo_pos[0x8];
6000         u8         reserved_8[0x8];
6001         u8         phase_eo_neg[0x8];
6002
6003         u8         ffe_set_tested[0x10];
6004         u8         test_errors_per_lane[0x10];
6005 };
6006
6007 struct mlx5_ifc_pvlc_reg_bits {
6008         u8         reserved_0[0x8];
6009         u8         local_port[0x8];
6010         u8         reserved_1[0x10];
6011
6012         u8         reserved_2[0x1c];
6013         u8         vl_hw_cap[0x4];
6014
6015         u8         reserved_3[0x1c];
6016         u8         vl_admin[0x4];
6017
6018         u8         reserved_4[0x1c];
6019         u8         vl_operational[0x4];
6020 };
6021
6022 struct mlx5_ifc_pude_reg_bits {
6023         u8         swid[0x8];
6024         u8         local_port[0x8];
6025         u8         reserved_0[0x4];
6026         u8         admin_status[0x4];
6027         u8         reserved_1[0x4];
6028         u8         oper_status[0x4];
6029
6030         u8         reserved_2[0x60];
6031 };
6032
6033 struct mlx5_ifc_ptys_reg_bits {
6034         u8         reserved_0[0x8];
6035         u8         local_port[0x8];
6036         u8         reserved_1[0xd];
6037         u8         proto_mask[0x3];
6038
6039         u8         reserved_2[0x40];
6040
6041         u8         eth_proto_capability[0x20];
6042
6043         u8         ib_link_width_capability[0x10];
6044         u8         ib_proto_capability[0x10];
6045
6046         u8         reserved_3[0x20];
6047
6048         u8         eth_proto_admin[0x20];
6049
6050         u8         ib_link_width_admin[0x10];
6051         u8         ib_proto_admin[0x10];
6052
6053         u8         reserved_4[0x20];
6054
6055         u8         eth_proto_oper[0x20];
6056
6057         u8         ib_link_width_oper[0x10];
6058         u8         ib_proto_oper[0x10];
6059
6060         u8         reserved_5[0x20];
6061
6062         u8         eth_proto_lp_advertise[0x20];
6063
6064         u8         reserved_6[0x60];
6065 };
6066
6067 struct mlx5_ifc_ptas_reg_bits {
6068         u8         reserved_0[0x20];
6069
6070         u8         algorithm_options[0x10];
6071         u8         reserved_1[0x4];
6072         u8         repetitions_mode[0x4];
6073         u8         num_of_repetitions[0x8];
6074
6075         u8         grade_version[0x8];
6076         u8         height_grade_type[0x4];
6077         u8         phase_grade_type[0x4];
6078         u8         height_grade_weight[0x8];
6079         u8         phase_grade_weight[0x8];
6080
6081         u8         gisim_measure_bits[0x10];
6082         u8         adaptive_tap_measure_bits[0x10];
6083
6084         u8         ber_bath_high_error_threshold[0x10];
6085         u8         ber_bath_mid_error_threshold[0x10];
6086
6087         u8         ber_bath_low_error_threshold[0x10];
6088         u8         one_ratio_high_threshold[0x10];
6089
6090         u8         one_ratio_high_mid_threshold[0x10];
6091         u8         one_ratio_low_mid_threshold[0x10];
6092
6093         u8         one_ratio_low_threshold[0x10];
6094         u8         ndeo_error_threshold[0x10];
6095
6096         u8         mixer_offset_step_size[0x10];
6097         u8         reserved_2[0x8];
6098         u8         mix90_phase_for_voltage_bath[0x8];
6099
6100         u8         mixer_offset_start[0x10];
6101         u8         mixer_offset_end[0x10];
6102
6103         u8         reserved_3[0x15];
6104         u8         ber_test_time[0xb];
6105 };
6106
6107 struct mlx5_ifc_pspa_reg_bits {
6108         u8         swid[0x8];
6109         u8         local_port[0x8];
6110         u8         sub_port[0x8];
6111         u8         reserved_0[0x8];
6112
6113         u8         reserved_1[0x20];
6114 };
6115
6116 struct mlx5_ifc_pqdr_reg_bits {
6117         u8         reserved_0[0x8];
6118         u8         local_port[0x8];
6119         u8         reserved_1[0x5];
6120         u8         prio[0x3];
6121         u8         reserved_2[0x6];
6122         u8         mode[0x2];
6123
6124         u8         reserved_3[0x20];
6125
6126         u8         reserved_4[0x10];
6127         u8         min_threshold[0x10];
6128
6129         u8         reserved_5[0x10];
6130         u8         max_threshold[0x10];
6131
6132         u8         reserved_6[0x10];
6133         u8         mark_probability_denominator[0x10];
6134
6135         u8         reserved_7[0x60];
6136 };
6137
6138 struct mlx5_ifc_ppsc_reg_bits {
6139         u8         reserved_0[0x8];
6140         u8         local_port[0x8];
6141         u8         reserved_1[0x10];
6142
6143         u8         reserved_2[0x60];
6144
6145         u8         reserved_3[0x1c];
6146         u8         wrps_admin[0x4];
6147
6148         u8         reserved_4[0x1c];
6149         u8         wrps_status[0x4];
6150
6151         u8         reserved_5[0x8];
6152         u8         up_threshold[0x8];
6153         u8         reserved_6[0x8];
6154         u8         down_threshold[0x8];
6155
6156         u8         reserved_7[0x20];
6157
6158         u8         reserved_8[0x1c];
6159         u8         srps_admin[0x4];
6160
6161         u8         reserved_9[0x1c];
6162         u8         srps_status[0x4];
6163
6164         u8         reserved_10[0x40];
6165 };
6166
6167 struct mlx5_ifc_pplr_reg_bits {
6168         u8         reserved_0[0x8];
6169         u8         local_port[0x8];
6170         u8         reserved_1[0x10];
6171
6172         u8         reserved_2[0x8];
6173         u8         lb_cap[0x8];
6174         u8         reserved_3[0x8];
6175         u8         lb_en[0x8];
6176 };
6177
6178 struct mlx5_ifc_pplm_reg_bits {
6179         u8         reserved_0[0x8];
6180         u8         local_port[0x8];
6181         u8         reserved_1[0x10];
6182
6183         u8         reserved_2[0x20];
6184
6185         u8         port_profile_mode[0x8];
6186         u8         static_port_profile[0x8];
6187         u8         active_port_profile[0x8];
6188         u8         reserved_3[0x8];
6189
6190         u8         retransmission_active[0x8];
6191         u8         fec_mode_active[0x18];
6192
6193         u8         reserved_4[0x20];
6194 };
6195
6196 struct mlx5_ifc_ppcnt_reg_bits {
6197         u8         swid[0x8];
6198         u8         local_port[0x8];
6199         u8         pnat[0x2];
6200         u8         reserved_0[0x8];
6201         u8         grp[0x6];
6202
6203         u8         clr[0x1];
6204         u8         reserved_1[0x1c];
6205         u8         prio_tc[0x3];
6206
6207         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6208 };
6209
6210 struct mlx5_ifc_ppad_reg_bits {
6211         u8         reserved_0[0x3];
6212         u8         single_mac[0x1];
6213         u8         reserved_1[0x4];
6214         u8         local_port[0x8];
6215         u8         mac_47_32[0x10];
6216
6217         u8         mac_31_0[0x20];
6218
6219         u8         reserved_2[0x40];
6220 };
6221
6222 struct mlx5_ifc_pmtu_reg_bits {
6223         u8         reserved_0[0x8];
6224         u8         local_port[0x8];
6225         u8         reserved_1[0x10];
6226
6227         u8         max_mtu[0x10];
6228         u8         reserved_2[0x10];
6229
6230         u8         admin_mtu[0x10];
6231         u8         reserved_3[0x10];
6232
6233         u8         oper_mtu[0x10];
6234         u8         reserved_4[0x10];
6235 };
6236
6237 struct mlx5_ifc_pmpr_reg_bits {
6238         u8         reserved_0[0x8];
6239         u8         module[0x8];
6240         u8         reserved_1[0x10];
6241
6242         u8         reserved_2[0x18];
6243         u8         attenuation_5g[0x8];
6244
6245         u8         reserved_3[0x18];
6246         u8         attenuation_7g[0x8];
6247
6248         u8         reserved_4[0x18];
6249         u8         attenuation_12g[0x8];
6250 };
6251
6252 struct mlx5_ifc_pmpe_reg_bits {
6253         u8         reserved_0[0x8];
6254         u8         module[0x8];
6255         u8         reserved_1[0xc];
6256         u8         module_status[0x4];
6257
6258         u8         reserved_2[0x60];
6259 };
6260
6261 struct mlx5_ifc_pmpc_reg_bits {
6262         u8         module_state_updated[32][0x8];
6263 };
6264
6265 struct mlx5_ifc_pmlpn_reg_bits {
6266         u8         reserved_0[0x4];
6267         u8         mlpn_status[0x4];
6268         u8         local_port[0x8];
6269         u8         reserved_1[0x10];
6270
6271         u8         e[0x1];
6272         u8         reserved_2[0x1f];
6273 };
6274
6275 struct mlx5_ifc_pmlp_reg_bits {
6276         u8         rxtx[0x1];
6277         u8         reserved_0[0x7];
6278         u8         local_port[0x8];
6279         u8         reserved_1[0x8];
6280         u8         width[0x8];
6281
6282         u8         lane0_module_mapping[0x20];
6283
6284         u8         lane1_module_mapping[0x20];
6285
6286         u8         lane2_module_mapping[0x20];
6287
6288         u8         lane3_module_mapping[0x20];
6289
6290         u8         reserved_2[0x160];
6291 };
6292
6293 struct mlx5_ifc_pmaos_reg_bits {
6294         u8         reserved_0[0x8];
6295         u8         module[0x8];
6296         u8         reserved_1[0x4];
6297         u8         admin_status[0x4];
6298         u8         reserved_2[0x4];
6299         u8         oper_status[0x4];
6300
6301         u8         ase[0x1];
6302         u8         ee[0x1];
6303         u8         reserved_3[0x1c];
6304         u8         e[0x2];
6305
6306         u8         reserved_4[0x40];
6307 };
6308
6309 struct mlx5_ifc_plpc_reg_bits {
6310         u8         reserved_0[0x4];
6311         u8         profile_id[0xc];
6312         u8         reserved_1[0x4];
6313         u8         proto_mask[0x4];
6314         u8         reserved_2[0x8];
6315
6316         u8         reserved_3[0x10];
6317         u8         lane_speed[0x10];
6318
6319         u8         reserved_4[0x17];
6320         u8         lpbf[0x1];
6321         u8         fec_mode_policy[0x8];
6322
6323         u8         retransmission_capability[0x8];
6324         u8         fec_mode_capability[0x18];
6325
6326         u8         retransmission_support_admin[0x8];
6327         u8         fec_mode_support_admin[0x18];
6328
6329         u8         retransmission_request_admin[0x8];
6330         u8         fec_mode_request_admin[0x18];
6331
6332         u8         reserved_5[0x80];
6333 };
6334
6335 struct mlx5_ifc_plib_reg_bits {
6336         u8         reserved_0[0x8];
6337         u8         local_port[0x8];
6338         u8         reserved_1[0x8];
6339         u8         ib_port[0x8];
6340
6341         u8         reserved_2[0x60];
6342 };
6343
6344 struct mlx5_ifc_plbf_reg_bits {
6345         u8         reserved_0[0x8];
6346         u8         local_port[0x8];
6347         u8         reserved_1[0xd];
6348         u8         lbf_mode[0x3];
6349
6350         u8         reserved_2[0x20];
6351 };
6352
6353 struct mlx5_ifc_pipg_reg_bits {
6354         u8         reserved_0[0x8];
6355         u8         local_port[0x8];
6356         u8         reserved_1[0x10];
6357
6358         u8         dic[0x1];
6359         u8         reserved_2[0x19];
6360         u8         ipg[0x4];
6361         u8         reserved_3[0x2];
6362 };
6363
6364 struct mlx5_ifc_pifr_reg_bits {
6365         u8         reserved_0[0x8];
6366         u8         local_port[0x8];
6367         u8         reserved_1[0x10];
6368
6369         u8         reserved_2[0xe0];
6370
6371         u8         port_filter[8][0x20];
6372
6373         u8         port_filter_update_en[8][0x20];
6374 };
6375
6376 struct mlx5_ifc_pfcc_reg_bits {
6377         u8         reserved_0[0x8];
6378         u8         local_port[0x8];
6379         u8         reserved_1[0x10];
6380
6381         u8         ppan[0x4];
6382         u8         reserved_2[0x4];
6383         u8         prio_mask_tx[0x8];
6384         u8         reserved_3[0x8];
6385         u8         prio_mask_rx[0x8];
6386
6387         u8         pptx[0x1];
6388         u8         aptx[0x1];
6389         u8         reserved_4[0x6];
6390         u8         pfctx[0x8];
6391         u8         reserved_5[0x10];
6392
6393         u8         pprx[0x1];
6394         u8         aprx[0x1];
6395         u8         reserved_6[0x6];
6396         u8         pfcrx[0x8];
6397         u8         reserved_7[0x10];
6398
6399         u8         reserved_8[0x80];
6400 };
6401
6402 struct mlx5_ifc_pelc_reg_bits {
6403         u8         op[0x4];
6404         u8         reserved_0[0x4];
6405         u8         local_port[0x8];
6406         u8         reserved_1[0x10];
6407
6408         u8         op_admin[0x8];
6409         u8         op_capability[0x8];
6410         u8         op_request[0x8];
6411         u8         op_active[0x8];
6412
6413         u8         admin[0x40];
6414
6415         u8         capability[0x40];
6416
6417         u8         request[0x40];
6418
6419         u8         active[0x40];
6420
6421         u8         reserved_2[0x80];
6422 };
6423
6424 struct mlx5_ifc_peir_reg_bits {
6425         u8         reserved_0[0x8];
6426         u8         local_port[0x8];
6427         u8         reserved_1[0x10];
6428
6429         u8         reserved_2[0xc];
6430         u8         error_count[0x4];
6431         u8         reserved_3[0x10];
6432
6433         u8         reserved_4[0xc];
6434         u8         lane[0x4];
6435         u8         reserved_5[0x8];
6436         u8         error_type[0x8];
6437 };
6438
6439 struct mlx5_ifc_pcap_reg_bits {
6440         u8         reserved_0[0x8];
6441         u8         local_port[0x8];
6442         u8         reserved_1[0x10];
6443
6444         u8         port_capability_mask[4][0x20];
6445 };
6446
6447 struct mlx5_ifc_paos_reg_bits {
6448         u8         swid[0x8];
6449         u8         local_port[0x8];
6450         u8         reserved_0[0x4];
6451         u8         admin_status[0x4];
6452         u8         reserved_1[0x4];
6453         u8         oper_status[0x4];
6454
6455         u8         ase[0x1];
6456         u8         ee[0x1];
6457         u8         reserved_2[0x1c];
6458         u8         e[0x2];
6459
6460         u8         reserved_3[0x40];
6461 };
6462
6463 struct mlx5_ifc_pamp_reg_bits {
6464         u8         reserved_0[0x8];
6465         u8         opamp_group[0x8];
6466         u8         reserved_1[0xc];
6467         u8         opamp_group_type[0x4];
6468
6469         u8         start_index[0x10];
6470         u8         reserved_2[0x4];
6471         u8         num_of_indices[0xc];
6472
6473         u8         index_data[18][0x10];
6474 };
6475
6476 struct mlx5_ifc_lane_2_module_mapping_bits {
6477         u8         reserved_0[0x6];
6478         u8         rx_lane[0x2];
6479         u8         reserved_1[0x6];
6480         u8         tx_lane[0x2];
6481         u8         reserved_2[0x8];
6482         u8         module[0x8];
6483 };
6484
6485 struct mlx5_ifc_bufferx_reg_bits {
6486         u8         reserved_0[0x6];
6487         u8         lossy[0x1];
6488         u8         epsb[0x1];
6489         u8         reserved_1[0xc];
6490         u8         size[0xc];
6491
6492         u8         xoff_threshold[0x10];
6493         u8         xon_threshold[0x10];
6494 };
6495
6496 struct mlx5_ifc_set_node_in_bits {
6497         u8         node_description[64][0x8];
6498 };
6499
6500 struct mlx5_ifc_register_power_settings_bits {
6501         u8         reserved_0[0x18];
6502         u8         power_settings_level[0x8];
6503
6504         u8         reserved_1[0x60];
6505 };
6506
6507 struct mlx5_ifc_register_host_endianness_bits {
6508         u8         he[0x1];
6509         u8         reserved_0[0x1f];
6510
6511         u8         reserved_1[0x60];
6512 };
6513
6514 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6515         u8         reserved_0[0x20];
6516
6517         u8         mkey[0x20];
6518
6519         u8         addressh_63_32[0x20];
6520
6521         u8         addressl_31_0[0x20];
6522 };
6523
6524 struct mlx5_ifc_ud_adrs_vector_bits {
6525         u8         dc_key[0x40];
6526
6527         u8         ext[0x1];
6528         u8         reserved_0[0x7];
6529         u8         destination_qp_dct[0x18];
6530
6531         u8         static_rate[0x4];
6532         u8         sl_eth_prio[0x4];
6533         u8         fl[0x1];
6534         u8         mlid[0x7];
6535         u8         rlid_udp_sport[0x10];
6536
6537         u8         reserved_1[0x20];
6538
6539         u8         rmac_47_16[0x20];
6540
6541         u8         rmac_15_0[0x10];
6542         u8         tclass[0x8];
6543         u8         hop_limit[0x8];
6544
6545         u8         reserved_2[0x1];
6546         u8         grh[0x1];
6547         u8         reserved_3[0x2];
6548         u8         src_addr_index[0x8];
6549         u8         flow_label[0x14];
6550
6551         u8         rgid_rip[16][0x8];
6552 };
6553
6554 struct mlx5_ifc_pages_req_event_bits {
6555         u8         reserved_0[0x10];
6556         u8         function_id[0x10];
6557
6558         u8         num_pages[0x20];
6559
6560         u8         reserved_1[0xa0];
6561 };
6562
6563 struct mlx5_ifc_eqe_bits {
6564         u8         reserved_0[0x8];
6565         u8         event_type[0x8];
6566         u8         reserved_1[0x8];
6567         u8         event_sub_type[0x8];
6568
6569         u8         reserved_2[0xe0];
6570
6571         union mlx5_ifc_event_auto_bits event_data;
6572
6573         u8         reserved_3[0x10];
6574         u8         signature[0x8];
6575         u8         reserved_4[0x7];
6576         u8         owner[0x1];
6577 };
6578
6579 enum {
6580         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
6581 };
6582
6583 struct mlx5_ifc_cmd_queue_entry_bits {
6584         u8         type[0x8];
6585         u8         reserved_0[0x18];
6586
6587         u8         input_length[0x20];
6588
6589         u8         input_mailbox_pointer_63_32[0x20];
6590
6591         u8         input_mailbox_pointer_31_9[0x17];
6592         u8         reserved_1[0x9];
6593
6594         u8         command_input_inline_data[16][0x8];
6595
6596         u8         command_output_inline_data[16][0x8];
6597
6598         u8         output_mailbox_pointer_63_32[0x20];
6599
6600         u8         output_mailbox_pointer_31_9[0x17];
6601         u8         reserved_2[0x9];
6602
6603         u8         output_length[0x20];
6604
6605         u8         token[0x8];
6606         u8         signature[0x8];
6607         u8         reserved_3[0x8];
6608         u8         status[0x7];
6609         u8         ownership[0x1];
6610 };
6611
6612 struct mlx5_ifc_cmd_out_bits {
6613         u8         status[0x8];
6614         u8         reserved_0[0x18];
6615
6616         u8         syndrome[0x20];
6617
6618         u8         command_output[0x20];
6619 };
6620
6621 struct mlx5_ifc_cmd_in_bits {
6622         u8         opcode[0x10];
6623         u8         reserved_0[0x10];
6624
6625         u8         reserved_1[0x10];
6626         u8         op_mod[0x10];
6627
6628         u8         command[0][0x20];
6629 };
6630
6631 struct mlx5_ifc_cmd_if_box_bits {
6632         u8         mailbox_data[512][0x8];
6633
6634         u8         reserved_0[0x180];
6635
6636         u8         next_pointer_63_32[0x20];
6637
6638         u8         next_pointer_31_10[0x16];
6639         u8         reserved_1[0xa];
6640
6641         u8         block_number[0x20];
6642
6643         u8         reserved_2[0x8];
6644         u8         token[0x8];
6645         u8         ctrl_signature[0x8];
6646         u8         signature[0x8];
6647 };
6648
6649 struct mlx5_ifc_mtt_bits {
6650         u8         ptag_63_32[0x20];
6651
6652         u8         ptag_31_8[0x18];
6653         u8         reserved_0[0x6];
6654         u8         wr_en[0x1];
6655         u8         rd_en[0x1];
6656 };
6657
6658 enum {
6659         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
6660         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
6661         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
6662 };
6663
6664 enum {
6665         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
6666         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
6667         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
6668 };
6669
6670 enum {
6671         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
6672         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
6673         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
6674         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
6675         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
6676         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
6677         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
6678         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
6679         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
6680         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
6681         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
6682 };
6683
6684 struct mlx5_ifc_initial_seg_bits {
6685         u8         fw_rev_minor[0x10];
6686         u8         fw_rev_major[0x10];
6687
6688         u8         cmd_interface_rev[0x10];
6689         u8         fw_rev_subminor[0x10];
6690
6691         u8         reserved_0[0x40];
6692
6693         u8         cmdq_phy_addr_63_32[0x20];
6694
6695         u8         cmdq_phy_addr_31_12[0x14];
6696         u8         reserved_1[0x2];
6697         u8         nic_interface[0x2];
6698         u8         log_cmdq_size[0x4];
6699         u8         log_cmdq_stride[0x4];
6700
6701         u8         command_doorbell_vector[0x20];
6702
6703         u8         reserved_2[0xf00];
6704
6705         u8         initializing[0x1];
6706         u8         reserved_3[0x4];
6707         u8         nic_interface_supported[0x3];
6708         u8         reserved_4[0x18];
6709
6710         struct mlx5_ifc_health_buffer_bits health_buffer;
6711
6712         u8         no_dram_nic_offset[0x20];
6713
6714         u8         reserved_5[0x6e40];
6715
6716         u8         reserved_6[0x1f];
6717         u8         clear_int[0x1];
6718
6719         u8         health_syndrome[0x8];
6720         u8         health_counter[0x18];
6721
6722         u8         reserved_7[0x17fc0];
6723 };
6724
6725 union mlx5_ifc_ports_control_registers_document_bits {
6726         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6727         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6728         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6729         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6730         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6731         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6732         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6733         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6734         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6735         struct mlx5_ifc_pamp_reg_bits pamp_reg;
6736         struct mlx5_ifc_paos_reg_bits paos_reg;
6737         struct mlx5_ifc_pcap_reg_bits pcap_reg;
6738         struct mlx5_ifc_peir_reg_bits peir_reg;
6739         struct mlx5_ifc_pelc_reg_bits pelc_reg;
6740         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6741         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6742         struct mlx5_ifc_pifr_reg_bits pifr_reg;
6743         struct mlx5_ifc_pipg_reg_bits pipg_reg;
6744         struct mlx5_ifc_plbf_reg_bits plbf_reg;
6745         struct mlx5_ifc_plib_reg_bits plib_reg;
6746         struct mlx5_ifc_plpc_reg_bits plpc_reg;
6747         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6748         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6749         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6750         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6751         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6752         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6753         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6754         struct mlx5_ifc_ppad_reg_bits ppad_reg;
6755         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6756         struct mlx5_ifc_pplm_reg_bits pplm_reg;
6757         struct mlx5_ifc_pplr_reg_bits pplr_reg;
6758         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6759         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6760         struct mlx5_ifc_pspa_reg_bits pspa_reg;
6761         struct mlx5_ifc_ptas_reg_bits ptas_reg;
6762         struct mlx5_ifc_ptys_reg_bits ptys_reg;
6763         struct mlx5_ifc_pude_reg_bits pude_reg;
6764         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6765         struct mlx5_ifc_slrg_reg_bits slrg_reg;
6766         struct mlx5_ifc_sltp_reg_bits sltp_reg;
6767         u8         reserved_0[0x60e0];
6768 };
6769
6770 union mlx5_ifc_debug_enhancements_document_bits {
6771         struct mlx5_ifc_health_buffer_bits health_buffer;
6772         u8         reserved_0[0x200];
6773 };
6774
6775 union mlx5_ifc_uplink_pci_interface_document_bits {
6776         struct mlx5_ifc_initial_seg_bits initial_seg;
6777         u8         reserved_0[0x20060];
6778 };
6779
6780 #endif /* MLX5_IFC_H */