2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
126 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
127 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
128 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
129 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
130 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
131 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
132 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
133 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
134 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
135 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
136 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
137 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
138 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
139 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
140 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
141 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
142 MLX5_CMD_OP_ALLOC_PD = 0x800,
143 MLX5_CMD_OP_DEALLOC_PD = 0x801,
144 MLX5_CMD_OP_ALLOC_UAR = 0x802,
145 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
146 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
147 MLX5_CMD_OP_ACCESS_REG = 0x805,
148 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
149 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
150 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
151 MLX5_CMD_OP_MAD_IFC = 0x50d,
152 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
153 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
154 MLX5_CMD_OP_NOP = 0x80d,
155 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
156 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
157 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
158 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
159 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
160 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
161 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
162 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
163 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
164 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
165 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
166 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
167 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
168 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
169 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
170 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
171 MLX5_CMD_OP_CREATE_TIR = 0x900,
172 MLX5_CMD_OP_MODIFY_TIR = 0x901,
173 MLX5_CMD_OP_DESTROY_TIR = 0x902,
174 MLX5_CMD_OP_QUERY_TIR = 0x903,
175 MLX5_CMD_OP_CREATE_SQ = 0x904,
176 MLX5_CMD_OP_MODIFY_SQ = 0x905,
177 MLX5_CMD_OP_DESTROY_SQ = 0x906,
178 MLX5_CMD_OP_QUERY_SQ = 0x907,
179 MLX5_CMD_OP_CREATE_RQ = 0x908,
180 MLX5_CMD_OP_MODIFY_RQ = 0x909,
181 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
182 MLX5_CMD_OP_QUERY_RQ = 0x90b,
183 MLX5_CMD_OP_CREATE_RMP = 0x90c,
184 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
185 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
186 MLX5_CMD_OP_QUERY_RMP = 0x90f,
187 MLX5_CMD_OP_CREATE_TIS = 0x912,
188 MLX5_CMD_OP_MODIFY_TIS = 0x913,
189 MLX5_CMD_OP_DESTROY_TIS = 0x914,
190 MLX5_CMD_OP_QUERY_TIS = 0x915,
191 MLX5_CMD_OP_CREATE_RQT = 0x916,
192 MLX5_CMD_OP_MODIFY_RQT = 0x917,
193 MLX5_CMD_OP_DESTROY_RQT = 0x918,
194 MLX5_CMD_OP_QUERY_RQT = 0x919,
195 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
196 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
197 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
198 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
199 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
200 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
201 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
202 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
203 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
204 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
205 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c
208 struct mlx5_ifc_flow_table_fields_supported_bits {
211 u8 outer_ether_type[0x1];
212 u8 reserved_at_3[0x1];
213 u8 outer_first_prio[0x1];
214 u8 outer_first_cfi[0x1];
215 u8 outer_first_vid[0x1];
216 u8 reserved_at_7[0x1];
217 u8 outer_second_prio[0x1];
218 u8 outer_second_cfi[0x1];
219 u8 outer_second_vid[0x1];
220 u8 reserved_at_b[0x1];
224 u8 outer_ip_protocol[0x1];
225 u8 outer_ip_ecn[0x1];
226 u8 outer_ip_dscp[0x1];
227 u8 outer_udp_sport[0x1];
228 u8 outer_udp_dport[0x1];
229 u8 outer_tcp_sport[0x1];
230 u8 outer_tcp_dport[0x1];
231 u8 outer_tcp_flags[0x1];
232 u8 outer_gre_protocol[0x1];
233 u8 outer_gre_key[0x1];
234 u8 outer_vxlan_vni[0x1];
235 u8 reserved_at_1a[0x5];
236 u8 source_eswitch_port[0x1];
240 u8 inner_ether_type[0x1];
241 u8 reserved_at_23[0x1];
242 u8 inner_first_prio[0x1];
243 u8 inner_first_cfi[0x1];
244 u8 inner_first_vid[0x1];
245 u8 reserved_at_27[0x1];
246 u8 inner_second_prio[0x1];
247 u8 inner_second_cfi[0x1];
248 u8 inner_second_vid[0x1];
249 u8 reserved_at_2b[0x1];
253 u8 inner_ip_protocol[0x1];
254 u8 inner_ip_ecn[0x1];
255 u8 inner_ip_dscp[0x1];
256 u8 inner_udp_sport[0x1];
257 u8 inner_udp_dport[0x1];
258 u8 inner_tcp_sport[0x1];
259 u8 inner_tcp_dport[0x1];
260 u8 inner_tcp_flags[0x1];
261 u8 reserved_at_37[0x9];
263 u8 reserved_at_40[0x40];
266 struct mlx5_ifc_flow_table_prop_layout_bits {
268 u8 reserved_at_1[0x2];
269 u8 flow_modify_en[0x1];
271 u8 identified_miss_table_mode[0x1];
272 u8 flow_table_modify[0x1];
273 u8 reserved_at_7[0x19];
275 u8 reserved_at_20[0x2];
276 u8 log_max_ft_size[0x6];
277 u8 reserved_at_28[0x10];
278 u8 max_ft_level[0x8];
280 u8 reserved_at_40[0x20];
282 u8 reserved_at_60[0x18];
283 u8 log_max_ft_num[0x8];
285 u8 reserved_at_80[0x18];
286 u8 log_max_destination[0x8];
288 u8 reserved_at_a0[0x18];
289 u8 log_max_flow[0x8];
291 u8 reserved_at_c0[0x40];
293 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
295 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
298 struct mlx5_ifc_odp_per_transport_service_cap_bits {
303 u8 reserved_at_4[0x1];
305 u8 reserved_at_6[0x1a];
308 struct mlx5_ifc_ipv4_layout_bits {
309 u8 reserved_at_0[0x60];
314 struct mlx5_ifc_ipv6_layout_bits {
318 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
319 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
320 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
321 u8 reserved_at_0[0x80];
324 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
341 u8 reserved_at_91[0x1];
343 u8 reserved_at_93[0x4];
349 u8 reserved_at_c0[0x20];
354 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
356 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
359 struct mlx5_ifc_fte_match_set_misc_bits {
360 u8 reserved_at_0[0x20];
362 u8 reserved_at_20[0x10];
363 u8 source_port[0x10];
365 u8 outer_second_prio[0x3];
366 u8 outer_second_cfi[0x1];
367 u8 outer_second_vid[0xc];
368 u8 inner_second_prio[0x3];
369 u8 inner_second_cfi[0x1];
370 u8 inner_second_vid[0xc];
372 u8 outer_second_vlan_tag[0x1];
373 u8 inner_second_vlan_tag[0x1];
374 u8 reserved_at_62[0xe];
375 u8 gre_protocol[0x10];
381 u8 reserved_at_b8[0x8];
383 u8 reserved_at_c0[0x20];
385 u8 reserved_at_e0[0xc];
386 u8 outer_ipv6_flow_label[0x14];
388 u8 reserved_at_100[0xc];
389 u8 inner_ipv6_flow_label[0x14];
391 u8 reserved_at_120[0xe0];
394 struct mlx5_ifc_cmd_pas_bits {
398 u8 reserved_at_34[0xc];
401 struct mlx5_ifc_uint64_bits {
408 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
409 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
410 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
411 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
412 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
413 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
414 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
415 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
416 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
417 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
420 struct mlx5_ifc_ads_bits {
423 u8 reserved_at_2[0xe];
426 u8 reserved_at_20[0x8];
432 u8 reserved_at_45[0x3];
433 u8 src_addr_index[0x8];
434 u8 reserved_at_50[0x4];
438 u8 reserved_at_60[0x4];
442 u8 rgid_rip[16][0x8];
444 u8 reserved_at_100[0x4];
447 u8 reserved_at_106[0x1];
462 struct mlx5_ifc_flow_table_nic_cap_bits {
463 u8 nic_rx_multi_path_tirs[0x1];
464 u8 reserved_at_1[0x1ff];
466 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
468 u8 reserved_at_400[0x200];
470 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
472 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
474 u8 reserved_at_a00[0x200];
476 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
478 u8 reserved_at_e00[0x7200];
481 struct mlx5_ifc_flow_table_eswitch_cap_bits {
482 u8 reserved_at_0[0x200];
484 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
486 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
488 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
490 u8 reserved_at_800[0x7800];
493 struct mlx5_ifc_e_switch_cap_bits {
494 u8 vport_svlan_strip[0x1];
495 u8 vport_cvlan_strip[0x1];
496 u8 vport_svlan_insert[0x1];
497 u8 vport_cvlan_insert_if_not_exist[0x1];
498 u8 vport_cvlan_insert_overwrite[0x1];
499 u8 reserved_at_5[0x1b];
501 u8 reserved_at_20[0x7e0];
504 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
508 u8 lro_psh_flag[0x1];
509 u8 lro_time_stamp[0x1];
510 u8 reserved_at_5[0x3];
511 u8 self_lb_en_modifiable[0x1];
512 u8 reserved_at_9[0x2];
514 u8 reserved_at_10[0x4];
515 u8 rss_ind_tbl_cap[0x4];
516 u8 reserved_at_18[0x3];
517 u8 tunnel_lso_const_out_ip_id[0x1];
518 u8 reserved_at_1c[0x2];
519 u8 tunnel_statless_gre[0x1];
520 u8 tunnel_stateless_vxlan[0x1];
522 u8 reserved_at_20[0x20];
524 u8 reserved_at_40[0x10];
525 u8 lro_min_mss_size[0x10];
527 u8 reserved_at_60[0x120];
529 u8 lro_timer_supported_periods[4][0x20];
531 u8 reserved_at_200[0x600];
534 struct mlx5_ifc_roce_cap_bits {
536 u8 reserved_at_1[0x1f];
538 u8 reserved_at_20[0x60];
540 u8 reserved_at_80[0xc];
542 u8 reserved_at_90[0x8];
543 u8 roce_version[0x8];
545 u8 reserved_at_a0[0x10];
546 u8 r_roce_dest_udp_port[0x10];
548 u8 r_roce_max_src_udp_port[0x10];
549 u8 r_roce_min_src_udp_port[0x10];
551 u8 reserved_at_e0[0x10];
552 u8 roce_address_table_size[0x10];
554 u8 reserved_at_100[0x700];
558 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
559 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
560 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
561 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
562 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
563 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
564 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
565 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
566 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
570 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
571 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
572 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
573 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
574 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
575 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
576 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
577 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
578 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
581 struct mlx5_ifc_atomic_caps_bits {
582 u8 reserved_at_0[0x40];
584 u8 atomic_req_8B_endianess_mode[0x2];
585 u8 reserved_at_42[0x4];
586 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
588 u8 reserved_at_47[0x19];
590 u8 reserved_at_60[0x20];
592 u8 reserved_at_80[0x10];
593 u8 atomic_operations[0x10];
595 u8 reserved_at_a0[0x10];
596 u8 atomic_size_qp[0x10];
598 u8 reserved_at_c0[0x10];
599 u8 atomic_size_dc[0x10];
601 u8 reserved_at_e0[0x720];
604 struct mlx5_ifc_odp_cap_bits {
605 u8 reserved_at_0[0x40];
608 u8 reserved_at_41[0x1f];
610 u8 reserved_at_60[0x20];
612 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
614 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
616 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
618 u8 reserved_at_e0[0x720];
622 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
623 MLX5_WQ_TYPE_CYCLIC = 0x1,
624 MLX5_WQ_TYPE_STRQ = 0x2,
628 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
629 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
633 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
634 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
635 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
636 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
637 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
641 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
642 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
643 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
644 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
645 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
646 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
650 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
651 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
655 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
656 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
657 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
661 MLX5_CAP_PORT_TYPE_IB = 0x0,
662 MLX5_CAP_PORT_TYPE_ETH = 0x1,
665 struct mlx5_ifc_cmd_hca_cap_bits {
666 u8 reserved_at_0[0x80];
668 u8 log_max_srq_sz[0x8];
669 u8 log_max_qp_sz[0x8];
670 u8 reserved_at_90[0xb];
673 u8 reserved_at_a0[0xb];
675 u8 reserved_at_b0[0x10];
677 u8 reserved_at_c0[0x8];
678 u8 log_max_cq_sz[0x8];
679 u8 reserved_at_d0[0xb];
682 u8 log_max_eq_sz[0x8];
683 u8 reserved_at_e8[0x2];
684 u8 log_max_mkey[0x6];
685 u8 reserved_at_f0[0xc];
688 u8 max_indirection[0x8];
689 u8 reserved_at_108[0x1];
690 u8 log_max_mrw_sz[0x7];
691 u8 reserved_at_110[0x2];
692 u8 log_max_bsf_list_size[0x6];
693 u8 reserved_at_118[0x2];
694 u8 log_max_klm_list_size[0x6];
696 u8 reserved_at_120[0xa];
697 u8 log_max_ra_req_dc[0x6];
698 u8 reserved_at_130[0xa];
699 u8 log_max_ra_res_dc[0x6];
701 u8 reserved_at_140[0xa];
702 u8 log_max_ra_req_qp[0x6];
703 u8 reserved_at_150[0xa];
704 u8 log_max_ra_res_qp[0x6];
707 u8 cc_query_allowed[0x1];
708 u8 cc_modify_allowed[0x1];
709 u8 reserved_at_163[0xd];
710 u8 gid_table_size[0x10];
712 u8 out_of_seq_cnt[0x1];
713 u8 vport_counters[0x1];
714 u8 reserved_at_182[0x4];
716 u8 pkey_table_size[0x10];
718 u8 vport_group_manager[0x1];
719 u8 vhca_group_manager[0x1];
722 u8 reserved_at_1a4[0x1];
724 u8 nic_flow_table[0x1];
725 u8 eswitch_flow_table[0x1];
727 u8 reserved_at_1a8[0x2];
728 u8 local_ca_ack_delay[0x5];
729 u8 reserved_at_1af[0x6];
733 u8 reserved_at_1bf[0x3];
735 u8 reserved_at_1c7[0x4];
737 u8 reserved_at_1cf[0x6];
740 u8 reserved_at_1d7[0x1];
749 u8 stat_rate_support[0x10];
750 u8 reserved_at_1ef[0xc];
753 u8 compact_address_vector[0x1];
754 u8 reserved_at_200[0x3];
755 u8 ipoib_basic_offloads[0x1];
756 u8 reserved_at_204[0xa];
757 u8 drain_sigerr[0x1];
758 u8 cmdif_checksum[0x2];
760 u8 reserved_at_212[0x1];
761 u8 wq_signature[0x1];
762 u8 sctr_data_cqe[0x1];
763 u8 reserved_at_215[0x1];
768 u8 reserved_at_21a[0x1];
769 u8 eth_net_offloads[0x1];
772 u8 reserved_at_21e[0x1];
776 u8 cq_moderation[0x1];
777 u8 reserved_at_222[0x3];
781 u8 reserved_at_228[0x1];
782 u8 scqe_break_moderation[0x1];
783 u8 reserved_at_22a[0x1];
785 u8 reserved_at_22c[0x1];
787 u8 reserved_at_22e[0x2];
789 u8 reserved_at_231[0x4];
792 u8 set_deth_sqpn[0x1];
793 u8 reserved_at_239[0x3];
799 u8 reserved_at_23f[0xa];
801 u8 reserved_at_24f[0x8];
805 u8 reserved_at_260[0x1];
806 u8 pad_tx_eth_packet[0x1];
807 u8 reserved_at_262[0x8];
808 u8 log_bf_reg_size[0x5];
809 u8 reserved_at_26f[0x10];
811 u8 reserved_at_27f[0x10];
812 u8 max_wqe_sz_sq[0x10];
814 u8 reserved_at_29f[0x10];
815 u8 max_wqe_sz_rq[0x10];
817 u8 reserved_at_2bf[0x10];
818 u8 max_wqe_sz_sq_dc[0x10];
820 u8 reserved_at_2df[0x7];
823 u8 reserved_at_2ff[0x18];
826 u8 reserved_at_31f[0x3];
827 u8 log_max_transport_domain[0x5];
828 u8 reserved_at_327[0x3];
830 u8 reserved_at_32f[0xb];
831 u8 log_max_xrcd[0x5];
833 u8 reserved_at_33f[0x20];
835 u8 reserved_at_35f[0x3];
837 u8 reserved_at_367[0x3];
839 u8 reserved_at_36f[0x3];
841 u8 reserved_at_377[0x3];
844 u8 basic_cyclic_rcv_wqe[0x1];
845 u8 reserved_at_380[0x2];
847 u8 reserved_at_387[0x3];
849 u8 reserved_at_38f[0x3];
850 u8 log_max_rqt_size[0x5];
851 u8 reserved_at_397[0x3];
852 u8 log_max_tis_per_sq[0x5];
854 u8 reserved_at_39f[0x3];
855 u8 log_max_stride_sz_rq[0x5];
856 u8 reserved_at_3a7[0x3];
857 u8 log_min_stride_sz_rq[0x5];
858 u8 reserved_at_3af[0x3];
859 u8 log_max_stride_sz_sq[0x5];
860 u8 reserved_at_3b7[0x3];
861 u8 log_min_stride_sz_sq[0x5];
863 u8 reserved_at_3bf[0x1b];
864 u8 log_max_wq_sz[0x5];
866 u8 nic_vport_change_event[0x1];
867 u8 reserved_at_3e0[0xa];
868 u8 log_max_vlan_list[0x5];
869 u8 reserved_at_3ef[0x3];
870 u8 log_max_current_mc_list[0x5];
871 u8 reserved_at_3f7[0x3];
872 u8 log_max_current_uc_list[0x5];
874 u8 reserved_at_3ff[0x80];
876 u8 reserved_at_47f[0x3];
877 u8 log_max_l2_table[0x5];
878 u8 reserved_at_487[0x8];
879 u8 log_uar_page_sz[0x10];
881 u8 reserved_at_49f[0x20];
882 u8 device_frequency_mhz[0x20];
883 u8 device_frequency_khz[0x20];
884 u8 reserved_at_4ff[0x5f];
887 u8 cqe_zip_timeout[0x10];
888 u8 cqe_zip_max_num[0x10];
890 u8 reserved_at_57f[0x220];
893 enum mlx5_flow_destination_type {
894 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
895 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
896 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
899 struct mlx5_ifc_dest_format_struct_bits {
900 u8 destination_type[0x8];
901 u8 destination_id[0x18];
903 u8 reserved_at_20[0x20];
906 struct mlx5_ifc_fte_match_param_bits {
907 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
909 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
911 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
913 u8 reserved_at_600[0xa00];
917 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
918 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
919 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
920 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
921 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
924 struct mlx5_ifc_rx_hash_field_select_bits {
925 u8 l3_prot_type[0x1];
926 u8 l4_prot_type[0x1];
927 u8 selected_fields[0x1e];
931 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
932 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
936 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
937 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
940 struct mlx5_ifc_wq_bits {
942 u8 wq_signature[0x1];
943 u8 end_padding_mode[0x2];
945 u8 reserved_at_8[0x18];
947 u8 hds_skip_first_sge[0x1];
948 u8 log2_hds_buf_size[0x3];
949 u8 reserved_at_24[0x7];
953 u8 reserved_at_40[0x8];
956 u8 reserved_at_60[0x8];
965 u8 reserved_at_100[0xc];
966 u8 log_wq_stride[0x4];
967 u8 reserved_at_110[0x3];
968 u8 log_wq_pg_sz[0x5];
969 u8 reserved_at_118[0x3];
972 u8 reserved_at_120[0x4e0];
974 struct mlx5_ifc_cmd_pas_bits pas[0];
977 struct mlx5_ifc_rq_num_bits {
978 u8 reserved_at_0[0x8];
982 struct mlx5_ifc_mac_address_layout_bits {
983 u8 reserved_at_0[0x10];
984 u8 mac_addr_47_32[0x10];
986 u8 mac_addr_31_0[0x20];
989 struct mlx5_ifc_vlan_layout_bits {
990 u8 reserved_at_0[0x14];
993 u8 reserved_at_20[0x20];
996 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
997 u8 reserved_at_0[0xa0];
999 u8 min_time_between_cnps[0x20];
1001 u8 reserved_at_c0[0x12];
1003 u8 reserved_at_d8[0x5];
1004 u8 cnp_802p_prio[0x3];
1006 u8 reserved_at_e0[0x720];
1009 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1010 u8 reserved_at_0[0x60];
1012 u8 reserved_at_60[0x4];
1013 u8 clamp_tgt_rate[0x1];
1014 u8 reserved_at_65[0x3];
1015 u8 clamp_tgt_rate_after_time_inc[0x1];
1016 u8 reserved_at_69[0x17];
1018 u8 reserved_at_80[0x20];
1020 u8 rpg_time_reset[0x20];
1022 u8 rpg_byte_reset[0x20];
1024 u8 rpg_threshold[0x20];
1026 u8 rpg_max_rate[0x20];
1028 u8 rpg_ai_rate[0x20];
1030 u8 rpg_hai_rate[0x20];
1034 u8 rpg_min_dec_fac[0x20];
1036 u8 rpg_min_rate[0x20];
1038 u8 reserved_at_1c0[0xe0];
1040 u8 rate_to_set_on_first_cnp[0x20];
1044 u8 dce_tcp_rtt[0x20];
1046 u8 rate_reduce_monitor_period[0x20];
1048 u8 reserved_at_320[0x20];
1050 u8 initial_alpha_value[0x20];
1052 u8 reserved_at_360[0x4a0];
1055 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1056 u8 reserved_at_0[0x80];
1058 u8 rppp_max_rps[0x20];
1060 u8 rpg_time_reset[0x20];
1062 u8 rpg_byte_reset[0x20];
1064 u8 rpg_threshold[0x20];
1066 u8 rpg_max_rate[0x20];
1068 u8 rpg_ai_rate[0x20];
1070 u8 rpg_hai_rate[0x20];
1074 u8 rpg_min_dec_fac[0x20];
1076 u8 rpg_min_rate[0x20];
1078 u8 reserved_at_1c0[0x640];
1082 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1083 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1084 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1087 struct mlx5_ifc_resize_field_select_bits {
1088 u8 resize_field_select[0x20];
1092 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1093 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1094 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1095 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1098 struct mlx5_ifc_modify_field_select_bits {
1099 u8 modify_field_select[0x20];
1102 struct mlx5_ifc_field_select_r_roce_np_bits {
1103 u8 field_select_r_roce_np[0x20];
1106 struct mlx5_ifc_field_select_r_roce_rp_bits {
1107 u8 field_select_r_roce_rp[0x20];
1111 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1112 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1113 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1114 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1115 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1116 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1117 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1118 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1119 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1120 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1123 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1124 u8 field_select_8021qaurp[0x20];
1127 struct mlx5_ifc_phys_layer_cntrs_bits {
1128 u8 time_since_last_clear_high[0x20];
1130 u8 time_since_last_clear_low[0x20];
1132 u8 symbol_errors_high[0x20];
1134 u8 symbol_errors_low[0x20];
1136 u8 sync_headers_errors_high[0x20];
1138 u8 sync_headers_errors_low[0x20];
1140 u8 edpl_bip_errors_lane0_high[0x20];
1142 u8 edpl_bip_errors_lane0_low[0x20];
1144 u8 edpl_bip_errors_lane1_high[0x20];
1146 u8 edpl_bip_errors_lane1_low[0x20];
1148 u8 edpl_bip_errors_lane2_high[0x20];
1150 u8 edpl_bip_errors_lane2_low[0x20];
1152 u8 edpl_bip_errors_lane3_high[0x20];
1154 u8 edpl_bip_errors_lane3_low[0x20];
1156 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1158 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1160 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1162 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1164 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1166 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1168 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1170 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1172 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1174 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1176 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1178 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1180 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1182 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1184 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1186 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1188 u8 rs_fec_corrected_blocks_high[0x20];
1190 u8 rs_fec_corrected_blocks_low[0x20];
1192 u8 rs_fec_uncorrectable_blocks_high[0x20];
1194 u8 rs_fec_uncorrectable_blocks_low[0x20];
1196 u8 rs_fec_no_errors_blocks_high[0x20];
1198 u8 rs_fec_no_errors_blocks_low[0x20];
1200 u8 rs_fec_single_error_blocks_high[0x20];
1202 u8 rs_fec_single_error_blocks_low[0x20];
1204 u8 rs_fec_corrected_symbols_total_high[0x20];
1206 u8 rs_fec_corrected_symbols_total_low[0x20];
1208 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1210 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1212 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1214 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1216 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1218 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1220 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1222 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1224 u8 link_down_events[0x20];
1226 u8 successful_recovery_events[0x20];
1228 u8 reserved_at_640[0x180];
1231 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1232 u8 symbol_error_counter[0x10];
1234 u8 link_error_recovery_counter[0x8];
1236 u8 link_downed_counter[0x8];
1238 u8 port_rcv_errors[0x10];
1240 u8 port_rcv_remote_physical_errors[0x10];
1242 u8 port_rcv_switch_relay_errors[0x10];
1244 u8 port_xmit_discards[0x10];
1246 u8 port_xmit_constraint_errors[0x8];
1248 u8 port_rcv_constraint_errors[0x8];
1250 u8 reserved_at_70[0x8];
1252 u8 link_overrun_errors[0x8];
1254 u8 reserved_at_80[0x10];
1256 u8 vl_15_dropped[0x10];
1258 u8 reserved_at_a0[0xa0];
1261 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1262 u8 transmit_queue_high[0x20];
1264 u8 transmit_queue_low[0x20];
1266 u8 reserved_at_40[0x780];
1269 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1270 u8 rx_octets_high[0x20];
1272 u8 rx_octets_low[0x20];
1274 u8 reserved_at_40[0xc0];
1276 u8 rx_frames_high[0x20];
1278 u8 rx_frames_low[0x20];
1280 u8 tx_octets_high[0x20];
1282 u8 tx_octets_low[0x20];
1284 u8 reserved_at_180[0xc0];
1286 u8 tx_frames_high[0x20];
1288 u8 tx_frames_low[0x20];
1290 u8 rx_pause_high[0x20];
1292 u8 rx_pause_low[0x20];
1294 u8 rx_pause_duration_high[0x20];
1296 u8 rx_pause_duration_low[0x20];
1298 u8 tx_pause_high[0x20];
1300 u8 tx_pause_low[0x20];
1302 u8 tx_pause_duration_high[0x20];
1304 u8 tx_pause_duration_low[0x20];
1306 u8 rx_pause_transition_high[0x20];
1308 u8 rx_pause_transition_low[0x20];
1310 u8 reserved_at_3c0[0x400];
1313 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1314 u8 port_transmit_wait_high[0x20];
1316 u8 port_transmit_wait_low[0x20];
1318 u8 reserved_at_40[0x780];
1321 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1322 u8 dot3stats_alignment_errors_high[0x20];
1324 u8 dot3stats_alignment_errors_low[0x20];
1326 u8 dot3stats_fcs_errors_high[0x20];
1328 u8 dot3stats_fcs_errors_low[0x20];
1330 u8 dot3stats_single_collision_frames_high[0x20];
1332 u8 dot3stats_single_collision_frames_low[0x20];
1334 u8 dot3stats_multiple_collision_frames_high[0x20];
1336 u8 dot3stats_multiple_collision_frames_low[0x20];
1338 u8 dot3stats_sqe_test_errors_high[0x20];
1340 u8 dot3stats_sqe_test_errors_low[0x20];
1342 u8 dot3stats_deferred_transmissions_high[0x20];
1344 u8 dot3stats_deferred_transmissions_low[0x20];
1346 u8 dot3stats_late_collisions_high[0x20];
1348 u8 dot3stats_late_collisions_low[0x20];
1350 u8 dot3stats_excessive_collisions_high[0x20];
1352 u8 dot3stats_excessive_collisions_low[0x20];
1354 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1356 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1358 u8 dot3stats_carrier_sense_errors_high[0x20];
1360 u8 dot3stats_carrier_sense_errors_low[0x20];
1362 u8 dot3stats_frame_too_longs_high[0x20];
1364 u8 dot3stats_frame_too_longs_low[0x20];
1366 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1368 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1370 u8 dot3stats_symbol_errors_high[0x20];
1372 u8 dot3stats_symbol_errors_low[0x20];
1374 u8 dot3control_in_unknown_opcodes_high[0x20];
1376 u8 dot3control_in_unknown_opcodes_low[0x20];
1378 u8 dot3in_pause_frames_high[0x20];
1380 u8 dot3in_pause_frames_low[0x20];
1382 u8 dot3out_pause_frames_high[0x20];
1384 u8 dot3out_pause_frames_low[0x20];
1386 u8 reserved_at_400[0x3c0];
1389 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1390 u8 ether_stats_drop_events_high[0x20];
1392 u8 ether_stats_drop_events_low[0x20];
1394 u8 ether_stats_octets_high[0x20];
1396 u8 ether_stats_octets_low[0x20];
1398 u8 ether_stats_pkts_high[0x20];
1400 u8 ether_stats_pkts_low[0x20];
1402 u8 ether_stats_broadcast_pkts_high[0x20];
1404 u8 ether_stats_broadcast_pkts_low[0x20];
1406 u8 ether_stats_multicast_pkts_high[0x20];
1408 u8 ether_stats_multicast_pkts_low[0x20];
1410 u8 ether_stats_crc_align_errors_high[0x20];
1412 u8 ether_stats_crc_align_errors_low[0x20];
1414 u8 ether_stats_undersize_pkts_high[0x20];
1416 u8 ether_stats_undersize_pkts_low[0x20];
1418 u8 ether_stats_oversize_pkts_high[0x20];
1420 u8 ether_stats_oversize_pkts_low[0x20];
1422 u8 ether_stats_fragments_high[0x20];
1424 u8 ether_stats_fragments_low[0x20];
1426 u8 ether_stats_jabbers_high[0x20];
1428 u8 ether_stats_jabbers_low[0x20];
1430 u8 ether_stats_collisions_high[0x20];
1432 u8 ether_stats_collisions_low[0x20];
1434 u8 ether_stats_pkts64octets_high[0x20];
1436 u8 ether_stats_pkts64octets_low[0x20];
1438 u8 ether_stats_pkts65to127octets_high[0x20];
1440 u8 ether_stats_pkts65to127octets_low[0x20];
1442 u8 ether_stats_pkts128to255octets_high[0x20];
1444 u8 ether_stats_pkts128to255octets_low[0x20];
1446 u8 ether_stats_pkts256to511octets_high[0x20];
1448 u8 ether_stats_pkts256to511octets_low[0x20];
1450 u8 ether_stats_pkts512to1023octets_high[0x20];
1452 u8 ether_stats_pkts512to1023octets_low[0x20];
1454 u8 ether_stats_pkts1024to1518octets_high[0x20];
1456 u8 ether_stats_pkts1024to1518octets_low[0x20];
1458 u8 ether_stats_pkts1519to2047octets_high[0x20];
1460 u8 ether_stats_pkts1519to2047octets_low[0x20];
1462 u8 ether_stats_pkts2048to4095octets_high[0x20];
1464 u8 ether_stats_pkts2048to4095octets_low[0x20];
1466 u8 ether_stats_pkts4096to8191octets_high[0x20];
1468 u8 ether_stats_pkts4096to8191octets_low[0x20];
1470 u8 ether_stats_pkts8192to10239octets_high[0x20];
1472 u8 ether_stats_pkts8192to10239octets_low[0x20];
1474 u8 reserved_at_540[0x280];
1477 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1478 u8 if_in_octets_high[0x20];
1480 u8 if_in_octets_low[0x20];
1482 u8 if_in_ucast_pkts_high[0x20];
1484 u8 if_in_ucast_pkts_low[0x20];
1486 u8 if_in_discards_high[0x20];
1488 u8 if_in_discards_low[0x20];
1490 u8 if_in_errors_high[0x20];
1492 u8 if_in_errors_low[0x20];
1494 u8 if_in_unknown_protos_high[0x20];
1496 u8 if_in_unknown_protos_low[0x20];
1498 u8 if_out_octets_high[0x20];
1500 u8 if_out_octets_low[0x20];
1502 u8 if_out_ucast_pkts_high[0x20];
1504 u8 if_out_ucast_pkts_low[0x20];
1506 u8 if_out_discards_high[0x20];
1508 u8 if_out_discards_low[0x20];
1510 u8 if_out_errors_high[0x20];
1512 u8 if_out_errors_low[0x20];
1514 u8 if_in_multicast_pkts_high[0x20];
1516 u8 if_in_multicast_pkts_low[0x20];
1518 u8 if_in_broadcast_pkts_high[0x20];
1520 u8 if_in_broadcast_pkts_low[0x20];
1522 u8 if_out_multicast_pkts_high[0x20];
1524 u8 if_out_multicast_pkts_low[0x20];
1526 u8 if_out_broadcast_pkts_high[0x20];
1528 u8 if_out_broadcast_pkts_low[0x20];
1530 u8 reserved_at_340[0x480];
1533 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1534 u8 a_frames_transmitted_ok_high[0x20];
1536 u8 a_frames_transmitted_ok_low[0x20];
1538 u8 a_frames_received_ok_high[0x20];
1540 u8 a_frames_received_ok_low[0x20];
1542 u8 a_frame_check_sequence_errors_high[0x20];
1544 u8 a_frame_check_sequence_errors_low[0x20];
1546 u8 a_alignment_errors_high[0x20];
1548 u8 a_alignment_errors_low[0x20];
1550 u8 a_octets_transmitted_ok_high[0x20];
1552 u8 a_octets_transmitted_ok_low[0x20];
1554 u8 a_octets_received_ok_high[0x20];
1556 u8 a_octets_received_ok_low[0x20];
1558 u8 a_multicast_frames_xmitted_ok_high[0x20];
1560 u8 a_multicast_frames_xmitted_ok_low[0x20];
1562 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1564 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1566 u8 a_multicast_frames_received_ok_high[0x20];
1568 u8 a_multicast_frames_received_ok_low[0x20];
1570 u8 a_broadcast_frames_received_ok_high[0x20];
1572 u8 a_broadcast_frames_received_ok_low[0x20];
1574 u8 a_in_range_length_errors_high[0x20];
1576 u8 a_in_range_length_errors_low[0x20];
1578 u8 a_out_of_range_length_field_high[0x20];
1580 u8 a_out_of_range_length_field_low[0x20];
1582 u8 a_frame_too_long_errors_high[0x20];
1584 u8 a_frame_too_long_errors_low[0x20];
1586 u8 a_symbol_error_during_carrier_high[0x20];
1588 u8 a_symbol_error_during_carrier_low[0x20];
1590 u8 a_mac_control_frames_transmitted_high[0x20];
1592 u8 a_mac_control_frames_transmitted_low[0x20];
1594 u8 a_mac_control_frames_received_high[0x20];
1596 u8 a_mac_control_frames_received_low[0x20];
1598 u8 a_unsupported_opcodes_received_high[0x20];
1600 u8 a_unsupported_opcodes_received_low[0x20];
1602 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1604 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1606 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1608 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1610 u8 reserved_at_4c0[0x300];
1613 struct mlx5_ifc_cmd_inter_comp_event_bits {
1614 u8 command_completion_vector[0x20];
1616 u8 reserved_at_20[0xc0];
1619 struct mlx5_ifc_stall_vl_event_bits {
1620 u8 reserved_at_0[0x18];
1622 u8 reserved_at_19[0x3];
1625 u8 reserved_at_20[0xa0];
1628 struct mlx5_ifc_db_bf_congestion_event_bits {
1629 u8 event_subtype[0x8];
1630 u8 reserved_at_8[0x8];
1631 u8 congestion_level[0x8];
1632 u8 reserved_at_18[0x8];
1634 u8 reserved_at_20[0xa0];
1637 struct mlx5_ifc_gpio_event_bits {
1638 u8 reserved_at_0[0x60];
1640 u8 gpio_event_hi[0x20];
1642 u8 gpio_event_lo[0x20];
1644 u8 reserved_at_a0[0x40];
1647 struct mlx5_ifc_port_state_change_event_bits {
1648 u8 reserved_at_0[0x40];
1651 u8 reserved_at_44[0x1c];
1653 u8 reserved_at_60[0x80];
1656 struct mlx5_ifc_dropped_packet_logged_bits {
1657 u8 reserved_at_0[0xe0];
1661 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1662 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1665 struct mlx5_ifc_cq_error_bits {
1666 u8 reserved_at_0[0x8];
1669 u8 reserved_at_20[0x20];
1671 u8 reserved_at_40[0x18];
1674 u8 reserved_at_60[0x80];
1677 struct mlx5_ifc_rdma_page_fault_event_bits {
1678 u8 bytes_committed[0x20];
1682 u8 reserved_at_40[0x10];
1683 u8 packet_len[0x10];
1685 u8 rdma_op_len[0x20];
1689 u8 reserved_at_c0[0x5];
1696 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1697 u8 bytes_committed[0x20];
1699 u8 reserved_at_20[0x10];
1702 u8 reserved_at_40[0x10];
1705 u8 reserved_at_60[0x60];
1707 u8 reserved_at_c0[0x5];
1714 struct mlx5_ifc_qp_events_bits {
1715 u8 reserved_at_0[0xa0];
1718 u8 reserved_at_a8[0x18];
1720 u8 reserved_at_c0[0x8];
1721 u8 qpn_rqn_sqn[0x18];
1724 struct mlx5_ifc_dct_events_bits {
1725 u8 reserved_at_0[0xc0];
1727 u8 reserved_at_c0[0x8];
1728 u8 dct_number[0x18];
1731 struct mlx5_ifc_comp_event_bits {
1732 u8 reserved_at_0[0xc0];
1734 u8 reserved_at_c0[0x8];
1739 MLX5_QPC_STATE_RST = 0x0,
1740 MLX5_QPC_STATE_INIT = 0x1,
1741 MLX5_QPC_STATE_RTR = 0x2,
1742 MLX5_QPC_STATE_RTS = 0x3,
1743 MLX5_QPC_STATE_SQER = 0x4,
1744 MLX5_QPC_STATE_ERR = 0x6,
1745 MLX5_QPC_STATE_SQD = 0x7,
1746 MLX5_QPC_STATE_SUSPENDED = 0x9,
1750 MLX5_QPC_ST_RC = 0x0,
1751 MLX5_QPC_ST_UC = 0x1,
1752 MLX5_QPC_ST_UD = 0x2,
1753 MLX5_QPC_ST_XRC = 0x3,
1754 MLX5_QPC_ST_DCI = 0x5,
1755 MLX5_QPC_ST_QP0 = 0x7,
1756 MLX5_QPC_ST_QP1 = 0x8,
1757 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1758 MLX5_QPC_ST_REG_UMR = 0xc,
1762 MLX5_QPC_PM_STATE_ARMED = 0x0,
1763 MLX5_QPC_PM_STATE_REARM = 0x1,
1764 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1765 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1769 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1770 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1774 MLX5_QPC_MTU_256_BYTES = 0x1,
1775 MLX5_QPC_MTU_512_BYTES = 0x2,
1776 MLX5_QPC_MTU_1K_BYTES = 0x3,
1777 MLX5_QPC_MTU_2K_BYTES = 0x4,
1778 MLX5_QPC_MTU_4K_BYTES = 0x5,
1779 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1783 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1784 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1785 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1786 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1787 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1788 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1789 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1790 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1794 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1795 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1796 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1800 MLX5_QPC_CS_RES_DISABLE = 0x0,
1801 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1802 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1805 struct mlx5_ifc_qpc_bits {
1807 u8 reserved_at_4[0x4];
1809 u8 reserved_at_10[0x3];
1811 u8 reserved_at_15[0x7];
1812 u8 end_padding_mode[0x2];
1813 u8 reserved_at_1e[0x2];
1815 u8 wq_signature[0x1];
1816 u8 block_lb_mc[0x1];
1817 u8 atomic_like_write_en[0x1];
1818 u8 latency_sensitive[0x1];
1819 u8 reserved_at_24[0x1];
1820 u8 drain_sigerr[0x1];
1821 u8 reserved_at_26[0x2];
1825 u8 log_msg_max[0x5];
1826 u8 reserved_at_48[0x1];
1827 u8 log_rq_size[0x4];
1828 u8 log_rq_stride[0x3];
1830 u8 log_sq_size[0x4];
1831 u8 reserved_at_55[0x6];
1833 u8 ulp_stateless_offload_mode[0x4];
1835 u8 counter_set_id[0x8];
1838 u8 reserved_at_80[0x8];
1839 u8 user_index[0x18];
1841 u8 reserved_at_a0[0x3];
1842 u8 log_page_size[0x5];
1843 u8 remote_qpn[0x18];
1845 struct mlx5_ifc_ads_bits primary_address_path;
1847 struct mlx5_ifc_ads_bits secondary_address_path;
1849 u8 log_ack_req_freq[0x4];
1850 u8 reserved_at_384[0x4];
1851 u8 log_sra_max[0x3];
1852 u8 reserved_at_38b[0x2];
1853 u8 retry_count[0x3];
1855 u8 reserved_at_393[0x1];
1857 u8 cur_rnr_retry[0x3];
1858 u8 cur_retry_count[0x3];
1859 u8 reserved_at_39b[0x5];
1861 u8 reserved_at_3a0[0x20];
1863 u8 reserved_at_3c0[0x8];
1864 u8 next_send_psn[0x18];
1866 u8 reserved_at_3e0[0x8];
1869 u8 reserved_at_400[0x40];
1871 u8 reserved_at_440[0x8];
1872 u8 last_acked_psn[0x18];
1874 u8 reserved_at_460[0x8];
1877 u8 reserved_at_480[0x8];
1878 u8 log_rra_max[0x3];
1879 u8 reserved_at_48b[0x1];
1880 u8 atomic_mode[0x4];
1884 u8 reserved_at_493[0x1];
1885 u8 page_offset[0x6];
1886 u8 reserved_at_49a[0x3];
1887 u8 cd_slave_receive[0x1];
1888 u8 cd_slave_send[0x1];
1891 u8 reserved_at_4a0[0x3];
1892 u8 min_rnr_nak[0x5];
1893 u8 next_rcv_psn[0x18];
1895 u8 reserved_at_4c0[0x8];
1898 u8 reserved_at_4e0[0x8];
1905 u8 reserved_at_560[0x5];
1909 u8 reserved_at_580[0x8];
1912 u8 hw_sq_wqebb_counter[0x10];
1913 u8 sw_sq_wqebb_counter[0x10];
1915 u8 hw_rq_counter[0x20];
1917 u8 sw_rq_counter[0x20];
1919 u8 reserved_at_600[0x20];
1921 u8 reserved_at_620[0xf];
1926 u8 dc_access_key[0x40];
1928 u8 reserved_at_680[0xc0];
1931 struct mlx5_ifc_roce_addr_layout_bits {
1932 u8 source_l3_address[16][0x8];
1934 u8 reserved_at_80[0x3];
1937 u8 source_mac_47_32[0x10];
1939 u8 source_mac_31_0[0x20];
1941 u8 reserved_at_c0[0x14];
1942 u8 roce_l3_type[0x4];
1943 u8 roce_version[0x8];
1945 u8 reserved_at_e0[0x20];
1948 union mlx5_ifc_hca_cap_union_bits {
1949 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1950 struct mlx5_ifc_odp_cap_bits odp_cap;
1951 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1952 struct mlx5_ifc_roce_cap_bits roce_cap;
1953 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1954 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1955 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
1956 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
1957 u8 reserved_at_0[0x8000];
1961 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1962 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1963 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1966 struct mlx5_ifc_flow_context_bits {
1967 u8 reserved_at_0[0x20];
1971 u8 reserved_at_40[0x8];
1974 u8 reserved_at_60[0x10];
1977 u8 reserved_at_80[0x8];
1978 u8 destination_list_size[0x18];
1980 u8 reserved_at_a0[0x160];
1982 struct mlx5_ifc_fte_match_param_bits match_value;
1984 u8 reserved_at_1200[0x600];
1986 struct mlx5_ifc_dest_format_struct_bits destination[0];
1990 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1991 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1994 struct mlx5_ifc_xrc_srqc_bits {
1996 u8 log_xrc_srq_size[0x4];
1997 u8 reserved_at_8[0x18];
1999 u8 wq_signature[0x1];
2001 u8 reserved_at_22[0x1];
2003 u8 basic_cyclic_rcv_wqe[0x1];
2004 u8 log_rq_stride[0x3];
2007 u8 page_offset[0x6];
2008 u8 reserved_at_46[0x2];
2011 u8 reserved_at_60[0x20];
2013 u8 user_index_equal_xrc_srqn[0x1];
2014 u8 reserved_at_81[0x1];
2015 u8 log_page_size[0x6];
2016 u8 user_index[0x18];
2018 u8 reserved_at_a0[0x20];
2020 u8 reserved_at_c0[0x8];
2026 u8 reserved_at_100[0x40];
2028 u8 db_record_addr_h[0x20];
2030 u8 db_record_addr_l[0x1e];
2031 u8 reserved_at_17e[0x2];
2033 u8 reserved_at_180[0x80];
2036 struct mlx5_ifc_traffic_counter_bits {
2042 struct mlx5_ifc_tisc_bits {
2043 u8 reserved_at_0[0xc];
2045 u8 reserved_at_10[0x10];
2047 u8 reserved_at_20[0x100];
2049 u8 reserved_at_120[0x8];
2050 u8 transport_domain[0x18];
2052 u8 reserved_at_140[0x3c0];
2056 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2057 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2061 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2062 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2066 MLX5_RX_HASH_FN_NONE = 0x0,
2067 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2068 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2072 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2073 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2076 struct mlx5_ifc_tirc_bits {
2077 u8 reserved_at_0[0x20];
2080 u8 reserved_at_24[0x1c];
2082 u8 reserved_at_40[0x40];
2084 u8 reserved_at_80[0x4];
2085 u8 lro_timeout_period_usecs[0x10];
2086 u8 lro_enable_mask[0x4];
2087 u8 lro_max_ip_payload_size[0x8];
2089 u8 reserved_at_a0[0x40];
2091 u8 reserved_at_e0[0x8];
2092 u8 inline_rqn[0x18];
2094 u8 rx_hash_symmetric[0x1];
2095 u8 reserved_at_101[0x1];
2096 u8 tunneled_offload_en[0x1];
2097 u8 reserved_at_103[0x5];
2098 u8 indirect_table[0x18];
2101 u8 reserved_at_124[0x2];
2102 u8 self_lb_block[0x2];
2103 u8 transport_domain[0x18];
2105 u8 rx_hash_toeplitz_key[10][0x20];
2107 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2109 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2111 u8 reserved_at_2c0[0x4c0];
2115 MLX5_SRQC_STATE_GOOD = 0x0,
2116 MLX5_SRQC_STATE_ERROR = 0x1,
2119 struct mlx5_ifc_srqc_bits {
2121 u8 log_srq_size[0x4];
2122 u8 reserved_at_8[0x18];
2124 u8 wq_signature[0x1];
2126 u8 reserved_at_22[0x1];
2128 u8 reserved_at_24[0x1];
2129 u8 log_rq_stride[0x3];
2132 u8 page_offset[0x6];
2133 u8 reserved_at_46[0x2];
2136 u8 reserved_at_60[0x20];
2138 u8 reserved_at_80[0x2];
2139 u8 log_page_size[0x6];
2140 u8 reserved_at_88[0x18];
2142 u8 reserved_at_a0[0x20];
2144 u8 reserved_at_c0[0x8];
2150 u8 reserved_at_100[0x40];
2154 u8 reserved_at_180[0x80];
2158 MLX5_SQC_STATE_RST = 0x0,
2159 MLX5_SQC_STATE_RDY = 0x1,
2160 MLX5_SQC_STATE_ERR = 0x3,
2163 struct mlx5_ifc_sqc_bits {
2167 u8 flush_in_error_en[0x1];
2168 u8 reserved_at_4[0x4];
2170 u8 reserved_at_c[0x14];
2172 u8 reserved_at_20[0x8];
2173 u8 user_index[0x18];
2175 u8 reserved_at_40[0x8];
2178 u8 reserved_at_60[0xa0];
2180 u8 tis_lst_sz[0x10];
2181 u8 reserved_at_110[0x10];
2183 u8 reserved_at_120[0x40];
2185 u8 reserved_at_160[0x8];
2188 struct mlx5_ifc_wq_bits wq;
2191 struct mlx5_ifc_rqtc_bits {
2192 u8 reserved_at_0[0xa0];
2194 u8 reserved_at_a0[0x10];
2195 u8 rqt_max_size[0x10];
2197 u8 reserved_at_c0[0x10];
2198 u8 rqt_actual_size[0x10];
2200 u8 reserved_at_e0[0x6a0];
2202 struct mlx5_ifc_rq_num_bits rq_num[0];
2206 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2207 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2211 MLX5_RQC_STATE_RST = 0x0,
2212 MLX5_RQC_STATE_RDY = 0x1,
2213 MLX5_RQC_STATE_ERR = 0x3,
2216 struct mlx5_ifc_rqc_bits {
2218 u8 reserved_at_1[0x2];
2220 u8 mem_rq_type[0x4];
2222 u8 reserved_at_c[0x1];
2223 u8 flush_in_error_en[0x1];
2224 u8 reserved_at_e[0x12];
2226 u8 reserved_at_20[0x8];
2227 u8 user_index[0x18];
2229 u8 reserved_at_40[0x8];
2232 u8 counter_set_id[0x8];
2233 u8 reserved_at_68[0x18];
2235 u8 reserved_at_80[0x8];
2238 u8 reserved_at_a0[0xe0];
2240 struct mlx5_ifc_wq_bits wq;
2244 MLX5_RMPC_STATE_RDY = 0x1,
2245 MLX5_RMPC_STATE_ERR = 0x3,
2248 struct mlx5_ifc_rmpc_bits {
2249 u8 reserved_at_0[0x8];
2251 u8 reserved_at_c[0x14];
2253 u8 basic_cyclic_rcv_wqe[0x1];
2254 u8 reserved_at_21[0x1f];
2256 u8 reserved_at_40[0x140];
2258 struct mlx5_ifc_wq_bits wq;
2261 struct mlx5_ifc_nic_vport_context_bits {
2262 u8 reserved_at_0[0x1f];
2265 u8 arm_change_event[0x1];
2266 u8 reserved_at_21[0x1a];
2267 u8 event_on_mtu[0x1];
2268 u8 event_on_promisc_change[0x1];
2269 u8 event_on_vlan_change[0x1];
2270 u8 event_on_mc_address_change[0x1];
2271 u8 event_on_uc_address_change[0x1];
2273 u8 reserved_at_40[0xf0];
2277 u8 system_image_guid[0x40];
2281 u8 reserved_at_200[0x140];
2282 u8 qkey_violation_counter[0x10];
2283 u8 reserved_at_350[0x430];
2287 u8 promisc_all[0x1];
2288 u8 reserved_at_783[0x2];
2289 u8 allowed_list_type[0x3];
2290 u8 reserved_at_788[0xc];
2291 u8 allowed_list_size[0xc];
2293 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2295 u8 reserved_at_7e0[0x20];
2297 u8 current_uc_mac_address[0][0x40];
2301 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2302 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2303 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2306 struct mlx5_ifc_mkc_bits {
2307 u8 reserved_at_0[0x1];
2309 u8 reserved_at_2[0xd];
2310 u8 small_fence_on_rdma_read_response[0x1];
2317 u8 access_mode[0x2];
2318 u8 reserved_at_18[0x8];
2323 u8 reserved_at_40[0x20];
2328 u8 reserved_at_63[0x2];
2329 u8 expected_sigerr_count[0x1];
2330 u8 reserved_at_66[0x1];
2334 u8 start_addr[0x40];
2338 u8 bsf_octword_size[0x20];
2340 u8 reserved_at_120[0x80];
2342 u8 translations_octword_size[0x20];
2344 u8 reserved_at_1c0[0x1b];
2345 u8 log_page_size[0x5];
2347 u8 reserved_at_1e0[0x20];
2350 struct mlx5_ifc_pkey_bits {
2351 u8 reserved_at_0[0x10];
2355 struct mlx5_ifc_array128_auto_bits {
2356 u8 array128_auto[16][0x8];
2359 struct mlx5_ifc_hca_vport_context_bits {
2360 u8 field_select[0x20];
2362 u8 reserved_at_20[0xe0];
2364 u8 sm_virt_aware[0x1];
2367 u8 grh_required[0x1];
2368 u8 reserved_at_104[0xc];
2369 u8 port_physical_state[0x4];
2370 u8 vport_state_policy[0x4];
2372 u8 vport_state[0x4];
2374 u8 reserved_at_120[0x20];
2376 u8 system_image_guid[0x40];
2384 u8 cap_mask1_field_select[0x20];
2388 u8 cap_mask2_field_select[0x20];
2390 u8 reserved_at_280[0x80];
2393 u8 reserved_at_310[0x4];
2394 u8 init_type_reply[0x4];
2396 u8 subnet_timeout[0x5];
2400 u8 reserved_at_334[0xc];
2402 u8 qkey_violation_counter[0x10];
2403 u8 pkey_violation_counter[0x10];
2405 u8 reserved_at_360[0xca0];
2408 struct mlx5_ifc_esw_vport_context_bits {
2409 u8 reserved_at_0[0x3];
2410 u8 vport_svlan_strip[0x1];
2411 u8 vport_cvlan_strip[0x1];
2412 u8 vport_svlan_insert[0x1];
2413 u8 vport_cvlan_insert[0x2];
2414 u8 reserved_at_8[0x18];
2416 u8 reserved_at_20[0x20];
2425 u8 reserved_at_60[0x7a0];
2429 MLX5_EQC_STATUS_OK = 0x0,
2430 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2434 MLX5_EQC_ST_ARMED = 0x9,
2435 MLX5_EQC_ST_FIRED = 0xa,
2438 struct mlx5_ifc_eqc_bits {
2440 u8 reserved_at_4[0x9];
2443 u8 reserved_at_f[0x5];
2445 u8 reserved_at_18[0x8];
2447 u8 reserved_at_20[0x20];
2449 u8 reserved_at_40[0x14];
2450 u8 page_offset[0x6];
2451 u8 reserved_at_5a[0x6];
2453 u8 reserved_at_60[0x3];
2454 u8 log_eq_size[0x5];
2457 u8 reserved_at_80[0x20];
2459 u8 reserved_at_a0[0x18];
2462 u8 reserved_at_c0[0x3];
2463 u8 log_page_size[0x5];
2464 u8 reserved_at_c8[0x18];
2466 u8 reserved_at_e0[0x60];
2468 u8 reserved_at_140[0x8];
2469 u8 consumer_counter[0x18];
2471 u8 reserved_at_160[0x8];
2472 u8 producer_counter[0x18];
2474 u8 reserved_at_180[0x80];
2478 MLX5_DCTC_STATE_ACTIVE = 0x0,
2479 MLX5_DCTC_STATE_DRAINING = 0x1,
2480 MLX5_DCTC_STATE_DRAINED = 0x2,
2484 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2485 MLX5_DCTC_CS_RES_NA = 0x1,
2486 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2490 MLX5_DCTC_MTU_256_BYTES = 0x1,
2491 MLX5_DCTC_MTU_512_BYTES = 0x2,
2492 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2493 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2494 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2497 struct mlx5_ifc_dctc_bits {
2498 u8 reserved_at_0[0x4];
2500 u8 reserved_at_8[0x18];
2502 u8 reserved_at_20[0x8];
2503 u8 user_index[0x18];
2505 u8 reserved_at_40[0x8];
2508 u8 counter_set_id[0x8];
2509 u8 atomic_mode[0x4];
2513 u8 atomic_like_write_en[0x1];
2514 u8 latency_sensitive[0x1];
2517 u8 reserved_at_73[0xd];
2519 u8 reserved_at_80[0x8];
2521 u8 reserved_at_90[0x3];
2522 u8 min_rnr_nak[0x5];
2523 u8 reserved_at_98[0x8];
2525 u8 reserved_at_a0[0x8];
2528 u8 reserved_at_c0[0x8];
2532 u8 reserved_at_e8[0x4];
2533 u8 flow_label[0x14];
2535 u8 dc_access_key[0x40];
2537 u8 reserved_at_140[0x5];
2540 u8 pkey_index[0x10];
2542 u8 reserved_at_160[0x8];
2543 u8 my_addr_index[0x8];
2544 u8 reserved_at_170[0x8];
2547 u8 dc_access_key_violation_count[0x20];
2549 u8 reserved_at_1a0[0x14];
2555 u8 reserved_at_1c0[0x40];
2559 MLX5_CQC_STATUS_OK = 0x0,
2560 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2561 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2565 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2566 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2570 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2571 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2572 MLX5_CQC_ST_FIRED = 0xa,
2575 struct mlx5_ifc_cqc_bits {
2577 u8 reserved_at_4[0x4];
2580 u8 reserved_at_c[0x1];
2581 u8 scqe_break_moderation_en[0x1];
2583 u8 reserved_at_f[0x2];
2585 u8 mini_cqe_res_format[0x2];
2587 u8 reserved_at_18[0x8];
2589 u8 reserved_at_20[0x20];
2591 u8 reserved_at_40[0x14];
2592 u8 page_offset[0x6];
2593 u8 reserved_at_5a[0x6];
2595 u8 reserved_at_60[0x3];
2596 u8 log_cq_size[0x5];
2599 u8 reserved_at_80[0x4];
2601 u8 cq_max_count[0x10];
2603 u8 reserved_at_a0[0x18];
2606 u8 reserved_at_c0[0x3];
2607 u8 log_page_size[0x5];
2608 u8 reserved_at_c8[0x18];
2610 u8 reserved_at_e0[0x20];
2612 u8 reserved_at_100[0x8];
2613 u8 last_notified_index[0x18];
2615 u8 reserved_at_120[0x8];
2616 u8 last_solicit_index[0x18];
2618 u8 reserved_at_140[0x8];
2619 u8 consumer_counter[0x18];
2621 u8 reserved_at_160[0x8];
2622 u8 producer_counter[0x18];
2624 u8 reserved_at_180[0x40];
2629 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2630 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2631 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2632 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2633 u8 reserved_at_0[0x800];
2636 struct mlx5_ifc_query_adapter_param_block_bits {
2637 u8 reserved_at_0[0xc0];
2639 u8 reserved_at_c0[0x8];
2640 u8 ieee_vendor_id[0x18];
2642 u8 reserved_at_e0[0x10];
2643 u8 vsd_vendor_id[0x10];
2647 u8 vsd_contd_psid[16][0x8];
2650 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2651 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2652 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2653 u8 reserved_at_0[0x20];
2656 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2657 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2658 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2659 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2660 u8 reserved_at_0[0x20];
2663 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2664 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2665 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2666 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2667 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2668 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2669 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2670 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2671 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2672 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2673 u8 reserved_at_0[0x7c0];
2676 union mlx5_ifc_event_auto_bits {
2677 struct mlx5_ifc_comp_event_bits comp_event;
2678 struct mlx5_ifc_dct_events_bits dct_events;
2679 struct mlx5_ifc_qp_events_bits qp_events;
2680 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2681 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2682 struct mlx5_ifc_cq_error_bits cq_error;
2683 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2684 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2685 struct mlx5_ifc_gpio_event_bits gpio_event;
2686 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2687 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2688 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2689 u8 reserved_at_0[0xe0];
2692 struct mlx5_ifc_health_buffer_bits {
2693 u8 reserved_at_0[0x100];
2695 u8 assert_existptr[0x20];
2697 u8 assert_callra[0x20];
2699 u8 reserved_at_140[0x40];
2701 u8 fw_version[0x20];
2705 u8 reserved_at_1c0[0x20];
2707 u8 irisc_index[0x8];
2712 struct mlx5_ifc_register_loopback_control_bits {
2714 u8 reserved_at_1[0x7];
2716 u8 reserved_at_10[0x10];
2718 u8 reserved_at_20[0x60];
2721 struct mlx5_ifc_teardown_hca_out_bits {
2723 u8 reserved_at_8[0x18];
2727 u8 reserved_at_40[0x40];
2731 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2732 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2735 struct mlx5_ifc_teardown_hca_in_bits {
2737 u8 reserved_at_10[0x10];
2739 u8 reserved_at_20[0x10];
2742 u8 reserved_at_40[0x10];
2745 u8 reserved_at_60[0x20];
2748 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2750 u8 reserved_at_8[0x18];
2754 u8 reserved_at_40[0x40];
2757 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2759 u8 reserved_at_10[0x10];
2761 u8 reserved_at_20[0x10];
2764 u8 reserved_at_40[0x8];
2767 u8 reserved_at_60[0x20];
2769 u8 opt_param_mask[0x20];
2771 u8 reserved_at_a0[0x20];
2773 struct mlx5_ifc_qpc_bits qpc;
2775 u8 reserved_at_800[0x80];
2778 struct mlx5_ifc_sqd2rts_qp_out_bits {
2780 u8 reserved_at_8[0x18];
2784 u8 reserved_at_40[0x40];
2787 struct mlx5_ifc_sqd2rts_qp_in_bits {
2789 u8 reserved_at_10[0x10];
2791 u8 reserved_at_20[0x10];
2794 u8 reserved_at_40[0x8];
2797 u8 reserved_at_60[0x20];
2799 u8 opt_param_mask[0x20];
2801 u8 reserved_at_a0[0x20];
2803 struct mlx5_ifc_qpc_bits qpc;
2805 u8 reserved_at_800[0x80];
2808 struct mlx5_ifc_set_roce_address_out_bits {
2810 u8 reserved_at_8[0x18];
2814 u8 reserved_at_40[0x40];
2817 struct mlx5_ifc_set_roce_address_in_bits {
2819 u8 reserved_at_10[0x10];
2821 u8 reserved_at_20[0x10];
2824 u8 roce_address_index[0x10];
2825 u8 reserved_at_50[0x10];
2827 u8 reserved_at_60[0x20];
2829 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2832 struct mlx5_ifc_set_mad_demux_out_bits {
2834 u8 reserved_at_8[0x18];
2838 u8 reserved_at_40[0x40];
2842 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2843 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2846 struct mlx5_ifc_set_mad_demux_in_bits {
2848 u8 reserved_at_10[0x10];
2850 u8 reserved_at_20[0x10];
2853 u8 reserved_at_40[0x20];
2855 u8 reserved_at_60[0x6];
2857 u8 reserved_at_68[0x18];
2860 struct mlx5_ifc_set_l2_table_entry_out_bits {
2862 u8 reserved_at_8[0x18];
2866 u8 reserved_at_40[0x40];
2869 struct mlx5_ifc_set_l2_table_entry_in_bits {
2871 u8 reserved_at_10[0x10];
2873 u8 reserved_at_20[0x10];
2876 u8 reserved_at_40[0x60];
2878 u8 reserved_at_a0[0x8];
2879 u8 table_index[0x18];
2881 u8 reserved_at_c0[0x20];
2883 u8 reserved_at_e0[0x13];
2887 struct mlx5_ifc_mac_address_layout_bits mac_address;
2889 u8 reserved_at_140[0xc0];
2892 struct mlx5_ifc_set_issi_out_bits {
2894 u8 reserved_at_8[0x18];
2898 u8 reserved_at_40[0x40];
2901 struct mlx5_ifc_set_issi_in_bits {
2903 u8 reserved_at_10[0x10];
2905 u8 reserved_at_20[0x10];
2908 u8 reserved_at_40[0x10];
2909 u8 current_issi[0x10];
2911 u8 reserved_at_60[0x20];
2914 struct mlx5_ifc_set_hca_cap_out_bits {
2916 u8 reserved_at_8[0x18];
2920 u8 reserved_at_40[0x40];
2923 struct mlx5_ifc_set_hca_cap_in_bits {
2925 u8 reserved_at_10[0x10];
2927 u8 reserved_at_20[0x10];
2930 u8 reserved_at_40[0x40];
2932 union mlx5_ifc_hca_cap_union_bits capability;
2936 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
2937 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
2938 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
2939 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
2942 struct mlx5_ifc_set_fte_out_bits {
2944 u8 reserved_at_8[0x18];
2948 u8 reserved_at_40[0x40];
2951 struct mlx5_ifc_set_fte_in_bits {
2953 u8 reserved_at_10[0x10];
2955 u8 reserved_at_20[0x10];
2958 u8 reserved_at_40[0x40];
2961 u8 reserved_at_88[0x18];
2963 u8 reserved_at_a0[0x8];
2966 u8 reserved_at_c0[0x18];
2967 u8 modify_enable_mask[0x8];
2969 u8 reserved_at_e0[0x20];
2971 u8 flow_index[0x20];
2973 u8 reserved_at_120[0xe0];
2975 struct mlx5_ifc_flow_context_bits flow_context;
2978 struct mlx5_ifc_rts2rts_qp_out_bits {
2980 u8 reserved_at_8[0x18];
2984 u8 reserved_at_40[0x40];
2987 struct mlx5_ifc_rts2rts_qp_in_bits {
2989 u8 reserved_at_10[0x10];
2991 u8 reserved_at_20[0x10];
2994 u8 reserved_at_40[0x8];
2997 u8 reserved_at_60[0x20];
2999 u8 opt_param_mask[0x20];
3001 u8 reserved_at_a0[0x20];
3003 struct mlx5_ifc_qpc_bits qpc;
3005 u8 reserved_at_800[0x80];
3008 struct mlx5_ifc_rtr2rts_qp_out_bits {
3010 u8 reserved_at_8[0x18];
3014 u8 reserved_at_40[0x40];
3017 struct mlx5_ifc_rtr2rts_qp_in_bits {
3019 u8 reserved_at_10[0x10];
3021 u8 reserved_at_20[0x10];
3024 u8 reserved_at_40[0x8];
3027 u8 reserved_at_60[0x20];
3029 u8 opt_param_mask[0x20];
3031 u8 reserved_at_a0[0x20];
3033 struct mlx5_ifc_qpc_bits qpc;
3035 u8 reserved_at_800[0x80];
3038 struct mlx5_ifc_rst2init_qp_out_bits {
3040 u8 reserved_at_8[0x18];
3044 u8 reserved_at_40[0x40];
3047 struct mlx5_ifc_rst2init_qp_in_bits {
3049 u8 reserved_at_10[0x10];
3051 u8 reserved_at_20[0x10];
3054 u8 reserved_at_40[0x8];
3057 u8 reserved_at_60[0x20];
3059 u8 opt_param_mask[0x20];
3061 u8 reserved_at_a0[0x20];
3063 struct mlx5_ifc_qpc_bits qpc;
3065 u8 reserved_at_800[0x80];
3068 struct mlx5_ifc_query_xrc_srq_out_bits {
3070 u8 reserved_at_8[0x18];
3074 u8 reserved_at_40[0x40];
3076 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3078 u8 reserved_at_280[0x600];
3083 struct mlx5_ifc_query_xrc_srq_in_bits {
3085 u8 reserved_at_10[0x10];
3087 u8 reserved_at_20[0x10];
3090 u8 reserved_at_40[0x8];
3093 u8 reserved_at_60[0x20];
3097 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3098 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3101 struct mlx5_ifc_query_vport_state_out_bits {
3103 u8 reserved_at_8[0x18];
3107 u8 reserved_at_40[0x20];
3109 u8 reserved_at_60[0x18];
3110 u8 admin_state[0x4];
3115 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3116 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3119 struct mlx5_ifc_query_vport_state_in_bits {
3121 u8 reserved_at_10[0x10];
3123 u8 reserved_at_20[0x10];
3126 u8 other_vport[0x1];
3127 u8 reserved_at_41[0xf];
3128 u8 vport_number[0x10];
3130 u8 reserved_at_60[0x20];
3133 struct mlx5_ifc_query_vport_counter_out_bits {
3135 u8 reserved_at_8[0x18];
3139 u8 reserved_at_40[0x40];
3141 struct mlx5_ifc_traffic_counter_bits received_errors;
3143 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3145 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3147 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3149 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3151 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3153 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3155 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3157 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3159 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3161 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3163 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3165 u8 reserved_at_680[0xa00];
3169 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3172 struct mlx5_ifc_query_vport_counter_in_bits {
3174 u8 reserved_at_10[0x10];
3176 u8 reserved_at_20[0x10];
3179 u8 other_vport[0x1];
3180 u8 reserved_at_41[0xb];
3182 u8 vport_number[0x10];
3184 u8 reserved_at_60[0x60];
3187 u8 reserved_at_c1[0x1f];
3189 u8 reserved_at_e0[0x20];
3192 struct mlx5_ifc_query_tis_out_bits {
3194 u8 reserved_at_8[0x18];
3198 u8 reserved_at_40[0x40];
3200 struct mlx5_ifc_tisc_bits tis_context;
3203 struct mlx5_ifc_query_tis_in_bits {
3205 u8 reserved_at_10[0x10];
3207 u8 reserved_at_20[0x10];
3210 u8 reserved_at_40[0x8];
3213 u8 reserved_at_60[0x20];
3216 struct mlx5_ifc_query_tir_out_bits {
3218 u8 reserved_at_8[0x18];
3222 u8 reserved_at_40[0xc0];
3224 struct mlx5_ifc_tirc_bits tir_context;
3227 struct mlx5_ifc_query_tir_in_bits {
3229 u8 reserved_at_10[0x10];
3231 u8 reserved_at_20[0x10];
3234 u8 reserved_at_40[0x8];
3237 u8 reserved_at_60[0x20];
3240 struct mlx5_ifc_query_srq_out_bits {
3242 u8 reserved_at_8[0x18];
3246 u8 reserved_at_40[0x40];
3248 struct mlx5_ifc_srqc_bits srq_context_entry;
3250 u8 reserved_at_280[0x600];
3255 struct mlx5_ifc_query_srq_in_bits {
3257 u8 reserved_at_10[0x10];
3259 u8 reserved_at_20[0x10];
3262 u8 reserved_at_40[0x8];
3265 u8 reserved_at_60[0x20];
3268 struct mlx5_ifc_query_sq_out_bits {
3270 u8 reserved_at_8[0x18];
3274 u8 reserved_at_40[0xc0];
3276 struct mlx5_ifc_sqc_bits sq_context;
3279 struct mlx5_ifc_query_sq_in_bits {
3281 u8 reserved_at_10[0x10];
3283 u8 reserved_at_20[0x10];
3286 u8 reserved_at_40[0x8];
3289 u8 reserved_at_60[0x20];
3292 struct mlx5_ifc_query_special_contexts_out_bits {
3294 u8 reserved_at_8[0x18];
3298 u8 reserved_at_40[0x20];
3303 struct mlx5_ifc_query_special_contexts_in_bits {
3305 u8 reserved_at_10[0x10];
3307 u8 reserved_at_20[0x10];
3310 u8 reserved_at_40[0x40];
3313 struct mlx5_ifc_query_rqt_out_bits {
3315 u8 reserved_at_8[0x18];
3319 u8 reserved_at_40[0xc0];
3321 struct mlx5_ifc_rqtc_bits rqt_context;
3324 struct mlx5_ifc_query_rqt_in_bits {
3326 u8 reserved_at_10[0x10];
3328 u8 reserved_at_20[0x10];
3331 u8 reserved_at_40[0x8];
3334 u8 reserved_at_60[0x20];
3337 struct mlx5_ifc_query_rq_out_bits {
3339 u8 reserved_at_8[0x18];
3343 u8 reserved_at_40[0xc0];
3345 struct mlx5_ifc_rqc_bits rq_context;
3348 struct mlx5_ifc_query_rq_in_bits {
3350 u8 reserved_at_10[0x10];
3352 u8 reserved_at_20[0x10];
3355 u8 reserved_at_40[0x8];
3358 u8 reserved_at_60[0x20];
3361 struct mlx5_ifc_query_roce_address_out_bits {
3363 u8 reserved_at_8[0x18];
3367 u8 reserved_at_40[0x40];
3369 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3372 struct mlx5_ifc_query_roce_address_in_bits {
3374 u8 reserved_at_10[0x10];
3376 u8 reserved_at_20[0x10];
3379 u8 roce_address_index[0x10];
3380 u8 reserved_at_50[0x10];
3382 u8 reserved_at_60[0x20];
3385 struct mlx5_ifc_query_rmp_out_bits {
3387 u8 reserved_at_8[0x18];
3391 u8 reserved_at_40[0xc0];
3393 struct mlx5_ifc_rmpc_bits rmp_context;
3396 struct mlx5_ifc_query_rmp_in_bits {
3398 u8 reserved_at_10[0x10];
3400 u8 reserved_at_20[0x10];
3403 u8 reserved_at_40[0x8];
3406 u8 reserved_at_60[0x20];
3409 struct mlx5_ifc_query_qp_out_bits {
3411 u8 reserved_at_8[0x18];
3415 u8 reserved_at_40[0x40];
3417 u8 opt_param_mask[0x20];
3419 u8 reserved_at_a0[0x20];
3421 struct mlx5_ifc_qpc_bits qpc;
3423 u8 reserved_at_800[0x80];
3428 struct mlx5_ifc_query_qp_in_bits {
3430 u8 reserved_at_10[0x10];
3432 u8 reserved_at_20[0x10];
3435 u8 reserved_at_40[0x8];
3438 u8 reserved_at_60[0x20];
3441 struct mlx5_ifc_query_q_counter_out_bits {
3443 u8 reserved_at_8[0x18];
3447 u8 reserved_at_40[0x40];
3449 u8 rx_write_requests[0x20];
3451 u8 reserved_at_a0[0x20];
3453 u8 rx_read_requests[0x20];
3455 u8 reserved_at_e0[0x20];
3457 u8 rx_atomic_requests[0x20];
3459 u8 reserved_at_120[0x20];
3461 u8 rx_dct_connect[0x20];
3463 u8 reserved_at_160[0x20];
3465 u8 out_of_buffer[0x20];
3467 u8 reserved_at_1a0[0x20];
3469 u8 out_of_sequence[0x20];
3471 u8 reserved_at_1e0[0x620];
3474 struct mlx5_ifc_query_q_counter_in_bits {
3476 u8 reserved_at_10[0x10];
3478 u8 reserved_at_20[0x10];
3481 u8 reserved_at_40[0x80];
3484 u8 reserved_at_c1[0x1f];
3486 u8 reserved_at_e0[0x18];
3487 u8 counter_set_id[0x8];
3490 struct mlx5_ifc_query_pages_out_bits {
3492 u8 reserved_at_8[0x18];
3496 u8 reserved_at_40[0x10];
3497 u8 function_id[0x10];
3503 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3504 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3505 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3508 struct mlx5_ifc_query_pages_in_bits {
3510 u8 reserved_at_10[0x10];
3512 u8 reserved_at_20[0x10];
3515 u8 reserved_at_40[0x10];
3516 u8 function_id[0x10];
3518 u8 reserved_at_60[0x20];
3521 struct mlx5_ifc_query_nic_vport_context_out_bits {
3523 u8 reserved_at_8[0x18];
3527 u8 reserved_at_40[0x40];
3529 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3532 struct mlx5_ifc_query_nic_vport_context_in_bits {
3534 u8 reserved_at_10[0x10];
3536 u8 reserved_at_20[0x10];
3539 u8 other_vport[0x1];
3540 u8 reserved_at_41[0xf];
3541 u8 vport_number[0x10];
3543 u8 reserved_at_60[0x5];
3544 u8 allowed_list_type[0x3];
3545 u8 reserved_at_68[0x18];
3548 struct mlx5_ifc_query_mkey_out_bits {
3550 u8 reserved_at_8[0x18];
3554 u8 reserved_at_40[0x40];
3556 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3558 u8 reserved_at_280[0x600];
3560 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3562 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3565 struct mlx5_ifc_query_mkey_in_bits {
3567 u8 reserved_at_10[0x10];
3569 u8 reserved_at_20[0x10];
3572 u8 reserved_at_40[0x8];
3573 u8 mkey_index[0x18];
3576 u8 reserved_at_61[0x1f];
3579 struct mlx5_ifc_query_mad_demux_out_bits {
3581 u8 reserved_at_8[0x18];
3585 u8 reserved_at_40[0x40];
3587 u8 mad_dumux_parameters_block[0x20];
3590 struct mlx5_ifc_query_mad_demux_in_bits {
3592 u8 reserved_at_10[0x10];
3594 u8 reserved_at_20[0x10];
3597 u8 reserved_at_40[0x40];
3600 struct mlx5_ifc_query_l2_table_entry_out_bits {
3602 u8 reserved_at_8[0x18];
3606 u8 reserved_at_40[0xa0];
3608 u8 reserved_at_e0[0x13];
3612 struct mlx5_ifc_mac_address_layout_bits mac_address;
3614 u8 reserved_at_140[0xc0];
3617 struct mlx5_ifc_query_l2_table_entry_in_bits {
3619 u8 reserved_at_10[0x10];
3621 u8 reserved_at_20[0x10];
3624 u8 reserved_at_40[0x60];
3626 u8 reserved_at_a0[0x8];
3627 u8 table_index[0x18];
3629 u8 reserved_at_c0[0x140];
3632 struct mlx5_ifc_query_issi_out_bits {
3634 u8 reserved_at_8[0x18];
3638 u8 reserved_at_40[0x10];
3639 u8 current_issi[0x10];
3641 u8 reserved_at_60[0xa0];
3643 u8 reserved_at_100[76][0x8];
3644 u8 supported_issi_dw0[0x20];
3647 struct mlx5_ifc_query_issi_in_bits {
3649 u8 reserved_at_10[0x10];
3651 u8 reserved_at_20[0x10];
3654 u8 reserved_at_40[0x40];
3657 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3659 u8 reserved_at_8[0x18];
3663 u8 reserved_at_40[0x40];
3665 struct mlx5_ifc_pkey_bits pkey[0];
3668 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3670 u8 reserved_at_10[0x10];
3672 u8 reserved_at_20[0x10];
3675 u8 other_vport[0x1];
3676 u8 reserved_at_41[0xb];
3678 u8 vport_number[0x10];
3680 u8 reserved_at_60[0x10];
3681 u8 pkey_index[0x10];
3684 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3686 u8 reserved_at_8[0x18];
3690 u8 reserved_at_40[0x20];
3693 u8 reserved_at_70[0x10];
3695 struct mlx5_ifc_array128_auto_bits gid[0];
3698 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3700 u8 reserved_at_10[0x10];
3702 u8 reserved_at_20[0x10];
3705 u8 other_vport[0x1];
3706 u8 reserved_at_41[0xb];
3708 u8 vport_number[0x10];
3710 u8 reserved_at_60[0x10];
3714 struct mlx5_ifc_query_hca_vport_context_out_bits {
3716 u8 reserved_at_8[0x18];
3720 u8 reserved_at_40[0x40];
3722 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3725 struct mlx5_ifc_query_hca_vport_context_in_bits {
3727 u8 reserved_at_10[0x10];
3729 u8 reserved_at_20[0x10];
3732 u8 other_vport[0x1];
3733 u8 reserved_at_41[0xb];
3735 u8 vport_number[0x10];
3737 u8 reserved_at_60[0x20];
3740 struct mlx5_ifc_query_hca_cap_out_bits {
3742 u8 reserved_at_8[0x18];
3746 u8 reserved_at_40[0x40];
3748 union mlx5_ifc_hca_cap_union_bits capability;
3751 struct mlx5_ifc_query_hca_cap_in_bits {
3753 u8 reserved_at_10[0x10];
3755 u8 reserved_at_20[0x10];
3758 u8 reserved_at_40[0x40];
3761 struct mlx5_ifc_query_flow_table_out_bits {
3763 u8 reserved_at_8[0x18];
3767 u8 reserved_at_40[0x80];
3769 u8 reserved_at_c0[0x8];
3771 u8 reserved_at_d0[0x8];
3774 u8 reserved_at_e0[0x120];
3777 struct mlx5_ifc_query_flow_table_in_bits {
3779 u8 reserved_at_10[0x10];
3781 u8 reserved_at_20[0x10];
3784 u8 reserved_at_40[0x40];
3787 u8 reserved_at_88[0x18];
3789 u8 reserved_at_a0[0x8];
3792 u8 reserved_at_c0[0x140];
3795 struct mlx5_ifc_query_fte_out_bits {
3797 u8 reserved_at_8[0x18];
3801 u8 reserved_at_40[0x1c0];
3803 struct mlx5_ifc_flow_context_bits flow_context;
3806 struct mlx5_ifc_query_fte_in_bits {
3808 u8 reserved_at_10[0x10];
3810 u8 reserved_at_20[0x10];
3813 u8 reserved_at_40[0x40];
3816 u8 reserved_at_88[0x18];
3818 u8 reserved_at_a0[0x8];
3821 u8 reserved_at_c0[0x40];
3823 u8 flow_index[0x20];
3825 u8 reserved_at_120[0xe0];
3829 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3830 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3831 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3834 struct mlx5_ifc_query_flow_group_out_bits {
3836 u8 reserved_at_8[0x18];
3840 u8 reserved_at_40[0xa0];
3842 u8 start_flow_index[0x20];
3844 u8 reserved_at_100[0x20];
3846 u8 end_flow_index[0x20];
3848 u8 reserved_at_140[0xa0];
3850 u8 reserved_at_1e0[0x18];
3851 u8 match_criteria_enable[0x8];
3853 struct mlx5_ifc_fte_match_param_bits match_criteria;
3855 u8 reserved_at_1200[0xe00];
3858 struct mlx5_ifc_query_flow_group_in_bits {
3860 u8 reserved_at_10[0x10];
3862 u8 reserved_at_20[0x10];
3865 u8 reserved_at_40[0x40];
3868 u8 reserved_at_88[0x18];
3870 u8 reserved_at_a0[0x8];
3875 u8 reserved_at_e0[0x120];
3878 struct mlx5_ifc_query_esw_vport_context_out_bits {
3880 u8 reserved_at_8[0x18];
3884 u8 reserved_at_40[0x40];
3886 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3889 struct mlx5_ifc_query_esw_vport_context_in_bits {
3891 u8 reserved_at_10[0x10];
3893 u8 reserved_at_20[0x10];
3896 u8 other_vport[0x1];
3897 u8 reserved_at_41[0xf];
3898 u8 vport_number[0x10];
3900 u8 reserved_at_60[0x20];
3903 struct mlx5_ifc_modify_esw_vport_context_out_bits {
3905 u8 reserved_at_8[0x18];
3909 u8 reserved_at_40[0x40];
3912 struct mlx5_ifc_esw_vport_context_fields_select_bits {
3913 u8 reserved_at_0[0x1c];
3914 u8 vport_cvlan_insert[0x1];
3915 u8 vport_svlan_insert[0x1];
3916 u8 vport_cvlan_strip[0x1];
3917 u8 vport_svlan_strip[0x1];
3920 struct mlx5_ifc_modify_esw_vport_context_in_bits {
3922 u8 reserved_at_10[0x10];
3924 u8 reserved_at_20[0x10];
3927 u8 other_vport[0x1];
3928 u8 reserved_at_41[0xf];
3929 u8 vport_number[0x10];
3931 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3933 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3936 struct mlx5_ifc_query_eq_out_bits {
3938 u8 reserved_at_8[0x18];
3942 u8 reserved_at_40[0x40];
3944 struct mlx5_ifc_eqc_bits eq_context_entry;
3946 u8 reserved_at_280[0x40];
3948 u8 event_bitmask[0x40];
3950 u8 reserved_at_300[0x580];
3955 struct mlx5_ifc_query_eq_in_bits {
3957 u8 reserved_at_10[0x10];
3959 u8 reserved_at_20[0x10];
3962 u8 reserved_at_40[0x18];
3965 u8 reserved_at_60[0x20];
3968 struct mlx5_ifc_query_dct_out_bits {
3970 u8 reserved_at_8[0x18];
3974 u8 reserved_at_40[0x40];
3976 struct mlx5_ifc_dctc_bits dct_context_entry;
3978 u8 reserved_at_280[0x180];
3981 struct mlx5_ifc_query_dct_in_bits {
3983 u8 reserved_at_10[0x10];
3985 u8 reserved_at_20[0x10];
3988 u8 reserved_at_40[0x8];
3991 u8 reserved_at_60[0x20];
3994 struct mlx5_ifc_query_cq_out_bits {
3996 u8 reserved_at_8[0x18];
4000 u8 reserved_at_40[0x40];
4002 struct mlx5_ifc_cqc_bits cq_context;
4004 u8 reserved_at_280[0x600];
4009 struct mlx5_ifc_query_cq_in_bits {
4011 u8 reserved_at_10[0x10];
4013 u8 reserved_at_20[0x10];
4016 u8 reserved_at_40[0x8];
4019 u8 reserved_at_60[0x20];
4022 struct mlx5_ifc_query_cong_status_out_bits {
4024 u8 reserved_at_8[0x18];
4028 u8 reserved_at_40[0x20];
4032 u8 reserved_at_62[0x1e];
4035 struct mlx5_ifc_query_cong_status_in_bits {
4037 u8 reserved_at_10[0x10];
4039 u8 reserved_at_20[0x10];
4042 u8 reserved_at_40[0x18];
4044 u8 cong_protocol[0x4];
4046 u8 reserved_at_60[0x20];
4049 struct mlx5_ifc_query_cong_statistics_out_bits {
4051 u8 reserved_at_8[0x18];
4055 u8 reserved_at_40[0x40];
4061 u8 cnp_ignored_high[0x20];
4063 u8 cnp_ignored_low[0x20];
4065 u8 cnp_handled_high[0x20];
4067 u8 cnp_handled_low[0x20];
4069 u8 reserved_at_140[0x100];
4071 u8 time_stamp_high[0x20];
4073 u8 time_stamp_low[0x20];
4075 u8 accumulators_period[0x20];
4077 u8 ecn_marked_roce_packets_high[0x20];
4079 u8 ecn_marked_roce_packets_low[0x20];
4081 u8 cnps_sent_high[0x20];
4083 u8 cnps_sent_low[0x20];
4085 u8 reserved_at_320[0x560];
4088 struct mlx5_ifc_query_cong_statistics_in_bits {
4090 u8 reserved_at_10[0x10];
4092 u8 reserved_at_20[0x10];
4096 u8 reserved_at_41[0x1f];
4098 u8 reserved_at_60[0x20];
4101 struct mlx5_ifc_query_cong_params_out_bits {
4103 u8 reserved_at_8[0x18];
4107 u8 reserved_at_40[0x40];
4109 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4112 struct mlx5_ifc_query_cong_params_in_bits {
4114 u8 reserved_at_10[0x10];
4116 u8 reserved_at_20[0x10];
4119 u8 reserved_at_40[0x1c];
4120 u8 cong_protocol[0x4];
4122 u8 reserved_at_60[0x20];
4125 struct mlx5_ifc_query_adapter_out_bits {
4127 u8 reserved_at_8[0x18];
4131 u8 reserved_at_40[0x40];
4133 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4136 struct mlx5_ifc_query_adapter_in_bits {
4138 u8 reserved_at_10[0x10];
4140 u8 reserved_at_20[0x10];
4143 u8 reserved_at_40[0x40];
4146 struct mlx5_ifc_qp_2rst_out_bits {
4148 u8 reserved_at_8[0x18];
4152 u8 reserved_at_40[0x40];
4155 struct mlx5_ifc_qp_2rst_in_bits {
4157 u8 reserved_at_10[0x10];
4159 u8 reserved_at_20[0x10];
4162 u8 reserved_at_40[0x8];
4165 u8 reserved_at_60[0x20];
4168 struct mlx5_ifc_qp_2err_out_bits {
4170 u8 reserved_at_8[0x18];
4174 u8 reserved_at_40[0x40];
4177 struct mlx5_ifc_qp_2err_in_bits {
4179 u8 reserved_at_10[0x10];
4181 u8 reserved_at_20[0x10];
4184 u8 reserved_at_40[0x8];
4187 u8 reserved_at_60[0x20];
4190 struct mlx5_ifc_page_fault_resume_out_bits {
4192 u8 reserved_at_8[0x18];
4196 u8 reserved_at_40[0x40];
4199 struct mlx5_ifc_page_fault_resume_in_bits {
4201 u8 reserved_at_10[0x10];
4203 u8 reserved_at_20[0x10];
4207 u8 reserved_at_41[0x4];
4213 u8 reserved_at_60[0x20];
4216 struct mlx5_ifc_nop_out_bits {
4218 u8 reserved_at_8[0x18];
4222 u8 reserved_at_40[0x40];
4225 struct mlx5_ifc_nop_in_bits {
4227 u8 reserved_at_10[0x10];
4229 u8 reserved_at_20[0x10];
4232 u8 reserved_at_40[0x40];
4235 struct mlx5_ifc_modify_vport_state_out_bits {
4237 u8 reserved_at_8[0x18];
4241 u8 reserved_at_40[0x40];
4244 struct mlx5_ifc_modify_vport_state_in_bits {
4246 u8 reserved_at_10[0x10];
4248 u8 reserved_at_20[0x10];
4251 u8 other_vport[0x1];
4252 u8 reserved_at_41[0xf];
4253 u8 vport_number[0x10];
4255 u8 reserved_at_60[0x18];
4256 u8 admin_state[0x4];
4257 u8 reserved_at_7c[0x4];
4260 struct mlx5_ifc_modify_tis_out_bits {
4262 u8 reserved_at_8[0x18];
4266 u8 reserved_at_40[0x40];
4269 struct mlx5_ifc_modify_tis_bitmask_bits {
4270 u8 reserved_at_0[0x20];
4272 u8 reserved_at_20[0x1f];
4276 struct mlx5_ifc_modify_tis_in_bits {
4278 u8 reserved_at_10[0x10];
4280 u8 reserved_at_20[0x10];
4283 u8 reserved_at_40[0x8];
4286 u8 reserved_at_60[0x20];
4288 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4290 u8 reserved_at_c0[0x40];
4292 struct mlx5_ifc_tisc_bits ctx;
4295 struct mlx5_ifc_modify_tir_bitmask_bits {
4296 u8 reserved_at_0[0x20];
4298 u8 reserved_at_20[0x1b];
4300 u8 reserved_at_3c[0x1];
4302 u8 reserved_at_3e[0x1];
4306 struct mlx5_ifc_modify_tir_out_bits {
4308 u8 reserved_at_8[0x18];
4312 u8 reserved_at_40[0x40];
4315 struct mlx5_ifc_modify_tir_in_bits {
4317 u8 reserved_at_10[0x10];
4319 u8 reserved_at_20[0x10];
4322 u8 reserved_at_40[0x8];
4325 u8 reserved_at_60[0x20];
4327 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4329 u8 reserved_at_c0[0x40];
4331 struct mlx5_ifc_tirc_bits ctx;
4334 struct mlx5_ifc_modify_sq_out_bits {
4336 u8 reserved_at_8[0x18];
4340 u8 reserved_at_40[0x40];
4343 struct mlx5_ifc_modify_sq_in_bits {
4345 u8 reserved_at_10[0x10];
4347 u8 reserved_at_20[0x10];
4351 u8 reserved_at_44[0x4];
4354 u8 reserved_at_60[0x20];
4356 u8 modify_bitmask[0x40];
4358 u8 reserved_at_c0[0x40];
4360 struct mlx5_ifc_sqc_bits ctx;
4363 struct mlx5_ifc_modify_rqt_out_bits {
4365 u8 reserved_at_8[0x18];
4369 u8 reserved_at_40[0x40];
4372 struct mlx5_ifc_rqt_bitmask_bits {
4373 u8 reserved_at_0[0x20];
4375 u8 reserved_at_20[0x1f];
4379 struct mlx5_ifc_modify_rqt_in_bits {
4381 u8 reserved_at_10[0x10];
4383 u8 reserved_at_20[0x10];
4386 u8 reserved_at_40[0x8];
4389 u8 reserved_at_60[0x20];
4391 struct mlx5_ifc_rqt_bitmask_bits bitmask;
4393 u8 reserved_at_c0[0x40];
4395 struct mlx5_ifc_rqtc_bits ctx;
4398 struct mlx5_ifc_modify_rq_out_bits {
4400 u8 reserved_at_8[0x18];
4404 u8 reserved_at_40[0x40];
4407 struct mlx5_ifc_modify_rq_in_bits {
4409 u8 reserved_at_10[0x10];
4411 u8 reserved_at_20[0x10];
4415 u8 reserved_at_44[0x4];
4418 u8 reserved_at_60[0x20];
4420 u8 modify_bitmask[0x40];
4422 u8 reserved_at_c0[0x40];
4424 struct mlx5_ifc_rqc_bits ctx;
4427 struct mlx5_ifc_modify_rmp_out_bits {
4429 u8 reserved_at_8[0x18];
4433 u8 reserved_at_40[0x40];
4436 struct mlx5_ifc_rmp_bitmask_bits {
4437 u8 reserved_at_0[0x20];
4439 u8 reserved_at_20[0x1f];
4443 struct mlx5_ifc_modify_rmp_in_bits {
4445 u8 reserved_at_10[0x10];
4447 u8 reserved_at_20[0x10];
4451 u8 reserved_at_44[0x4];
4454 u8 reserved_at_60[0x20];
4456 struct mlx5_ifc_rmp_bitmask_bits bitmask;
4458 u8 reserved_at_c0[0x40];
4460 struct mlx5_ifc_rmpc_bits ctx;
4463 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4465 u8 reserved_at_8[0x18];
4469 u8 reserved_at_40[0x40];
4472 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4473 u8 reserved_at_0[0x19];
4475 u8 change_event[0x1];
4477 u8 permanent_address[0x1];
4478 u8 addresses_list[0x1];
4480 u8 reserved_at_1f[0x1];
4483 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4485 u8 reserved_at_10[0x10];
4487 u8 reserved_at_20[0x10];
4490 u8 other_vport[0x1];
4491 u8 reserved_at_41[0xf];
4492 u8 vport_number[0x10];
4494 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4496 u8 reserved_at_80[0x780];
4498 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4501 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4503 u8 reserved_at_8[0x18];
4507 u8 reserved_at_40[0x40];
4510 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4512 u8 reserved_at_10[0x10];
4514 u8 reserved_at_20[0x10];
4517 u8 other_vport[0x1];
4518 u8 reserved_at_41[0xb];
4520 u8 vport_number[0x10];
4522 u8 reserved_at_60[0x20];
4524 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4527 struct mlx5_ifc_modify_cq_out_bits {
4529 u8 reserved_at_8[0x18];
4533 u8 reserved_at_40[0x40];
4537 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4538 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4541 struct mlx5_ifc_modify_cq_in_bits {
4543 u8 reserved_at_10[0x10];
4545 u8 reserved_at_20[0x10];
4548 u8 reserved_at_40[0x8];
4551 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4553 struct mlx5_ifc_cqc_bits cq_context;
4555 u8 reserved_at_280[0x600];
4560 struct mlx5_ifc_modify_cong_status_out_bits {
4562 u8 reserved_at_8[0x18];
4566 u8 reserved_at_40[0x40];
4569 struct mlx5_ifc_modify_cong_status_in_bits {
4571 u8 reserved_at_10[0x10];
4573 u8 reserved_at_20[0x10];
4576 u8 reserved_at_40[0x18];
4578 u8 cong_protocol[0x4];
4582 u8 reserved_at_62[0x1e];
4585 struct mlx5_ifc_modify_cong_params_out_bits {
4587 u8 reserved_at_8[0x18];
4591 u8 reserved_at_40[0x40];
4594 struct mlx5_ifc_modify_cong_params_in_bits {
4596 u8 reserved_at_10[0x10];
4598 u8 reserved_at_20[0x10];
4601 u8 reserved_at_40[0x1c];
4602 u8 cong_protocol[0x4];
4604 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4606 u8 reserved_at_80[0x80];
4608 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4611 struct mlx5_ifc_manage_pages_out_bits {
4613 u8 reserved_at_8[0x18];
4617 u8 output_num_entries[0x20];
4619 u8 reserved_at_60[0x20];
4625 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4626 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4627 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4630 struct mlx5_ifc_manage_pages_in_bits {
4632 u8 reserved_at_10[0x10];
4634 u8 reserved_at_20[0x10];
4637 u8 reserved_at_40[0x10];
4638 u8 function_id[0x10];
4640 u8 input_num_entries[0x20];
4645 struct mlx5_ifc_mad_ifc_out_bits {
4647 u8 reserved_at_8[0x18];
4651 u8 reserved_at_40[0x40];
4653 u8 response_mad_packet[256][0x8];
4656 struct mlx5_ifc_mad_ifc_in_bits {
4658 u8 reserved_at_10[0x10];
4660 u8 reserved_at_20[0x10];
4663 u8 remote_lid[0x10];
4664 u8 reserved_at_50[0x8];
4667 u8 reserved_at_60[0x20];
4672 struct mlx5_ifc_init_hca_out_bits {
4674 u8 reserved_at_8[0x18];
4678 u8 reserved_at_40[0x40];
4681 struct mlx5_ifc_init_hca_in_bits {
4683 u8 reserved_at_10[0x10];
4685 u8 reserved_at_20[0x10];
4688 u8 reserved_at_40[0x40];
4691 struct mlx5_ifc_init2rtr_qp_out_bits {
4693 u8 reserved_at_8[0x18];
4697 u8 reserved_at_40[0x40];
4700 struct mlx5_ifc_init2rtr_qp_in_bits {
4702 u8 reserved_at_10[0x10];
4704 u8 reserved_at_20[0x10];
4707 u8 reserved_at_40[0x8];
4710 u8 reserved_at_60[0x20];
4712 u8 opt_param_mask[0x20];
4714 u8 reserved_at_a0[0x20];
4716 struct mlx5_ifc_qpc_bits qpc;
4718 u8 reserved_at_800[0x80];
4721 struct mlx5_ifc_init2init_qp_out_bits {
4723 u8 reserved_at_8[0x18];
4727 u8 reserved_at_40[0x40];
4730 struct mlx5_ifc_init2init_qp_in_bits {
4732 u8 reserved_at_10[0x10];
4734 u8 reserved_at_20[0x10];
4737 u8 reserved_at_40[0x8];
4740 u8 reserved_at_60[0x20];
4742 u8 opt_param_mask[0x20];
4744 u8 reserved_at_a0[0x20];
4746 struct mlx5_ifc_qpc_bits qpc;
4748 u8 reserved_at_800[0x80];
4751 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4753 u8 reserved_at_8[0x18];
4757 u8 reserved_at_40[0x40];
4759 u8 packet_headers_log[128][0x8];
4761 u8 packet_syndrome[64][0x8];
4764 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4766 u8 reserved_at_10[0x10];
4768 u8 reserved_at_20[0x10];
4771 u8 reserved_at_40[0x40];
4774 struct mlx5_ifc_gen_eqe_in_bits {
4776 u8 reserved_at_10[0x10];
4778 u8 reserved_at_20[0x10];
4781 u8 reserved_at_40[0x18];
4784 u8 reserved_at_60[0x20];
4789 struct mlx5_ifc_gen_eq_out_bits {
4791 u8 reserved_at_8[0x18];
4795 u8 reserved_at_40[0x40];
4798 struct mlx5_ifc_enable_hca_out_bits {
4800 u8 reserved_at_8[0x18];
4804 u8 reserved_at_40[0x20];
4807 struct mlx5_ifc_enable_hca_in_bits {
4809 u8 reserved_at_10[0x10];
4811 u8 reserved_at_20[0x10];
4814 u8 reserved_at_40[0x10];
4815 u8 function_id[0x10];
4817 u8 reserved_at_60[0x20];
4820 struct mlx5_ifc_drain_dct_out_bits {
4822 u8 reserved_at_8[0x18];
4826 u8 reserved_at_40[0x40];
4829 struct mlx5_ifc_drain_dct_in_bits {
4831 u8 reserved_at_10[0x10];
4833 u8 reserved_at_20[0x10];
4836 u8 reserved_at_40[0x8];
4839 u8 reserved_at_60[0x20];
4842 struct mlx5_ifc_disable_hca_out_bits {
4844 u8 reserved_at_8[0x18];
4848 u8 reserved_at_40[0x20];
4851 struct mlx5_ifc_disable_hca_in_bits {
4853 u8 reserved_at_10[0x10];
4855 u8 reserved_at_20[0x10];
4858 u8 reserved_at_40[0x10];
4859 u8 function_id[0x10];
4861 u8 reserved_at_60[0x20];
4864 struct mlx5_ifc_detach_from_mcg_out_bits {
4866 u8 reserved_at_8[0x18];
4870 u8 reserved_at_40[0x40];
4873 struct mlx5_ifc_detach_from_mcg_in_bits {
4875 u8 reserved_at_10[0x10];
4877 u8 reserved_at_20[0x10];
4880 u8 reserved_at_40[0x8];
4883 u8 reserved_at_60[0x20];
4885 u8 multicast_gid[16][0x8];
4888 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4890 u8 reserved_at_8[0x18];
4894 u8 reserved_at_40[0x40];
4897 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4899 u8 reserved_at_10[0x10];
4901 u8 reserved_at_20[0x10];
4904 u8 reserved_at_40[0x8];
4907 u8 reserved_at_60[0x20];
4910 struct mlx5_ifc_destroy_tis_out_bits {
4912 u8 reserved_at_8[0x18];
4916 u8 reserved_at_40[0x40];
4919 struct mlx5_ifc_destroy_tis_in_bits {
4921 u8 reserved_at_10[0x10];
4923 u8 reserved_at_20[0x10];
4926 u8 reserved_at_40[0x8];
4929 u8 reserved_at_60[0x20];
4932 struct mlx5_ifc_destroy_tir_out_bits {
4934 u8 reserved_at_8[0x18];
4938 u8 reserved_at_40[0x40];
4941 struct mlx5_ifc_destroy_tir_in_bits {
4943 u8 reserved_at_10[0x10];
4945 u8 reserved_at_20[0x10];
4948 u8 reserved_at_40[0x8];
4951 u8 reserved_at_60[0x20];
4954 struct mlx5_ifc_destroy_srq_out_bits {
4956 u8 reserved_at_8[0x18];
4960 u8 reserved_at_40[0x40];
4963 struct mlx5_ifc_destroy_srq_in_bits {
4965 u8 reserved_at_10[0x10];
4967 u8 reserved_at_20[0x10];
4970 u8 reserved_at_40[0x8];
4973 u8 reserved_at_60[0x20];
4976 struct mlx5_ifc_destroy_sq_out_bits {
4978 u8 reserved_at_8[0x18];
4982 u8 reserved_at_40[0x40];
4985 struct mlx5_ifc_destroy_sq_in_bits {
4987 u8 reserved_at_10[0x10];
4989 u8 reserved_at_20[0x10];
4992 u8 reserved_at_40[0x8];
4995 u8 reserved_at_60[0x20];
4998 struct mlx5_ifc_destroy_rqt_out_bits {
5000 u8 reserved_at_8[0x18];
5004 u8 reserved_at_40[0x40];
5007 struct mlx5_ifc_destroy_rqt_in_bits {
5009 u8 reserved_at_10[0x10];
5011 u8 reserved_at_20[0x10];
5014 u8 reserved_at_40[0x8];
5017 u8 reserved_at_60[0x20];
5020 struct mlx5_ifc_destroy_rq_out_bits {
5022 u8 reserved_at_8[0x18];
5026 u8 reserved_at_40[0x40];
5029 struct mlx5_ifc_destroy_rq_in_bits {
5031 u8 reserved_at_10[0x10];
5033 u8 reserved_at_20[0x10];
5036 u8 reserved_at_40[0x8];
5039 u8 reserved_at_60[0x20];
5042 struct mlx5_ifc_destroy_rmp_out_bits {
5044 u8 reserved_at_8[0x18];
5048 u8 reserved_at_40[0x40];
5051 struct mlx5_ifc_destroy_rmp_in_bits {
5053 u8 reserved_at_10[0x10];
5055 u8 reserved_at_20[0x10];
5058 u8 reserved_at_40[0x8];
5061 u8 reserved_at_60[0x20];
5064 struct mlx5_ifc_destroy_qp_out_bits {
5066 u8 reserved_at_8[0x18];
5070 u8 reserved_at_40[0x40];
5073 struct mlx5_ifc_destroy_qp_in_bits {
5075 u8 reserved_at_10[0x10];
5077 u8 reserved_at_20[0x10];
5080 u8 reserved_at_40[0x8];
5083 u8 reserved_at_60[0x20];
5086 struct mlx5_ifc_destroy_psv_out_bits {
5088 u8 reserved_at_8[0x18];
5092 u8 reserved_at_40[0x40];
5095 struct mlx5_ifc_destroy_psv_in_bits {
5097 u8 reserved_at_10[0x10];
5099 u8 reserved_at_20[0x10];
5102 u8 reserved_at_40[0x8];
5105 u8 reserved_at_60[0x20];
5108 struct mlx5_ifc_destroy_mkey_out_bits {
5110 u8 reserved_at_8[0x18];
5114 u8 reserved_at_40[0x40];
5117 struct mlx5_ifc_destroy_mkey_in_bits {
5119 u8 reserved_at_10[0x10];
5121 u8 reserved_at_20[0x10];
5124 u8 reserved_at_40[0x8];
5125 u8 mkey_index[0x18];
5127 u8 reserved_at_60[0x20];
5130 struct mlx5_ifc_destroy_flow_table_out_bits {
5132 u8 reserved_at_8[0x18];
5136 u8 reserved_at_40[0x40];
5139 struct mlx5_ifc_destroy_flow_table_in_bits {
5141 u8 reserved_at_10[0x10];
5143 u8 reserved_at_20[0x10];
5146 u8 reserved_at_40[0x40];
5149 u8 reserved_at_88[0x18];
5151 u8 reserved_at_a0[0x8];
5154 u8 reserved_at_c0[0x140];
5157 struct mlx5_ifc_destroy_flow_group_out_bits {
5159 u8 reserved_at_8[0x18];
5163 u8 reserved_at_40[0x40];
5166 struct mlx5_ifc_destroy_flow_group_in_bits {
5168 u8 reserved_at_10[0x10];
5170 u8 reserved_at_20[0x10];
5173 u8 reserved_at_40[0x40];
5176 u8 reserved_at_88[0x18];
5178 u8 reserved_at_a0[0x8];
5183 u8 reserved_at_e0[0x120];
5186 struct mlx5_ifc_destroy_eq_out_bits {
5188 u8 reserved_at_8[0x18];
5192 u8 reserved_at_40[0x40];
5195 struct mlx5_ifc_destroy_eq_in_bits {
5197 u8 reserved_at_10[0x10];
5199 u8 reserved_at_20[0x10];
5202 u8 reserved_at_40[0x18];
5205 u8 reserved_at_60[0x20];
5208 struct mlx5_ifc_destroy_dct_out_bits {
5210 u8 reserved_at_8[0x18];
5214 u8 reserved_at_40[0x40];
5217 struct mlx5_ifc_destroy_dct_in_bits {
5219 u8 reserved_at_10[0x10];
5221 u8 reserved_at_20[0x10];
5224 u8 reserved_at_40[0x8];
5227 u8 reserved_at_60[0x20];
5230 struct mlx5_ifc_destroy_cq_out_bits {
5232 u8 reserved_at_8[0x18];
5236 u8 reserved_at_40[0x40];
5239 struct mlx5_ifc_destroy_cq_in_bits {
5241 u8 reserved_at_10[0x10];
5243 u8 reserved_at_20[0x10];
5246 u8 reserved_at_40[0x8];
5249 u8 reserved_at_60[0x20];
5252 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5254 u8 reserved_at_8[0x18];
5258 u8 reserved_at_40[0x40];
5261 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5263 u8 reserved_at_10[0x10];
5265 u8 reserved_at_20[0x10];
5268 u8 reserved_at_40[0x20];
5270 u8 reserved_at_60[0x10];
5271 u8 vxlan_udp_port[0x10];
5274 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5276 u8 reserved_at_8[0x18];
5280 u8 reserved_at_40[0x40];
5283 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5285 u8 reserved_at_10[0x10];
5287 u8 reserved_at_20[0x10];
5290 u8 reserved_at_40[0x60];
5292 u8 reserved_at_a0[0x8];
5293 u8 table_index[0x18];
5295 u8 reserved_at_c0[0x140];
5298 struct mlx5_ifc_delete_fte_out_bits {
5300 u8 reserved_at_8[0x18];
5304 u8 reserved_at_40[0x40];
5307 struct mlx5_ifc_delete_fte_in_bits {
5309 u8 reserved_at_10[0x10];
5311 u8 reserved_at_20[0x10];
5314 u8 reserved_at_40[0x40];
5317 u8 reserved_at_88[0x18];
5319 u8 reserved_at_a0[0x8];
5322 u8 reserved_at_c0[0x40];
5324 u8 flow_index[0x20];
5326 u8 reserved_at_120[0xe0];
5329 struct mlx5_ifc_dealloc_xrcd_out_bits {
5331 u8 reserved_at_8[0x18];
5335 u8 reserved_at_40[0x40];
5338 struct mlx5_ifc_dealloc_xrcd_in_bits {
5340 u8 reserved_at_10[0x10];
5342 u8 reserved_at_20[0x10];
5345 u8 reserved_at_40[0x8];
5348 u8 reserved_at_60[0x20];
5351 struct mlx5_ifc_dealloc_uar_out_bits {
5353 u8 reserved_at_8[0x18];
5357 u8 reserved_at_40[0x40];
5360 struct mlx5_ifc_dealloc_uar_in_bits {
5362 u8 reserved_at_10[0x10];
5364 u8 reserved_at_20[0x10];
5367 u8 reserved_at_40[0x8];
5370 u8 reserved_at_60[0x20];
5373 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5375 u8 reserved_at_8[0x18];
5379 u8 reserved_at_40[0x40];
5382 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5384 u8 reserved_at_10[0x10];
5386 u8 reserved_at_20[0x10];
5389 u8 reserved_at_40[0x8];
5390 u8 transport_domain[0x18];
5392 u8 reserved_at_60[0x20];
5395 struct mlx5_ifc_dealloc_q_counter_out_bits {
5397 u8 reserved_at_8[0x18];
5401 u8 reserved_at_40[0x40];
5404 struct mlx5_ifc_dealloc_q_counter_in_bits {
5406 u8 reserved_at_10[0x10];
5408 u8 reserved_at_20[0x10];
5411 u8 reserved_at_40[0x18];
5412 u8 counter_set_id[0x8];
5414 u8 reserved_at_60[0x20];
5417 struct mlx5_ifc_dealloc_pd_out_bits {
5419 u8 reserved_at_8[0x18];
5423 u8 reserved_at_40[0x40];
5426 struct mlx5_ifc_dealloc_pd_in_bits {
5428 u8 reserved_at_10[0x10];
5430 u8 reserved_at_20[0x10];
5433 u8 reserved_at_40[0x8];
5436 u8 reserved_at_60[0x20];
5439 struct mlx5_ifc_create_xrc_srq_out_bits {
5441 u8 reserved_at_8[0x18];
5445 u8 reserved_at_40[0x8];
5448 u8 reserved_at_60[0x20];
5451 struct mlx5_ifc_create_xrc_srq_in_bits {
5453 u8 reserved_at_10[0x10];
5455 u8 reserved_at_20[0x10];
5458 u8 reserved_at_40[0x40];
5460 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5462 u8 reserved_at_280[0x600];
5467 struct mlx5_ifc_create_tis_out_bits {
5469 u8 reserved_at_8[0x18];
5473 u8 reserved_at_40[0x8];
5476 u8 reserved_at_60[0x20];
5479 struct mlx5_ifc_create_tis_in_bits {
5481 u8 reserved_at_10[0x10];
5483 u8 reserved_at_20[0x10];
5486 u8 reserved_at_40[0xc0];
5488 struct mlx5_ifc_tisc_bits ctx;
5491 struct mlx5_ifc_create_tir_out_bits {
5493 u8 reserved_at_8[0x18];
5497 u8 reserved_at_40[0x8];
5500 u8 reserved_at_60[0x20];
5503 struct mlx5_ifc_create_tir_in_bits {
5505 u8 reserved_at_10[0x10];
5507 u8 reserved_at_20[0x10];
5510 u8 reserved_at_40[0xc0];
5512 struct mlx5_ifc_tirc_bits ctx;
5515 struct mlx5_ifc_create_srq_out_bits {
5517 u8 reserved_at_8[0x18];
5521 u8 reserved_at_40[0x8];
5524 u8 reserved_at_60[0x20];
5527 struct mlx5_ifc_create_srq_in_bits {
5529 u8 reserved_at_10[0x10];
5531 u8 reserved_at_20[0x10];
5534 u8 reserved_at_40[0x40];
5536 struct mlx5_ifc_srqc_bits srq_context_entry;
5538 u8 reserved_at_280[0x600];
5543 struct mlx5_ifc_create_sq_out_bits {
5545 u8 reserved_at_8[0x18];
5549 u8 reserved_at_40[0x8];
5552 u8 reserved_at_60[0x20];
5555 struct mlx5_ifc_create_sq_in_bits {
5557 u8 reserved_at_10[0x10];
5559 u8 reserved_at_20[0x10];
5562 u8 reserved_at_40[0xc0];
5564 struct mlx5_ifc_sqc_bits ctx;
5567 struct mlx5_ifc_create_rqt_out_bits {
5569 u8 reserved_at_8[0x18];
5573 u8 reserved_at_40[0x8];
5576 u8 reserved_at_60[0x20];
5579 struct mlx5_ifc_create_rqt_in_bits {
5581 u8 reserved_at_10[0x10];
5583 u8 reserved_at_20[0x10];
5586 u8 reserved_at_40[0xc0];
5588 struct mlx5_ifc_rqtc_bits rqt_context;
5591 struct mlx5_ifc_create_rq_out_bits {
5593 u8 reserved_at_8[0x18];
5597 u8 reserved_at_40[0x8];
5600 u8 reserved_at_60[0x20];
5603 struct mlx5_ifc_create_rq_in_bits {
5605 u8 reserved_at_10[0x10];
5607 u8 reserved_at_20[0x10];
5610 u8 reserved_at_40[0xc0];
5612 struct mlx5_ifc_rqc_bits ctx;
5615 struct mlx5_ifc_create_rmp_out_bits {
5617 u8 reserved_at_8[0x18];
5621 u8 reserved_at_40[0x8];
5624 u8 reserved_at_60[0x20];
5627 struct mlx5_ifc_create_rmp_in_bits {
5629 u8 reserved_at_10[0x10];
5631 u8 reserved_at_20[0x10];
5634 u8 reserved_at_40[0xc0];
5636 struct mlx5_ifc_rmpc_bits ctx;
5639 struct mlx5_ifc_create_qp_out_bits {
5641 u8 reserved_at_8[0x18];
5645 u8 reserved_at_40[0x8];
5648 u8 reserved_at_60[0x20];
5651 struct mlx5_ifc_create_qp_in_bits {
5653 u8 reserved_at_10[0x10];
5655 u8 reserved_at_20[0x10];
5658 u8 reserved_at_40[0x40];
5660 u8 opt_param_mask[0x20];
5662 u8 reserved_at_a0[0x20];
5664 struct mlx5_ifc_qpc_bits qpc;
5666 u8 reserved_at_800[0x80];
5671 struct mlx5_ifc_create_psv_out_bits {
5673 u8 reserved_at_8[0x18];
5677 u8 reserved_at_40[0x40];
5679 u8 reserved_at_80[0x8];
5680 u8 psv0_index[0x18];
5682 u8 reserved_at_a0[0x8];
5683 u8 psv1_index[0x18];
5685 u8 reserved_at_c0[0x8];
5686 u8 psv2_index[0x18];
5688 u8 reserved_at_e0[0x8];
5689 u8 psv3_index[0x18];
5692 struct mlx5_ifc_create_psv_in_bits {
5694 u8 reserved_at_10[0x10];
5696 u8 reserved_at_20[0x10];
5700 u8 reserved_at_44[0x4];
5703 u8 reserved_at_60[0x20];
5706 struct mlx5_ifc_create_mkey_out_bits {
5708 u8 reserved_at_8[0x18];
5712 u8 reserved_at_40[0x8];
5713 u8 mkey_index[0x18];
5715 u8 reserved_at_60[0x20];
5718 struct mlx5_ifc_create_mkey_in_bits {
5720 u8 reserved_at_10[0x10];
5722 u8 reserved_at_20[0x10];
5725 u8 reserved_at_40[0x20];
5728 u8 reserved_at_61[0x1f];
5730 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5732 u8 reserved_at_280[0x80];
5734 u8 translations_octword_actual_size[0x20];
5736 u8 reserved_at_320[0x560];
5738 u8 klm_pas_mtt[0][0x20];
5741 struct mlx5_ifc_create_flow_table_out_bits {
5743 u8 reserved_at_8[0x18];
5747 u8 reserved_at_40[0x8];
5750 u8 reserved_at_60[0x20];
5753 struct mlx5_ifc_create_flow_table_in_bits {
5755 u8 reserved_at_10[0x10];
5757 u8 reserved_at_20[0x10];
5760 u8 reserved_at_40[0x40];
5763 u8 reserved_at_88[0x18];
5765 u8 reserved_at_a0[0x20];
5767 u8 reserved_at_c0[0x4];
5768 u8 table_miss_mode[0x4];
5770 u8 reserved_at_d0[0x8];
5773 u8 reserved_at_e0[0x8];
5774 u8 table_miss_id[0x18];
5776 u8 reserved_at_100[0x100];
5779 struct mlx5_ifc_create_flow_group_out_bits {
5781 u8 reserved_at_8[0x18];
5785 u8 reserved_at_40[0x8];
5788 u8 reserved_at_60[0x20];
5792 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5793 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5794 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5797 struct mlx5_ifc_create_flow_group_in_bits {
5799 u8 reserved_at_10[0x10];
5801 u8 reserved_at_20[0x10];
5804 u8 reserved_at_40[0x40];
5807 u8 reserved_at_88[0x18];
5809 u8 reserved_at_a0[0x8];
5812 u8 reserved_at_c0[0x20];
5814 u8 start_flow_index[0x20];
5816 u8 reserved_at_100[0x20];
5818 u8 end_flow_index[0x20];
5820 u8 reserved_at_140[0xa0];
5822 u8 reserved_at_1e0[0x18];
5823 u8 match_criteria_enable[0x8];
5825 struct mlx5_ifc_fte_match_param_bits match_criteria;
5827 u8 reserved_at_1200[0xe00];
5830 struct mlx5_ifc_create_eq_out_bits {
5832 u8 reserved_at_8[0x18];
5836 u8 reserved_at_40[0x18];
5839 u8 reserved_at_60[0x20];
5842 struct mlx5_ifc_create_eq_in_bits {
5844 u8 reserved_at_10[0x10];
5846 u8 reserved_at_20[0x10];
5849 u8 reserved_at_40[0x40];
5851 struct mlx5_ifc_eqc_bits eq_context_entry;
5853 u8 reserved_at_280[0x40];
5855 u8 event_bitmask[0x40];
5857 u8 reserved_at_300[0x580];
5862 struct mlx5_ifc_create_dct_out_bits {
5864 u8 reserved_at_8[0x18];
5868 u8 reserved_at_40[0x8];
5871 u8 reserved_at_60[0x20];
5874 struct mlx5_ifc_create_dct_in_bits {
5876 u8 reserved_at_10[0x10];
5878 u8 reserved_at_20[0x10];
5881 u8 reserved_at_40[0x40];
5883 struct mlx5_ifc_dctc_bits dct_context_entry;
5885 u8 reserved_at_280[0x180];
5888 struct mlx5_ifc_create_cq_out_bits {
5890 u8 reserved_at_8[0x18];
5894 u8 reserved_at_40[0x8];
5897 u8 reserved_at_60[0x20];
5900 struct mlx5_ifc_create_cq_in_bits {
5902 u8 reserved_at_10[0x10];
5904 u8 reserved_at_20[0x10];
5907 u8 reserved_at_40[0x40];
5909 struct mlx5_ifc_cqc_bits cq_context;
5911 u8 reserved_at_280[0x600];
5916 struct mlx5_ifc_config_int_moderation_out_bits {
5918 u8 reserved_at_8[0x18];
5922 u8 reserved_at_40[0x4];
5924 u8 int_vector[0x10];
5926 u8 reserved_at_60[0x20];
5930 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5931 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5934 struct mlx5_ifc_config_int_moderation_in_bits {
5936 u8 reserved_at_10[0x10];
5938 u8 reserved_at_20[0x10];
5941 u8 reserved_at_40[0x4];
5943 u8 int_vector[0x10];
5945 u8 reserved_at_60[0x20];
5948 struct mlx5_ifc_attach_to_mcg_out_bits {
5950 u8 reserved_at_8[0x18];
5954 u8 reserved_at_40[0x40];
5957 struct mlx5_ifc_attach_to_mcg_in_bits {
5959 u8 reserved_at_10[0x10];
5961 u8 reserved_at_20[0x10];
5964 u8 reserved_at_40[0x8];
5967 u8 reserved_at_60[0x20];
5969 u8 multicast_gid[16][0x8];
5972 struct mlx5_ifc_arm_xrc_srq_out_bits {
5974 u8 reserved_at_8[0x18];
5978 u8 reserved_at_40[0x40];
5982 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5985 struct mlx5_ifc_arm_xrc_srq_in_bits {
5987 u8 reserved_at_10[0x10];
5989 u8 reserved_at_20[0x10];
5992 u8 reserved_at_40[0x8];
5995 u8 reserved_at_60[0x10];
5999 struct mlx5_ifc_arm_rq_out_bits {
6001 u8 reserved_at_8[0x18];
6005 u8 reserved_at_40[0x40];
6009 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
6012 struct mlx5_ifc_arm_rq_in_bits {
6014 u8 reserved_at_10[0x10];
6016 u8 reserved_at_20[0x10];
6019 u8 reserved_at_40[0x8];
6020 u8 srq_number[0x18];
6022 u8 reserved_at_60[0x10];
6026 struct mlx5_ifc_arm_dct_out_bits {
6028 u8 reserved_at_8[0x18];
6032 u8 reserved_at_40[0x40];
6035 struct mlx5_ifc_arm_dct_in_bits {
6037 u8 reserved_at_10[0x10];
6039 u8 reserved_at_20[0x10];
6042 u8 reserved_at_40[0x8];
6043 u8 dct_number[0x18];
6045 u8 reserved_at_60[0x20];
6048 struct mlx5_ifc_alloc_xrcd_out_bits {
6050 u8 reserved_at_8[0x18];
6054 u8 reserved_at_40[0x8];
6057 u8 reserved_at_60[0x20];
6060 struct mlx5_ifc_alloc_xrcd_in_bits {
6062 u8 reserved_at_10[0x10];
6064 u8 reserved_at_20[0x10];
6067 u8 reserved_at_40[0x40];
6070 struct mlx5_ifc_alloc_uar_out_bits {
6072 u8 reserved_at_8[0x18];
6076 u8 reserved_at_40[0x8];
6079 u8 reserved_at_60[0x20];
6082 struct mlx5_ifc_alloc_uar_in_bits {
6084 u8 reserved_at_10[0x10];
6086 u8 reserved_at_20[0x10];
6089 u8 reserved_at_40[0x40];
6092 struct mlx5_ifc_alloc_transport_domain_out_bits {
6094 u8 reserved_at_8[0x18];
6098 u8 reserved_at_40[0x8];
6099 u8 transport_domain[0x18];
6101 u8 reserved_at_60[0x20];
6104 struct mlx5_ifc_alloc_transport_domain_in_bits {
6106 u8 reserved_at_10[0x10];
6108 u8 reserved_at_20[0x10];
6111 u8 reserved_at_40[0x40];
6114 struct mlx5_ifc_alloc_q_counter_out_bits {
6116 u8 reserved_at_8[0x18];
6120 u8 reserved_at_40[0x18];
6121 u8 counter_set_id[0x8];
6123 u8 reserved_at_60[0x20];
6126 struct mlx5_ifc_alloc_q_counter_in_bits {
6128 u8 reserved_at_10[0x10];
6130 u8 reserved_at_20[0x10];
6133 u8 reserved_at_40[0x40];
6136 struct mlx5_ifc_alloc_pd_out_bits {
6138 u8 reserved_at_8[0x18];
6142 u8 reserved_at_40[0x8];
6145 u8 reserved_at_60[0x20];
6148 struct mlx5_ifc_alloc_pd_in_bits {
6150 u8 reserved_at_10[0x10];
6152 u8 reserved_at_20[0x10];
6155 u8 reserved_at_40[0x40];
6158 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6160 u8 reserved_at_8[0x18];
6164 u8 reserved_at_40[0x40];
6167 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6169 u8 reserved_at_10[0x10];
6171 u8 reserved_at_20[0x10];
6174 u8 reserved_at_40[0x20];
6176 u8 reserved_at_60[0x10];
6177 u8 vxlan_udp_port[0x10];
6180 struct mlx5_ifc_access_register_out_bits {
6182 u8 reserved_at_8[0x18];
6186 u8 reserved_at_40[0x40];
6188 u8 register_data[0][0x20];
6192 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6193 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6196 struct mlx5_ifc_access_register_in_bits {
6198 u8 reserved_at_10[0x10];
6200 u8 reserved_at_20[0x10];
6203 u8 reserved_at_40[0x10];
6204 u8 register_id[0x10];
6208 u8 register_data[0][0x20];
6211 struct mlx5_ifc_sltp_reg_bits {
6216 u8 reserved_at_12[0x2];
6218 u8 reserved_at_18[0x8];
6220 u8 reserved_at_20[0x20];
6222 u8 reserved_at_40[0x7];
6228 u8 reserved_at_60[0xc];
6229 u8 ob_preemp_mode[0x4];
6233 u8 reserved_at_80[0x20];
6236 struct mlx5_ifc_slrg_reg_bits {
6241 u8 reserved_at_12[0x2];
6243 u8 reserved_at_18[0x8];
6245 u8 time_to_link_up[0x10];
6246 u8 reserved_at_30[0xc];
6247 u8 grade_lane_speed[0x4];
6249 u8 grade_version[0x8];
6252 u8 reserved_at_60[0x4];
6253 u8 height_grade_type[0x4];
6254 u8 height_grade[0x18];
6259 u8 reserved_at_a0[0x10];
6260 u8 height_sigma[0x10];
6262 u8 reserved_at_c0[0x20];
6264 u8 reserved_at_e0[0x4];
6265 u8 phase_grade_type[0x4];
6266 u8 phase_grade[0x18];
6268 u8 reserved_at_100[0x8];
6269 u8 phase_eo_pos[0x8];
6270 u8 reserved_at_110[0x8];
6271 u8 phase_eo_neg[0x8];
6273 u8 ffe_set_tested[0x10];
6274 u8 test_errors_per_lane[0x10];
6277 struct mlx5_ifc_pvlc_reg_bits {
6278 u8 reserved_at_0[0x8];
6280 u8 reserved_at_10[0x10];
6282 u8 reserved_at_20[0x1c];
6285 u8 reserved_at_40[0x1c];
6288 u8 reserved_at_60[0x1c];
6289 u8 vl_operational[0x4];
6292 struct mlx5_ifc_pude_reg_bits {
6295 u8 reserved_at_10[0x4];
6296 u8 admin_status[0x4];
6297 u8 reserved_at_18[0x4];
6298 u8 oper_status[0x4];
6300 u8 reserved_at_20[0x60];
6303 struct mlx5_ifc_ptys_reg_bits {
6304 u8 reserved_at_0[0x8];
6306 u8 reserved_at_10[0xd];
6309 u8 reserved_at_20[0x40];
6311 u8 eth_proto_capability[0x20];
6313 u8 ib_link_width_capability[0x10];
6314 u8 ib_proto_capability[0x10];
6316 u8 reserved_at_a0[0x20];
6318 u8 eth_proto_admin[0x20];
6320 u8 ib_link_width_admin[0x10];
6321 u8 ib_proto_admin[0x10];
6323 u8 reserved_at_100[0x20];
6325 u8 eth_proto_oper[0x20];
6327 u8 ib_link_width_oper[0x10];
6328 u8 ib_proto_oper[0x10];
6330 u8 reserved_at_160[0x20];
6332 u8 eth_proto_lp_advertise[0x20];
6334 u8 reserved_at_1a0[0x60];
6337 struct mlx5_ifc_ptas_reg_bits {
6338 u8 reserved_at_0[0x20];
6340 u8 algorithm_options[0x10];
6341 u8 reserved_at_30[0x4];
6342 u8 repetitions_mode[0x4];
6343 u8 num_of_repetitions[0x8];
6345 u8 grade_version[0x8];
6346 u8 height_grade_type[0x4];
6347 u8 phase_grade_type[0x4];
6348 u8 height_grade_weight[0x8];
6349 u8 phase_grade_weight[0x8];
6351 u8 gisim_measure_bits[0x10];
6352 u8 adaptive_tap_measure_bits[0x10];
6354 u8 ber_bath_high_error_threshold[0x10];
6355 u8 ber_bath_mid_error_threshold[0x10];
6357 u8 ber_bath_low_error_threshold[0x10];
6358 u8 one_ratio_high_threshold[0x10];
6360 u8 one_ratio_high_mid_threshold[0x10];
6361 u8 one_ratio_low_mid_threshold[0x10];
6363 u8 one_ratio_low_threshold[0x10];
6364 u8 ndeo_error_threshold[0x10];
6366 u8 mixer_offset_step_size[0x10];
6367 u8 reserved_at_110[0x8];
6368 u8 mix90_phase_for_voltage_bath[0x8];
6370 u8 mixer_offset_start[0x10];
6371 u8 mixer_offset_end[0x10];
6373 u8 reserved_at_140[0x15];
6374 u8 ber_test_time[0xb];
6377 struct mlx5_ifc_pspa_reg_bits {
6381 u8 reserved_at_18[0x8];
6383 u8 reserved_at_20[0x20];
6386 struct mlx5_ifc_pqdr_reg_bits {
6387 u8 reserved_at_0[0x8];
6389 u8 reserved_at_10[0x5];
6391 u8 reserved_at_18[0x6];
6394 u8 reserved_at_20[0x20];
6396 u8 reserved_at_40[0x10];
6397 u8 min_threshold[0x10];
6399 u8 reserved_at_60[0x10];
6400 u8 max_threshold[0x10];
6402 u8 reserved_at_80[0x10];
6403 u8 mark_probability_denominator[0x10];
6405 u8 reserved_at_a0[0x60];
6408 struct mlx5_ifc_ppsc_reg_bits {
6409 u8 reserved_at_0[0x8];
6411 u8 reserved_at_10[0x10];
6413 u8 reserved_at_20[0x60];
6415 u8 reserved_at_80[0x1c];
6418 u8 reserved_at_a0[0x1c];
6419 u8 wrps_status[0x4];
6421 u8 reserved_at_c0[0x8];
6422 u8 up_threshold[0x8];
6423 u8 reserved_at_d0[0x8];
6424 u8 down_threshold[0x8];
6426 u8 reserved_at_e0[0x20];
6428 u8 reserved_at_100[0x1c];
6431 u8 reserved_at_120[0x1c];
6432 u8 srps_status[0x4];
6434 u8 reserved_at_140[0x40];
6437 struct mlx5_ifc_pplr_reg_bits {
6438 u8 reserved_at_0[0x8];
6440 u8 reserved_at_10[0x10];
6442 u8 reserved_at_20[0x8];
6444 u8 reserved_at_30[0x8];
6448 struct mlx5_ifc_pplm_reg_bits {
6449 u8 reserved_at_0[0x8];
6451 u8 reserved_at_10[0x10];
6453 u8 reserved_at_20[0x20];
6455 u8 port_profile_mode[0x8];
6456 u8 static_port_profile[0x8];
6457 u8 active_port_profile[0x8];
6458 u8 reserved_at_58[0x8];
6460 u8 retransmission_active[0x8];
6461 u8 fec_mode_active[0x18];
6463 u8 reserved_at_80[0x20];
6466 struct mlx5_ifc_ppcnt_reg_bits {
6470 u8 reserved_at_12[0x8];
6474 u8 reserved_at_21[0x1c];
6477 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6480 struct mlx5_ifc_ppad_reg_bits {
6481 u8 reserved_at_0[0x3];
6483 u8 reserved_at_4[0x4];
6489 u8 reserved_at_40[0x40];
6492 struct mlx5_ifc_pmtu_reg_bits {
6493 u8 reserved_at_0[0x8];
6495 u8 reserved_at_10[0x10];
6498 u8 reserved_at_30[0x10];
6501 u8 reserved_at_50[0x10];
6504 u8 reserved_at_70[0x10];
6507 struct mlx5_ifc_pmpr_reg_bits {
6508 u8 reserved_at_0[0x8];
6510 u8 reserved_at_10[0x10];
6512 u8 reserved_at_20[0x18];
6513 u8 attenuation_5g[0x8];
6515 u8 reserved_at_40[0x18];
6516 u8 attenuation_7g[0x8];
6518 u8 reserved_at_60[0x18];
6519 u8 attenuation_12g[0x8];
6522 struct mlx5_ifc_pmpe_reg_bits {
6523 u8 reserved_at_0[0x8];
6525 u8 reserved_at_10[0xc];
6526 u8 module_status[0x4];
6528 u8 reserved_at_20[0x60];
6531 struct mlx5_ifc_pmpc_reg_bits {
6532 u8 module_state_updated[32][0x8];
6535 struct mlx5_ifc_pmlpn_reg_bits {
6536 u8 reserved_at_0[0x4];
6537 u8 mlpn_status[0x4];
6539 u8 reserved_at_10[0x10];
6542 u8 reserved_at_21[0x1f];
6545 struct mlx5_ifc_pmlp_reg_bits {
6547 u8 reserved_at_1[0x7];
6549 u8 reserved_at_10[0x8];
6552 u8 lane0_module_mapping[0x20];
6554 u8 lane1_module_mapping[0x20];
6556 u8 lane2_module_mapping[0x20];
6558 u8 lane3_module_mapping[0x20];
6560 u8 reserved_at_a0[0x160];
6563 struct mlx5_ifc_pmaos_reg_bits {
6564 u8 reserved_at_0[0x8];
6566 u8 reserved_at_10[0x4];
6567 u8 admin_status[0x4];
6568 u8 reserved_at_18[0x4];
6569 u8 oper_status[0x4];
6573 u8 reserved_at_22[0x1c];
6576 u8 reserved_at_40[0x40];
6579 struct mlx5_ifc_plpc_reg_bits {
6580 u8 reserved_at_0[0x4];
6582 u8 reserved_at_10[0x4];
6584 u8 reserved_at_18[0x8];
6586 u8 reserved_at_20[0x10];
6587 u8 lane_speed[0x10];
6589 u8 reserved_at_40[0x17];
6591 u8 fec_mode_policy[0x8];
6593 u8 retransmission_capability[0x8];
6594 u8 fec_mode_capability[0x18];
6596 u8 retransmission_support_admin[0x8];
6597 u8 fec_mode_support_admin[0x18];
6599 u8 retransmission_request_admin[0x8];
6600 u8 fec_mode_request_admin[0x18];
6602 u8 reserved_at_c0[0x80];
6605 struct mlx5_ifc_plib_reg_bits {
6606 u8 reserved_at_0[0x8];
6608 u8 reserved_at_10[0x8];
6611 u8 reserved_at_20[0x60];
6614 struct mlx5_ifc_plbf_reg_bits {
6615 u8 reserved_at_0[0x8];
6617 u8 reserved_at_10[0xd];
6620 u8 reserved_at_20[0x20];
6623 struct mlx5_ifc_pipg_reg_bits {
6624 u8 reserved_at_0[0x8];
6626 u8 reserved_at_10[0x10];
6629 u8 reserved_at_21[0x19];
6631 u8 reserved_at_3e[0x2];
6634 struct mlx5_ifc_pifr_reg_bits {
6635 u8 reserved_at_0[0x8];
6637 u8 reserved_at_10[0x10];
6639 u8 reserved_at_20[0xe0];
6641 u8 port_filter[8][0x20];
6643 u8 port_filter_update_en[8][0x20];
6646 struct mlx5_ifc_pfcc_reg_bits {
6647 u8 reserved_at_0[0x8];
6649 u8 reserved_at_10[0x10];
6652 u8 reserved_at_24[0x4];
6653 u8 prio_mask_tx[0x8];
6654 u8 reserved_at_30[0x8];
6655 u8 prio_mask_rx[0x8];
6659 u8 reserved_at_42[0x6];
6661 u8 reserved_at_50[0x10];
6665 u8 reserved_at_62[0x6];
6667 u8 reserved_at_70[0x10];
6669 u8 reserved_at_80[0x80];
6672 struct mlx5_ifc_pelc_reg_bits {
6674 u8 reserved_at_4[0x4];
6676 u8 reserved_at_10[0x10];
6679 u8 op_capability[0x8];
6685 u8 capability[0x40];
6691 u8 reserved_at_140[0x80];
6694 struct mlx5_ifc_peir_reg_bits {
6695 u8 reserved_at_0[0x8];
6697 u8 reserved_at_10[0x10];
6699 u8 reserved_at_20[0xc];
6700 u8 error_count[0x4];
6701 u8 reserved_at_30[0x10];
6703 u8 reserved_at_40[0xc];
6705 u8 reserved_at_50[0x8];
6709 struct mlx5_ifc_pcap_reg_bits {
6710 u8 reserved_at_0[0x8];
6712 u8 reserved_at_10[0x10];
6714 u8 port_capability_mask[4][0x20];
6717 struct mlx5_ifc_paos_reg_bits {
6720 u8 reserved_at_10[0x4];
6721 u8 admin_status[0x4];
6722 u8 reserved_at_18[0x4];
6723 u8 oper_status[0x4];
6727 u8 reserved_at_22[0x1c];
6730 u8 reserved_at_40[0x40];
6733 struct mlx5_ifc_pamp_reg_bits {
6734 u8 reserved_at_0[0x8];
6735 u8 opamp_group[0x8];
6736 u8 reserved_at_10[0xc];
6737 u8 opamp_group_type[0x4];
6739 u8 start_index[0x10];
6740 u8 reserved_at_30[0x4];
6741 u8 num_of_indices[0xc];
6743 u8 index_data[18][0x10];
6746 struct mlx5_ifc_lane_2_module_mapping_bits {
6747 u8 reserved_at_0[0x6];
6749 u8 reserved_at_8[0x6];
6751 u8 reserved_at_10[0x8];
6755 struct mlx5_ifc_bufferx_reg_bits {
6756 u8 reserved_at_0[0x6];
6759 u8 reserved_at_8[0xc];
6762 u8 xoff_threshold[0x10];
6763 u8 xon_threshold[0x10];
6766 struct mlx5_ifc_set_node_in_bits {
6767 u8 node_description[64][0x8];
6770 struct mlx5_ifc_register_power_settings_bits {
6771 u8 reserved_at_0[0x18];
6772 u8 power_settings_level[0x8];
6774 u8 reserved_at_20[0x60];
6777 struct mlx5_ifc_register_host_endianness_bits {
6779 u8 reserved_at_1[0x1f];
6781 u8 reserved_at_20[0x60];
6784 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6785 u8 reserved_at_0[0x20];
6789 u8 addressh_63_32[0x20];
6791 u8 addressl_31_0[0x20];
6794 struct mlx5_ifc_ud_adrs_vector_bits {
6798 u8 reserved_at_41[0x7];
6799 u8 destination_qp_dct[0x18];
6801 u8 static_rate[0x4];
6802 u8 sl_eth_prio[0x4];
6805 u8 rlid_udp_sport[0x10];
6807 u8 reserved_at_80[0x20];
6809 u8 rmac_47_16[0x20];
6815 u8 reserved_at_e0[0x1];
6817 u8 reserved_at_e2[0x2];
6818 u8 src_addr_index[0x8];
6819 u8 flow_label[0x14];
6821 u8 rgid_rip[16][0x8];
6824 struct mlx5_ifc_pages_req_event_bits {
6825 u8 reserved_at_0[0x10];
6826 u8 function_id[0x10];
6830 u8 reserved_at_40[0xa0];
6833 struct mlx5_ifc_eqe_bits {
6834 u8 reserved_at_0[0x8];
6836 u8 reserved_at_10[0x8];
6837 u8 event_sub_type[0x8];
6839 u8 reserved_at_20[0xe0];
6841 union mlx5_ifc_event_auto_bits event_data;
6843 u8 reserved_at_1e0[0x10];
6845 u8 reserved_at_1f8[0x7];
6850 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6853 struct mlx5_ifc_cmd_queue_entry_bits {
6855 u8 reserved_at_8[0x18];
6857 u8 input_length[0x20];
6859 u8 input_mailbox_pointer_63_32[0x20];
6861 u8 input_mailbox_pointer_31_9[0x17];
6862 u8 reserved_at_77[0x9];
6864 u8 command_input_inline_data[16][0x8];
6866 u8 command_output_inline_data[16][0x8];
6868 u8 output_mailbox_pointer_63_32[0x20];
6870 u8 output_mailbox_pointer_31_9[0x17];
6871 u8 reserved_at_1b7[0x9];
6873 u8 output_length[0x20];
6877 u8 reserved_at_1f0[0x8];
6882 struct mlx5_ifc_cmd_out_bits {
6884 u8 reserved_at_8[0x18];
6888 u8 command_output[0x20];
6891 struct mlx5_ifc_cmd_in_bits {
6893 u8 reserved_at_10[0x10];
6895 u8 reserved_at_20[0x10];
6898 u8 command[0][0x20];
6901 struct mlx5_ifc_cmd_if_box_bits {
6902 u8 mailbox_data[512][0x8];
6904 u8 reserved_at_1000[0x180];
6906 u8 next_pointer_63_32[0x20];
6908 u8 next_pointer_31_10[0x16];
6909 u8 reserved_at_11b6[0xa];
6911 u8 block_number[0x20];
6913 u8 reserved_at_11e0[0x8];
6915 u8 ctrl_signature[0x8];
6919 struct mlx5_ifc_mtt_bits {
6920 u8 ptag_63_32[0x20];
6923 u8 reserved_at_38[0x6];
6928 struct mlx5_ifc_query_wol_rol_out_bits {
6930 u8 reserved_at_8[0x18];
6934 u8 reserved_at_40[0x10];
6938 u8 reserved_at_60[0x20];
6941 struct mlx5_ifc_query_wol_rol_in_bits {
6943 u8 reserved_at_10[0x10];
6945 u8 reserved_at_20[0x10];
6948 u8 reserved_at_40[0x40];
6951 struct mlx5_ifc_set_wol_rol_out_bits {
6953 u8 reserved_at_8[0x18];
6957 u8 reserved_at_40[0x40];
6960 struct mlx5_ifc_set_wol_rol_in_bits {
6962 u8 reserved_at_10[0x10];
6964 u8 reserved_at_20[0x10];
6967 u8 rol_mode_valid[0x1];
6968 u8 wol_mode_valid[0x1];
6969 u8 reserved_at_42[0xe];
6973 u8 reserved_at_60[0x20];
6977 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6978 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6979 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6983 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6984 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6985 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6989 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6990 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6991 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6992 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6993 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6994 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6995 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6996 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6997 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6998 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6999 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7002 struct mlx5_ifc_initial_seg_bits {
7003 u8 fw_rev_minor[0x10];
7004 u8 fw_rev_major[0x10];
7006 u8 cmd_interface_rev[0x10];
7007 u8 fw_rev_subminor[0x10];
7009 u8 reserved_at_40[0x40];
7011 u8 cmdq_phy_addr_63_32[0x20];
7013 u8 cmdq_phy_addr_31_12[0x14];
7014 u8 reserved_at_b4[0x2];
7015 u8 nic_interface[0x2];
7016 u8 log_cmdq_size[0x4];
7017 u8 log_cmdq_stride[0x4];
7019 u8 command_doorbell_vector[0x20];
7021 u8 reserved_at_e0[0xf00];
7023 u8 initializing[0x1];
7024 u8 reserved_at_fe1[0x4];
7025 u8 nic_interface_supported[0x3];
7026 u8 reserved_at_fe8[0x18];
7028 struct mlx5_ifc_health_buffer_bits health_buffer;
7030 u8 no_dram_nic_offset[0x20];
7032 u8 reserved_at_1220[0x6e40];
7034 u8 reserved_at_8060[0x1f];
7037 u8 health_syndrome[0x8];
7038 u8 health_counter[0x18];
7040 u8 reserved_at_80a0[0x17fc0];
7043 union mlx5_ifc_ports_control_registers_document_bits {
7044 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7045 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7046 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7047 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7048 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7049 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7050 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7051 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7052 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7053 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7054 struct mlx5_ifc_paos_reg_bits paos_reg;
7055 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7056 struct mlx5_ifc_peir_reg_bits peir_reg;
7057 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7058 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7059 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7060 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7061 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7062 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7063 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7064 struct mlx5_ifc_plib_reg_bits plib_reg;
7065 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7066 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7067 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7068 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7069 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7070 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7071 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7072 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7073 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7074 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7075 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7076 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7077 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7078 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7079 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7080 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7081 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7082 struct mlx5_ifc_pude_reg_bits pude_reg;
7083 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7084 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7085 struct mlx5_ifc_sltp_reg_bits sltp_reg;
7086 u8 reserved_at_0[0x60e0];
7089 union mlx5_ifc_debug_enhancements_document_bits {
7090 struct mlx5_ifc_health_buffer_bits health_buffer;
7091 u8 reserved_at_0[0x200];
7094 union mlx5_ifc_uplink_pci_interface_document_bits {
7095 struct mlx5_ifc_initial_seg_bits initial_seg;
7096 u8 reserved_at_0[0x20060];
7099 struct mlx5_ifc_set_flow_table_root_out_bits {
7101 u8 reserved_at_8[0x18];
7105 u8 reserved_at_40[0x40];
7108 struct mlx5_ifc_set_flow_table_root_in_bits {
7110 u8 reserved_at_10[0x10];
7112 u8 reserved_at_20[0x10];
7115 u8 reserved_at_40[0x40];
7118 u8 reserved_at_88[0x18];
7120 u8 reserved_at_a0[0x8];
7123 u8 reserved_at_c0[0x140];
7127 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7130 struct mlx5_ifc_modify_flow_table_out_bits {
7132 u8 reserved_at_8[0x18];
7136 u8 reserved_at_40[0x40];
7139 struct mlx5_ifc_modify_flow_table_in_bits {
7141 u8 reserved_at_10[0x10];
7143 u8 reserved_at_20[0x10];
7146 u8 reserved_at_40[0x20];
7148 u8 reserved_at_60[0x10];
7149 u8 modify_field_select[0x10];
7152 u8 reserved_at_88[0x18];
7154 u8 reserved_at_a0[0x8];
7157 u8 reserved_at_c0[0x4];
7158 u8 table_miss_mode[0x4];
7159 u8 reserved_at_c8[0x18];
7161 u8 reserved_at_e0[0x8];
7162 u8 table_miss_id[0x18];
7164 u8 reserved_at_100[0x100];
7167 struct mlx5_ifc_ets_tcn_config_reg_bits {
7171 u8 reserved_at_3[0x9];
7173 u8 reserved_at_10[0x9];
7174 u8 bw_allocation[0x7];
7176 u8 reserved_at_20[0xc];
7177 u8 max_bw_units[0x4];
7178 u8 reserved_at_30[0x8];
7179 u8 max_bw_value[0x8];
7182 struct mlx5_ifc_ets_global_config_reg_bits {
7183 u8 reserved_at_0[0x2];
7185 u8 reserved_at_3[0x1d];
7187 u8 reserved_at_20[0xc];
7188 u8 max_bw_units[0x4];
7189 u8 reserved_at_30[0x8];
7190 u8 max_bw_value[0x8];
7193 struct mlx5_ifc_qetc_reg_bits {
7194 u8 reserved_at_0[0x8];
7195 u8 port_number[0x8];
7196 u8 reserved_at_10[0x30];
7198 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
7199 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7202 struct mlx5_ifc_qtct_reg_bits {
7203 u8 reserved_at_0[0x8];
7204 u8 port_number[0x8];
7205 u8 reserved_at_10[0xd];
7208 u8 reserved_at_20[0x1d];
7212 #endif /* MLX5_IFC_H */